RTEMS  5.1
erc32.h
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1 
7 /* erc32.h
8  *
9  * This include file contains information pertaining to the ERC32.
10  * The ERC32 is a custom SPARC V7 implementation based on the Cypress
11  * 601/602 chipset. This CPU has a number of on-board peripherals and
12  * was developed by the European Space Agency to target space applications.
13  *
14  * NOTE: Other than where absolutely required, this version currently
15  * supports only the peripherals and bits used by the basic board
16  * support package. This includes at least significant pieces of
17  * the following items:
18  *
19  * + UART Channels A and B
20  * + General Purpose Timer
21  * + Real Time Clock
22  * + Watchdog Timer (so it can be disabled)
23  * + Control Register (so powerdown mode can be enabled)
24  * + Memory Control Register
25  * + Interrupt Control
26  *
27  * COPYRIGHT (c) 1989-1999.
28  * On-Line Applications Research Corporation (OAR).
29  *
30  * The license and distribution terms for this file may be
31  * found in the file LICENSE in this distribution or at
32  * http://www.rtems.org/license/LICENSE.
33  *
34  * Ported to ERC32 implementation of the SPARC by On-Line Applications
35  * Research Corporation (OAR) under contract to the European Space
36  * Agency (ESA).
37  *
38  * ERC32 modifications of respective RTEMS file: COPYRIGHT (c) 1995.
39  * European Space Agency.
40  */
41 
42 #ifndef _INCLUDE_ERC32_h
43 #define _INCLUDE_ERC32_h
44 
45 #include <rtems/score/sparc.h>
46 
47 #ifdef __cplusplus
48 extern "C" {
49 #endif
50 
51 /*
52  * Interrupt Sources
53  *
54  * The interrupt source numbers directly map to the trap type and to
55  * the bits used in the Interrupt Clear, Interrupt Force, Interrupt Mask,
56  * and the Interrupt Pending Registers.
57  */
58 
59 #define ERC32_INTERRUPT_MASKED_ERRORS 1
60 #define ERC32_INTERRUPT_EXTERNAL_1 2
61 #define ERC32_INTERRUPT_EXTERNAL_2 3
62 #define ERC32_INTERRUPT_UART_A_RX_TX 4
63 #define ERC32_INTERRUPT_UART_B_RX_TX 5
64 #define ERC32_INTERRUPT_CORRECTABLE_MEMORY_ERROR 6
65 #define ERC32_INTERRUPT_UART_ERROR 7
66 #define ERC32_INTERRUPT_DMA_ACCESS_ERROR 8
67 #define ERC32_INTERRUPT_DMA_TIMEOUT 9
68 #define ERC32_INTERRUPT_EXTERNAL_3 10
69 #define ERC32_INTERRUPT_EXTERNAL_4 11
70 #define ERC32_INTERRUPT_GENERAL_PURPOSE_TIMER 12
71 #define ERC32_INTERRUPT_REAL_TIME_CLOCK 13
72 #define ERC32_INTERRUPT_EXTERNAL_5 14
73 #define ERC32_INTERRUPT_WATCHDOG_TIMEOUT 15
74 
75 #ifndef ASM
76 
77 /*
78  * Trap Types for on-chip peripherals
79  *
80  * Source: Table 8 - Interrupt Trap Type and Default Priority Assignments
81  *
82  * NOTE: The priority level for each source corresponds to the least
83  * significant nibble of the trap type.
84  */
85 
86 #define ERC32_TRAP_TYPE( _source ) SPARC_ASYNCHRONOUS_TRAP((_source) + 0x10)
87 
88 #define ERC32_TRAP_SOURCE( _trap ) ((_trap) - 0x10)
89 
90 #define ERC32_Is_MEC_Trap( _trap ) \
91  ( (_trap) >= ERC32_TRAP_TYPE( ERC32_INTERRUPT_MASKED_ERRORS ) && \
92  (_trap) <= ERC32_TRAP_TYPE( ERC32_INTERRUPT_WATCHDOG_TIMEOUT ) )
93 
94 /*
95  * Structure for ERC32 memory mapped registers.
96  *
97  * Source: Section 3.25.2 - Register Address Map
98  *
99  * NOTE: There is only one of these structures per CPU, its base address
100  * is 0x01f80000, and the variable MEC is placed there by the
101  * linkcmds file.
102  */
103 
104 typedef struct {
105  volatile uint32_t Control; /* offset 0x00 */
106  volatile uint32_t Software_Reset; /* offset 0x04 */
107  volatile uint32_t Power_Down; /* offset 0x08 */
108  volatile uint32_t Unimplemented_0; /* offset 0x0c */
109  volatile uint32_t Memory_Configuration; /* offset 0x10 */
110  volatile uint32_t IO_Configuration; /* offset 0x14 */
111  volatile uint32_t Wait_State_Configuration; /* offset 0x18 */
112  volatile uint32_t Unimplemented_1; /* offset 0x1c */
113  volatile uint32_t Memory_Access_0; /* offset 0x20 */
114  volatile uint32_t Memory_Access_1; /* offset 0x24 */
115  volatile uint32_t Unimplemented_2[ 7 ]; /* offset 0x28 */
116  volatile uint32_t Interrupt_Shape; /* offset 0x44 */
117  volatile uint32_t Interrupt_Pending; /* offset 0x48 */
118  volatile uint32_t Interrupt_Mask; /* offset 0x4c */
119  volatile uint32_t Interrupt_Clear; /* offset 0x50 */
120  volatile uint32_t Interrupt_Force; /* offset 0x54 */
121  volatile uint32_t Unimplemented_3[ 2 ]; /* offset 0x58 */
122  /* offset 0x60 */
123  volatile uint32_t Watchdog_Program_and_Timeout_Acknowledge;
124  volatile uint32_t Watchdog_Trap_Door_Set; /* offset 0x64 */
125  volatile uint32_t Unimplemented_4[ 6 ]; /* offset 0x68 */
126  volatile uint32_t Real_Time_Clock_Counter; /* offset 0x80 */
127  volatile uint32_t Real_Time_Clock_Scalar; /* offset 0x84 */
128  volatile uint32_t General_Purpose_Timer_Counter; /* offset 0x88 */
129  volatile uint32_t General_Purpose_Timer_Scalar; /* offset 0x8c */
130  volatile uint32_t Unimplemented_5[ 2 ]; /* offset 0x90 */
131  volatile uint32_t Timer_Control; /* offset 0x98 */
132  volatile uint32_t Unimplemented_6; /* offset 0x9c */
133  volatile uint32_t System_Fault_Status; /* offset 0xa0 */
134  volatile uint32_t First_Failing_Address; /* offset 0xa4 */
135  volatile uint32_t First_Failing_Data; /* offset 0xa8 */
136  volatile uint32_t First_Failing_Syndrome_and_Check_Bits;/* offset 0xac */
137  volatile uint32_t Error_and_Reset_Status; /* offset 0xb0 */
138  volatile uint32_t Error_Mask; /* offset 0xb4 */
139  volatile uint32_t Unimplemented_7[ 2 ]; /* offset 0xb8 */
140  volatile uint32_t Debug_Control; /* offset 0xc0 */
141  volatile uint32_t Breakpoint; /* offset 0xc4 */
142  volatile uint32_t Watchpoint; /* offset 0xc8 */
143  volatile uint32_t Unimplemented_8; /* offset 0xcc */
144  volatile uint32_t Test_Control; /* offset 0xd0 */
145  volatile uint32_t Test_Data; /* offset 0xd4 */
146  volatile uint32_t Unimplemented_9[ 2 ]; /* offset 0xd8 */
147  volatile uint32_t UART_Channel_A; /* offset 0xe0 */
148  volatile uint32_t UART_Channel_B; /* offset 0xe4 */
149  volatile uint32_t UART_Status; /* offset 0xe8 */
150 } ERC32_Register_Map;
151 
152 #endif
153 
154 /*
155  * The following constants are intended to be used ONLY in assembly
156  * language files.
157  *
158  * NOTE: The intended style of usage is to load the address of MEC
159  * into a register and then use these as displacements from
160  * that register.
161  */
162 
163 #ifdef ASM
164 
165 #define ERC32_MEC_CONTROL_OFFSET 0x00
166 #define ERC32_MEC_SOFTWARE_RESET_OFFSET 0x04
167 #define ERC32_MEC_POWER_DOWN_OFFSET 0x08
168 #define ERC32_MEC_UNIMPLEMENTED_0_OFFSET 0x0C
169 #define ERC32_MEC_MEMORY_CONFIGURATION_OFFSET 0x10
170 #define ERC32_MEC_IO_CONFIGURATION_OFFSET 0x14
171 #define ERC32_MEC_WAIT_STATE_CONFIGURATION_OFFSET 0x18
172 #define ERC32_MEC_UNIMPLEMENTED_1_OFFSET 0x1C
173 #define ERC32_MEC_MEMORY_ACCESS_0_OFFSET 0x20
174 #define ERC32_MEC_MEMORY_ACCESS_1_OFFSET 0x24
175 #define ERC32_MEC_UNIMPLEMENTED_2_OFFSET 0x28
176 #define ERC32_MEC_INTERRUPT_SHAPE_OFFSET 0x44
177 #define ERC32_MEC_INTERRUPT_PENDING_OFFSET 0x48
178 #define ERC32_MEC_INTERRUPT_MASK_OFFSET 0x4C
179 #define ERC32_MEC_INTERRUPT_CLEAR_OFFSET 0x50
180 #define ERC32_MEC_INTERRUPT_FORCE_OFFSET 0x54
181 #define ERC32_MEC_UNIMPLEMENTED_3_OFFSET 0x58
182 #define ERC32_MEC_WATCHDOG_PROGRAM_AND_TIMEOUT_ACKNOWLEDGE_OFFSET 0x60
183 #define ERC32_MEC_WATCHDOG_TRAP_DOOR_SET_OFFSET 0x64
184 #define ERC32_MEC_UNIMPLEMENTED_4_OFFSET 0x6C
185 #define ERC32_MEC_REAL_TIME_CLOCK_COUNTER_OFFSET 0x80
186 #define ERC32_MEC_REAL_TIME_CLOCK_SCALAR_OFFSET 0x84
187 #define ERC32_MEC_GENERAL_PURPOSE_TIMER_COUNTER_OFFSET 0x88
188 #define ERC32_MEC_GENERAL_PURPOSE_TIMER_SCALAR_OFFSET 0x8C
189 #define ERC32_MEC_UNIMPLEMENTED_5_OFFSET 0x90
190 #define ERC32_MEC_TIMER_CONTROL_OFFSET 0x98
191 #define ERC32_MEC_UNIMPLEMENTED_6_OFFSET 0x9C
192 #define ERC32_MEC_SYSTEM_FAULT_STATUS_OFFSET 0xA0
193 #define ERC32_MEC_FIRST_FAILING_ADDRESS_OFFSET 0xA4
194 #define ERC32_MEC_FIRST_FAILING_DATA_OFFSET 0xA8
195 #define ERC32_MEC_FIRST_FAILING_SYNDROME_AND_CHECK_BITS_OFFSET 0xAC
196 #define ERC32_MEC_ERROR_AND_RESET_STATUS_OFFSET 0xB0
197 #define ERC32_MEC_ERROR_MASK_OFFSET 0xB4
198 #define ERC32_MEC_UNIMPLEMENTED_7_OFFSET 0xB8
199 #define ERC32_MEC_DEBUG_CONTROL_OFFSET 0xC0
200 #define ERC32_MEC_BREAKPOINT_OFFSET 0xC4
201 #define ERC32_MEC_WATCHPOINT_OFFSET 0xC8
202 #define ERC32_MEC_UNIMPLEMENTED_8_OFFSET 0xCC
203 #define ERC32_MEC_TEST_CONTROL_OFFSET 0xD0
204 #define ERC32_MEC_TEST_DATA_OFFSET 0xD4
205 #define ERC32_MEC_UNIMPLEMENTED_9_OFFSET 0xD8
206 #define ERC32_MEC_UART_CHANNEL_A_OFFSET 0xE0
207 #define ERC32_MEC_UART_CHANNEL_B_OFFSET 0xE4
208 #define ERC32_MEC_UART_STATUS_OFFSET 0xE8
209 
210 #endif
211 
212 /*
213  * The following defines the bits in the Configuration Register.
214  */
215 
216 #define ERC32_CONFIGURATION_POWER_DOWN_MASK 0x00000001
217 #define ERC32_CONFIGURATION_POWER_DOWN_ALLOWED 0x00000001
218 #define ERC32_CONFIGURATION_POWER_DOWN_DISABLED 0x00000000
219 
220 #define ERC32_CONFIGURATION_SOFTWARE_RESET_MASK 0x00000002
221 #define ERC32_CONFIGURATION_SOFTWARE_RESET_ALLOWED 0x00000002
222 #define ERC32_CONFIGURATION_SOFTWARE_RESET_DISABLED 0x00000000
223 
224 #define ERC32_CONFIGURATION_BUS_TIMEOUT_MASK 0x00000004
225 #define ERC32_CONFIGURATION_BUS_TIMEOUT_ENABLED 0x00000004
226 #define ERC32_CONFIGURATION_BUS_TIMEOUT_DISABLED 0x00000000
227 
228 #define ERC32_CONFIGURATION_ACCESS_PROTECTION_MASK 0x00000008
229 #define ERC32_CONFIGURATION_ACCESS_PROTECTION_ENABLED 0x00000008
230 #define ERC32_CONFIGURATION_ACCESS_PROTECTION_DISABLED 0x00000000
231 
232 /*
233  * The following defines the bits in the Memory Configuration Register.
234  */
235 
236 #define ERC32_MEMORY_CONFIGURATION_RAM_SIZE_MASK 0x00001C00
237 #define ERC32_MEMORY_CONFIGURATION_RAM_SIZE_256K ( 0 << 10 )
238 #define ERC32_MEMORY_CONFIGURATION_RAM_SIZE_512K ( 1 << 10 )
239 #define ERC32_MEMORY_CONFIGURATION_RAM_SIZE_1MB ( 2 << 10 )
240 #define ERC32_MEMORY_CONFIGURATION_RAM_SIZE_2MB ( 3 << 10 )
241 #define ERC32_MEMORY_CONFIGURATION_RAM_SIZE_4MB ( 4 << 10 )
242 #define ERC32_MEMORY_CONFIGURATION_RAM_SIZE_8MB ( 5 << 10 )
243 #define ERC32_MEMORY_CONFIGURATION_RAM_SIZE_16MB ( 6 << 10 )
244 #define ERC32_MEMORY_CONFIGURATION_RAM_SIZE_32MB ( 7 << 10 )
245 
246 #define ERC32_MEMORY_CONFIGURATION_PROM_SIZE_MASK 0x001C0000
247 #define ERC32_MEMORY_CONFIGURATION_PROM_SIZE_128K ( 0 << 18 )
248 #define ERC32_MEMORY_CONFIGURATION_PROM_SIZE_256K ( 1 << 18 )
249 #define ERC32_MEMORY_CONFIGURATION_PROM_SIZE_512K ( 2 << 18 )
250 #define ERC32_MEMORY_CONFIGURATION_PROM_SIZE_1M ( 3 << 18 )
251 #define ERC32_MEMORY_CONFIGURATION_PROM_SIZE_2M ( 4 << 18 )
252 #define ERC32_MEMORY_CONFIGURATION_PROM_SIZE_4M ( 5 << 18 )
253 #define ERC32_MEMORY_CONFIGURATION_PROM_SIZE_8M ( 6 << 18 )
254 #define ERC32_MEMORY_CONFIGURATION_PROM_SIZE_16M ( 7 << 18 )
255 
256 /*
257  * The following defines the bits in the Timer Control Register.
258  */
259 
260 #define ERC32_MEC_TIMER_CONTROL_GCR 0x00000001 /* 1 = reload at 0 */
261  /* 0 = stop at 0 */
262 #define ERC32_MEC_TIMER_CONTROL_GCL 0x00000002 /* 1 = load and start */
263  /* 0 = no function */
264 #define ERC32_MEC_TIMER_CONTROL_GSE 0x00000004 /* 1 = enable counting */
265  /* 0 = hold scalar and counter */
266 #define ERC32_MEC_TIMER_CONTROL_GSL 0x00000008 /* 1 = load scalar and start*/
267  /* 0 = no function */
268 
269 #define ERC32_MEC_TIMER_CONTROL_RTCCR 0x00000100 /* 1 = reload at 0 */
270  /* 0 = stop at 0 */
271 #define ERC32_MEC_TIMER_CONTROL_RTCCL 0x00000200 /* 1 = load and start */
272  /* 0 = no function */
273 #define ERC32_MEC_TIMER_CONTROL_RTCSE 0x00000400 /* 1 = enable counting */
274  /* 0 = hold scalar and counter */
275 #define ERC32_MEC_TIMER_CONTROL_RTCSL 0x00000800 /* 1 = load scalar and start*/
276  /* 0 = no function */
277 
278 /*
279  * The following defines the bits in the UART Control Registers.
280  *
281  */
282 
283 #define ERC32_MEC_UART_CONTROL_RTD 0x000000FF /* RX/TX data */
284 
285 /*
286  * The following defines the bits in the MEC UART Control Registers.
287  */
288 
289 #define ERC32_MEC_UART_STATUS_DR 0x00000001 /* Data Ready */
290 #define ERC32_MEC_UART_STATUS_TSE 0x00000002 /* TX Send Register Empty */
291 #define ERC32_MEC_UART_STATUS_THE 0x00000004 /* TX Hold Register Empty */
292 #define ERC32_MEC_UART_STATUS_FE 0x00000010 /* RX Framing Error */
293 #define ERC32_MEC_UART_STATUS_PE 0x00000020 /* RX Parity Error */
294 #define ERC32_MEC_UART_STATUS_OE 0x00000040 /* RX Overrun Error */
295 #define ERC32_MEC_UART_STATUS_CU 0x00000080 /* Clear Errors */
296 #define ERC32_MEC_UART_STATUS_TXE 0x00000006 /* TX Empty */
297 #define ERC32_MEC_UART_STATUS_CLRA 0x00000080 /* Clear UART A */
298 #define ERC32_MEC_UART_STATUS_CLRB 0x00800000 /* Clear UART B */
299 #define ERC32_MEC_UART_STATUS_ERRA 0x00000070 /* Error in UART A */
300 #define ERC32_MEC_UART_STATUS_ERRB 0x00700000 /* Error in UART B */
301 
302 #define ERC32_MEC_UART_STATUS_DRA (ERC32_MEC_UART_STATUS_DR << 0)
303 #define ERC32_MEC_UART_STATUS_TSEA (ERC32_MEC_UART_STATUS_TSE << 0)
304 #define ERC32_MEC_UART_STATUS_THEA (ERC32_MEC_UART_STATUS_THE << 0)
305 #define ERC32_MEC_UART_STATUS_FEA (ERC32_MEC_UART_STATUS_FE << 0)
306 #define ERC32_MEC_UART_STATUS_PEA (ERC32_MEC_UART_STATUS_PE << 0)
307 #define ERC32_MEC_UART_STATUS_OEA (ERC32_MEC_UART_STATUS_OE << 0)
308 #define ERC32_MEC_UART_STATUS_CUA (ERC32_MEC_UART_STATUS_CU << 0)
309 #define ERC32_MEC_UART_STATUS_TXEA (ERC32_MEC_UART_STATUS_TXE << 0)
310 
311 #define ERC32_MEC_UART_STATUS_DRB (ERC32_MEC_UART_STATUS_DR << 16)
312 #define ERC32_MEC_UART_STATUS_TSEB (ERC32_MEC_UART_STATUS_TSE << 16)
313 #define ERC32_MEC_UART_STATUS_THEB (ERC32_MEC_UART_STATUS_THE << 16)
314 #define ERC32_MEC_UART_STATUS_FEB (ERC32_MEC_UART_STATUS_FE << 16)
315 #define ERC32_MEC_UART_STATUS_PEB (ERC32_MEC_UART_STATUS_PE << 16)
316 #define ERC32_MEC_UART_STATUS_OEB (ERC32_MEC_UART_STATUS_OE << 16)
317 #define ERC32_MEC_UART_STATUS_CUB (ERC32_MEC_UART_STATUS_CU << 16)
318 #define ERC32_MEC_UART_STATUS_TXEB (ERC32_MEC_UART_STATUS_TXE << 16)
319 
320 #ifndef ASM
321 
322 /*
323  * This is used to manipulate the on-chip registers.
324  *
325  * The following symbol must be defined in the linkcmds file and point
326  * to the correct location.
327  */
328 
329 extern ERC32_Register_Map ERC32_MEC;
330 
331 static __inline__ int bsp_irq_fixup(int irq)
332 {
333  return irq;
334 }
335 
336 /*
337  * Macros to manipulate the Interrupt Clear, Interrupt Force, Interrupt Mask,
338  * and the Interrupt Pending Registers.
339  *
340  * NOTE: For operations which are not atomic, this code disables interrupts
341  * to guarantee there are no intervening accesses to the same register.
342  * The operations which read the register, modify the value and then
343  * store the result back are vulnerable.
344  */
345 
346 #define ERC32_Clear_interrupt( _source ) \
347  do { \
348  ERC32_MEC.Interrupt_Clear = (1 << (_source)); \
349  } while (0)
350 
351 #define ERC32_Force_interrupt( _source ) \
352  do { \
353  uint32_t _level; \
354  \
355  _level = sparc_disable_interrupts(); \
356  ERC32_MEC.Test_Control = ERC32_MEC.Test_Control | 0x80000; \
357  ERC32_MEC.Interrupt_Force = (1 << (_source)); \
358  sparc_enable_interrupts( _level ); \
359  } while (0)
360 
361 #define ERC32_Is_interrupt_pending( _source ) \
362  (ERC32_MEC.Interrupt_Pending & (1 << (_source)))
363 
364 #define ERC32_Is_interrupt_masked( _source ) \
365  (ERC32_MEC.Interrupt_Mask & (1 << (_source)))
366 
367 #define ERC32_Mask_interrupt( _source ) \
368  do { \
369  uint32_t _level; \
370  \
371  _level = sparc_disable_interrupts(); \
372  ERC32_MEC.Interrupt_Mask |= (1 << (_source)); \
373  sparc_enable_interrupts( _level ); \
374  } while (0)
375 
376 #define ERC32_Unmask_interrupt( _source ) \
377  do { \
378  uint32_t _level; \
379  \
380  _level = sparc_disable_interrupts(); \
381  ERC32_MEC.Interrupt_Mask &= ~(1 << (_source)); \
382  sparc_enable_interrupts( _level ); \
383  } while (0)
384 
385 #define ERC32_Disable_interrupt( _source, _previous ) \
386  do { \
387  uint32_t _level; \
388  uint32_t _mask = 1 << (_source); \
389  \
390  _level = sparc_disable_interrupts(); \
391  (_previous) = ERC32_MEC.Interrupt_Mask; \
392  ERC32_MEC.Interrupt_Mask = _previous | _mask; \
393  sparc_enable_interrupts( _level ); \
394  (_previous) &= _mask; \
395  } while (0)
396 
397 #define ERC32_Restore_interrupt( _source, _previous ) \
398  do { \
399  uint32_t _level; \
400  uint32_t _mask = 1 << (_source); \
401  \
402  _level = sparc_disable_interrupts(); \
403  ERC32_MEC.Interrupt_Mask = \
404  (ERC32_MEC.Interrupt_Mask & ~_mask) | (_previous); \
405  sparc_enable_interrupts( _level ); \
406  } while (0)
407 
408 /* Make all SPARC BSPs have common macros for interrupt handling on local CPU */
409 #define BSP_Clear_interrupt(_source) ERC32_Clear_interrupt(_source)
410 #define BSP_Force_interrupt(_source) ERC32_Force_interrupt(_source)
411 #define BSP_Is_interrupt_pending(_source) ERC32_Is_interrupt_pending(_source)
412 #define BSP_Is_interrupt_masked(_source) ERC32_Is_interrupt_masked(_source)
413 #define BSP_Unmask_interrupt(_source) ERC32_Unmask_interrupt(_source)
414 #define BSP_Mask_interrupt(_source) ERC32_Mask_interrupt(_source)
415 #define BSP_Disable_interrupt(_source, _previous) \
416  ERC32_Disable_interrupt(_source, _prev)
417 #define BSP_Restore_interrupt(_source, _previous) \
418  ERC32_Restore_interrupt(_source, _previous)
419 
420 /* Make all SPARC BSPs have common macros for interrupt handling on any CPU */
421 #define BSP_Cpu_Is_interrupt_masked(_source, _cpu) \
422  BSP_Is_interrupt_masked(_source)
423 #define BSP_Cpu_Unmask_interrupt(_source, _cpu) \
424  BSP_Unmask_interrupt(_source)
425 #define BSP_Cpu_Mask_interrupt(_source, _cpu) \
426  BSP_Mask_interrupt(_source)
427 #define BSP_Cpu_Disable_interrupt(_source, _previous, _cpu) \
428  BSP_Disable_interrupt(_source, _prev)
429 #define BSP_Cpu_Restore_interrupt(_source, _previous, _cpu) \
430  BSP_Cpu_Restore_interrupt(_source, _previous)
431 
432 /*
433  * The following macros attempt to hide the fact that the General Purpose
434  * Timer and Real Time Clock Timer share the Timer Control Register. Because
435  * the Timer Control Register is write only, we must mirror it in software
436  * and insure that writes to one timer do not alter the current settings
437  * and status of the other timer.
438  *
439  * This code promotes the view that the two timers are completely independent.
440  * By exclusively using the routines below to access the Timer Control
441  * Register, the application can view the system as having a General Purpose
442  * Timer Control Register and a Real Time Clock Timer Control Register
443  * rather than the single shared value.
444  *
445  * Each logical timer control register is organized as follows:
446  *
447  * D0 - Counter Reload
448  * 1 = reload counter at zero and restart
449  * 0 = stop counter at zero
450  *
451  * D1 - Counter Load
452  * 1 = load counter with preset value and restart
453  * 0 = no function
454  *
455  * D2 - Enable
456  * 1 = enable counting
457  * 0 = hold scaler and counter
458  *
459  * D3 - Scaler Load
460  * 1 = load scalar with preset value and restart
461  * 0 = no function
462  *
463  * To insure the management of the mirror is atomic, we disable interrupts
464  * around updates.
465  */
466 
467 #define ERC32_MEC_TIMER_COUNTER_RELOAD_AT_ZERO 0x00000001
468 #define ERC32_MEC_TIMER_COUNTER_STOP_AT_ZERO 0x00000000
469 
470 #define ERC32_MEC_TIMER_COUNTER_LOAD_COUNTER 0x00000002
471 
472 #define ERC32_MEC_TIMER_COUNTER_ENABLE_COUNTING 0x00000004
473 #define ERC32_MEC_TIMER_COUNTER_DISABLE_COUNTING 0x00000000
474 
475 #define ERC32_MEC_TIMER_COUNTER_LOAD_SCALER 0x00000008
476 
477 #define ERC32_MEC_TIMER_COUNTER_RELOAD_MASK 0x00000001
478 #define ERC32_MEC_TIMER_COUNTER_ENABLE_MASK 0x00000004
479 
480 #define ERC32_MEC_TIMER_COUNTER_DEFINED_MASK 0x0000000F
481 #define ERC32_MEC_TIMER_COUNTER_CURRENT_MODE_MASK 0x00000005
482 
483 extern uint32_t _ERC32_MEC_Timer_Control_Mirror;
484 
485 /*
486  * This macros manipulate the General Purpose Timer portion of the
487  * Timer Control register and promote the view that there are actually
488  * two independent Timer Control Registers.
489  */
490 
491 #define ERC32_MEC_Set_General_Purpose_Timer_Control( _value ) \
492  do { \
493  uint32_t _level; \
494  uint32_t _control; \
495  uint32_t __value; \
496  \
497  __value = ((_value) & 0x0f); \
498  _level = sparc_disable_interrupts(); \
499  _control = _ERC32_MEC_Timer_Control_Mirror; \
500  _control &= ERC32_MEC_TIMER_COUNTER_DEFINED_MASK << 8; \
501  _ERC32_MEC_Timer_Control_Mirror = _control | _value; \
502  _control &= (ERC32_MEC_TIMER_COUNTER_CURRENT_MODE_MASK << 8); \
503  _control |= __value; \
504  /* printf( "GPT 0x%x 0x%x 0x%x\n", _value, __value, _control ); */ \
505  ERC32_MEC.Timer_Control = _control; \
506  sparc_enable_interrupts( _level ); \
507  } while ( 0 )
508 
509 #define ERC32_MEC_Get_General_Purpose_Timer_Control( _value ) \
510  do { \
511  (_value) = _ERC32_MEC_Timer_Control_Mirror & 0xf; \
512  } while ( 0 )
513 
514 /*
515  * This macros manipulate the Real Timer Clock Timer portion of the
516  * Timer Control register and promote the view that there are actually
517  * two independent Timer Control Registers.
518  */
519 
520 #define ERC32_MEC_Set_Real_Time_Clock_Timer_Control( _value ) \
521  do { \
522  uint32_t _level; \
523  uint32_t _control; \
524  uint32_t __value; \
525  \
526  __value = ((_value) & 0x0f) << 8; \
527  _level = sparc_disable_interrupts(); \
528  _control = _ERC32_MEC_Timer_Control_Mirror; \
529  _control &= ERC32_MEC_TIMER_COUNTER_DEFINED_MASK; \
530  _ERC32_MEC_Timer_Control_Mirror = _control | __value; \
531  _control &= ERC32_MEC_TIMER_COUNTER_CURRENT_MODE_MASK; \
532  _control |= __value; \
533  /* printf( "RTC 0x%x 0x%x 0x%x\n", _value, __value, _control ); */ \
534  ERC32_MEC.Timer_Control = _control; \
535  sparc_enable_interrupts( _level ); \
536  } while ( 0 )
537 
538 #define ERC32_MEC_Get_Real_Time_Clock_Timer_Control( _value ) \
539  do { \
540  (_value) = (_ERC32_MEC_Timer_Control_Mirror >> 8) & 0xf; \
541  } while ( 0 )
542 
543 #endif /* !ASM */
544 
545 #ifdef __cplusplus
546 }
547 #endif
548 
549 #endif /* !_INCLUDE_ERC32_h */
sparc.h
Information Required to Build RTEMS for a Particular Member of the SPARC Family.
ERC32_Register_Map
Definition: erc32.h:104
Timer_Control
Definition: timerdata.h:41
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