18 #ifndef LIBBSP_MIPS_TX4938_IRQ_H    19 #define LIBBSP_MIPS_TX4938_IRQ_H    38 #define BSP_INTERRUPT_VECTOR_MIN   0    39 #define TX4938_IRQ_ECC         MIPS_INTERRUPT_BASE+0    40 #define TX4938_IRQ_WTE         MIPS_INTERRUPT_BASE+1    41 #define TX4938_IRQ_INT0        MIPS_INTERRUPT_BASE+2    42 #define TX4938_IRQ_INT1        MIPS_INTERRUPT_BASE+3    43 #define TX4938_IRQ_INT2        MIPS_INTERRUPT_BASE+4    44 #define TX4938_IRQ_INT3        MIPS_INTERRUPT_BASE+5    45 #define TX4938_IRQ_INT4        MIPS_INTERRUPT_BASE+6    46 #define TX4938_IRQ_INT5        MIPS_INTERRUPT_BASE+7    47 #define TX4938_IRQ_SIO0        MIPS_INTERRUPT_BASE+8    48 #define TX4938_IRQ_SIO1        MIPS_INTERRUPT_BASE+9    49 #define TX4938_IRQ_DMAC00      MIPS_INTERRUPT_BASE+10    50 #define TX4938_IRQ_DMAC01      MIPS_INTERRUPT_BASE+11    51 #define TX4938_IRQ_DMAC02      MIPS_INTERRUPT_BASE+12    52 #define TX4938_IRQ_DMAC03      MIPS_INTERRUPT_BASE+13    53 #define TX4938_IRQ_IRC         MIPS_INTERRUPT_BASE+14    54 #define TX4938_IRQ_PDMAC       MIPS_INTERRUPT_BASE+15    55 #define TX4938_IRQ_PCIC        MIPS_INTERRUPT_BASE+16    56 #define TX4938_IRQ_TMR0        MIPS_INTERRUPT_BASE+17    57 #define TX4938_IRQ_TMR1        MIPS_INTERRUPT_BASE+18    58 #define TX4938_IRQ_TMR2        MIPS_INTERRUPT_BASE+19    59 #define TX4938_IRQ_RSV1        MIPS_INTERRUPT_BASE+20    60 #define TX4938_IRQ_NDFMC       MIPS_INTERRUPT_BASE+21    61 #define TX4938_IRQ_PCIERR      MIPS_INTERRUPT_BASE+22    62 #define TX4938_IRQ_PCIPMC      MIPS_INTERRUPT_BASE+23    63 #define TX4938_IRQ_ACLC        MIPS_INTERRUPT_BASE+24    64 #define TX4938_IRQ_ACLCPME     MIPS_INTERRUPT_BASE+25    65 #define TX4938_IRQ_PCIC1NT     MIPS_INTERRUPT_BASE+26    66 #define TX4938_IRQ_ACLCPME     MIPS_INTERRUPT_BASE+27    67 #define TX4938_IRQ_DMAC10      MIPS_INTERRUPT_BASE+28    68 #define TX4938_IRQ_DMAC11      MIPS_INTERRUPT_BASE+29    69 #define TX4938_IRQ_DMAC12      MIPS_INTERRUPT_BASE+30    70 #define TX4938_IRQ_DMAC13      MIPS_INTERRUPT_BASE+31    72 #define TX4938_IRQ_SOFTWARE_1  MIPS_INTERRUPT_BASE+32    73 #define TX4938_IRQ_SOFTWARE_2  MIPS_INTERRUPT_BASE+33    74 #define TX4938_MAXIMUM_VECTORS MIPS_INTERRUPT_BASE+34    76 #define BSP_INTERRUPT_VECTOR_MAX TX4938_MAXIMUM_VECTORS Header file for the Interrupt Manager Extension.
 
Information to build RTEMS for a "no cpu" while in protected mode.