15 #ifndef _RTEMS_SCORE_CPUIMPL_H    16 #define _RTEMS_SCORE_CPUIMPL_H    18 #include <rtems/score/cpu.h>    30 #define CPU_PER_CPU_CONTROL_SIZE 0    32 #ifdef ARM_MULTILIB_ARCH_V4    34 #if defined(ARM_MULTILIB_VFP_D32)    35 #define CPU_INTERRUPT_FRAME_SIZE 240    36 #elif defined(ARM_MULTILIB_VFP)    37 #define CPU_INTERRUPT_FRAME_SIZE 112    39 #define CPU_INTERRUPT_FRAME_SIZE 40    50 #ifdef ARM_MULTILIB_ARCH_V4    53 #ifdef ARM_MULTILIB_VFP    55 #ifdef ARM_MULTILIB_VFP_D32    96 static inline struct Per_CPU_Control *_ARM_Get_current_per_CPU_control( 
void )
   102     "mrc p15, 0, %0, c13, c0, 4"   109 #define _CPU_Get_current_per_CPU_control() _ARM_Get_current_per_CPU_control()   115 void _CPU_Context_volatile_clobber( uintptr_t pattern );
   117 void _CPU_Context_validate( uintptr_t pattern );
 Interrupt stack frame (ISF).
Definition: cpu.h:191
 
Per CPU Core Structure.
Definition: percpu.h:347
 
RTEMS_INLINE_ROUTINE void _CPU_Instruction_no_operation(void)
Emits a no operation instruction (nop).
Definition: cpuimpl.h:132
 
register struct Per_CPU_Control *_SPARC_Per_CPU_current __asm__("g6")
The pointer to the current per-CPU control is available via register g6.
 
RTEMS_INLINE_ROUTINE void _CPU_Instruction_illegal(void)
Emits an illegal instruction.
Definition: cpuimpl.h:122
 
#define RTEMS_INLINE_ROUTINE
Definition: basedefs.h:66