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#define | _AVR_IOXXX_H_ "iomxx0_1.h" |
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#define | PINA _SFR_IO8(0X00) |
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#define | PINA7 7 |
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#define | PINA6 6 |
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#define | PINA5 5 |
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#define | PINA4 4 |
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#define | PINA3 3 |
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#define | PINA2 2 |
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#define | PINA1 1 |
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#define | PINA0 0 |
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#define | DDRA _SFR_IO8(0X01) |
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#define | DDA7 7 |
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#define | DDA6 6 |
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#define | DDA5 5 |
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#define | DDA4 4 |
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#define | DDA3 3 |
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#define | DDA2 2 |
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#define | DDA1 1 |
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#define | DDA0 0 |
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#define | PORTA _SFR_IO8(0X02) |
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#define | PA7 7 |
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#define | PA6 6 |
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#define | PA5 5 |
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#define | PA4 4 |
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#define | PA3 3 |
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#define | PA2 2 |
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#define | PA1 1 |
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#define | PA0 0 |
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#define | PINB _SFR_IO8(0X03) |
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#define | PINB7 7 |
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#define | PINB6 6 |
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#define | PINB5 5 |
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#define | PINB4 4 |
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#define | PINB3 3 |
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#define | PINB2 2 |
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#define | PINB1 1 |
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#define | PINB0 0 |
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#define | DDRB _SFR_IO8(0x04) |
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#define | DDB7 7 |
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#define | DDB6 6 |
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#define | DDB5 5 |
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#define | DDB4 4 |
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#define | DDB3 3 |
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#define | DDB2 2 |
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#define | DDB1 1 |
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#define | DDB0 0 |
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#define | PORTB _SFR_IO8(0x05) |
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#define | PB7 7 |
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#define | PB6 6 |
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#define | PB5 5 |
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#define | PB4 4 |
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#define | PB3 3 |
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#define | PB2 2 |
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#define | PB1 1 |
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#define | PB0 0 |
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#define | PINC _SFR_IO8(0x06) |
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#define | PINC7 7 |
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#define | PINC6 6 |
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#define | PINC5 5 |
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#define | PINC4 4 |
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#define | PINC3 3 |
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#define | PINC2 2 |
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#define | PINC1 1 |
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#define | PINC0 0 |
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#define | DDRC _SFR_IO8(0x07) |
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#define | DDC7 7 |
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#define | DDC6 6 |
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#define | DDC5 5 |
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#define | DDC4 4 |
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#define | DDC3 3 |
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#define | DDC2 2 |
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#define | DDC1 1 |
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#define | DDC0 0 |
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#define | PORTC _SFR_IO8(0x08) |
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#define | PC7 7 |
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#define | PC6 6 |
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#define | PC5 5 |
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#define | PC4 4 |
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#define | PC3 3 |
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#define | PC2 2 |
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#define | PC1 1 |
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#define | PC0 0 |
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#define | PIND _SFR_IO8(0x09) |
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#define | PIND7 7 |
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#define | PIND6 6 |
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#define | PIND5 5 |
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#define | PIND4 4 |
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#define | PIND3 3 |
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#define | PIND2 2 |
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#define | PIND1 1 |
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#define | PIND0 0 |
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#define | DDRD _SFR_IO8(0x0A) |
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#define | DDD7 7 |
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#define | DDD6 6 |
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#define | DDD5 5 |
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#define | DDD4 4 |
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#define | DDD3 3 |
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#define | DDD2 2 |
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#define | DDD1 1 |
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#define | DDD0 0 |
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#define | PORTD _SFR_IO8(0x0B) |
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#define | PD7 7 |
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#define | PD6 6 |
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#define | PD5 5 |
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#define | PD4 4 |
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#define | PD3 3 |
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#define | PD2 2 |
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#define | PD1 1 |
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#define | PD0 0 |
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#define | PINE _SFR_IO8(0x0C) |
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#define | PINE7 7 |
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#define | PINE6 6 |
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#define | PINE5 5 |
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#define | PINE4 4 |
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#define | PINE3 3 |
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#define | PINE2 2 |
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#define | PINE1 1 |
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#define | PINE0 0 |
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#define | DDRE _SFR_IO8(0x0D) |
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#define | DDE7 7 |
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#define | DDE6 6 |
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#define | DDE5 5 |
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#define | DDE4 4 |
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#define | DDE3 3 |
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#define | DDE2 2 |
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#define | DDE1 1 |
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#define | DDE0 0 |
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#define | PORTE _SFR_IO8(0x0E) |
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#define | PE7 7 |
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#define | PE6 6 |
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#define | PE5 5 |
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#define | PE4 4 |
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#define | PE3 3 |
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#define | PE2 2 |
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#define | PE1 1 |
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#define | PE0 0 |
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#define | PINF _SFR_IO8(0x0F) |
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#define | PINF7 7 |
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#define | PINF6 6 |
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#define | PINF5 5 |
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#define | PINF4 4 |
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#define | PINF3 3 |
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#define | PINF2 2 |
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#define | PINF1 1 |
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#define | PINF0 0 |
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#define | DDRF _SFR_IO8(0x10) |
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#define | DDF7 7 |
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#define | DDF6 6 |
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#define | DDF5 5 |
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#define | DDF4 4 |
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#define | DDF3 3 |
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#define | DDF2 2 |
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#define | DDF1 1 |
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#define | DDF0 0 |
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#define | PORTF _SFR_IO8(0x11) |
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#define | PF7 7 |
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#define | PF6 6 |
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#define | PF5 5 |
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#define | PF4 4 |
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#define | PF3 3 |
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#define | PF2 2 |
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#define | PF1 1 |
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#define | PF0 0 |
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#define | PING _SFR_IO8(0x12) |
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#define | PING5 5 |
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#define | PING4 4 |
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#define | PING3 3 |
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#define | PING2 2 |
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#define | PING1 1 |
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#define | PING0 0 |
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#define | DDRG _SFR_IO8(0x13) |
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#define | DDG5 5 |
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#define | DDG4 4 |
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#define | DDG3 3 |
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#define | DDG2 2 |
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#define | DDG1 1 |
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#define | DDG0 0 |
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#define | PORTG _SFR_IO8(0x14) |
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#define | PG5 5 |
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#define | PG4 4 |
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#define | PG3 3 |
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#define | PG2 2 |
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#define | PG1 1 |
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#define | PG0 0 |
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#define | TIFR0 _SFR_IO8(0x15) |
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#define | OCF0B 2 |
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#define | OCF0A 1 |
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#define | TOV0 0 |
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#define | TIFR1 _SFR_IO8(0x16) |
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#define | ICF1 5 |
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#define | OCF1C 3 |
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#define | OCF1B 2 |
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#define | OCF1A 1 |
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#define | TOV1 0 |
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#define | TIFR2 _SFR_IO8(0x17) |
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#define | OCF2B 2 |
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#define | OCF2A 1 |
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#define | TOV2 0 |
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#define | TIFR3 _SFR_IO8(0x18) |
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#define | ICF3 5 |
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#define | OCF3C 3 |
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#define | OCF3B 2 |
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#define | OCF3A 1 |
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#define | TOV3 0 |
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#define | TIFR4 _SFR_IO8(0x19) |
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#define | ICF4 5 |
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#define | OCF4C 3 |
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#define | OCF4B 2 |
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#define | OCF4A 1 |
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#define | TOV4 0 |
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#define | TIFR5 _SFR_IO8(0x1A) |
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#define | ICF5 5 |
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#define | OCF5C 3 |
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#define | OCF5B 2 |
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#define | OCF5A 1 |
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#define | TOV5 0 |
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#define | PCIFR _SFR_IO8(0x1B) |
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#define | PCIF1 1 |
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#define | PCIF0 0 |
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#define | EIFR _SFR_IO8(0x1C) |
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#define | INTF7 7 |
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#define | INTF6 6 |
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#define | INTF5 5 |
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#define | INTF4 4 |
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#define | INTF3 3 |
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#define | INTF2 2 |
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#define | INTF1 1 |
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#define | INTF0 0 |
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#define | EIMSK _SFR_IO8(0x1D) |
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#define | INT7 7 |
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#define | INT6 6 |
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#define | INT5 5 |
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#define | INT4 4 |
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#define | INT3 3 |
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#define | INT2 2 |
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#define | INT1 1 |
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#define | INT0 0 |
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#define | GPIOR0 _SFR_IO8(0x1E) |
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#define | EECR _SFR_IO8(0x1F) |
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#define | EEPM1 5 |
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#define | EEPM0 4 |
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#define | EERIE 3 |
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#define | EEMPE 2 |
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#define | EEPE 1 |
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#define | EERE 0 |
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#define | EEDR _SFR_IO8(0X20) |
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#define | EEAR _SFR_IO16(0x21) |
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#define | EEARL _SFR_IO8(0x21) |
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#define | EEARH _SFR_IO8(0X22) |
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#define | __EEPROM_REG_LOCATIONS__ 1F2021 |
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#define | GTCCR _SFR_IO8(0x23) |
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#define | TSM 7 |
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#define | PSRASY 1 |
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#define | PSRSYNC 0 |
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#define | TCCR0A _SFR_IO8(0x24) |
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#define | COM0A1 7 |
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#define | COM0A0 6 |
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#define | COM0B1 5 |
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#define | COM0B0 4 |
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#define | WGM01 1 |
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#define | WGM00 0 |
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#define | TCCR0B _SFR_IO8(0x25) |
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#define | FOC0A 7 |
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#define | FOC0B 6 |
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#define | WGM02 3 |
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#define | CS02 2 |
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#define | CS01 1 |
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#define | CS00 0 |
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#define | TCNT0 _SFR_IO8(0X26) |
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#define | OCR0A _SFR_IO8(0X27) |
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#define | OCR0B _SFR_IO8(0X28) |
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#define | GPIOR1 _SFR_IO8(0x2A) |
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#define | GPIOR2 _SFR_IO8(0x2B) |
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#define | SPCR _SFR_IO8(0x2C) |
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#define | SPIE 7 |
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#define | SPE 6 |
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#define | DORD 5 |
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#define | MSTR 4 |
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#define | CPOL 3 |
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#define | CPHA 2 |
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#define | SPR1 1 |
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#define | SPR0 0 |
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#define | SPSR _SFR_IO8(0x2D) |
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#define | SPIF 7 |
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#define | WCOL 6 |
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#define | SPI2X 0 |
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#define | SPDR _SFR_IO8(0X2E) |
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#define | ACSR _SFR_IO8(0x30) |
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#define | ACD 7 |
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#define | ACBG 6 |
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#define | ACO 5 |
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#define | ACI 4 |
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#define | ACIE 3 |
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#define | ACIC 2 |
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#define | ACIS1 1 |
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#define | ACIS0 0 |
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#define | MONDR _SFR_IO8(0x31) |
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#define | OCDR _SFR_IO8(0x31) |
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#define | IDRD 7 |
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#define | OCDR7 7 |
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#define | OCDR6 6 |
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#define | OCDR5 5 |
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#define | OCDR4 4 |
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#define | OCDR3 3 |
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#define | OCDR2 2 |
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#define | OCDR1 1 |
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#define | OCDR0 0 |
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#define | SMCR _SFR_IO8(0x33) |
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#define | SM2 3 |
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#define | SM1 2 |
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#define | SM0 1 |
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#define | SE 0 |
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#define | MCUSR _SFR_IO8(0x34) |
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#define | JTRF 4 |
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#define | WDRF 3 |
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#define | BORF 2 |
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#define | EXTRF 1 |
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#define | PORF 0 |
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#define | MCUCR _SFR_IO8(0X35) |
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#define | JTD 7 |
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#define | PUD 4 |
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#define | IVSEL 1 |
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#define | IVCE 0 |
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#define | SPMCSR _SFR_IO8(0x37) |
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#define | SPMIE 7 |
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#define | RWWSB 6 |
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#define | SIGRD 5 |
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#define | RWWSRE 4 |
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#define | BLBSET 3 |
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#define | PGWRT 2 |
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#define | PGERS 1 |
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#define | SPMEN 0 |
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#define | RAMPZ _SFR_IO8(0X3B) |
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#define | RAMPZ0 0 |
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#define | EIND _SFR_IO8(0X3C) |
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#define | EIND0 0 |
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#define | WDTCSR _SFR_MEM8(0x60) |
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#define | WDIF 7 |
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#define | WDIE 6 |
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#define | WDP3 5 |
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#define | WDCE 4 |
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#define | WDE 3 |
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#define | WDP2 2 |
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#define | WDP1 1 |
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#define | WDP0 0 |
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#define | CLKPR _SFR_MEM8(0x61) |
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#define | CLKPCE 7 |
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#define | CLKPS3 3 |
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#define | CLKPS2 2 |
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#define | CLKPS1 1 |
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#define | CLKPS0 0 |
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#define | PRR0 _SFR_MEM8(0x64) |
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#define | PRTWI 7 |
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#define | PRTIM2 6 |
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#define | PRTIM0 5 |
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#define | PRTIM1 3 |
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#define | PRSPI 2 |
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#define | PRUSART0 1 |
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#define | PRADC 0 |
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#define | PRR1 _SFR_MEM8(0x65) |
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#define | PRTIM5 5 |
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#define | PRTIM4 4 |
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#define | PRTIM3 3 |
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#define | PRUSART3 2 |
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#define | PRUSART2 1 |
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#define | PRUSART1 0 |
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#define | OSCCAL _SFR_MEM8(0x66) |
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#define | PCICR _SFR_MEM8(0x68) |
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#define | PCIE1 1 |
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#define | PCIE0 0 |
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#define | EICRA _SFR_MEM8(0x69) |
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#define | ISC31 7 |
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#define | ISC30 6 |
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#define | ISC21 5 |
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#define | ISC20 4 |
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#define | ISC11 3 |
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#define | ISC10 2 |
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#define | ISC01 1 |
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#define | ISC00 0 |
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#define | EICRB _SFR_MEM8(0x6A) |
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#define | ISC71 7 |
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#define | ISC70 6 |
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#define | ISC61 5 |
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#define | ISC60 4 |
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#define | ISC51 3 |
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#define | ISC50 2 |
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#define | ISC41 1 |
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#define | ISC40 0 |
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#define | PCMSK0 _SFR_MEM8(0x6B) |
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#define | PCINT7 7 |
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#define | PCINT6 6 |
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#define | PCINT5 5 |
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#define | PCINT4 4 |
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#define | PCINT3 3 |
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#define | PCINT2 2 |
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#define | PCINT1 1 |
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#define | PCINT0 0 |
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#define | PCMSK1 _SFR_MEM8(0x6C) |
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#define | PCINT15 7 |
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#define | PCINT14 6 |
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#define | PCINT13 5 |
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#define | PCINT12 4 |
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#define | PCINT11 3 |
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#define | PCINT10 2 |
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#define | PCINT9 1 |
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#define | PCINT8 0 |
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#define | TIMSK0 _SFR_MEM8(0x6E) |
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#define | OCIE0B 2 |
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#define | OCIE0A 1 |
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#define | TOIE0 0 |
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#define | TIMSK1 _SFR_MEM8(0x6F) |
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#define | ICIE1 5 |
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#define | OCIE1C 3 |
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#define | OCIE1B 2 |
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#define | OCIE1A 1 |
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#define | TOIE1 0 |
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#define | TIMSK2 _SFR_MEM8(0x70) |
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#define | OCIE2B 2 |
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#define | OCIE2A 1 |
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#define | TOIE2 0 |
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#define | TIMSK3 _SFR_MEM8(0x71) |
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#define | ICIE3 5 |
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#define | OCIE3C 3 |
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#define | OCIE3B 2 |
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#define | OCIE3A 1 |
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#define | TOIE3 0 |
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#define | TIMSK4 _SFR_MEM8(0x72) |
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#define | ICIE4 5 |
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#define | OCIE4C 3 |
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#define | OCIE4B 2 |
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#define | OCIE4A 1 |
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#define | TOIE4 0 |
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#define | TIMSK5 _SFR_MEM8(0x73) |
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#define | ICIE5 5 |
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#define | OCIE5C 3 |
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#define | OCIE5B 2 |
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#define | OCIE5A 1 |
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#define | TOIE5 0 |
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#define | XMCRA _SFR_MEM8(0x74) |
| |
|
#define | SRE 7 |
| |
|
#define | SRL2 6 |
| |
|
#define | SRL1 5 |
| |
|
#define | SRL0 4 |
| |
|
#define | SRW11 3 |
| |
|
#define | SRW10 2 |
| |
|
#define | SRW01 1 |
| |
|
#define | SRW00 0 |
| |
|
#define | XMCRB _SFR_MEM8(0x75) |
| |
|
#define | XMBK 7 |
| |
|
#define | XMM2 2 |
| |
|
#define | XMM1 1 |
| |
|
#define | XMM0 0 |
| |
|
#define | ADC _SFR_MEM16(0x78) |
| |
|
#define | ADCW _SFR_MEM16(0x78) |
| |
|
#define | ADCL _SFR_MEM8(0x78) |
| |
|
#define | ADCH _SFR_MEM8(0x79) |
| |
|
#define | ADCSRA _SFR_MEM8(0x7A) |
| |
|
#define | ADEN 7 |
| |
|
#define | ADSC 6 |
| |
|
#define | ADATE 5 |
| |
|
#define | ADIF 4 |
| |
|
#define | ADIE 3 |
| |
|
#define | ADPS2 2 |
| |
|
#define | ADPS1 1 |
| |
|
#define | ADPS0 0 |
| |
|
#define | ADCSRB _SFR_MEM8(0x7B) |
| |
|
#define | ACME 6 |
| |
|
#define | ADTS2 2 |
| |
|
#define | ADTS1 1 |
| |
|
#define | ADTS0 0 |
| |
|
#define | ADMUX _SFR_MEM8(0x7C) |
| |
|
#define | REFS1 7 |
| |
|
#define | REFS0 6 |
| |
|
#define | ADLAR 5 |
| |
|
#define | MUX4 4 |
| |
|
#define | MUX3 3 |
| |
|
#define | MUX2 2 |
| |
|
#define | MUX1 1 |
| |
|
#define | MUX0 0 |
| |
|
#define | DIDR2 _SFR_MEM8(0x7D) |
| |
|
#define | ADC15D 7 |
| |
|
#define | ADC14D 6 |
| |
|
#define | ADC13D 5 |
| |
|
#define | ADC12D 4 |
| |
|
#define | ADC11D 3 |
| |
|
#define | ADC10D 2 |
| |
|
#define | ADC9D 1 |
| |
|
#define | ADC8D 0 |
| |
|
#define | DIDR0 _SFR_MEM8(0x7E) |
| |
|
#define | ADC7D 7 |
| |
|
#define | ADC6D 6 |
| |
|
#define | ADC5D 5 |
| |
|
#define | ADC4D 4 |
| |
|
#define | ADC3D 3 |
| |
|
#define | ADC2D 2 |
| |
|
#define | ADC1D 1 |
| |
|
#define | ADC0D 0 |
| |
|
#define | DIDR1 _SFR_MEM8(0x7F) |
| |
|
#define | AIN1D 1 |
| |
|
#define | AIN0D 0 |
| |
|
#define | TCCR1A _SFR_MEM8(0x80) |
| |
|
#define | COM1A1 7 |
| |
|
#define | COM1A0 6 |
| |
|
#define | COM1B1 5 |
| |
|
#define | COM1B0 4 |
| |
|
#define | COM1C1 3 |
| |
|
#define | COM1C0 2 |
| |
|
#define | WGM11 1 |
| |
|
#define | WGM10 0 |
| |
|
#define | TCCR1B _SFR_MEM8(0x81) |
| |
|
#define | ICNC1 7 |
| |
|
#define | ICES1 6 |
| |
|
#define | WGM13 4 |
| |
|
#define | WGM12 3 |
| |
|
#define | CS12 2 |
| |
|
#define | CS11 1 |
| |
|
#define | CS10 0 |
| |
|
#define | TCCR1C _SFR_MEM8(0x82) |
| |
|
#define | FOC1A 7 |
| |
|
#define | FOC1B 6 |
| |
|
#define | FOC1C 5 |
| |
|
#define | TCNT1 _SFR_MEM16(0x84) |
| |
|
#define | TCNT1L _SFR_MEM8(0x84) |
| |
|
#define | TCNT1H _SFR_MEM8(0x85) |
| |
|
#define | ICR1 _SFR_MEM16(0x86) |
| |
|
#define | ICR1L _SFR_MEM8(0x86) |
| |
|
#define | ICR1H _SFR_MEM8(0x87) |
| |
|
#define | OCR1A _SFR_MEM16(0x88) |
| |
|
#define | OCR1AL _SFR_MEM8(0x88) |
| |
|
#define | OCR1AH _SFR_MEM8(0x89) |
| |
|
#define | OCR1B _SFR_MEM16(0x8A) |
| |
|
#define | OCR1BL _SFR_MEM8(0x8A) |
| |
|
#define | OCR1BH _SFR_MEM8(0x8B) |
| |
|
#define | OCR1C _SFR_MEM16(0x8C) |
| |
|
#define | OCR1CL _SFR_MEM8(0x8C) |
| |
|
#define | OCR1CH _SFR_MEM8(0x8D) |
| |
|
#define | TCCR3A _SFR_MEM8(0x90) |
| |
|
#define | COM3A1 7 |
| |
|
#define | COM3A0 6 |
| |
|
#define | COM3B1 5 |
| |
|
#define | COM3B0 4 |
| |
|
#define | COM3C1 3 |
| |
|
#define | COM3C0 2 |
| |
|
#define | WGM31 1 |
| |
|
#define | WGM30 0 |
| |
|
#define | TCCR3B _SFR_MEM8(0x91) |
| |
|
#define | ICNC3 7 |
| |
|
#define | ICES3 6 |
| |
|
#define | WGM33 4 |
| |
|
#define | WGM32 3 |
| |
|
#define | CS32 2 |
| |
|
#define | CS31 1 |
| |
|
#define | CS30 0 |
| |
|
#define | TCCR3C _SFR_MEM8(0x92) |
| |
|
#define | FOC3A 7 |
| |
|
#define | FOC3B 6 |
| |
|
#define | FOC3C 5 |
| |
|
#define | TCNT3 _SFR_MEM16(0x94) |
| |
|
#define | TCNT3L _SFR_MEM8(0x94) |
| |
|
#define | TCNT3H _SFR_MEM8(0x95) |
| |
|
#define | ICR3 _SFR_MEM16(0x96) |
| |
|
#define | ICR3L _SFR_MEM8(0x96) |
| |
|
#define | ICR3H _SFR_MEM8(0x97) |
| |
|
#define | OCR3A _SFR_MEM16(0x98) |
| |
|
#define | OCR3AL _SFR_MEM8(0x98) |
| |
|
#define | OCR3AH _SFR_MEM8(0x99) |
| |
|
#define | OCR3B _SFR_MEM16(0x9A) |
| |
|
#define | OCR3BL _SFR_MEM8(0x9A) |
| |
|
#define | OCR3BH _SFR_MEM8(0x9B) |
| |
|
#define | OCR3C _SFR_MEM16(0x9C) |
| |
|
#define | OCR3CL _SFR_MEM8(0x9C) |
| |
|
#define | OCR3CH _SFR_MEM8(0x9D) |
| |
|
#define | TCCR4A _SFR_MEM8(0xA0) |
| |
|
#define | COM4A1 7 |
| |
|
#define | COM4A0 6 |
| |
|
#define | COM4B1 5 |
| |
|
#define | COM4B0 4 |
| |
|
#define | COM4C1 3 |
| |
|
#define | COM4C0 2 |
| |
|
#define | WGM41 1 |
| |
|
#define | WGM40 0 |
| |
|
#define | TCCR4B _SFR_MEM8(0xA1) |
| |
|
#define | ICNC4 7 |
| |
|
#define | ICES4 6 |
| |
|
#define | WGM43 4 |
| |
|
#define | WGM42 3 |
| |
|
#define | CS42 2 |
| |
|
#define | CS41 1 |
| |
|
#define | CS40 0 |
| |
|
#define | TCCR4C _SFR_MEM8(0xA2) |
| |
|
#define | FOC4A 7 |
| |
|
#define | FOC4B 6 |
| |
|
#define | FOC4C 5 |
| |
|
#define | TCNT4 _SFR_MEM16(0xA4) |
| |
|
#define | TCNT4L _SFR_MEM8(0xA4) |
| |
|
#define | TCNT4H _SFR_MEM8(0xA5) |
| |
|
#define | ICR4 _SFR_MEM16(0xA6) |
| |
|
#define | ICR4L _SFR_MEM8(0xA6) |
| |
|
#define | ICR4H _SFR_MEM8(0xA7) |
| |
|
#define | OCR4A _SFR_MEM16(0xA8) |
| |
|
#define | OCR4AL _SFR_MEM8(0xA8) |
| |
|
#define | OCR4AH _SFR_MEM8(0xA9) |
| |
|
#define | OCR4B _SFR_MEM16(0xAA) |
| |
|
#define | OCR4BL _SFR_MEM8(0xAA) |
| |
|
#define | OCR4BH _SFR_MEM8(0xAB) |
| |
|
#define | OCR4C _SFR_MEM16(0xAC) |
| |
|
#define | OCR4CL _SFR_MEM8(0xAC) |
| |
|
#define | OCR4CH _SFR_MEM8(0xAD) |
| |
|
#define | TCCR2A _SFR_MEM8(0xB0) |
| |
|
#define | COM2A1 7 |
| |
|
#define | COM2A0 6 |
| |
|
#define | COM2B1 5 |
| |
|
#define | COM2B0 4 |
| |
|
#define | WGM21 1 |
| |
|
#define | WGM20 0 |
| |
|
#define | TCCR2B _SFR_MEM8(0xB1) |
| |
|
#define | FOC2A 7 |
| |
|
#define | FOC2B 6 |
| |
|
#define | WGM22 3 |
| |
|
#define | CS22 2 |
| |
|
#define | CS21 1 |
| |
|
#define | CS20 0 |
| |
|
#define | TCNT2 _SFR_MEM8(0xB2) |
| |
|
#define | OCR2A _SFR_MEM8(0xB3) |
| |
|
#define | OCR2B _SFR_MEM8(0xB4) |
| |
|
#define | ASSR _SFR_MEM8(0xB6) |
| |
|
#define | EXCLK 6 |
| |
|
#define | AS2 5 |
| |
|
#define | TCN2UB 4 |
| |
|
#define | OCR2AUB 3 |
| |
|
#define | OCR2BUB 2 |
| |
|
#define | TCR2AUB 1 |
| |
|
#define | TCR2BUB 0 |
| |
|
#define | TWBR _SFR_MEM8(0xB8) |
| |
|
#define | TWSR _SFR_MEM8(0xB9) |
| |
|
#define | TWS7 7 |
| |
|
#define | TWS6 6 |
| |
|
#define | TWS5 5 |
| |
|
#define | TWS4 4 |
| |
|
#define | TWS3 3 |
| |
|
#define | TWPS1 1 |
| |
|
#define | TWPS0 0 |
| |
|
#define | TWAR _SFR_MEM8(0xBA) |
| |
|
#define | TWA6 7 |
| |
|
#define | TWA5 6 |
| |
|
#define | TWA4 5 |
| |
|
#define | TWA3 4 |
| |
|
#define | TWA2 3 |
| |
|
#define | TWA1 2 |
| |
|
#define | TWA0 1 |
| |
|
#define | TWGCE 0 |
| |
|
#define | TWDR _SFR_MEM8(0xBB) |
| |
|
#define | TWCR _SFR_MEM8(0xBC) |
| |
|
#define | TWINT 7 |
| |
|
#define | TWEA 6 |
| |
|
#define | TWSTA 5 |
| |
|
#define | TWSTO 4 |
| |
|
#define | TWWC 3 |
| |
|
#define | TWEN 2 |
| |
|
#define | TWIE 0 |
| |
|
#define | TWAMR _SFR_MEM8(0xBD) |
| |
|
#define | TWAM6 7 |
| |
|
#define | TWAM5 6 |
| |
|
#define | TWAM4 5 |
| |
|
#define | TWAM3 4 |
| |
|
#define | TWAM2 3 |
| |
|
#define | TWAM1 2 |
| |
|
#define | TWAM0 1 |
| |
|
#define | UCSR0A _SFR_MEM8(0xC0) |
| |
|
#define | RXC0 7 |
| |
|
#define | TXC0 6 |
| |
|
#define | UDRE0 5 |
| |
|
#define | FE0 4 |
| |
|
#define | DOR0 3 |
| |
|
#define | UPE0 2 |
| |
|
#define | U2X0 1 |
| |
|
#define | MPCM0 0 |
| |
|
#define | UCSR0B _SFR_MEM8(0XC1) |
| |
|
#define | RXCIE0 7 |
| |
|
#define | TXCIE0 6 |
| |
|
#define | UDRIE0 5 |
| |
|
#define | RXEN0 4 |
| |
|
#define | TXEN0 3 |
| |
|
#define | UCSZ02 2 |
| |
|
#define | RXB80 1 |
| |
|
#define | TXB80 0 |
| |
|
#define | UCSR0C _SFR_MEM8(0xC2) |
| |
|
#define | UMSEL01 7 |
| |
|
#define | UMSEL00 6 |
| |
|
#define | UPM01 5 |
| |
|
#define | UPM00 4 |
| |
|
#define | USBS0 3 |
| |
|
#define | UCSZ01 2 |
| |
|
#define | UCSZ00 1 |
| |
|
#define | UCPOL0 0 |
| |
|
#define | UBRR0 _SFR_MEM16(0xC4) |
| |
|
#define | UBRR0L _SFR_MEM8(0xC4) |
| |
|
#define | UBRR0H _SFR_MEM8(0xC5) |
| |
|
#define | UDR0 _SFR_MEM8(0XC6) |
| |
|
#define | UCSR1A _SFR_MEM8(0xC8) |
| |
|
#define | RXC1 7 |
| |
|
#define | TXC1 6 |
| |
|
#define | UDRE1 5 |
| |
|
#define | FE1 4 |
| |
|
#define | DOR1 3 |
| |
|
#define | UPE1 2 |
| |
|
#define | U2X1 1 |
| |
|
#define | MPCM1 0 |
| |
|
#define | UCSR1B _SFR_MEM8(0XC9) |
| |
|
#define | RXCIE1 7 |
| |
|
#define | TXCIE1 6 |
| |
|
#define | UDRIE1 5 |
| |
|
#define | RXEN1 4 |
| |
|
#define | TXEN1 3 |
| |
|
#define | UCSZ12 2 |
| |
|
#define | RXB81 1 |
| |
|
#define | TXB81 0 |
| |
|
#define | UCSR1C _SFR_MEM8(0xCA) |
| |
|
#define | UMSEL11 7 |
| |
|
#define | UMSEL10 6 |
| |
|
#define | UPM11 5 |
| |
|
#define | UPM10 4 |
| |
|
#define | USBS1 3 |
| |
|
#define | UCSZ11 2 |
| |
|
#define | UCSZ10 1 |
| |
|
#define | UCPOL1 0 |
| |
|
#define | UBRR1 _SFR_MEM16(0xCC) |
| |
|
#define | UBRR1L _SFR_MEM8(0xCC) |
| |
|
#define | UBRR1H _SFR_MEM8(0xCD) |
| |
|
#define | UDR1 _SFR_MEM8(0XCE) |
| |
|
#define | TCCR5A _SFR_MEM8(0x120) |
| |
|
#define | COM5A1 7 |
| |
|
#define | COM5A0 6 |
| |
|
#define | COM5B1 5 |
| |
|
#define | COM5B0 4 |
| |
|
#define | COM5C1 3 |
| |
|
#define | COM5C0 2 |
| |
|
#define | WGM51 1 |
| |
|
#define | WGM50 0 |
| |
|
#define | TCCR5B _SFR_MEM8(0x121) |
| |
|
#define | ICNC5 7 |
| |
|
#define | ICES5 6 |
| |
|
#define | WGM53 4 |
| |
|
#define | WGM52 3 |
| |
|
#define | CS52 2 |
| |
|
#define | CS51 1 |
| |
|
#define | CS50 0 |
| |
|
#define | TCCR5C _SFR_MEM8(0x122) |
| |
|
#define | FOC5A 7 |
| |
|
#define | FOC5B 6 |
| |
|
#define | FOC5C 5 |
| |
|
#define | TCNT5 _SFR_MEM16(0x124) |
| |
|
#define | TCNT5L _SFR_MEM8(0x124) |
| |
|
#define | TCNT5H _SFR_MEM8(0x125) |
| |
|
#define | ICR5 _SFR_MEM16(0x126) |
| |
|
#define | ICR5L _SFR_MEM8(0x126) |
| |
|
#define | ICR5H _SFR_MEM8(0x127) |
| |
|
#define | OCR5A _SFR_MEM16(0x128) |
| |
|
#define | OCR5AL _SFR_MEM8(0x128) |
| |
|
#define | OCR5AH _SFR_MEM8(0x129) |
| |
|
#define | OCR5B _SFR_MEM16(0x12A) |
| |
|
#define | OCR5BL _SFR_MEM8(0x12A) |
| |
|
#define | OCR5BH _SFR_MEM8(0x12B) |
| |
|
#define | OCR5C _SFR_MEM16(0x12C) |
| |
|
#define | OCR5CL _SFR_MEM8(0x12C) |
| |
|
#define | OCR5CH _SFR_MEM8(0x12D) |
| |
|
#define | INT0_vect _VECTOR(1) |
| |
|
#define | SIG_INTERRUPT0 _VECTOR(1) |
| |
|
#define | INT1_vect _VECTOR(2) |
| |
|
#define | SIG_INTERRUPT1 _VECTOR(2) |
| |
|
#define | INT2_vect _VECTOR(3) |
| |
|
#define | SIG_INTERRUPT2 _VECTOR(3) |
| |
|
#define | INT3_vect _VECTOR(4) |
| |
|
#define | SIG_INTERRUPT3 _VECTOR(4) |
| |
|
#define | INT4_vect _VECTOR(5) |
| |
|
#define | SIG_INTERRUPT4 _VECTOR(5) |
| |
|
#define | INT5_vect _VECTOR(6) |
| |
|
#define | SIG_INTERRUPT5 _VECTOR(6) |
| |
|
#define | INT6_vect _VECTOR(7) |
| |
|
#define | SIG_INTERRUPT6 _VECTOR(7) |
| |
|
#define | INT7_vect _VECTOR(8) |
| |
|
#define | SIG_INTERRUPT7 _VECTOR(8) |
| |
|
#define | PCINT0_vect _VECTOR(9) |
| |
|
#define | SIG_PIN_CHANGE0 _VECTOR(9) |
| |
|
#define | PCINT1_vect _VECTOR(10) |
| |
|
#define | SIG_PIN_CHANGE1 _VECTOR(10) |
| |
|
#define | WDT_vect _VECTOR(12) |
| |
|
#define | SIG_WATCHDOG_TIMEOUT _VECTOR(12) |
| |
|
#define | TIMER2_COMPA_vect _VECTOR(13) |
| |
|
#define | SIG_OUTPUT_COMPARE2A _VECTOR(13) |
| |
|
#define | TIMER2_COMPB_vect _VECTOR(14) |
| |
|
#define | SIG_OUTPUT_COMPARE2B _VECTOR(14) |
| |
|
#define | TIMER2_OVF_vect _VECTOR(15) |
| |
|
#define | SIG_OVERFLOW2 _VECTOR(15) |
| |
|
#define | TIMER1_CAPT_vect _VECTOR(16) |
| |
|
#define | SIG_INPUT_CAPTURE1 _VECTOR(16) |
| |
|
#define | TIMER1_COMPA_vect _VECTOR(17) |
| |
|
#define | SIG_OUTPUT_COMPARE1A _VECTOR(17) |
| |
|
#define | TIMER1_COMPB_vect _VECTOR(18) |
| |
|
#define | SIG_OUTPUT_COMPARE1B _VECTOR(18) |
| |
|
#define | TIMER1_COMPC_vect _VECTOR(19) |
| |
|
#define | SIG_OUTPUT_COMPARE1C _VECTOR(19) |
| |
|
#define | TIMER1_OVF_vect _VECTOR(20) |
| |
|
#define | SIG_OVERFLOW1 _VECTOR(20) |
| |
|
#define | TIMER0_COMPA_vect _VECTOR(21) |
| |
|
#define | SIG_OUTPUT_COMPARE0A _VECTOR(21) |
| |
|
#define | TIMER0_COMPB_vect _VECTOR(22) |
| |
|
#define | SIG_OUTPUT_COMPARE0B _VECTOR(22) |
| |
|
#define | TIMER0_OVF_vect _VECTOR(23) |
| |
|
#define | SIG_OVERFLOW0 _VECTOR(23) |
| |
|
#define | SPI_STC_vect _VECTOR(24) |
| |
|
#define | SIG_SPI _VECTOR(24) |
| |
|
#define | USART0_RX_vect _VECTOR(25) |
| |
|
#define | SIG_USART0_RECV _VECTOR(25) |
| |
|
#define | USART0_UDRE_vect _VECTOR(26) |
| |
|
#define | SIG_USART0_DATA _VECTOR(26) |
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#define | USART0_TX_vect _VECTOR(27) |
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#define | SIG_USART0_TRANS _VECTOR(27) |
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#define | ANALOG_COMP_vect _VECTOR(28) |
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#define | SIG_COMPARATOR _VECTOR(28) |
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#define | ADC_vect _VECTOR(29) |
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#define | SIG_ADC _VECTOR(29) |
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#define | EE_READY_vect _VECTOR(30) |
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#define | SIG_EEPROM_READY _VECTOR(30) |
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#define | TIMER3_CAPT_vect _VECTOR(31) |
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#define | SIG_INPUT_CAPTURE3 _VECTOR(31) |
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#define | TIMER3_COMPA_vect _VECTOR(32) |
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#define | SIG_OUTPUT_COMPARE3A _VECTOR(32) |
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#define | TIMER3_COMPB_vect _VECTOR(33) |
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#define | SIG_OUTPUT_COMPARE3B _VECTOR(33) |
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#define | TIMER3_COMPC_vect _VECTOR(34) |
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#define | SIG_OUTPUT_COMPARE3C _VECTOR(34) |
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#define | TIMER3_OVF_vect _VECTOR(35) |
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#define | SIG_OVERFLOW3 _VECTOR(35) |
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#define | USART1_RX_vect _VECTOR(36) |
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#define | SIG_USART1_RECV _VECTOR(36) |
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#define | USART1_UDRE_vect _VECTOR(37) |
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#define | SIG_USART1_DATA _VECTOR(37) |
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#define | USART1_TX_vect _VECTOR(38) |
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#define | SIG_USART1_TRANS _VECTOR(38) |
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#define | TWI_vect _VECTOR(39) |
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#define | SIG_2WIRE_SERIAL _VECTOR(39) |
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#define | SPM_READY_vect _VECTOR(40) |
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#define | SIG_SPM_READY _VECTOR(40) |
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#define | TIMER4_COMPA_vect _VECTOR(42) |
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#define | SIG_OUTPUT_COMPARE4A _VECTOR(42) |
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#define | TIMER4_COMPB_vect _VECTOR(43) |
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#define | SIG_OUTPUT_COMPARE4B _VECTOR(43) |
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#define | TIMER4_COMPC_vect _VECTOR(44) |
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#define | SIG_OUTPUT_COMPARE4C _VECTOR(44) |
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#define | TIMER4_OVF_vect _VECTOR(45) |
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#define | SIG_OVERFLOW4 _VECTOR(45) |
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#define | TIMER5_COMPA_vect _VECTOR(47) |
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#define | SIG_OUTPUT_COMPARE5A _VECTOR(47) |
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#define | TIMER5_COMPB_vect _VECTOR(48) |
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#define | SIG_OUTPUT_COMPARE5B _VECTOR(48) |
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#define | TIMER5_COMPC_vect _VECTOR(49) |
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#define | SIG_OUTPUT_COMPARE5C _VECTOR(49) |
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#define | TIMER5_OVF_vect _VECTOR(50) |
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#define | SIG_OVERFLOW5 _VECTOR(50) |
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#define | USART2_RX_vect _VECTOR(51) |
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#define | SIG_USART2_RECV _VECTOR(51) |
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#define | USART2_UDRE_vect _VECTOR(52) |
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#define | SIG_USART2_DATA _VECTOR(52) |
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#define | USART2_TX_vect _VECTOR(53) |
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#define | SIG_USART2_TRANS _VECTOR(53) |
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#define | USART3_RX_vect _VECTOR(54) |
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#define | SIG_USART3_RECV _VECTOR(54) |
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#define | USART3_UDRE_vect _VECTOR(55) |
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#define | SIG_USART3_DATA _VECTOR(55) |
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#define | USART3_TX_vect _VECTOR(56) |
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#define | SIG_USART3_TRANS _VECTOR(56) |
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#define | _VECTORS_SIZE 228 |
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