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#define | _AVR_IOXXX_H_ "iom162.h" |
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#define | TCCR3A _SFR_MEM8(0x8B) |
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#define | TCCR3B _SFR_MEM8(0x8A) |
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#define | TCNT3H _SFR_MEM8(0x89) |
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#define | TCNT3L _SFR_MEM8(0x88) |
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#define | TCNT3 _SFR_MEM16(0x88) |
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#define | OCR3AH _SFR_MEM8(0x87) |
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#define | OCR3AL _SFR_MEM8(0x86) |
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#define | OCR3A _SFR_MEM16(0x86) |
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#define | OCR3BH _SFR_MEM8(0x85) |
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#define | OCR3BL _SFR_MEM8(0x84) |
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#define | OCR3B _SFR_MEM16(0x84) |
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#define | ICR3H _SFR_MEM8(0x81) |
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#define | ICR3L _SFR_MEM8(0x80) |
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#define | ICR3 _SFR_MEM16(0x80) |
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#define | ETIMSK _SFR_MEM8(0x7D) |
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#define | ETIFR _SFR_MEM8(0x7C) |
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#define | PCMSK1 _SFR_MEM8(0x6C) |
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#define | PCMSK0 _SFR_MEM8(0x6B) |
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#define | CLKPR _SFR_MEM8(0x61) |
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#define | UBRR1H _SFR_IO8(0x3C) /* USART 1 Baud Rate Register High Byte, Shared with UCSR1C */ |
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#define | UCSR1C _SFR_IO8(0x3C) /* USART 1 Control and Status Register, Shared with UBRR1H */ |
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#define | GICR _SFR_IO8(0x3B) /* General Interrupt Control Register */ |
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#define | GIFR _SFR_IO8(0x3A) /* General Interrupt Flag Register */ |
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#define | TIMSK _SFR_IO8(0x39) /* Timer Interrupt Mask */ |
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#define | TIFR _SFR_IO8(0x38) /* Timer Interrupt Flag Register */ |
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#define | SPMCR _SFR_IO8(0x37) /* Store Program Memory Control Register */ |
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#define | EMCUCR _SFR_IO8(0x36) /* Extended MCU Control Register */ |
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#define | MCUCR _SFR_IO8(0x35) /* MCU Control Register */ |
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#define | MCUCSR _SFR_IO8(0x34) /* MCU Control and Status Register */ |
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#define | TCCR0 _SFR_IO8(0x33) /* Timer/Counter 0 Control Register */ |
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#define | TCNT0 _SFR_IO8(0x32) /* TImer/Counter 0 */ |
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#define | OCR0 _SFR_IO8(0x31) /* Output Compare Register 0 */ |
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#define | SFIOR _SFR_IO8(0x30) /* Special Function I/O Register */ |
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#define | TCCR1A _SFR_IO8(0x2F) /* Timer/Counter 1 Control Register A */ |
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#define | TCCR1B _SFR_IO8(0x2E) /* Timer/Counter 1 Control Register A */ |
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#define | TCNT1H _SFR_IO8(0x2D) /* Timer/Counter 1 High Byte */ |
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#define | TCNT1L _SFR_IO8(0x2C) /* Timer/Counter 1 Low Byte */ |
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#define | TCNT1 _SFR_IO16(0x2C) /* Timer/Counter 1 */ |
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#define | OCR1AH _SFR_IO8(0x2B) /* Timer/Counter 1 Output Compare Register A High Byte */ |
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#define | OCR1AL _SFR_IO8(0x2A) /* Timer/Counter 1 Output Compare Register A Low Byte */ |
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#define | OCR1A _SFR_IO16(0x2A) /* Timer/Counter 1 Output Compare Register A */ |
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#define | OCR1BH _SFR_IO8(0x29) /* Timer/Counter 1 Output Compare Register B High Byte */ |
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#define | OCR1BL _SFR_IO8(0x28) /* Timer/Counter 1 Output Compare Register B Low Byte */ |
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#define | OCR1B _SFR_IO16(0x28) /* Timer/Counter 1 Output Compare Register B */ |
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#define | TCCR2 _SFR_IO8(0x27) /* Timer/Counter 2 Control Register */ |
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#define | ASSR _SFR_IO8(0x26) /* Asynchronous Status Register */ |
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#define | ICR1H _SFR_IO8(0x25) /* Input Capture Register 1 High Byte */ |
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#define | ICR1L _SFR_IO8(0x24) /* Input Capture Register 1 Low Byte */ |
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#define | ICR1 _SFR_IO16(0x24) /* Input Capture Register 1 */ |
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#define | TCNT2 _SFR_IO8(0x23) /* Timer/Counter 2 */ |
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#define | OCR2 _SFR_IO8(0x22) /* Timer/Counter 2 Output Compare Register */ |
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#define | WDTCR _SFR_IO8(0x21) /* Watchdow Timer Control Register */ |
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#define | UBRR0H _SFR_IO8(0x20) /* USART 0 Baud-Rate Register High Byte, Shared with UCSR0C */ |
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#define | UCSR0C _SFR_IO8(0x20) /* USART 0 Control and Status Register C, Shared with UBRR0H */ |
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#define | EEARH _SFR_IO8(0x1F) /* EEPROM Address Register High Byte */ |
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#define | EEARL _SFR_IO8(0x1E) /* EEPROM Address Register Low Byte */ |
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#define | EEAR _SFR_IO16(0x1E) /* EEPROM Address Register */ |
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#define | EEDR _SFR_IO8(0x1D) /* EEPROM Data Register */ |
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#define | EECR _SFR_IO8(0x1C) /* EEPROM Control Register */ |
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#define | PORTA _SFR_IO8(0x1B) /* Port A */ |
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#define | DDRA _SFR_IO8(0x1A) /* Port A Data Direction Register */ |
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#define | PINA _SFR_IO8(0x19) /* Port A Pin Register */ |
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#define | PORTB _SFR_IO8(0x18) /* Port B */ |
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#define | DDRB _SFR_IO8(0x17) /* Port B Data Direction Register */ |
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#define | PINB _SFR_IO8(0x16) /* Port B Pin Register */ |
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#define | PORTC _SFR_IO8(0x15) /* Port C */ |
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#define | DDRC _SFR_IO8(0x14) /* Port C Data Direction Register */ |
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#define | PINC _SFR_IO8(0x13) /* Port C Pin Register */ |
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#define | PORTD _SFR_IO8(0x12) /* Port D */ |
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#define | DDRD _SFR_IO8(0x11) /* Port D Data Direction Register */ |
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#define | PIND _SFR_IO8(0x10) /* Port D Pin Register */ |
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#define | SPDR _SFR_IO8(0x0F) /* SPI Data Register */ |
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#define | SPSR _SFR_IO8(0x0E) /* SPI Status Register */ |
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#define | SPCR _SFR_IO8(0x0D) /* SPI Control Register */ |
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#define | UDR0 _SFR_IO8(0x0C) /* USART 0 Data Register */ |
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#define | UCSR0A _SFR_IO8(0x0B) /* USART 0 Control and Status Register A */ |
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#define | UCSR0B _SFR_IO8(0x0A) /* USART 0 Control and Status Register B */ |
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#define | UBRR0L _SFR_IO8(0x09) /* USART 0 Baud-Rate Register Low Byte */ |
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#define | ACSR _SFR_IO8(0x08) /* Analog Comparator Status Register */ |
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#define | PORTE _SFR_IO8(0x07) /* Port E */ |
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#define | DDRE _SFR_IO8(0x06) /* Port E Data Direction Register */ |
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#define | PINE _SFR_IO8(0x05) /* Port E Pin Register */ |
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#define | OSCCAL _SFR_IO8(0x04) /* Oscillator Calibration, Shared with OCDR */ |
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#define | OCDR _SFR_IO8(0x04) /* On-Chip Debug Register, Shared with OSCCAL */ |
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#define | UDR1 _SFR_IO8(0x03) /* USART 1 Data Register */ |
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#define | UCSR1A _SFR_IO8(0x02) /* USART 1 Control and Status Register A */ |
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#define | UCSR1B _SFR_IO8(0x01) /* USART 1 Control and Status Register B */ |
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#define | UBRR1L _SFR_IO8(0x00) /* USART 0 Baud Rate Register High Byte */ |
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#define | INT0_vect _VECTOR(1) |
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#define | SIG_INTERRUPT0 _VECTOR(1) |
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#define | INT1_vect _VECTOR(2) |
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#define | SIG_INTERRUPT1 _VECTOR(2) |
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#define | INT2_vect _VECTOR(3) |
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#define | SIG_INTERRUPT2 _VECTOR(3) |
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#define | PCINT0_vect _VECTOR(4) |
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#define | SIG_PIN_CHANGE0 _VECTOR(4) |
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#define | PCINT1_vect _VECTOR(5) |
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#define | SIG_PIN_CHANGE1 _VECTOR(5) |
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#define | TIMER3_CAPT_vect _VECTOR(6) |
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#define | SIG_INPUT_CAPTURE3 _VECTOR(6) |
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#define | TIMER3_COMPA_vect _VECTOR(7) |
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#define | SIG_OUTPUT_COMPARE3A _VECTOR(7) |
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#define | TIMER3_COMPB_vect _VECTOR(8) |
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#define | SIG_OUTPUT_COMPARE3B _VECTOR(8) |
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#define | TIMER3_OVF_vect _VECTOR(9) |
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#define | SIG_OVERFLOW3 _VECTOR(9) |
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#define | TIMER2_COMP_vect _VECTOR(10) |
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#define | SIG_OUTPUT_COMPARE2 _VECTOR(10) |
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#define | TIMER2_OVF_vect _VECTOR(11) |
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#define | SIG_OVERFLOW2 _VECTOR(11) |
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#define | TIMER1_CAPT_vect _VECTOR(12) |
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#define | SIG_INPUT_CAPTURE1 _VECTOR(12) |
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#define | TIMER1_COMPA_vect _VECTOR(13) |
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#define | SIG_OUTPUT_COMPARE1A _VECTOR(13) |
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#define | TIMER1_COMPB_vect _VECTOR(14) |
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#define | SIG_OUTPUT_COMPARE1B _VECTOR(14) |
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#define | TIMER1_OVF_vect _VECTOR(15) |
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#define | SIG_OVERFLOW1 _VECTOR(15) |
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#define | TIMER0_COMP_vect _VECTOR(16) |
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#define | SIG_OUTPUT_COMPARE0 _VECTOR(16) |
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#define | TIMER0_OVF_vect _VECTOR(17) |
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#define | SIG_OVERFLOW0 _VECTOR(17) |
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#define | SPI_STC_vect _VECTOR(18) |
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#define | SIG_SPI _VECTOR(18) |
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#define | USART0_RXC_vect _VECTOR(19) |
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#define | SIG_USART0_RECV _VECTOR(19) |
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#define | USART1_RXC_vect _VECTOR(20) |
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#define | SIG_USART1_RECV _VECTOR(20) |
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#define | USART0_UDRE_vect _VECTOR(21) |
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#define | SIG_USART0_DATA _VECTOR(21) |
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#define | USART1_UDRE_vect _VECTOR(22) |
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#define | SIG_USART1_DATA _VECTOR(22) |
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#define | USART0_TXC_vect _VECTOR(23) |
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#define | SIG_USART0_TRANS _VECTOR(23) |
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#define | USART1_TXC_vect _VECTOR(24) |
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#define | SIG_USART1_TRANS _VECTOR(24) |
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#define | EE_RDY_vect _VECTOR(25) |
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#define | SIG_EEPROM_READY _VECTOR(25) |
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#define | ANA_COMP_vect _VECTOR(26) |
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#define | SIG_COMPARATOR _VECTOR(26) |
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#define | SPM_RDY_vect _VECTOR(27) |
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#define | SIG_SPM_READY _VECTOR(27) |
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#define | _VECTORS_SIZE 112 /* = (num vec+1) * 4 */ |
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#define | ICNC3 7 |
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#define | ICES3 6 |
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#define | WGM33 4 |
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#define | WGM32 3 |
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#define | CS32 2 |
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#define | CS31 1 |
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#define | CS30 0 |
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#define | COM3A1 7 |
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#define | COM3A0 6 |
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#define | COM3B1 5 |
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#define | COM3B0 4 |
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#define | FOC3A 3 |
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#define | FOC3B 2 |
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#define | WGM31 1 |
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#define | WGM30 0 |
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#define | TICIE3 5 |
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#define | OCIE3A 4 |
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#define | OCIE3B 3 |
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#define | TOIE3 2 |
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#define | ICF3 5 |
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#define | OCF3A 4 |
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#define | OCF3B 3 |
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#define | TOV3 2 |
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#define | PCINT15 7 |
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#define | PCINT14 6 |
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#define | PCINT13 5 |
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#define | PCINT12 4 |
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#define | PCINT11 3 |
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#define | PCINT10 2 |
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#define | PCINT9 1 |
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#define | PCINT8 0 |
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#define | PCINT7 7 |
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#define | PCINT6 6 |
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#define | PCINT5 5 |
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#define | PCINT4 4 |
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#define | PCINT3 3 |
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#define | PCINT2 2 |
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#define | PCINT1 1 |
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#define | PCINT0 0 |
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#define | CLKPCE 7 |
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#define | CLKPS3 3 |
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#define | CLKPS2 2 |
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#define | CLKPS1 1 |
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#define | CLKPS0 0 |
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#define | SP15 15 |
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#define | SP14 14 |
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#define | SP13 13 |
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#define | SP12 12 |
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#define | SP11 11 |
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#define | SP10 10 |
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#define | SP9 9 |
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#define | SP8 8 |
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#define | SP7 7 |
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#define | SP6 6 |
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#define | SP5 5 |
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#define | SP4 4 |
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#define | SP3 3 |
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#define | SP2 2 |
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#define | SP1 1 |
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#define | SP0 0 |
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#define | URSEL1 7 |
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#define | URSEL1 7 |
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#define | UBRR111 3 |
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#define | UBRR110 2 |
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#define | UBRR19 1 |
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#define | UBRR18 0 |
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#define | UMSEL1 6 |
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#define | UPM11 5 |
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#define | UPM10 4 |
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#define | USBS1 3 |
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#define | UCSZ11 2 |
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#define | UCSZ10 1 |
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#define | UCPOL1 0 |
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#define | INT1 7 |
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#define | INT0 6 |
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#define | INT2 5 |
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#define | PCIE1 4 |
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#define | PCIE0 3 |
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#define | IVSEL 1 |
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#define | IVCE 0 |
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#define | INTF1 7 |
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#define | INTF0 6 |
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#define | INTF2 5 |
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#define | PCIF1 4 |
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#define | PCIF0 3 |
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#define | TOIE1 7 |
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#define | OCIE1A 6 |
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#define | OCIE1B 5 |
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#define | OCIE2 4 |
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#define | TICIE1 3 |
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#define | TOIE2 2 |
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#define | TOIE0 1 |
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#define | OCIE0 0 |
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#define | TOV1 7 |
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#define | OCF1A 6 |
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#define | OCF1B 5 |
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#define | OCF2 4 |
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#define | ICF1 3 |
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#define | TOV2 2 |
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#define | TOV0 1 |
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#define | OCF0 0 |
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#define | SPMIE 7 |
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#define | RWWSB 6 |
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#define | RWWSRE 4 |
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#define | BLBSET 3 |
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#define | PGWRT 2 |
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#define | PGERS 1 |
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#define | SPMEN 0 |
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#define | SM0 7 |
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#define | SRL2 6 |
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#define | SRL1 5 |
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#define | SRL0 4 |
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#define | SRW01 3 |
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#define | SRW00 2 |
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#define | SRW11 1 |
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#define | ISC2 0 |
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#define | SRE 7 |
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#define | SRW10 6 |
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#define | SE 5 |
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#define | SM1 4 |
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#define | ISC11 3 |
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#define | ISC10 2 |
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#define | ISC01 1 |
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#define | ISC00 0 |
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#define | JTD 7 |
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#define | SM2 5 |
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#define | JTRF 4 |
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#define | WDRF 3 |
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#define | BORF 2 |
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#define | EXTRF 1 |
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#define | PORF 0 |
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#define | FOC0 7 |
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#define | WGM00 6 |
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#define | COM01 5 |
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#define | COM00 4 |
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#define | WGM01 3 |
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#define | CS02 2 |
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#define | CS01 1 |
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#define | CS00 0 |
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#define | TSM 7 |
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#define | XMBK 6 |
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#define | XMM2 5 |
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#define | XMM1 4 |
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#define | XMM0 3 |
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#define | PUD 2 |
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#define | PSR2 1 |
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#define | PSR310 0 |
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#define | COM1A1 7 |
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#define | COM1A0 6 |
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#define | COM1B1 5 |
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#define | COM1B0 4 |
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#define | FOC1A 3 |
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#define | FOC1B 2 |
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#define | WGM11 1 |
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#define | WGM10 0 |
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#define | ICNC1 7 /* Input Capture Noise Canceler */ |
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#define | ICES1 6 /* Input Capture Edge Select */ |
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#define | WGM13 4 /* Waveform Generation Mode 3 */ |
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#define | WGM12 3 /* Waveform Generation Mode 2 */ |
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#define | CS12 2 /* Clock Select 2 */ |
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#define | CS11 1 /* Clock Select 1 */ |
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#define | CS10 0 /* Clock Select 0 */ |
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#define | FOC2 7 |
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#define | WGM20 6 |
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#define | COM21 5 |
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#define | COM20 4 |
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#define | WGM21 3 |
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#define | CS22 2 |
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#define | CS21 1 |
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#define | CS20 0 |
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#define | AS2 3 |
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#define | TCN2UB 2 |
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#define | TCON2UB 2 /* Kept for backwards compatibility. */ |
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#define | OCR2UB 1 |
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#define | TCR2UB 0 |
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#define | WDCE 4 |
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#define | WDE 3 |
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#define | WDP2 2 |
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#define | WDP1 1 |
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#define | WDP0 0 |
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#define | URSEL0 7 |
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#define | URSEL0 7 |
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#define | UBRR011 3 |
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#define | UBRR010 2 |
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#define | UBRR09 1 |
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#define | UBRR08 0 |
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#define | UMSEL0 6 |
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#define | UPM01 5 |
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#define | UPM00 4 |
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#define | USBS0 3 |
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#define | UCSZ01 2 |
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#define | UCSZ00 1 |
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#define | UCPOL0 0 |
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#define | EEAR8 0 |
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#define | EERIE 3 |
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#define | EEMWE 2 |
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#define | EEWE 1 |
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#define | EERE 0 |
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#define | PA7 7 |
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#define | PA6 6 |
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#define | PA5 5 |
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#define | PA4 4 |
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#define | PA3 3 |
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#define | PA2 2 |
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#define | PA1 1 |
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#define | PA0 0 |
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#define | DDA7 7 |
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#define | DDA6 6 |
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#define | DDA5 5 |
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#define | DDA4 4 |
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#define | DDA3 3 |
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#define | DDA2 2 |
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#define | DDA1 1 |
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#define | DDA0 0 |
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#define | PINA7 7 |
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#define | PINA6 6 |
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#define | PINA5 5 |
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#define | PINA4 4 |
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#define | PINA3 3 |
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#define | PINA2 2 |
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#define | PINA1 1 |
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#define | PINA0 0 |
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#define | PB7 7 |
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#define | PB6 6 |
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#define | PB5 5 |
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#define | PB4 4 |
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#define | PB3 3 |
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#define | PB2 2 |
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#define | PB1 1 |
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#define | PB0 0 |
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#define | DDB7 7 |
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#define | DDB6 6 |
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#define | DDB5 5 |
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#define | DDB4 4 |
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#define | DDB3 3 |
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#define | DDB2 2 |
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#define | DDB1 1 |
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#define | DDB0 0 |
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#define | PINB7 7 |
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#define | PINB6 6 |
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#define | PINB5 5 |
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#define | PINB4 4 |
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#define | PINB3 3 |
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#define | PINB2 2 |
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#define | PINB1 1 |
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#define | PINB0 0 |
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#define | PC7 7 |
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#define | PC6 6 |
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#define | PC5 5 |
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#define | PC4 4 |
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#define | PC3 3 |
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#define | PC2 2 |
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#define | PC1 1 |
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#define | PC0 0 |
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#define | DDC7 7 |
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#define | DDC6 6 |
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#define | DDC5 5 |
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#define | DDC4 4 |
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#define | DDC3 3 |
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#define | DDC2 2 |
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#define | DDC1 1 |
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#define | DDC0 0 |
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#define | PINC7 7 |
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#define | PINC6 6 |
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#define | PINC5 5 |
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#define | PINC4 4 |
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#define | PINC3 3 |
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#define | PINC2 2 |
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#define | PINC1 1 |
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#define | PINC0 0 |
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#define | PD7 7 |
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#define | PD6 6 |
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#define | PD5 5 |
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#define | PD4 4 |
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#define | PD3 3 |
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#define | PD2 2 |
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#define | PD1 1 |
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#define | PD0 0 |
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#define | DDD7 7 |
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#define | DDD6 6 |
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#define | DDD5 5 |
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#define | DDD4 4 |
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#define | DDD3 3 |
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#define | DDD2 2 |
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#define | DDD1 1 |
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#define | DDD0 0 |
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#define | PIND7 7 |
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#define | PIND6 6 |
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#define | PIND5 5 |
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#define | PIND4 4 |
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#define | PIND3 3 |
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#define | PIND2 2 |
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#define | PIND1 1 |
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#define | PIND0 0 |
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#define | SPIF 7 |
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#define | WCOL 6 |
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#define | SPI2X 0 |
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#define | SPIE 7 |
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#define | SPE 6 |
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#define | DORD 5 |
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#define | MSTR 4 |
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#define | CPOL 3 |
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#define | CPHA 2 |
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#define | SPR1 1 |
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#define | SPR0 0 |
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#define | RXC0 7 |
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#define | TXC0 6 |
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#define | UDRE0 5 |
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#define | FE0 4 |
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#define | DOR0 3 |
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#define | UPE0 2 |
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#define | U2X0 1 |
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#define | MPCM0 0 |
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#define | RXCIE0 7 |
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#define | TXCIE0 6 |
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#define | UDRIE0 5 |
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#define | RXEN0 4 |
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#define | TXEN0 3 |
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#define | UCSZ02 2 |
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#define | RXB80 1 |
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#define | TXB80 0 |
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#define | ACD 7 |
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#define | ACBG 6 |
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#define | ACO 5 |
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#define | ACI 4 |
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#define | ACIE 3 |
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#define | ACIC 2 |
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#define | ACIS1 1 |
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#define | ACIS0 0 |
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#define | PE2 2 |
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#define | PE1 1 |
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#define | PE0 0 |
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#define | DDE2 2 |
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#define | DDE1 1 |
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#define | DDE0 0 |
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#define | PINE2 2 |
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#define | PINE1 1 |
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#define | PINE0 0 |
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#define | RXC1 7 |
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#define | TXC1 6 |
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#define | UDRE1 5 |
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#define | FE1 4 |
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#define | DOR1 3 |
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#define | UPE1 2 |
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#define | U2X1 1 |
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#define | MPCM1 0 |
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#define | RXCIE1 7 |
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#define | TXCIE1 6 |
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#define | UDRIE1 5 |
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#define | RXEN1 4 |
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#define | TXEN1 3 |
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#define | UCSZ12 2 |
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#define | RXB81 1 |
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#define | TXB81 0 |
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#define | SPM_PAGESIZE 128 |
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#define | RAMEND 0x4FF |
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#define | XRAMEND 0xFFFF |
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#define | E2END 0x1FF |
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#define | E2PAGESIZE 4 |
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#define | FLASHEND 0x3FFF |
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#define | FUSE_MEMORY_SIZE 3 |
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#define | FUSE_CKSEL0 (unsigned char)~_BV(0) |
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#define | FUSE_CKSEL1 (unsigned char)~_BV(1) |
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#define | FUSE_CKSEL2 (unsigned char)~_BV(2) |
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#define | FUSE_CKSEL3 (unsigned char)~_BV(3) |
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#define | FUSE_SUT0 (unsigned char)~_BV(4) |
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#define | FUSE_SUT1 (unsigned char)~_BV(5) |
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#define | FUSE_CKOUT (unsigned char)~_BV(6) |
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#define | FUSE_CKDIV8 (unsigned char)~_BV(7) |
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#define | LFUSE_DEFAULT (FUSE_CKSEL0 & FUSE_CKSEL2 & FUSE_CKSEL3 & FUSE_SUT0 & FUSE_CKDIV8) |
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#define | FUSE_BOOTRST (unsigned char)~_BV(0) |
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#define | FUSE_BOOTSZ0 (unsigned char)~_BV(1) |
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#define | FUSE_BOOTSZ1 (unsigned char)~_BV(2) |
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#define | FUSE_EESAVE (unsigned char)~_BV(3) |
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#define | FUSE_WDTON (unsigned char)~_BV(4) |
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#define | FUSE_SPIEN (unsigned char)~_BV(5) |
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#define | FUSE_JTAGEN (unsigned char)~_BV(6) |
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#define | FUSE_OCDEN (unsigned char)~_BV(7) |
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#define | HFUSE_DEFAULT (FUSE_BOOTSZ0 & FUSE_BOOTSZ1 & FUSE_SPIEN & FUSE_JTAGEN) |
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#define | FUSE_BODLEVEL0 (unsigned char)~_BV(1) |
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#define | FUSE_BODLEVEL1 (unsigned char)~_BV(2) |
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#define | FUSE_BODLEVEL2 (unsigned char)~_BV(3) |
| |
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#define | FUSE_M161C (unsigned char)~_BV(4) |
| |
|
#define | EFUSE_DEFAULT (0xFF) |
| |
|
#define | __LOCK_BITS_EXIST |
| |
|
#define | __BOOT_LOCK_BITS_0_EXIST |
| |
|
#define | __BOOT_LOCK_BITS_1_EXIST |
| |
|
#define | SIGNATURE_0 0x1E |
| |
|
#define | SIGNATURE_1 0x94 |
| |
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#define | SIGNATURE_2 0x04 |
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