RTEMS CPU Kit with SuperCore  4.11.3
sleep.h
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1 
8 /* Copyright (c) 2002, 2004 Theodore A. Roth
9  Copyright (c) 2004, 2007, 2008 Eric B. Weddington
10  Copyright (c) 2005, 2006, 2007 Joerg Wunsch
11  All rights reserved.
12 
13  Redistribution and use in source and binary forms, with or without
14  modification, are permitted provided that the following conditions are met:
15 
16  * Redistributions of source code must retain the above copyright
17  notice, this list of conditions and the following disclaimer.
18 
19  * Redistributions in binary form must reproduce the above copyright
20  notice, this list of conditions and the following disclaimer in
21  the documentation and/or other materials provided with the
22  distribution.
23 
24  * Neither the name of the copyright holders nor the names of
25  contributors may be used to endorse or promote products derived
26  from this software without specific prior written permission.
27 
28  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
29  AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
30  IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
31  ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
32  LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
33  CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
34  SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
35  INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
36  CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
37  ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
38  POSSIBILITY OF SUCH DAMAGE. */
39 
40 
41 #ifndef _AVR_SLEEP_H_
42 #define _AVR_SLEEP_H_ 1
43 
44 #include <avr/io.h>
45 #include <stdint.h>
46 
141 /*
142  * Define an internal sleep control register and
143  * an internal sleep enable bit mask.
144  */
145 #if defined(SLEEP_CTRL)
146 
147  /* XMEGA devices */
148  #define _SLEEP_CONTROL_REG SLEEP_CTRL
149  #define _SLEEP_ENABLE_MASK SLEEP_SEN_bm
150 
151 #elif defined(SMCR)
152 
153  #define _SLEEP_CONTROL_REG SMCR
154  #define _SLEEP_ENABLE_MASK _BV(SE)
155 
156 #elif defined(__AVR_AT94K__)
157 
158  #define _SLEEP_CONTROL_REG MCUR
159  #define _SLEEP_ENABLE_MASK _BV(SE)
160 
161 #else
162 
163  #define _SLEEP_CONTROL_REG MCUCR
164  #define _SLEEP_ENABLE_MASK _BV(SE)
165 
166 #endif
167 
168 
169 /* Define set_sleep_mode() and sleep mode values per device. */
170 #if defined(__AVR_ATmega161__)
171 
172  #define SLEEP_MODE_IDLE 0
173  #define SLEEP_MODE_PWR_DOWN 1
174  #define SLEEP_MODE_PWR_SAVE 2
175 
176  #define set_sleep_mode(mode) \
177  do { \
178  MCUCR = ((MCUCR & ~_BV(SM1)) | \
179  ((mode) == SLEEP_MODE_PWR_DOWN || \
180  (mode) == SLEEP_MODE_PWR_SAVE ? _BV(SM1) : 0)); \
181  EMCUCR = ((EMCUCR & ~_BV(SM0)) | \
182  ((mode) == SLEEP_MODE_PWR_SAVE ? _BV(SM0) : 0)); \
183  } while(0)
184 
185 
186 #elif defined(__AVR_ATmega162__) \
187 || defined(__AVR_ATmega8515__)
188 
189  #define SLEEP_MODE_IDLE 0
190  #define SLEEP_MODE_PWR_DOWN 1
191  #define SLEEP_MODE_PWR_SAVE 2
192  #define SLEEP_MODE_ADC 3
193  #define SLEEP_MODE_STANDBY 4
194  #define SLEEP_MODE_EXT_STANDBY 5
195 
196  #define set_sleep_mode(mode) \
197  do { \
198  MCUCR = ((MCUCR & ~_BV(SM1)) | \
199  ((mode) == SLEEP_MODE_IDLE ? 0 : _BV(SM1))); \
200  MCUCSR = ((MCUCSR & ~_BV(SM2)) | ((mode) == SLEEP_MODE_STANDBY || \
201  (mode) == SLEEP_MODE_EXT_STANDBY ? _BV(SM2) : 0)); \
202  EMCUCR = ((EMCUCR & ~_BV(SM0)) | ((mode) == SLEEP_MODE_PWR_SAVE || \
203  (mode) == SLEEP_MODE_EXT_STANDBY ? _BV(SM0) : 0)); \
204  } while(0)
205 
206 #elif defined(__AVR_AT90S2313__) \
207 || defined(__AVR_AT90S2323__) \
208 || defined(__AVR_AT90S2333__) \
209 || defined(__AVR_AT90S2343__) \
210 || defined(__AVR_AT43USB320__) \
211 || defined(__AVR_AT43USB355__) \
212 || defined(__AVR_AT90S4414__) \
213 || defined(__AVR_AT90S4433__) \
214 || defined(__AVR_AT90S8515__) \
215 || defined(__AVR_ATtiny22__)
216 
217  #define SLEEP_MODE_IDLE 0
218  #define SLEEP_MODE_PWR_DOWN _BV(SM)
219 
220  #define set_sleep_mode(mode) \
221  do { \
222  _SLEEP_CONTROL_REG = ((_SLEEP_CONTROL_REG & ~__BV(SM)) | (mode)); \
223  } while(0)
224 
225 #elif defined(__AVR_ATtiny167__) \
226 || defined(__AVR_ATtiny87__)
227 
228  #define SLEEP_MODE_IDLE 0
229  #define SLEEP_MODE_ADC _BV(SM0)
230  #define SLEEP_MODE_PWR_DOWN _BV(SM1)
231 
232  #define set_sleep_mode(mode) \
233  do { \
234  _SLEEP_CONTROL_REG = ((_SLEEP_CONTROL_REG & \
235  ~(_BV(SM0) | _BV(SM1))) | (mode)); \
236  } while(0)
237 
238 #elif defined(__AVR_AT90S4434__) \
239 || defined(__AVR_AT76C711__) \
240 || defined(__AVR_AT90S8535__) \
241 || defined(__AVR_ATmega103__) \
242 || defined(__AVR_ATmega161__) \
243 || defined(__AVR_ATmega163__) \
244 || defined(__AVR_ATtiny13__) \
245 || defined(__AVR_ATtiny13A__) \
246 || defined(__AVR_ATtiny15__) \
247 || defined(__AVR_ATtiny24__) \
248 || defined(__AVR_ATtiny24A__) \
249 || defined(__AVR_ATtiny44__) \
250 || defined(__AVR_ATtiny44A__) \
251 || defined(__AVR_ATtiny84__) \
252 || defined(__AVR_ATtiny25__) \
253 || defined(__AVR_ATtiny45__) \
254 || defined(__AVR_ATtiny48__) \
255 || defined(__AVR_ATtiny85__) \
256 || defined(__AVR_ATtiny261__) \
257 || defined(__AVR_ATtiny261A__) \
258 || defined(__AVR_ATtiny461__) \
259 || defined(__AVR_ATtiny461A__) \
260 || defined(__AVR_ATtiny861__) \
261 || defined(__AVR_ATtiny861A__) \
262 || defined(__AVR_ATtiny88__)
263 
264  #define SLEEP_MODE_IDLE 0
265  #define SLEEP_MODE_ADC _BV(SM0)
266  #define SLEEP_MODE_PWR_DOWN _BV(SM1)
267  #define SLEEP_MODE_PWR_SAVE (_BV(SM0) | _BV(SM1))
268 
269  #define set_sleep_mode(mode) \
270  do { \
271  _SLEEP_CONTROL_REG = ((_SLEEP_CONTROL_REG & \
272  ~(_BV(SM0) | _BV(SM1))) | (mode)); \
273  } while(0)
274 
275 #elif defined(__AVR_ATtiny2313__) \
276 || defined(__AVR_ATtiny2313A__) \
277 || defined(__AVR_ATtiny4313__)
278 
279  #define SLEEP_MODE_IDLE 0
280  #define SLEEP_MODE_PWR_DOWN (_BV(SM0) | _BV(SM1))
281  #define SLEEP_MODE_STANDBY _BV(SM1)
282 
283  #define set_sleep_mode(mode) \
284  do { \
285  _SLEEP_CONTROL_REG = ((_SLEEP_CONTROL_REG & \
286  ~(_BV(SM0) | _BV(SM1))) | (mode)); \
287  } while(0)
288 
289 #elif defined(__AVR_AT94K__)
290 
291  #define SLEEP_MODE_IDLE 0
292  #define SLEEP_MODE_PWR_DOWN _BV(SM1)
293  #define SLEEP_MODE_PWR_SAVE (_BV(SM0) | _BV(SM1))
294 
295  #define set_sleep_mode(mode) \
296  do { \
297  _SLEEP_CONTROL_REG = ((_SLEEP_CONTROL_REG & \
298  ~(_BV(SM0) | _BV(SM1))) | (mode)); \
299  } while(0)
300 
301 #elif defined(__AVR_ATtiny26__) \
302 || defined(__AVR_ATtiny43U__)
303 
304  #define SLEEP_MODE_IDLE 0
305  #define SLEEP_MODE_ADC _BV(SM0)
306  #define SLEEP_MODE_PWR_DOWN _BV(SM1)
307  #define SLEEP_MODE_STANDBY (_BV(SM0) | _BV(SM1))
308 
309  #define set_sleep_mode(mode) \
310  do { \
311  _SLEEP_CONTROL_REG = ((_SLEEP_CONTROL_REG & \
312  ~(_BV(SM0) | _BV(SM1))) | (mode)); \
313  } while(0)
314 
315 #elif defined(__AVR_AT90PWM216__) \
316 || defined(__AVR_AT90PWM316__) \
317 || defined(__AVR_AT90PWM81__)
318 
319  #define SLEEP_MODE_IDLE 0
320  #define SLEEP_MODE_ADC _BV(SM0)
321  #define SLEEP_MODE_PWR_DOWN _BV(SM1)
322  #define SLEEP_MODE_STANDBY (_BV(SM1) | _BV(SM2))
323 
324  #define set_sleep_mode(mode) \
325  do { \
326  _SLEEP_CONTROL_REG = ((_SLEEP_CONTROL_REG & \
327  ~(_BV(SM0) | _BV(SM1) | _BV(SM2))) | (mode)); \
328  } while(0)
329 
330 #elif defined(__AVR_AT90CAN128__) \
331 || defined(__AVR_AT90CAN32__) \
332 || defined(__AVR_AT90CAN64__) \
333 || defined(__AVR_AT90PWM1__) \
334 || defined(__AVR_AT90PWM2__) \
335 || defined(__AVR_AT90PWM2B__) \
336 || defined(__AVR_AT90PWM3__) \
337 || defined(__AVR_AT90PWM3B__) \
338 || defined(__AVR_AT90USB162__) \
339 || defined(__AVR_AT90USB82__) \
340 || defined(__AVR_AT90USB1286__) \
341 || defined(__AVR_AT90USB1287__) \
342 || defined(__AVR_AT90USB646__) \
343 || defined(__AVR_AT90USB647__) \
344 || defined(__AVR_ATmega128__) \
345 || defined(__AVR_ATmega1280__) \
346 || defined(__AVR_ATmega1281__) \
347 || defined(__AVR_ATmega1284P__) \
348 || defined(__AVR_ATmega128RFA1__) \
349 || defined(__AVR_ATmega16__) \
350 || defined(__AVR_ATmega16A__) \
351 || defined(__AVR_ATmega162__) \
352 || defined(__AVR_ATmega164A__) \
353 || defined(__AVR_ATmega164P__) \
354 || defined(__AVR_ATmega165__) \
355 || defined(__AVR_ATmega165A__) \
356 || defined(__AVR_ATmega165P__) \
357 || defined(__AVR_ATmega168__) \
358 || defined(__AVR_ATmega168A__) \
359 || defined(__AVR_ATmega168P__) \
360 || defined(__AVR_ATmega169__) \
361 || defined(__AVR_ATmega169A__) \
362 || defined(__AVR_ATmega169P__) \
363 || defined(__AVR_ATmega169PA__) \
364 || defined(__AVR_ATmega16HVA__) \
365 || defined(__AVR_ATmega16HVA2__) \
366 || defined(__AVR_ATmega16HVB__) \
367 || defined(__AVR_ATmega16M1__) \
368 || defined(__AVR_ATmega16U2__) \
369 || defined(__AVR_ATmega16U4__) \
370 || defined(__AVR_ATmega2560__) \
371 || defined(__AVR_ATmega2561__) \
372 || defined(__AVR_ATmega32__) \
373 || defined(__AVR_ATmega323__) \
374 || defined(__AVR_ATmega324A__) \
375 || defined(__AVR_ATmega324P__) \
376 || defined(__AVR_ATmega324PA__) \
377 || defined(__AVR_ATmega325__) \
378 || defined(__AVR_ATmega3250__) \
379 || defined(__AVR_ATmega328__) \
380 || defined(__AVR_ATmega328P__) \
381 || defined(__AVR_ATmega329__) \
382 || defined(__AVR_ATmega329P__) \
383 || defined(__AVR_ATmega329PA__) \
384 || defined(__AVR_ATmega3290__) \
385 || defined(__AVR_ATmega3290P__) \
386 || defined(__AVR_ATmega32C1__) \
387 || defined(__AVR_ATmega32HVB__) \
388 || defined(__AVR_ATmega32M1__) \
389 || defined(__AVR_ATmega32U2__) \
390 || defined(__AVR_ATmega32U4__) \
391 || defined(__AVR_ATmega32U6__) \
392 || defined(__AVR_ATmega406__) \
393 || defined(__AVR_ATmega48__) \
394 || defined(__AVR_ATmega48A__) \
395 || defined(__AVR_ATmega48P__) \
396 || defined(__AVR_ATmega64__) \
397 || defined(__AVR_ATmega640__) \
398 || defined(__AVR_ATmega644__) \
399 || defined(__AVR_ATmega644A__) \
400 || defined(__AVR_ATmega644P__) \
401 || defined(__AVR_ATmega644PA__) \
402 || defined(__AVR_ATmega645__) \
403 || defined(__AVR_ATmega645A__) \
404 || defined(__AVR_ATmega645P__) \
405 || defined(__AVR_ATmega6450__) \
406 || defined(__AVR_ATmega6450A__) \
407 || defined(__AVR_ATmega6450P__) \
408 || defined(__AVR_ATmega649__) \
409 || defined(__AVR_ATmega649A__) \
410 || defined(__AVR_ATmega6490__) \
411 || defined(__AVR_ATmega6490A__) \
412 || defined(__AVR_ATmega6490P__) \
413 || defined(__AVR_ATmega649P__) \
414 || defined(__AVR_ATmega64C1__) \
415 || defined(__AVR_ATmega64HVE__) \
416 || defined(__AVR_ATmega64M1__) \
417 || defined(__AVR_ATmega8__) \
418 || defined(__AVR_ATmega8515__) \
419 || defined(__AVR_ATmega8535__) \
420 || defined(__AVR_ATmega88__) \
421 || defined(__AVR_ATmega88A__) \
422 || defined(__AVR_ATmega88P__) \
423 || defined(__AVR_ATmega88PA__) \
424 || defined(__AVR_ATmega8HVA__) \
425 || defined(__AVR_ATmega8U2__)
426 
427 
428  #define SLEEP_MODE_IDLE (0)
429  #define SLEEP_MODE_ADC _BV(SM0)
430  #define SLEEP_MODE_PWR_DOWN _BV(SM1)
431  #define SLEEP_MODE_PWR_SAVE (_BV(SM0) | _BV(SM1))
432  #define SLEEP_MODE_STANDBY (_BV(SM1) | _BV(SM2))
433  #define SLEEP_MODE_EXT_STANDBY (_BV(SM0) | _BV(SM1) | _BV(SM2))
434 
435 
436  #define set_sleep_mode(mode) \
437  do { \
438  _SLEEP_CONTROL_REG = ((_SLEEP_CONTROL_REG & \
439  ~(_BV(SM0) | _BV(SM1) | _BV(SM2))) | (mode)); \
440  } while(0)
441 
442 #elif defined(__AVR_ATxmega16A4__) \
443 || defined(__AVR_ATxmega16D4__) \
444 || defined(__AVR_ATxmega32A4__) \
445 || defined(__AVR_ATxmega32D4__) \
446 || defined(__AVR_ATxmega64A1__) \
447 || defined(__AVR_ATxmega64A3__) \
448 || defined(__AVR_ATxmega64D3__) \
449 || defined(__AVR_ATxmega128A1__) \
450 || defined(__AVR_ATxmega128A3__) \
451 || defined(__AVR_ATxmega128D3__) \
452 || defined(__AVR_ATxmega192A3__) \
453 || defined(__AVR_ATxmega192D3__) \
454 || defined(__AVR_ATxmega256A3__) \
455 || defined(__AVR_ATxmega256D3__) \
456 || defined(__AVR_ATxmega256A3B__)
457 
458  #define SLEEP_MODE_IDLE (0)
459  #define SLEEP_MODE_PWR_DOWN (SLEEP_SMODE1_bm)
460  #define SLEEP_MODE_PWR_SAVE (SLEEP_SMODE1_bm | SLEEP_SMODE0_bm)
461  #define SLEEP_MODE_STANDBY (SLEEP_SMODE2_bm | SLEEP_SMODE1_bm)
462  #define SLEEP_MODE_EXT_STANDBY (SLEEP_SMODE2_bm | SLEEP_SMODE1_bm | \
463  SLEEP_SMODE0_bm)
464 
465  #define set_sleep_mode(mode) \
466  do { \
467  _SLEEP_CONTROL_REG = ((_SLEEP_CONTROL_REG & \
468  ~(SLEEP_SMODE2_bm | SLEEP_SMODE1_bm | SLEEP_SMODE0_bm)) | (mode)); \
469  } while(0)
470 
471 #elif defined(__AVR_AT90SCR100__)
472 
473  #define SLEEP_MODE_IDLE (0)
474  #define SLEEP_MODE_PWR_DOWN _BV(SM1)
475  #define SLEEP_MODE_PWR_SAVE (_BV(SM0) | _BV(SM1))
476  #define SLEEP_MODE_STANDBY (_BV(SM1) | _BV(SM2))
477  #define SLEEP_MODE_EXT_STANDBY (_BV(SM0) | _BV(SM1) | _BV(SM2))
478 
479  #define set_sleep_mode(mode) \
480  do { \
481  _SLEEP_CONTROL_REG = ((_SLEEP_CONTROL_REG & \
482  ~(_BV(SM0) | _BV(SM1) | _BV(SM2))) | (mode)); \
483  } while(0)
484 
485 #elif defined(__AVR_ATA6289__)
486 
487  #define SLEEP_MODE_IDLE (0)
488  #define SLEEP_MODE_SENSOR_NOISE_REDUCTION (_BV(SM0))
489  #define SLEEP_MODE_PWR_DOWN (_BV(SM1))
490 
491  #define set_sleep_mode(mode) \
492  do { \
493  _SLEEP_CONTROL_REG = ((_SLEEP_CONTROL_REG & \
494  ~(_BV(SM0) | _BV(SM1) | _BV(SM2))) | (mode)); \
495  } while(0)
496 
497 #else
498 
499  #error "No SLEEP mode defined for this device."
500 
501 #endif
502 
503 
504 
512 #if defined(__DOXYGEN__)
513 
517 extern void sleep_enable (void);
518 
519 #else
520 
521 #define sleep_enable() \
522 do { \
523  _SLEEP_CONTROL_REG |= (uint8_t)_SLEEP_ENABLE_MASK; \
524 } while(0)
525 
526 #endif
527 
528 
529 #if defined(__DOXYGEN__)
530 
534 extern void sleep_disable (void);
535 
536 #else
537 
538 #define sleep_disable() \
539 do { \
540  _SLEEP_CONTROL_REG &= (uint8_t)(~_SLEEP_ENABLE_MASK); \
541 } while(0)
542 
543 #endif
544 
545 
550 #if defined(__DOXYGEN__)
551 
552 extern void sleep_cpu (void);
553 
554 #else
555 
556 #define sleep_cpu() \
557 do { \
558  __asm__ __volatile__ ( "sleep" "\n\t" :: ); \
559 } while(0)
560 
561 #endif
562 
563 
564 #if defined(__DOXYGEN__)
565 
566 extern void sleep_mode (void);
567 
568 #else
569 
570 #define sleep_mode() \
571 do { \
572  sleep_enable(); \
573  sleep_cpu(); \
574  sleep_disable(); \
575 } while (0)
576 
577 #endif
578 
579 
580 #if defined(__DOXYGEN__)
581 
582 extern void sleep_bod_disable (void);
583 
584 #else
585 
586 #if defined(BODS) && defined(BODSE)
587 
588 #define sleep_bod_disable() \
589 do { \
590  uint8_t tempreg; \
591  __asm__ __volatile__("in %[tempreg], %[mcucr]" "\n\t" \
592  "ori %[tempreg], %[bods_bodse]" "\n\t" \
593  "out %[mcucr], %[tempreg]" "\n\t" \
594  "andi %[tempreg], %[not_bodse]" "\n\t" \
595  "out %[mcucr], %[tempreg]" \
596  : [tempreg] "=&d" (tempreg) \
597  : [mcucr] "I" _SFR_IO_ADDR(MCUCR), \
598  [bods_bodse] "i" (_BV(BODS) | _BV(BODSE)), \
599  [not_bodse] "i" (~_BV(BODSE))); \
600 } while (0)
601 
602 #endif
603 
604 #endif
605 
606 
609 #endif /* _AVR_SLEEP_H_ */
sleep_enable
#define sleep_enable()
Put the device in sleep mode.
Definition: sleep.h:521
sleep_cpu
#define sleep_cpu()
Put the device into sleep mode.
Definition: sleep.h:556
io.h
AVR device-specific IO Definitions.
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