RTEMS CPU Kit with SuperCore  4.11.3
asm.h
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1 
17 /*
18  * COPYRIGHT:
19  *
20  * This file is based on similar code found in newlib available
21  * from ftp.cygnus.com. The file which was used had no copyright
22  * notice. This file is freely distributable as long as the source
23  * of the file is noted. This file is:
24  *
25  * COPYRIGHT (c) 1995.
26  * i-cubed ltd.
27  *
28  * COPYRIGHT (c) 1994.
29  * On-Line Applications Research Corporation (OAR).
30  */
31 
32 #ifndef _RTEMS_ASM_H
33 #define _RTEMS_ASM_H
34 
35 /*
36  * Indicate we are in an assembly file and get the basic CPU definitions.
37  */
38 
39 #ifndef ASM
40 #define ASM
41 #endif
42 #include <rtems/score/cpuopts.h>
43 #include <rtems/score/powerpc.h>
44 
45 /*
46  * Recent versions of GNU cpp define variables which indicate the
47  * need for underscores and percents. If not using GNU cpp or
48  * the version does not support this, then you will obviously
49  * have to define these as appropriate.
50  */
51 
52 #ifndef __USER_LABEL_PREFIX__
53 #define __USER_LABEL_PREFIX__
54 #endif
55 
56 #ifndef __REGISTER_PREFIX__
57 #define __REGISTER_PREFIX__
58 #endif
59 
60 #ifndef __FLOAT_REGISTER_PREFIX__
61 #define __FLOAT_REGISTER_PREFIX__ __REGISTER_PREFIX__
62 #endif
63 
64 #ifndef __PROC_LABEL_PREFIX__
65 #define __PROC_LABEL_PREFIX__ __USER_LABEL_PREFIX__
66 #endif
67 
68 #include <rtems/concat.h>
69 
70 /* Use the right prefix for global labels. */
71 
72 #define SYM(x) CONCAT1 (__USER_LABEL_PREFIX__, x)
73 
74 /* Use the right prefix for procedure labels. */
75 
76 #define PROC(x) CONCAT1 (__PROC_LABEL_PREFIX__, x)
77 
78 /* Use the right prefix for registers. */
79 
80 #define REG(x) CONCAT1 (__REGISTER_PREFIX__, x)
81 
82 /* Use the right prefix for floating point registers. */
83 
84 #define FREG(x) CONCAT1 (__FLOAT_REGISTER_PREFIX__, x)
85 
86 /*
87  * define macros for all of the registers on this CPU
88  *
89  * EXAMPLE: #define d0 REG (d0)
90  */
91 #define r0 REG(0)
92 #define r1 REG(1)
93 #define r2 REG(2)
94 #define r3 REG(3)
95 #define r4 REG(4)
96 #define r5 REG(5)
97 #define r6 REG(6)
98 #define r7 REG(7)
99 #define r8 REG(8)
100 #define r9 REG(9)
101 #define r10 REG(10)
102 #define r11 REG(11)
103 #define r12 REG(12)
104 #define r13 REG(13)
105 #define r14 REG(14)
106 #define r15 REG(15)
107 #define r16 REG(16)
108 #define r17 REG(17)
109 #define r18 REG(18)
110 #define r19 REG(19)
111 #define r20 REG(20)
112 #define r21 REG(21)
113 #define r22 REG(22)
114 #define r23 REG(23)
115 #define r24 REG(24)
116 #define r25 REG(25)
117 #define r26 REG(26)
118 #define r27 REG(27)
119 #define r28 REG(28)
120 #define r29 REG(29)
121 #define r30 REG(30)
122 #define r31 REG(31)
123 #define f0 FREG(0)
124 #define f1 FREG(1)
125 #define f2 FREG(2)
126 #define f3 FREG(3)
127 #define f4 FREG(4)
128 #define f5 FREG(5)
129 #define f6 FREG(6)
130 #define f7 FREG(7)
131 #define f8 FREG(8)
132 #define f9 FREG(9)
133 #define f10 FREG(10)
134 #define f11 FREG(11)
135 #define f12 FREG(12)
136 #define f13 FREG(13)
137 #define f14 FREG(14)
138 #define f15 FREG(15)
139 #define f16 FREG(16)
140 #define f17 FREG(17)
141 #define f18 FREG(18)
142 #define f19 FREG(19)
143 #define f20 FREG(20)
144 #define f21 FREG(21)
145 #define f22 FREG(22)
146 #define f23 FREG(23)
147 #define f24 FREG(24)
148 #define f25 FREG(25)
149 #define f26 FREG(26)
150 #define f27 FREG(27)
151 #define f28 FREG(28)
152 #define f29 FREG(29)
153 #define f30 FREG(30)
154 #define f31 FREG(31)
155 #define v0 0
156 #define v1 1
157 #define v2 2
158 #define v3 3
159 #define v4 4
160 #define v5 5
161 #define v6 6
162 #define v7 7
163 #define v8 8
164 #define v9 9
165 #define v10 10
166 #define v11 11
167 #define v12 12
168 #define v13 13
169 #define v14 14
170 #define v15 15
171 #define v16 16
172 #define v17 17
173 #define v18 18
174 #define v19 19
175 #define v20 20
176 #define v21 21
177 #define v22 22
178 #define v23 23
179 #define v24 24
180 #define v25 25
181 #define v26 26
182 #define v27 27
183 #define v28 28
184 #define v29 29
185 #define v30 30
186 #define v31 31
187 
188 /*
189  * Some special purpose registers (SPRs).
190  */
191 #define srr0 0x01a
192 #define srr1 0x01b
193 #define srr2 0x3de /* IBM 400 series only */
194 #define srr3 0x3df /* IBM 400 series only */
195 #define csrr0 58 /* Book E */
196 #define csrr1 59 /* Book E */
197 #define mcsrr0 570 /* e500 */
198 #define mcsrr1 571 /* e500 */
199 #define dsrr0 574 /* e200 */
200 #define dsrr1 575 /* e200 */
201 
202 #define sprg0 0x110
203 #define sprg1 0x111
204 #define sprg2 0x112
205 #define sprg3 0x113
206 #define sprg4 276
207 #define sprg5 277
208 #define sprg6 278
209 #define sprg7 279
210 
211 #define usprg0 256
212 
213 #define dar 0x013 /* Data Address Register */
214 #define dec 0x016 /* Decrementer Register */
215 
216 #if defined(ppc403) || defined(ppc405)
217 /* the following SPR/DCR registers exist only in IBM 400 series */
218 #define dear 0x3d5
219 #define evpr 0x3d6 /* SPR: exception vector prefix register */
220 #define iccr 0x3fb /* SPR: instruction cache control reg. */
221 #define dccr 0x3fa /* SPR: data cache control reg. */
222 
223 #if defined (ppc403)
224 #define exisr 0x040 /* DCR: external interrupt status register */
225 #define exier 0x042 /* DCR: external interrupt enable register */
226 #endif /* ppc403 */
227 #if defined(ppc405)
228 #define exisr 0x0C0 /* DCR: external interrupt status register */
229 #define exier 0x0C2 /* DCR: external interrupt enable register */
230 #endif /* ppc405 */
231 
232 #define br0 0x080 /* DCR: memory bank register 0 */
233 #define br1 0x081 /* DCR: memory bank register 1 */
234 #define br2 0x082 /* DCR: memory bank register 2 */
235 #define br3 0x083 /* DCR: memory bank register 3 */
236 #define br4 0x084 /* DCR: memory bank register 4 */
237 #define br5 0x085 /* DCR: memory bank register 5 */
238 #define br6 0x086 /* DCR: memory bank register 6 */
239 #define br7 0x087 /* DCR: memory bank register 7 */
240 
241 /* end of IBM400 series register definitions */
242 
243 #elif defined(mpc555)
244 /* The following registers are for the MPC5xx */
245 #define eie 0x050 /* External Interrupt Enable Register */
246 #define eid 0x051 /* External Interrupt Disable Register */
247 #define nri 0x052 /* Non-Recoverable Interrupt Register */
248 
249 #elif defined(mpc860) || defined(mpc821)
250 /* The following registers are for the MPC8x0 */
251 #define der 0x095 /* Debug Enable Register */
252 #define ictrl 0x09E /* Instruction Support Control Register */
253 #define immr 0x27E /* Internal Memory Map Register */
254 /* end of MPC8x0 registers */
255 #endif
256 
257 /*
258  * Following must be tailor for a particular flavor of the C compiler.
259  * They may need to put underscores in front of the symbols.
260  */
261 
262 #define PUBLIC_VAR(sym) .globl SYM (sym)
263 #define EXTERN_VAR(sym) .extern SYM (sym)
264 #define PUBLIC_PROC(sym) .globl PROC (sym)
265 #define EXTERN_PROC(sym) .extern PROC (sym)
266 
267 /* Other potentially assembler specific operations */
268 #if PPC_ASM == PPC_ASM_ELF
269 #define ALIGN(n,p) .align p
270 #define DESCRIPTOR(x) \
271  .section .descriptors,"aw"; \
272  PUBLIC_VAR (x); \
273 SYM (x):; \
274  .long PROC (x); \
275  .long s.got; \
276  .long 0
277 
278 #define EXT_SYM_REF(x) .long x
279 #define EXT_PROC_REF(x) .long x
280 
281 /*
282  * Define macros to handle section beginning and ends.
283  */
284 
285 #define BEGIN_CODE_DCL .text
286 #define END_CODE_DCL
287 #define BEGIN_DATA_DCL .data
288 #define END_DATA_DCL
289 #define BEGIN_CODE .text
290 #define END_CODE
291 #define BEGIN_DATA .data
292 #define END_DATA
293 #define BEGIN_BSS .bss
294 #define END_BSS
295 #define END
296 
297 #else
298 #error "PPC_ASM_TYPE is not properly defined"
299 #endif
300 #ifndef PPC_ASM
301 #error "PPC_ASM_TYPE is not properly defined"
302 #endif
303 
304 
305 #endif
IBM/Motorola Power Pc Definitions.
This include file defines ANSI concatenation macros.