RTEMS CPU Kit with SuperCore  4.11.3
iox32a4.h
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1 
9 /*
10  * Copyright (c) 2009 Atmel Corporation
11  * All rights reserved.
12  *
13  * Redistribution and use in source and binary forms, with or without
14  * modification, are permitted provided that the following conditions are met:
15  *
16  * * Redistributions of source code must retain the above copyright
17  * notice, this list of conditions and the following disclaimer.
18  *
19  * * Redistributions in binary form must reproduce the above copyright
20  * notice, this list of conditions and the following disclaimer in
21  * the documentation and/or other materials provided with the
22  * distribution.
23  *
24  * * Neither the name of the copyright holders nor the names of
25  * contributors may be used to endorse or promote products derived
26  * from this software without specific prior written permission.
27  *
28  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
29  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
30  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
31  * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
32  * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
33  * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
34  * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
35  * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
36  * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
37  * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
38  * POSSIBILITY OF SUCH DAMAGE.
39  */
40 
41 #ifndef _AVR_IO_H_
42 # error "Include <avr/io.h> instead of this file."
43 #endif
44 
45 #ifndef _AVR_IOXXX_H_
46 # define _AVR_IOXXX_H_ "iox32a4.h"
47 #else
48 # error "Attempt to include more than one <avr/ioXXX.h> file."
49 #endif
50 
51 
52 #ifndef _AVR_ATxmega32A4_H_
53 #define _AVR_ATxmega32A4_H_ 1
54 
62 /* Ungrouped common registers */
63 #define GPIO0 _SFR_MEM8(0x0000) /* General Purpose IO Register 0 */
64 #define GPIO1 _SFR_MEM8(0x0001) /* General Purpose IO Register 1 */
65 #define GPIO2 _SFR_MEM8(0x0002) /* General Purpose IO Register 2 */
66 #define GPIO3 _SFR_MEM8(0x0003) /* General Purpose IO Register 3 */
67 #define GPIO4 _SFR_MEM8(0x0004) /* General Purpose IO Register 4 */
68 #define GPIO5 _SFR_MEM8(0x0005) /* General Purpose IO Register 5 */
69 #define GPIO6 _SFR_MEM8(0x0006) /* General Purpose IO Register 6 */
70 #define GPIO7 _SFR_MEM8(0x0007) /* General Purpose IO Register 7 */
71 #define GPIO8 _SFR_MEM8(0x0008) /* General Purpose IO Register 8 */
72 #define GPIO9 _SFR_MEM8(0x0009) /* General Purpose IO Register 9 */
73 #define GPIOA _SFR_MEM8(0x000A) /* General Purpose IO Register 10 */
74 #define GPIOB _SFR_MEM8(0x000B) /* General Purpose IO Register 11 */
75 #define GPIOC _SFR_MEM8(0x000C) /* General Purpose IO Register 12 */
76 #define GPIOD _SFR_MEM8(0x000D) /* General Purpose IO Register 13 */
77 #define GPIOE _SFR_MEM8(0x000E) /* General Purpose IO Register 14 */
78 #define GPIOF _SFR_MEM8(0x000F) /* General Purpose IO Register 15 */
79 
80 #define CCP _SFR_MEM8(0x0034) /* Configuration Change Protection */
81 #define RAMPD _SFR_MEM8(0x0038) /* Ramp D */
82 #define RAMPX _SFR_MEM8(0x0039) /* Ramp X */
83 #define RAMPY _SFR_MEM8(0x003A) /* Ramp Y */
84 #define RAMPZ _SFR_MEM8(0x003B) /* Ramp Z */
85 #define EIND _SFR_MEM8(0x003C) /* Extended Indirect Jump */
86 #define SPL _SFR_MEM8(0x003D) /* Stack Pointer Low */
87 #define SPH _SFR_MEM8(0x003E) /* Stack Pointer High */
88 #define SREG _SFR_MEM8(0x003F) /* Status Register */
89 
90 
91 /* C Language Only */
92 #if !defined (__ASSEMBLER__)
93 
94 #include <stdint.h>
95 
96 typedef volatile uint8_t register8_t;
97 typedef volatile uint16_t register16_t;
98 typedef volatile uint32_t register32_t;
99 
100 
101 #ifdef _WORDREGISTER
102 #undef _WORDREGISTER
103 #endif
104 #define _WORDREGISTER(regname) \
105  __extension__ union \
106  { \
107  register16_t regname; \
108  struct \
109  { \
110  register8_t regname ## L; \
111  register8_t regname ## H; \
112  }; \
113  }
114 
115 #ifdef _DWORDREGISTER
116 #undef _DWORDREGISTER
117 #endif
118 #define _DWORDREGISTER(regname) \
119  __extension__ union \
120  { \
121  register32_t regname; \
122  struct \
123  { \
124  register8_t regname ## 0; \
125  register8_t regname ## 1; \
126  register8_t regname ## 2; \
127  register8_t regname ## 3; \
128  }; \
129  }
130 
131 
132 /*
133 ==========================================================================
134 IO Module Structures
135 ==========================================================================
136 */
137 
138 
139 /*
140 --------------------------------------------------------------------------
141 XOCD - On-Chip Debug System
142 --------------------------------------------------------------------------
143 */
144 
145 /* On-Chip Debug System */
146 typedef struct OCD_struct
147 {
148  register8_t OCDR0; /* OCD Register 0 */
149  register8_t OCDR1; /* OCD Register 1 */
150 } OCD_t;
151 
152 
153 /* CCP signatures */
154 typedef enum CCP_enum
155 {
156  CCP_SPM_gc = (0x9D<<0), /* SPM Instruction Protection */
157  CCP_IOREG_gc = (0xD8<<0), /* IO Register Protection */
158 } CCP_t;
159 
160 
161 /*
162 --------------------------------------------------------------------------
163 CLK - Clock System
164 --------------------------------------------------------------------------
165 */
166 
167 /* Clock System */
168 typedef struct CLK_struct
169 {
170  register8_t CTRL; /* Control Register */
171  register8_t PSCTRL; /* Prescaler Control Register */
172  register8_t LOCK; /* Lock register */
173  register8_t RTCCTRL; /* RTC Control Register */
174 } CLK_t;
175 
176 /*
177 --------------------------------------------------------------------------
178 CLK - Clock System
179 --------------------------------------------------------------------------
180 */
181 
182 /* Power Reduction */
183 typedef struct PR_struct
184 {
185  register8_t PRGEN; /* General Power Reduction */
186  register8_t PRPA; /* Power Reduction Port A */
187  register8_t PRPB; /* Power Reduction Port B */
188  register8_t PRPC; /* Power Reduction Port C */
189  register8_t PRPD; /* Power Reduction Port D */
190  register8_t PRPE; /* Power Reduction Port E */
191  register8_t PRPF; /* Power Reduction Port F */
192 } PR_t;
193 
194 /* System Clock Selection */
195 typedef enum CLK_SCLKSEL_enum
196 {
197  CLK_SCLKSEL_RC2M_gc = (0x00<<0), /* Internal 2MHz RC Oscillator */
198  CLK_SCLKSEL_RC32M_gc = (0x01<<0), /* Internal 32MHz RC Oscillator */
199  CLK_SCLKSEL_RC32K_gc = (0x02<<0), /* Internal 32kHz RC Oscillator */
200  CLK_SCLKSEL_XOSC_gc = (0x03<<0), /* External Crystal Oscillator or Clock */
201  CLK_SCLKSEL_PLL_gc = (0x04<<0), /* Phase Locked Loop */
202 } CLK_SCLKSEL_t;
203 
204 /* Prescaler A Division Factor */
205 typedef enum CLK_PSADIV_enum
206 {
207  CLK_PSADIV_1_gc = (0x00<<2), /* Divide by 1 */
208  CLK_PSADIV_2_gc = (0x01<<2), /* Divide by 2 */
209  CLK_PSADIV_4_gc = (0x03<<2), /* Divide by 4 */
210  CLK_PSADIV_8_gc = (0x05<<2), /* Divide by 8 */
211  CLK_PSADIV_16_gc = (0x07<<2), /* Divide by 16 */
212  CLK_PSADIV_32_gc = (0x09<<2), /* Divide by 32 */
213  CLK_PSADIV_64_gc = (0x0B<<2), /* Divide by 64 */
214  CLK_PSADIV_128_gc = (0x0D<<2), /* Divide by 128 */
215  CLK_PSADIV_256_gc = (0x0F<<2), /* Divide by 256 */
216  CLK_PSADIV_512_gc = (0x11<<2), /* Divide by 512 */
217 } CLK_PSADIV_t;
218 
219 /* Prescaler B and C Division Factor */
220 typedef enum CLK_PSBCDIV_enum
221 {
222  CLK_PSBCDIV_1_1_gc = (0x00<<0), /* Divide B by 1 and C by 1 */
223  CLK_PSBCDIV_1_2_gc = (0x01<<0), /* Divide B by 1 and C by 2 */
224  CLK_PSBCDIV_4_1_gc = (0x02<<0), /* Divide B by 4 and C by 1 */
225  CLK_PSBCDIV_2_2_gc = (0x03<<0), /* Divide B by 2 and C by 2 */
226 } CLK_PSBCDIV_t;
227 
228 /* RTC Clock Source */
229 typedef enum CLK_RTCSRC_enum
230 {
231  CLK_RTCSRC_ULP_gc = (0x00<<1), /* 1kHz from internal 32kHz ULP */
232  CLK_RTCSRC_TOSC_gc = (0x01<<1), /* 1kHz from 32kHz crystal oscillator on TOSC */
233  CLK_RTCSRC_RCOSC_gc = (0x02<<1), /* 1kHz from internal 32kHz RC oscillator */
234  CLK_RTCSRC_TOSC32_gc = (0x05<<1), /* 32kHz from 32kHz crystal oscillator on TOSC */
235 } CLK_RTCSRC_t;
236 
237 
238 /*
239 --------------------------------------------------------------------------
240 SLEEP - Sleep Controller
241 --------------------------------------------------------------------------
242 */
243 
244 /* Sleep Controller */
245 typedef struct SLEEP_struct
246 {
247  register8_t CTRL; /* Control Register */
248 } SLEEP_t;
249 
250 /* Sleep Mode */
251 typedef enum SLEEP_SMODE_enum
252 {
253  SLEEP_SMODE_IDLE_gc = (0x00<<1), /* Idle mode */
254  SLEEP_SMODE_PDOWN_gc = (0x02<<1), /* Power-down Mode */
255  SLEEP_SMODE_PSAVE_gc = (0x03<<1), /* Power-save Mode */
256  SLEEP_SMODE_STDBY_gc = (0x06<<1), /* Standby Mode */
257  SLEEP_SMODE_ESTDBY_gc = (0x07<<1), /* Extended Standby Mode */
258 } SLEEP_SMODE_t;
259 
260 
261 /*
262 --------------------------------------------------------------------------
263 OSC - Oscillator
264 --------------------------------------------------------------------------
265 */
266 
267 /* Oscillator */
268 typedef struct OSC_struct
269 {
270  register8_t CTRL; /* Control Register */
271  register8_t STATUS; /* Status Register */
272  register8_t XOSCCTRL; /* External Oscillator Control Register */
273  register8_t XOSCFAIL; /* External Oscillator Failure Detection Register */
274  register8_t RC32KCAL; /* 32kHz Internal Oscillator Calibration Register */
275  register8_t PLLCTRL; /* PLL Control REgister */
276  register8_t DFLLCTRL; /* DFLL Control Register */
277 } OSC_t;
278 
279 /* Oscillator Frequency Range */
280 typedef enum OSC_FRQRANGE_enum
281 {
282  OSC_FRQRANGE_04TO2_gc = (0x00<<6), /* 0.4 - 2 MHz */
283  OSC_FRQRANGE_2TO9_gc = (0x01<<6), /* 2 - 9 MHz */
284  OSC_FRQRANGE_9TO12_gc = (0x02<<6), /* 9 - 12 MHz */
285  OSC_FRQRANGE_12TO16_gc = (0x03<<6), /* 12 - 16 MHz */
286 } OSC_FRQRANGE_t;
287 
288 /* External Oscillator Selection and Startup Time */
289 typedef enum OSC_XOSCSEL_enum
290 {
291  OSC_XOSCSEL_EXTCLK_gc = (0x00<<0), /* External Clock - 6 CLK */
292  OSC_XOSCSEL_32KHz_gc = (0x02<<0), /* 32kHz TOSC - 32K CLK */
293  OSC_XOSCSEL_XTAL_256CLK_gc = (0x03<<0), /* 0.4-16MHz XTAL - 256 CLK */
294  OSC_XOSCSEL_XTAL_1KCLK_gc = (0x07<<0), /* 0.4-16MHz XTAL - 1K CLK */
295  OSC_XOSCSEL_XTAL_16KCLK_gc = (0x0B<<0), /* 0.4-16MHz XTAL - 16K CLK */
296 } OSC_XOSCSEL_t;
297 
298 /* PLL Clock Source */
299 typedef enum OSC_PLLSRC_enum
300 {
301  OSC_PLLSRC_RC2M_gc = (0x00<<6), /* Internal 2MHz RC Oscillator */
302  OSC_PLLSRC_RC32M_gc = (0x02<<6), /* Internal 32MHz RC Oscillator */
303  OSC_PLLSRC_XOSC_gc = (0x03<<6), /* External Oscillator */
304 } OSC_PLLSRC_t;
305 
306 
307 /*
308 --------------------------------------------------------------------------
309 DFLL - DFLL
310 --------------------------------------------------------------------------
311 */
312 
313 /* DFLL */
314 typedef struct DFLL_struct
315 {
316  register8_t CTRL; /* Control Register */
317  register8_t reserved_0x01;
318  register8_t CALA; /* Calibration Register A */
319  register8_t CALB; /* Calibration Register B */
320  register8_t COMP0; /* Oscillator Compare Register 0 */
321  register8_t COMP1; /* Oscillator Compare Register 1 */
322  register8_t COMP2; /* Oscillator Compare Register 2 */
323  register8_t reserved_0x07;
324 } DFLL_t;
325 
326 
327 /*
328 --------------------------------------------------------------------------
329 RST - Reset
330 --------------------------------------------------------------------------
331 */
332 
333 /* Reset */
334 typedef struct RST_struct
335 {
336  register8_t STATUS; /* Status Register */
337  register8_t CTRL; /* Control Register */
338 } RST_t;
339 
340 
341 /*
342 --------------------------------------------------------------------------
343 WDT - Watch-Dog Timer
344 --------------------------------------------------------------------------
345 */
346 
347 /* Watch-Dog Timer */
348 typedef struct WDT_struct
349 {
350  register8_t CTRL; /* Control */
351  register8_t WINCTRL; /* Windowed Mode Control */
352  register8_t STATUS; /* Status */
353 } WDT_t;
354 
355 /* Period setting */
356 typedef enum WDT_PER_enum
357 {
358  WDT_PER_8CLK_gc = (0x00<<2), /* 8 cycles (8ms @ 3.3V) */
359  WDT_PER_16CLK_gc = (0x01<<2), /* 16 cycles (16ms @ 3.3V) */
360  WDT_PER_32CLK_gc = (0x02<<2), /* 32 cycles (32ms @ 3.3V) */
361  WDT_PER_64CLK_gc = (0x03<<2), /* 64 cycles (64ms @ 3.3V) */
362  WDT_PER_128CLK_gc = (0x04<<2), /* 128 cycles (0.125s @ 3.3V) */
363  WDT_PER_256CLK_gc = (0x05<<2), /* 256 cycles (0.25s @ 3.3V) */
364  WDT_PER_512CLK_gc = (0x06<<2), /* 512 cycles (0.5s @ 3.3V) */
365  WDT_PER_1KCLK_gc = (0x07<<2), /* 1K cycles (1s @ 3.3V) */
366  WDT_PER_2KCLK_gc = (0x08<<2), /* 2K cycles (2s @ 3.3V) */
367  WDT_PER_4KCLK_gc = (0x09<<2), /* 4K cycles (4s @ 3.3V) */
368  WDT_PER_8KCLK_gc = (0x0A<<2), /* 8K cycles (8s @ 3.3V) */
369 } WDT_PER_t;
370 
371 /* Closed window period */
372 typedef enum WDT_WPER_enum
373 {
374  WDT_WPER_8CLK_gc = (0x00<<2), /* 8 cycles (8ms @ 3.3V) */
375  WDT_WPER_16CLK_gc = (0x01<<2), /* 16 cycles (16ms @ 3.3V) */
376  WDT_WPER_32CLK_gc = (0x02<<2), /* 32 cycles (32ms @ 3.3V) */
377  WDT_WPER_64CLK_gc = (0x03<<2), /* 64 cycles (64ms @ 3.3V) */
378  WDT_WPER_128CLK_gc = (0x04<<2), /* 128 cycles (0.125s @ 3.3V) */
379  WDT_WPER_256CLK_gc = (0x05<<2), /* 256 cycles (0.25s @ 3.3V) */
380  WDT_WPER_512CLK_gc = (0x06<<2), /* 512 cycles (0.5s @ 3.3V) */
381  WDT_WPER_1KCLK_gc = (0x07<<2), /* 1K cycles (1s @ 3.3V) */
382  WDT_WPER_2KCLK_gc = (0x08<<2), /* 2K cycles (2s @ 3.3V) */
383  WDT_WPER_4KCLK_gc = (0x09<<2), /* 4K cycles (4s @ 3.3V) */
384  WDT_WPER_8KCLK_gc = (0x0A<<2), /* 8K cycles (8s @ 3.3V) */
385 } WDT_WPER_t;
386 
387 
388 /*
389 --------------------------------------------------------------------------
390 MCU - MCU Control
391 --------------------------------------------------------------------------
392 */
393 
394 /* MCU Control */
395 typedef struct MCU_struct
396 {
397  register8_t DEVID0; /* Device ID byte 0 */
398  register8_t DEVID1; /* Device ID byte 1 */
399  register8_t DEVID2; /* Device ID byte 2 */
400  register8_t REVID; /* Revision ID */
401  register8_t JTAGUID; /* JTAG User ID */
402  register8_t reserved_0x05;
403  register8_t MCUCR; /* MCU Control */
404  register8_t reserved_0x07;
405  register8_t EVSYSLOCK; /* Event System Lock */
406  register8_t AWEXLOCK; /* AWEX Lock */
407  register8_t reserved_0x0A;
408  register8_t reserved_0x0B;
409 } MCU_t;
410 
411 
412 /*
413 --------------------------------------------------------------------------
414 PMIC - Programmable Multi-level Interrupt Controller
415 --------------------------------------------------------------------------
416 */
417 
418 /* Programmable Multi-level Interrupt Controller */
419 typedef struct PMIC_struct
420 {
421  register8_t STATUS; /* Status Register */
422  register8_t INTPRI; /* Interrupt Priority */
423  register8_t CTRL; /* Control Register */
424 } PMIC_t;
425 
426 
427 /*
428 --------------------------------------------------------------------------
429 DMA - DMA Controller
430 --------------------------------------------------------------------------
431 */
432 
433 /* DMA Channel */
434 typedef struct DMA_CH_struct
435 {
436  register8_t CTRLA; /* Channel Control */
437  register8_t CTRLB; /* Channel Control */
438  register8_t ADDRCTRL; /* Address Control */
439  register8_t TRIGSRC; /* Channel Trigger Source */
440  _WORDREGISTER(TRFCNT); /* Channel Block Transfer Count */
441  register8_t REPCNT; /* Channel Repeat Count */
442  register8_t reserved_0x07;
443  register8_t SRCADDR0; /* Channel Source Address 0 */
444  register8_t SRCADDR1; /* Channel Source Address 1 */
445  register8_t SRCADDR2; /* Channel Source Address 2 */
446  register8_t reserved_0x0B;
447  register8_t DESTADDR0; /* Channel Destination Address 0 */
448  register8_t DESTADDR1; /* Channel Destination Address 1 */
449  register8_t DESTADDR2; /* Channel Destination Address 2 */
450  register8_t reserved_0x0F;
451 } DMA_CH_t;
452 
453 /*
454 --------------------------------------------------------------------------
455 DMA - DMA Controller
456 --------------------------------------------------------------------------
457 */
458 
459 /* DMA Controller */
460 typedef struct DMA_struct
461 {
462  register8_t CTRL; /* Control */
463  register8_t reserved_0x01;
464  register8_t reserved_0x02;
465  register8_t INTFLAGS; /* Transfer Interrupt Status */
466  register8_t STATUS; /* Status */
467  register8_t reserved_0x05;
468  _WORDREGISTER(TEMP); /* Temporary Register For 16/24-bit Access */
469  register8_t reserved_0x08;
470  register8_t reserved_0x09;
471  register8_t reserved_0x0A;
472  register8_t reserved_0x0B;
473  register8_t reserved_0x0C;
474  register8_t reserved_0x0D;
475  register8_t reserved_0x0E;
476  register8_t reserved_0x0F;
477  DMA_CH_t CH0; /* DMA Channel 0 */
478  DMA_CH_t CH1; /* DMA Channel 1 */
479  DMA_CH_t CH2; /* DMA Channel 2 */
480  DMA_CH_t CH3; /* DMA Channel 3 */
481 } DMA_t;
482 
483 /* Burst mode */
484 typedef enum DMA_CH_BURSTLEN_enum
485 {
486  DMA_CH_BURSTLEN_1BYTE_gc = (0x00<<0), /* 1-byte burst mode */
487  DMA_CH_BURSTLEN_2BYTE_gc = (0x01<<0), /* 2-byte burst mode */
488  DMA_CH_BURSTLEN_4BYTE_gc = (0x02<<0), /* 4-byte burst mode */
489  DMA_CH_BURSTLEN_8BYTE_gc = (0x03<<0), /* 8-byte burst mode */
490 } DMA_CH_BURSTLEN_t;
491 
492 /* Source address reload mode */
493 typedef enum DMA_CH_SRCRELOAD_enum
494 {
495  DMA_CH_SRCRELOAD_NONE_gc = (0x00<<6), /* No reload */
496  DMA_CH_SRCRELOAD_BLOCK_gc = (0x01<<6), /* Reload at end of block */
497  DMA_CH_SRCRELOAD_BURST_gc = (0x02<<6), /* Reload at end of burst */
498  DMA_CH_SRCRELOAD_TRANSACTION_gc = (0x03<<6), /* Reload at end of transaction */
499 } DMA_CH_SRCRELOAD_t;
500 
501 /* Source addressing mode */
502 typedef enum DMA_CH_SRCDIR_enum
503 {
504  DMA_CH_SRCDIR_FIXED_gc = (0x00<<4), /* Fixed */
505  DMA_CH_SRCDIR_INC_gc = (0x01<<4), /* Increment */
506  DMA_CH_SRCDIR_DEC_gc = (0x02<<4), /* Decrement */
507 } DMA_CH_SRCDIR_t;
508 
509 /* Destination adress reload mode */
510 typedef enum DMA_CH_DESTRELOAD_enum
511 {
512  DMA_CH_DESTRELOAD_NONE_gc = (0x00<<2), /* No reload */
513  DMA_CH_DESTRELOAD_BLOCK_gc = (0x01<<2), /* Reload at end of block */
514  DMA_CH_DESTRELOAD_BURST_gc = (0x02<<2), /* Reload at end of burst */
515  DMA_CH_DESTRELOAD_TRANSACTION_gc = (0x03<<2), /* Reload at end of transaction */
516 } DMA_CH_DESTRELOAD_t;
517 
518 /* Destination adressing mode */
519 typedef enum DMA_CH_DESTDIR_enum
520 {
521  DMA_CH_DESTDIR_FIXED_gc = (0x00<<0), /* Fixed */
522  DMA_CH_DESTDIR_INC_gc = (0x01<<0), /* Increment */
523  DMA_CH_DESTDIR_DEC_gc = (0x02<<0), /* Decrement */
524 } DMA_CH_DESTDIR_t;
525 
526 /* Transfer trigger source */
527 typedef enum DMA_CH_TRIGSRC_enum
528 {
529  DMA_CH_TRIGSRC_OFF_gc = (0x00<<0), /* Off software triggers only */
530  DMA_CH_TRIGSRC_EVSYS_CH0_gc = (0x01<<0), /* Event System Channel 0 */
531  DMA_CH_TRIGSRC_EVSYS_CH1_gc = (0x02<<0), /* Event System Channel 1 */
532  DMA_CH_TRIGSRC_EVSYS_CH2_gc = (0x03<<0), /* Event System Channel 2 */
533  DMA_CH_TRIGSRC_ADCA_CH0_gc = (0x10<<0), /* ADCA Channel 0 */
534  DMA_CH_TRIGSRC_ADCA_CH1_gc = (0x11<<0), /* ADCA Channel 1 */
535  DMA_CH_TRIGSRC_ADCA_CH2_gc = (0x12<<0), /* ADCA Channel 2 */
536  DMA_CH_TRIGSRC_ADCA_CH3_gc = (0x13<<0), /* ADCA Channel 3 */
537  DMA_CH_TRIGSRC_ADCA_CH4_gc = (0x14<<0), /* ADCA Channel 0,1,2,3 combined */
538  DMA_CH_TRIGSRC_DACA_CH0_gc = (0x15<<0), /* DACA Channel 0 */
539  DMA_CH_TRIGSRC_DACA_CH1_gc = (0x16<<0), /* DACA Channel 1 */
540  DMA_CH_TRIGSRC_ADCB_CH0_gc = (0x20<<0), /* ADCB Channel 0 */
541  DMA_CH_TRIGSRC_ADCB_CH1_gc = (0x21<<0), /* ADCB Channel 1 */
542  DMA_CH_TRIGSRC_ADCB_CH2_gc = (0x22<<0), /* ADCB Channel 2 */
543  DMA_CH_TRIGSRC_ADCB_CH3_gc = (0x23<<0), /* ADCB Channel 3 */
544  DMA_CH_TRIGSRC_ADCB_CH4_gc = (0x24<<0), /* ADCB Channel 0,1,2,3 combined */
545  DMA_CH_TRIGSRC_DACB_CH0_gc = (0x25<<0), /* DACB Channel 0 */
546  DMA_CH_TRIGSRC_DACB_CH1_gc = (0x26<<0), /* DACB Channel 1 */
547  DMA_CH_TRIGSRC_TCC0_OVF_gc = (0x40<<0), /* Timer/Counter C0 Overflow */
548  DMA_CH_TRIGSRC_TCC0_ERR_gc = (0x41<<0), /* Timer/Counter C0 Error */
549  DMA_CH_TRIGSRC_TCC0_CCA_gc = (0x42<<0), /* Timer/Counter C0 Compare or Capture A */
550  DMA_CH_TRIGSRC_TCC0_CCB_gc = (0x43<<0), /* Timer/Counter C0 Compare or Capture B */
551  DMA_CH_TRIGSRC_TCC0_CCC_gc = (0x44<<0), /* Timer/Counter C0 Compare or Capture C */
552  DMA_CH_TRIGSRC_TCC0_CCD_gc = (0x45<<0), /* Timer/Counter C0 Compare or Capture D */
553  DMA_CH_TRIGSRC_TCC1_OVF_gc = (0x46<<0), /* Timer/Counter C1 Overflow */
554  DMA_CH_TRIGSRC_TCC1_ERR_gc = (0x47<<0), /* Timer/Counter C1 Error */
555  DMA_CH_TRIGSRC_TCC1_CCA_gc = (0x48<<0), /* Timer/Counter C1 Compare or Capture A */
556  DMA_CH_TRIGSRC_TCC1_CCB_gc = (0x49<<0), /* Timer/Counter C1 Compare or Capture B */
557  DMA_CH_TRIGSRC_SPIC_gc = (0x4A<<0), /* SPI C Transfer Complete */
558  DMA_CH_TRIGSRC_USARTC0_RXC_gc = (0x4B<<0), /* USART C0 Receive Complete */
559  DMA_CH_TRIGSRC_USARTC0_DRE_gc = (0x4C<<0), /* USART C0 Data Register Empty */
560  DMA_CH_TRIGSRC_USARTC1_RXC_gc = (0x4E<<0), /* USART C1 Receive Complete */
561  DMA_CH_TRIGSRC_USARTC1_DRE_gc = (0x4F<<0), /* USART C1 Data Register Empty */
562  DMA_CH_TRIGSRC_TCD0_OVF_gc = (0x60<<0), /* Timer/Counter D0 Overflow */
563  DMA_CH_TRIGSRC_TCD0_ERR_gc = (0x61<<0), /* Timer/Counter D0 Error */
564  DMA_CH_TRIGSRC_TCD0_CCA_gc = (0x62<<0), /* Timer/Counter D0 Compare or Capture A */
565  DMA_CH_TRIGSRC_TCD0_CCB_gc = (0x63<<0), /* Timer/Counter D0 Compare or Capture B */
566  DMA_CH_TRIGSRC_TCD0_CCC_gc = (0x64<<0), /* Timer/Counter D0 Compare or Capture C */
567  DMA_CH_TRIGSRC_TCD0_CCD_gc = (0x65<<0), /* Timer/Counter D0 Compare or Capture D */
568  DMA_CH_TRIGSRC_TCD1_OVF_gc = (0x66<<0), /* Timer/Counter D1 Overflow */
569  DMA_CH_TRIGSRC_TCD1_ERR_gc = (0x67<<0), /* Timer/Counter D1 Error */
570  DMA_CH_TRIGSRC_TCD1_CCA_gc = (0x68<<0), /* Timer/Counter D1 Compare or Capture A */
571  DMA_CH_TRIGSRC_TCD1_CCB_gc = (0x69<<0), /* Timer/Counter D1 Compare or Capture B */
572  DMA_CH_TRIGSRC_SPID_gc = (0x6A<<0), /* SPI D Transfer Complete */
573  DMA_CH_TRIGSRC_USARTD0_RXC_gc = (0x6B<<0), /* USART D0 Receive Complete */
574  DMA_CH_TRIGSRC_USARTD0_DRE_gc = (0x6C<<0), /* USART D0 Data Register Empty */
575  DMA_CH_TRIGSRC_USARTD1_RXC_gc = (0x6E<<0), /* USART D1 Receive Complete */
576  DMA_CH_TRIGSRC_USARTD1_DRE_gc = (0x6F<<0), /* USART D1 Data Register Empty */
577  DMA_CH_TRIGSRC_TCE0_OVF_gc = (0x80<<0), /* Timer/Counter E0 Overflow */
578  DMA_CH_TRIGSRC_TCE0_ERR_gc = (0x81<<0), /* Timer/Counter E0 Error */
579  DMA_CH_TRIGSRC_TCE0_CCA_gc = (0x82<<0), /* Timer/Counter E0 Compare or Capture A */
580  DMA_CH_TRIGSRC_TCE0_CCB_gc = (0x83<<0), /* Timer/Counter E0 Compare or Capture B */
581  DMA_CH_TRIGSRC_TCE0_CCC_gc = (0x84<<0), /* Timer/Counter E0 Compare or Capture C */
582  DMA_CH_TRIGSRC_TCE0_CCD_gc = (0x85<<0), /* Timer/Counter E0 Compare or Capture D */
583  DMA_CH_TRIGSRC_TCE1_OVF_gc = (0x86<<0), /* Timer/Counter E1 Overflow */
584  DMA_CH_TRIGSRC_TCE1_ERR_gc = (0x87<<0), /* Timer/Counter E1 Error */
585  DMA_CH_TRIGSRC_TCE1_CCA_gc = (0x88<<0), /* Timer/Counter E1 Compare or Capture A */
586  DMA_CH_TRIGSRC_TCE1_CCB_gc = (0x89<<0), /* Timer/Counter E1 Compare or Capture B */
587  DMA_CH_TRIGSRC_SPIE_gc = (0x8A<<0), /* SPI E Transfer Complete */
588  DMA_CH_TRIGSRC_USARTE0_RXC_gc = (0x8B<<0), /* USART E0 Receive Complete */
589  DMA_CH_TRIGSRC_USARTE0_DRE_gc = (0x8C<<0), /* USART E0 Data Register Empty */
590  DMA_CH_TRIGSRC_USARTE1_RXC_gc = (0x8E<<0), /* USART E1 Receive Complete */
591  DMA_CH_TRIGSRC_USARTE1_DRE_gc = (0x8F<<0), /* USART E1 Data Register Empty */
592  DMA_CH_TRIGSRC_TCF0_OVF_gc = (0xA0<<0), /* Timer/Counter F0 Overflow */
593  DMA_CH_TRIGSRC_TCF0_ERR_gc = (0xA1<<0), /* Timer/Counter F0 Error */
594  DMA_CH_TRIGSRC_TCF0_CCA_gc = (0xA2<<0), /* Timer/Counter F0 Compare or Capture A */
595  DMA_CH_TRIGSRC_TCF0_CCB_gc = (0xA3<<0), /* Timer/Counter F0 Compare or Capture B */
596  DMA_CH_TRIGSRC_TCF0_CCC_gc = (0xA4<<0), /* Timer/Counter F0 Compare or Capture C */
597  DMA_CH_TRIGSRC_TCF0_CCD_gc = (0xA5<<0), /* Timer/Counter F0 Compare or Capture D */
598  DMA_CH_TRIGSRC_TCF1_OVF_gc = (0xA6<<0), /* Timer/Counter F1 Overflow */
599  DMA_CH_TRIGSRC_TCF1_ERR_gc = (0xA7<<0), /* Timer/Counter F1 Error */
600  DMA_CH_TRIGSRC_TCF1_CCA_gc = (0xA8<<0), /* Timer/Counter F1 Compare or Capture A */
601  DMA_CH_TRIGSRC_TCF1_CCB_gc = (0xA9<<0), /* Timer/Counter F1 Compare or Capture B */
602  DMA_CH_TRIGSRC_SPIF_gc = (0xAA<<0), /* SPI F Transfer Complete */
603  DMA_CH_TRIGSRC_USARTF0_RXC_gc = (0xAB<<0), /* USART F0 Receive Complete */
604  DMA_CH_TRIGSRC_USARTF0_DRE_gc = (0xAC<<0), /* USART F0 Data Register Empty */
605  DMA_CH_TRIGSRC_USARTF1_RXC_gc = (0xAE<<0), /* USART F1 Receive Complete */
606  DMA_CH_TRIGSRC_USARTF1_DRE_gc = (0xAF<<0), /* USART F1 Data Register Empty */
607 } DMA_CH_TRIGSRC_t;
608 
609 /* Double buffering mode */
610 typedef enum DMA_DBUFMODE_enum
611 {
612  DMA_DBUFMODE_DISABLED_gc = (0x00<<2), /* Double buffering disabled */
613  DMA_DBUFMODE_CH01_gc = (0x01<<2), /* Double buffering enabled on channel 0/1 */
614  DMA_DBUFMODE_CH23_gc = (0x02<<2), /* Double buffering enabled on channel 2/3 */
615  DMA_DBUFMODE_CH01CH23_gc = (0x03<<2), /* Double buffering enabled on ch. 0/1 and ch. 2/3 */
616 } DMA_DBUFMODE_t;
617 
618 /* Priority mode */
619 typedef enum DMA_PRIMODE_enum
620 {
621  DMA_PRIMODE_RR0123_gc = (0x00<<0), /* Round Robin */
622  DMA_PRIMODE_CH0RR123_gc = (0x01<<0), /* Channel 0 > Round Robin on channel 1/2/3 */
623  DMA_PRIMODE_CH01RR23_gc = (0x02<<0), /* Channel 0 > channel 1 > Round Robin on channel 2/3 */
624  DMA_PRIMODE_CH0123_gc = (0x03<<0), /* Channel 0 > channel 1 > channel 2 > channel 3 */
625 } DMA_PRIMODE_t;
626 
627 /* Interrupt level */
628 typedef enum DMA_CH_ERRINTLVL_enum
629 {
630  DMA_CH_ERRINTLVL_OFF_gc = (0x00<<2), /* Interrupt disabled */
631  DMA_CH_ERRINTLVL_LO_gc = (0x01<<2), /* Low level */
632  DMA_CH_ERRINTLVL_MED_gc = (0x02<<2), /* Medium level */
633  DMA_CH_ERRINTLVL_HI_gc = (0x03<<2), /* High level */
634 } DMA_CH_ERRINTLVL_t;
635 
636 /* Interrupt level */
637 typedef enum DMA_CH_TRNINTLVL_enum
638 {
639  DMA_CH_TRNINTLVL_OFF_gc = (0x00<<0), /* Interrupt disabled */
640  DMA_CH_TRNINTLVL_LO_gc = (0x01<<0), /* Low level */
641  DMA_CH_TRNINTLVL_MED_gc = (0x02<<0), /* Medium level */
642  DMA_CH_TRNINTLVL_HI_gc = (0x03<<0), /* High level */
643 } DMA_CH_TRNINTLVL_t;
644 
645 
646 /*
647 --------------------------------------------------------------------------
648 EVSYS - Event System
649 --------------------------------------------------------------------------
650 */
651 
652 /* Event System */
653 typedef struct EVSYS_struct
654 {
655  register8_t CH0MUX; /* Event Channel 0 Multiplexer */
656  register8_t CH1MUX; /* Event Channel 1 Multiplexer */
657  register8_t CH2MUX; /* Event Channel 2 Multiplexer */
658  register8_t CH3MUX; /* Event Channel 3 Multiplexer */
659  register8_t CH4MUX; /* Event Channel 4 Multiplexer */
660  register8_t CH5MUX; /* Event Channel 5 Multiplexer */
661  register8_t CH6MUX; /* Event Channel 6 Multiplexer */
662  register8_t CH7MUX; /* Event Channel 7 Multiplexer */
663  register8_t CH0CTRL; /* Channel 0 Control Register */
664  register8_t CH1CTRL; /* Channel 1 Control Register */
665  register8_t CH2CTRL; /* Channel 2 Control Register */
666  register8_t CH3CTRL; /* Channel 3 Control Register */
667  register8_t CH4CTRL; /* Channel 4 Control Register */
668  register8_t CH5CTRL; /* Channel 5 Control Register */
669  register8_t CH6CTRL; /* Channel 6 Control Register */
670  register8_t CH7CTRL; /* Channel 7 Control Register */
671  register8_t STROBE; /* Event Strobe */
672  register8_t DATA; /* Event Data */
673 } EVSYS_t;
674 
675 /* Quadrature Decoder Index Recognition Mode */
676 typedef enum EVSYS_QDIRM_enum
677 {
678  EVSYS_QDIRM_00_gc = (0x00<<5), /* QDPH0 = 0, QDPH90 = 0 */
679  EVSYS_QDIRM_01_gc = (0x01<<5), /* QDPH0 = 0, QDPH90 = 1 */
680  EVSYS_QDIRM_10_gc = (0x02<<5), /* QDPH0 = 1, QDPH90 = 0 */
681  EVSYS_QDIRM_11_gc = (0x03<<5), /* QDPH0 = 1, QDPH90 = 1 */
682 } EVSYS_QDIRM_t;
683 
684 /* Digital filter coefficient */
685 typedef enum EVSYS_DIGFILT_enum
686 {
687  EVSYS_DIGFILT_1SAMPLE_gc = (0x00<<0), /* 1 SAMPLE */
688  EVSYS_DIGFILT_2SAMPLES_gc = (0x01<<0), /* 2 SAMPLES */
689  EVSYS_DIGFILT_3SAMPLES_gc = (0x02<<0), /* 3 SAMPLES */
690  EVSYS_DIGFILT_4SAMPLES_gc = (0x03<<0), /* 4 SAMPLES */
691  EVSYS_DIGFILT_5SAMPLES_gc = (0x04<<0), /* 5 SAMPLES */
692  EVSYS_DIGFILT_6SAMPLES_gc = (0x05<<0), /* 6 SAMPLES */
693  EVSYS_DIGFILT_7SAMPLES_gc = (0x06<<0), /* 7 SAMPLES */
694  EVSYS_DIGFILT_8SAMPLES_gc = (0x07<<0), /* 8 SAMPLES */
695 } EVSYS_DIGFILT_t;
696 
697 /* Event Channel multiplexer input selection */
698 typedef enum EVSYS_CHMUX_enum
699 {
700  EVSYS_CHMUX_OFF_gc = (0x00<<0), /* Off */
701  EVSYS_CHMUX_RTC_OVF_gc = (0x08<<0), /* RTC Overflow */
702  EVSYS_CHMUX_RTC_CMP_gc = (0x09<<0), /* RTC Compare Match */
703  EVSYS_CHMUX_ACA_CH0_gc = (0x10<<0), /* Analog Comparator A Channel 0 */
704  EVSYS_CHMUX_ACA_CH1_gc = (0x11<<0), /* Analog Comparator A Channel 1 */
705  EVSYS_CHMUX_ACA_WIN_gc = (0x12<<0), /* Analog Comparator A Window */
706  EVSYS_CHMUX_ACB_CH0_gc = (0x13<<0), /* Analog Comparator B Channel 0 */
707  EVSYS_CHMUX_ACB_CH1_gc = (0x14<<0), /* Analog Comparator B Channel 1 */
708  EVSYS_CHMUX_ACB_WIN_gc = (0x15<<0), /* Analog Comparator B Window */
709  EVSYS_CHMUX_ADCA_CH0_gc = (0x20<<0), /* ADC A Channel 0 */
710  EVSYS_CHMUX_ADCA_CH1_gc = (0x21<<0), /* ADC A Channel 1 */
711  EVSYS_CHMUX_ADCA_CH2_gc = (0x22<<0), /* ADC A Channel 2 */
712  EVSYS_CHMUX_ADCA_CH3_gc = (0x23<<0), /* ADC A Channel 3 */
713  EVSYS_CHMUX_ADCB_CH0_gc = (0x24<<0), /* ADC B Channel 0 */
714  EVSYS_CHMUX_ADCB_CH1_gc = (0x25<<0), /* ADC B Channel 1 */
715  EVSYS_CHMUX_ADCB_CH2_gc = (0x26<<0), /* ADC B Channel 2 */
716  EVSYS_CHMUX_ADCB_CH3_gc = (0x27<<0), /* ADC B Channel 3 */
717  EVSYS_CHMUX_PORTA_PIN0_gc = (0x50<<0), /* Port A, Pin0 */
718  EVSYS_CHMUX_PORTA_PIN1_gc = (0x51<<0), /* Port A, Pin1 */
719  EVSYS_CHMUX_PORTA_PIN2_gc = (0x52<<0), /* Port A, Pin2 */
720  EVSYS_CHMUX_PORTA_PIN3_gc = (0x53<<0), /* Port A, Pin3 */
721  EVSYS_CHMUX_PORTA_PIN4_gc = (0x54<<0), /* Port A, Pin4 */
722  EVSYS_CHMUX_PORTA_PIN5_gc = (0x55<<0), /* Port A, Pin5 */
723  EVSYS_CHMUX_PORTA_PIN6_gc = (0x56<<0), /* Port A, Pin6 */
724  EVSYS_CHMUX_PORTA_PIN7_gc = (0x57<<0), /* Port A, Pin7 */
725  EVSYS_CHMUX_PORTB_PIN0_gc = (0x58<<0), /* Port B, Pin0 */
726  EVSYS_CHMUX_PORTB_PIN1_gc = (0x59<<0), /* Port B, Pin1 */
727  EVSYS_CHMUX_PORTB_PIN2_gc = (0x5A<<0), /* Port B, Pin2 */
728  EVSYS_CHMUX_PORTB_PIN3_gc = (0x5B<<0), /* Port B, Pin3 */
729  EVSYS_CHMUX_PORTB_PIN4_gc = (0x5C<<0), /* Port B, Pin4 */
730  EVSYS_CHMUX_PORTB_PIN5_gc = (0x5D<<0), /* Port B, Pin5 */
731  EVSYS_CHMUX_PORTB_PIN6_gc = (0x5E<<0), /* Port B, Pin6 */
732  EVSYS_CHMUX_PORTB_PIN7_gc = (0x5F<<0), /* Port B, Pin7 */
733  EVSYS_CHMUX_PORTC_PIN0_gc = (0x60<<0), /* Port C, Pin0 */
734  EVSYS_CHMUX_PORTC_PIN1_gc = (0x61<<0), /* Port C, Pin1 */
735  EVSYS_CHMUX_PORTC_PIN2_gc = (0x62<<0), /* Port C, Pin2 */
736  EVSYS_CHMUX_PORTC_PIN3_gc = (0x63<<0), /* Port C, Pin3 */
737  EVSYS_CHMUX_PORTC_PIN4_gc = (0x64<<0), /* Port C, Pin4 */
738  EVSYS_CHMUX_PORTC_PIN5_gc = (0x65<<0), /* Port C, Pin5 */
739  EVSYS_CHMUX_PORTC_PIN6_gc = (0x66<<0), /* Port C, Pin6 */
740  EVSYS_CHMUX_PORTC_PIN7_gc = (0x67<<0), /* Port C, Pin7 */
741  EVSYS_CHMUX_PORTD_PIN0_gc = (0x68<<0), /* Port D, Pin0 */
742  EVSYS_CHMUX_PORTD_PIN1_gc = (0x69<<0), /* Port D, Pin1 */
743  EVSYS_CHMUX_PORTD_PIN2_gc = (0x6A<<0), /* Port D, Pin2 */
744  EVSYS_CHMUX_PORTD_PIN3_gc = (0x6B<<0), /* Port D, Pin3 */
745  EVSYS_CHMUX_PORTD_PIN4_gc = (0x6C<<0), /* Port D, Pin4 */
746  EVSYS_CHMUX_PORTD_PIN5_gc = (0x6D<<0), /* Port D, Pin5 */
747  EVSYS_CHMUX_PORTD_PIN6_gc = (0x6E<<0), /* Port D, Pin6 */
748  EVSYS_CHMUX_PORTD_PIN7_gc = (0x6F<<0), /* Port D, Pin7 */
749  EVSYS_CHMUX_PORTE_PIN0_gc = (0x70<<0), /* Port E, Pin0 */
750  EVSYS_CHMUX_PORTE_PIN1_gc = (0x71<<0), /* Port E, Pin1 */
751  EVSYS_CHMUX_PORTE_PIN2_gc = (0x72<<0), /* Port E, Pin2 */
752  EVSYS_CHMUX_PORTE_PIN3_gc = (0x73<<0), /* Port E, Pin3 */
753  EVSYS_CHMUX_PORTE_PIN4_gc = (0x74<<0), /* Port E, Pin4 */
754  EVSYS_CHMUX_PORTE_PIN5_gc = (0x75<<0), /* Port E, Pin5 */
755  EVSYS_CHMUX_PORTE_PIN6_gc = (0x76<<0), /* Port E, Pin6 */
756  EVSYS_CHMUX_PORTE_PIN7_gc = (0x77<<0), /* Port E, Pin7 */
757  EVSYS_CHMUX_PORTF_PIN0_gc = (0x78<<0), /* Port F, Pin0 */
758  EVSYS_CHMUX_PORTF_PIN1_gc = (0x79<<0), /* Port F, Pin1 */
759  EVSYS_CHMUX_PORTF_PIN2_gc = (0x7A<<0), /* Port F, Pin2 */
760  EVSYS_CHMUX_PORTF_PIN3_gc = (0x7B<<0), /* Port F, Pin3 */
761  EVSYS_CHMUX_PORTF_PIN4_gc = (0x7C<<0), /* Port F, Pin4 */
762  EVSYS_CHMUX_PORTF_PIN5_gc = (0x7D<<0), /* Port F, Pin5 */
763  EVSYS_CHMUX_PORTF_PIN6_gc = (0x7E<<0), /* Port F, Pin6 */
764  EVSYS_CHMUX_PORTF_PIN7_gc = (0x7F<<0), /* Port F, Pin7 */
765  EVSYS_CHMUX_PRESCALER_1_gc = (0x80<<0), /* Prescaler, divide by 1 */
766  EVSYS_CHMUX_PRESCALER_2_gc = (0x81<<0), /* Prescaler, divide by 2 */
767  EVSYS_CHMUX_PRESCALER_4_gc = (0x82<<0), /* Prescaler, divide by 4 */
768  EVSYS_CHMUX_PRESCALER_8_gc = (0x83<<0), /* Prescaler, divide by 8 */
769  EVSYS_CHMUX_PRESCALER_16_gc = (0x84<<0), /* Prescaler, divide by 16 */
770  EVSYS_CHMUX_PRESCALER_32_gc = (0x85<<0), /* Prescaler, divide by 32 */
771  EVSYS_CHMUX_PRESCALER_64_gc = (0x86<<0), /* Prescaler, divide by 64 */
772  EVSYS_CHMUX_PRESCALER_128_gc = (0x87<<0), /* Prescaler, divide by 128 */
773  EVSYS_CHMUX_PRESCALER_256_gc = (0x88<<0), /* Prescaler, divide by 256 */
774  EVSYS_CHMUX_PRESCALER_512_gc = (0x89<<0), /* Prescaler, divide by 512 */
775  EVSYS_CHMUX_PRESCALER_1024_gc = (0x8A<<0), /* Prescaler, divide by 1024 */
776  EVSYS_CHMUX_PRESCALER_2048_gc = (0x8B<<0), /* Prescaler, divide by 2048 */
777  EVSYS_CHMUX_PRESCALER_4096_gc = (0x8C<<0), /* Prescaler, divide by 4096 */
778  EVSYS_CHMUX_PRESCALER_8192_gc = (0x8D<<0), /* Prescaler, divide by 8192 */
779  EVSYS_CHMUX_PRESCALER_16384_gc = (0x8E<<0), /* Prescaler, divide by 16384 */
780  EVSYS_CHMUX_PRESCALER_32768_gc = (0x8F<<0), /* Prescaler, divide by 32768 */
781  EVSYS_CHMUX_TCC0_OVF_gc = (0xC0<<0), /* Timer/Counter C0 Overflow */
782  EVSYS_CHMUX_TCC0_ERR_gc = (0xC1<<0), /* Timer/Counter C0 Error */
783  EVSYS_CHMUX_TCC0_CCA_gc = (0xC4<<0), /* Timer/Counter C0 Compare or Capture A */
784  EVSYS_CHMUX_TCC0_CCB_gc = (0xC5<<0), /* Timer/Counter C0 Compare or Capture B */
785  EVSYS_CHMUX_TCC0_CCC_gc = (0xC6<<0), /* Timer/Counter C0 Compare or Capture C */
786  EVSYS_CHMUX_TCC0_CCD_gc = (0xC7<<0), /* Timer/Counter C0 Compare or Capture D */
787  EVSYS_CHMUX_TCC1_OVF_gc = (0xC8<<0), /* Timer/Counter C1 Overflow */
788  EVSYS_CHMUX_TCC1_ERR_gc = (0xC9<<0), /* Timer/Counter C1 Error */
789  EVSYS_CHMUX_TCC1_CCA_gc = (0xCC<<0), /* Timer/Counter C1 Compare or Capture A */
790  EVSYS_CHMUX_TCC1_CCB_gc = (0xCD<<0), /* Timer/Counter C1 Compare or Capture B */
791  EVSYS_CHMUX_TCD0_OVF_gc = (0xD0<<0), /* Timer/Counter D0 Overflow */
792  EVSYS_CHMUX_TCD0_ERR_gc = (0xD1<<0), /* Timer/Counter D0 Error */
793  EVSYS_CHMUX_TCD0_CCA_gc = (0xD4<<0), /* Timer/Counter D0 Compare or Capture A */
794  EVSYS_CHMUX_TCD0_CCB_gc = (0xD5<<0), /* Timer/Counter D0 Compare or Capture B */
795  EVSYS_CHMUX_TCD0_CCC_gc = (0xD6<<0), /* Timer/Counter D0 Compare or Capture C */
796  EVSYS_CHMUX_TCD0_CCD_gc = (0xD7<<0), /* Timer/Counter D0 Compare or Capture D */
797  EVSYS_CHMUX_TCD1_OVF_gc = (0xD8<<0), /* Timer/Counter D1 Overflow */
798  EVSYS_CHMUX_TCD1_ERR_gc = (0xD9<<0), /* Timer/Counter D1 Error */
799  EVSYS_CHMUX_TCD1_CCA_gc = (0xDC<<0), /* Timer/Counter D1 Compare or Capture A */
800  EVSYS_CHMUX_TCD1_CCB_gc = (0xDD<<0), /* Timer/Counter D1 Compare or Capture B */
801  EVSYS_CHMUX_TCE0_OVF_gc = (0xE0<<0), /* Timer/Counter E0 Overflow */
802  EVSYS_CHMUX_TCE0_ERR_gc = (0xE1<<0), /* Timer/Counter E0 Error */
803  EVSYS_CHMUX_TCE0_CCA_gc = (0xE4<<0), /* Timer/Counter E0 Compare or Capture A */
804  EVSYS_CHMUX_TCE0_CCB_gc = (0xE5<<0), /* Timer/Counter E0 Compare or Capture B */
805  EVSYS_CHMUX_TCE0_CCC_gc = (0xE6<<0), /* Timer/Counter E0 Compare or Capture C */
806  EVSYS_CHMUX_TCE0_CCD_gc = (0xE7<<0), /* Timer/Counter E0 Compare or Capture D */
807  EVSYS_CHMUX_TCE1_OVF_gc = (0xE8<<0), /* Timer/Counter E1 Overflow */
808  EVSYS_CHMUX_TCE1_ERR_gc = (0xE9<<0), /* Timer/Counter E1 Error */
809  EVSYS_CHMUX_TCE1_CCA_gc = (0xEC<<0), /* Timer/Counter E1 Compare or Capture A */
810  EVSYS_CHMUX_TCE1_CCB_gc = (0xED<<0), /* Timer/Counter E1 Compare or Capture B */
811  EVSYS_CHMUX_TCF0_OVF_gc = (0xF0<<0), /* Timer/Counter F0 Overflow */
812  EVSYS_CHMUX_TCF0_ERR_gc = (0xF1<<0), /* Timer/Counter F0 Error */
813  EVSYS_CHMUX_TCF0_CCA_gc = (0xF4<<0), /* Timer/Counter F0 Compare or Capture A */
814  EVSYS_CHMUX_TCF0_CCB_gc = (0xF5<<0), /* Timer/Counter F0 Compare or Capture B */
815  EVSYS_CHMUX_TCF0_CCC_gc = (0xF6<<0), /* Timer/Counter F0 Compare or Capture C */
816  EVSYS_CHMUX_TCF0_CCD_gc = (0xF7<<0), /* Timer/Counter F0 Compare or Capture D */
817  EVSYS_CHMUX_TCF1_OVF_gc = (0xF8<<0), /* Timer/Counter F1 Overflow */
818  EVSYS_CHMUX_TCF1_ERR_gc = (0xF9<<0), /* Timer/Counter F1 Error */
819  EVSYS_CHMUX_TCF1_CCA_gc = (0xFC<<0), /* Timer/Counter F1 Compare or Capture A */
820  EVSYS_CHMUX_TCF1_CCB_gc = (0xFD<<0), /* Timer/Counter F1 Compare or Capture B */
821 } EVSYS_CHMUX_t;
822 
823 
824 /*
825 --------------------------------------------------------------------------
826 NVM - Non Volatile Memory Controller
827 --------------------------------------------------------------------------
828 */
829 
830 /* Non-volatile Memory Controller */
831 typedef struct NVM_struct
832 {
833  register8_t ADDR0; /* Address Register 0 */
834  register8_t ADDR1; /* Address Register 1 */
835  register8_t ADDR2; /* Address Register 2 */
836  register8_t reserved_0x03;
837  register8_t DATA0; /* Data Register 0 */
838  register8_t DATA1; /* Data Register 1 */
839  register8_t DATA2; /* Data Register 2 */
840  register8_t reserved_0x07;
841  register8_t reserved_0x08;
842  register8_t reserved_0x09;
843  register8_t CMD; /* Command */
844  register8_t CTRLA; /* Control Register A */
845  register8_t CTRLB; /* Control Register B */
846  register8_t INTCTRL; /* Interrupt Control */
847  register8_t reserved_0x0E;
848  register8_t STATUS; /* Status */
849  register8_t LOCKBITS; /* Lock Bits */
850 } NVM_t;
851 
852 /*
853 --------------------------------------------------------------------------
854 NVM - Non Volatile Memory Controller
855 --------------------------------------------------------------------------
856 */
857 
858 /* Lock Bits */
859 typedef struct NVM_LOCKBITS_struct
860 {
861  register8_t LOCKBITS; /* Lock Bits */
862 } NVM_LOCKBITS_t;
863 
864 /*
865 --------------------------------------------------------------------------
866 NVM - Non Volatile Memory Controller
867 --------------------------------------------------------------------------
868 */
869 
870 /* Fuses */
871 typedef struct NVM_FUSES_struct
872 {
873  register8_t FUSEBYTE0; /* User ID */
874  register8_t FUSEBYTE1; /* Watchdog Configuration */
875  register8_t FUSEBYTE2; /* Reset Configuration */
876  register8_t reserved_0x03;
877  register8_t FUSEBYTE4; /* Start-up Configuration */
878  register8_t FUSEBYTE5; /* EESAVE and BOD Level */
879 } NVM_FUSES_t;
880 
881 /*
882 --------------------------------------------------------------------------
883 NVM - Non Volatile Memory Controller
884 --------------------------------------------------------------------------
885 */
886 
887 /* Production Signatures */
888 typedef struct NVM_PROD_SIGNATURES_struct
889 {
890  register8_t RCOSC2M; /* RCOSC 2MHz Calibration Value */
891  register8_t reserved_0x01;
892  register8_t RCOSC32K; /* RCOSC 32kHz Calibration Value */
893  register8_t RCOSC32M; /* RCOSC 32MHz Calibration Value */
894  register8_t reserved_0x04;
895  register8_t reserved_0x05;
896  register8_t reserved_0x06;
897  register8_t reserved_0x07;
898  register8_t LOTNUM0; /* Lot Number Byte 0, ASCII */
899  register8_t LOTNUM1; /* Lot Number Byte 1, ASCII */
900  register8_t LOTNUM2; /* Lot Number Byte 2, ASCII */
901  register8_t LOTNUM3; /* Lot Number Byte 3, ASCII */
902  register8_t LOTNUM4; /* Lot Number Byte 4, ASCII */
903  register8_t LOTNUM5; /* Lot Number Byte 5, ASCII */
904  register8_t reserved_0x0E;
905  register8_t reserved_0x0F;
906  register8_t WAFNUM; /* Wafer Number */
907  register8_t reserved_0x11;
908  register8_t COORDX0; /* Wafer Coordinate X Byte 0 */
909  register8_t COORDX1; /* Wafer Coordinate X Byte 1 */
910  register8_t COORDY0; /* Wafer Coordinate Y Byte 0 */
911  register8_t COORDY1; /* Wafer Coordinate Y Byte 1 */
912  register8_t reserved_0x16;
913  register8_t reserved_0x17;
914  register8_t reserved_0x18;
915  register8_t reserved_0x19;
916  register8_t reserved_0x1A;
917  register8_t reserved_0x1B;
918  register8_t reserved_0x1C;
919  register8_t reserved_0x1D;
920  register8_t reserved_0x1E;
921  register8_t reserved_0x1F;
922  register8_t ADCACAL0; /* ADCA Calibration Byte 0 */
923  register8_t ADCACAL1; /* ADCA Calibration Byte 1 */
924  register8_t reserved_0x22;
925  register8_t reserved_0x23;
926  register8_t ADCBCAL0; /* ADCB Calibration Byte 0 */
927  register8_t ADCBCAL1; /* ADCB Calibration Byte 1 */
928  register8_t reserved_0x26;
929  register8_t reserved_0x27;
930  register8_t reserved_0x28;
931  register8_t reserved_0x29;
932  register8_t reserved_0x2A;
933  register8_t reserved_0x2B;
934  register8_t reserved_0x2C;
935  register8_t reserved_0x2D;
936  register8_t TEMPSENSE0; /* Temperature Sensor Calibration Byte 0 */
937  register8_t TEMPSENSE1; /* Temperature Sensor Calibration Byte 0 */
938  register8_t DACAOFFCAL; /* DACA Calibration Byte 0 */
939  register8_t DACAGAINCAL; /* DACA Calibration Byte 1 */
940  register8_t DACBOFFCAL; /* DACB Calibration Byte 0 */
941  register8_t DACBGAINCAL; /* DACB Calibration Byte 1 */
942  register8_t reserved_0x34;
943  register8_t reserved_0x35;
944  register8_t reserved_0x36;
945  register8_t reserved_0x37;
946  register8_t reserved_0x38;
947  register8_t reserved_0x39;
948  register8_t reserved_0x3A;
949  register8_t reserved_0x3B;
950  register8_t reserved_0x3C;
951  register8_t reserved_0x3D;
952  register8_t reserved_0x3E;
953 } NVM_PROD_SIGNATURES_t;
954 
955 /* NVM Command */
956 typedef enum NVM_CMD_enum
957 {
958  NVM_CMD_NO_OPERATION_gc = (0x00<<0), /* Noop/Ordinary LPM */
959  NVM_CMD_READ_CALIB_ROW_gc = (0x02<<0), /* Read calibration row */
960  NVM_CMD_READ_USER_SIG_ROW_gc = (0x01<<0), /* Read user signature row */
961  NVM_CMD_READ_EEPROM_gc = (0x06<<0), /* Read EEPROM */
962  NVM_CMD_READ_FUSES_gc = (0x07<<0), /* Read fuse byte */
963  NVM_CMD_WRITE_LOCK_BITS_gc = (0x08<<0), /* Write lock bits */
964  NVM_CMD_ERASE_USER_SIG_ROW_gc = (0x18<<0), /* Erase user signature row */
965  NVM_CMD_WRITE_USER_SIG_ROW_gc = (0x1A<<0), /* Write user signature row */
966  NVM_CMD_ERASE_APP_gc = (0x20<<0), /* Erase Application Section */
967  NVM_CMD_ERASE_APP_PAGE_gc = (0x22<<0), /* Erase Application Section page */
968  NVM_CMD_LOAD_FLASH_BUFFER_gc = (0x23<<0), /* Load Flash page buffer */
969  NVM_CMD_WRITE_APP_PAGE_gc = (0x24<<0), /* Write Application Section page */
970  NVM_CMD_ERASE_WRITE_APP_PAGE_gc = (0x25<<0), /* Erase-and-write Application Section page */
971  NVM_CMD_ERASE_FLASH_BUFFER_gc = (0x26<<0), /* Erase/flush Flash page buffer */
972  NVM_CMD_ERASE_BOOT_PAGE_gc = (0x2A<<0), /* Erase Boot Section page */
973  NVM_CMD_WRITE_BOOT_PAGE_gc = (0x2C<<0), /* Write Boot Section page */
974  NVM_CMD_ERASE_WRITE_BOOT_PAGE_gc = (0x2D<<0), /* Erase-and-write Boot Section page */
975  NVM_CMD_ERASE_EEPROM_gc = (0x30<<0), /* Erase EEPROM */
976  NVM_CMD_ERASE_EEPROM_PAGE_gc = (0x32<<0), /* Erase EEPROM page */
977  NVM_CMD_LOAD_EEPROM_BUFFER_gc = (0x33<<0), /* Load EEPROM page buffer */
978  NVM_CMD_WRITE_EEPROM_PAGE_gc = (0x34<<0), /* Write EEPROM page */
979  NVM_CMD_ERASE_WRITE_EEPROM_PAGE_gc = (0x35<<0), /* Erase-and-write EEPROM page */
980  NVM_CMD_ERASE_EEPROM_BUFFER_gc = (0x36<<0), /* Erase/flush EEPROM page buffer */
981  NVM_CMD_APP_CRC_gc = (0x38<<0), /* Generate Application section CRC */
982  NVM_CMD_BOOT_CRC_gc = (0x39<<0), /* Generate Boot Section CRC */
983  NVM_CMD_FLASH_RANGE_CRC_gc = (0x3A<<0), /* Generate Flash Range CRC */
984 } NVM_CMD_t;
985 
986 /* SPM ready interrupt level */
987 typedef enum NVM_SPMLVL_enum
988 {
989  NVM_SPMLVL_OFF_gc = (0x00<<2), /* Interrupt disabled */
990  NVM_SPMLVL_LO_gc = (0x01<<2), /* Low level */
991  NVM_SPMLVL_MED_gc = (0x02<<2), /* Medium level */
992  NVM_SPMLVL_HI_gc = (0x03<<2), /* High level */
993 } NVM_SPMLVL_t;
994 
995 /* EEPROM ready interrupt level */
996 typedef enum NVM_EELVL_enum
997 {
998  NVM_EELVL_OFF_gc = (0x00<<0), /* Interrupt disabled */
999  NVM_EELVL_LO_gc = (0x01<<0), /* Low level */
1000  NVM_EELVL_MED_gc = (0x02<<0), /* Medium level */
1001  NVM_EELVL_HI_gc = (0x03<<0), /* High level */
1002 } NVM_EELVL_t;
1003 
1004 /* Boot lock bits - boot setcion */
1005 typedef enum NVM_BLBB_enum
1006 {
1007  NVM_BLBB_NOLOCK_gc = (0x03<<6), /* No locks */
1008  NVM_BLBB_WLOCK_gc = (0x02<<6), /* Write not allowed */
1009  NVM_BLBB_RLOCK_gc = (0x01<<6), /* Read not allowed */
1010  NVM_BLBB_RWLOCK_gc = (0x00<<6), /* Read and write not allowed */
1011 } NVM_BLBB_t;
1012 
1013 /* Boot lock bits - application section */
1014 typedef enum NVM_BLBA_enum
1015 {
1016  NVM_BLBA_NOLOCK_gc = (0x03<<4), /* No locks */
1017  NVM_BLBA_WLOCK_gc = (0x02<<4), /* Write not allowed */
1018  NVM_BLBA_RLOCK_gc = (0x01<<4), /* Read not allowed */
1019  NVM_BLBA_RWLOCK_gc = (0x00<<4), /* Read and write not allowed */
1020 } NVM_BLBA_t;
1021 
1022 /* Boot lock bits - application table section */
1023 typedef enum NVM_BLBAT_enum
1024 {
1025  NVM_BLBAT_NOLOCK_gc = (0x03<<2), /* No locks */
1026  NVM_BLBAT_WLOCK_gc = (0x02<<2), /* Write not allowed */
1027  NVM_BLBAT_RLOCK_gc = (0x01<<2), /* Read not allowed */
1028  NVM_BLBAT_RWLOCK_gc = (0x00<<2), /* Read and write not allowed */
1029 } NVM_BLBAT_t;
1030 
1031 /* Lock bits */
1032 typedef enum NVM_LB_enum
1033 {
1034  NVM_LB_NOLOCK_gc = (0x03<<0), /* No locks */
1035  NVM_LB_WLOCK_gc = (0x02<<0), /* Write not allowed */
1036  NVM_LB_RWLOCK_gc = (0x00<<0), /* Read and write not allowed */
1037 } NVM_LB_t;
1038 
1039 /* Boot Loader Section Reset Vector */
1040 typedef enum BOOTRST_enum
1041 {
1042  BOOTRST_BOOTLDR_gc = (0x00<<6), /* Boot Loader Reset */
1043  BOOTRST_APPLICATION_gc = (0x01<<6), /* Application Reset */
1044 } BOOTRST_t;
1045 
1046 /* BOD operation */
1047 typedef enum BOD_enum
1048 {
1049  BOD_INSAMPLEDMODE_gc = (0x01<<0), /* BOD enabled in sampled mode */
1050  BOD_CONTINOUSLY_gc = (0x02<<0), /* BOD enabled continuously */
1051  BOD_DISABLED_gc = (0x03<<0), /* BOD Disabled */
1052 } BOD_t;
1053 
1054 /* Watchdog (Window) Timeout Period */
1055 typedef enum WD_enum
1056 {
1057  WD_8CLK_gc = (0x00<<4), /* 8 cycles (8ms @ 3.3V) */
1058  WD_16CLK_gc = (0x01<<4), /* 16 cycles (16ms @ 3.3V) */
1059  WD_32CLK_gc = (0x02<<4), /* 32 cycles (32ms @ 3.3V) */
1060  WD_64CLK_gc = (0x03<<4), /* 64 cycles (64ms @ 3.3V) */
1061  WD_128CLK_gc = (0x04<<4), /* 128 cycles (0.125s @ 3.3V) */
1062  WD_256CLK_gc = (0x05<<4), /* 256 cycles (0.25s @ 3.3V) */
1063  WD_512CLK_gc = (0x06<<4), /* 512 cycles (0.5s @ 3.3V) */
1064  WD_1KCLK_gc = (0x07<<4), /* 1K cycles (1s @ 3.3V) */
1065  WD_2KCLK_gc = (0x08<<4), /* 2K cycles (2s @ 3.3V) */
1066  WD_4KCLK_gc = (0x09<<4), /* 4K cycles (4s @ 3.3V) */
1067  WD_8KCLK_gc = (0x0A<<4), /* 8K cycles (8s @ 3.3V) */
1068 } WD_t;
1069 
1070 /* Start-up Time */
1071 typedef enum SUT_enum
1072 {
1073  SUT_0MS_gc = (0x03<<2), /* 0 ms */
1074  SUT_4MS_gc = (0x01<<2), /* 4 ms */
1075  SUT_64MS_gc = (0x00<<2), /* 64 ms */
1076 } SUT_t;
1077 
1078 /* Brown Out Detection Voltage Level */
1079 typedef enum BODLVL_enum
1080 {
1081  BODLVL_1V6_gc = (0x07<<0), /* 1.6 V */
1082  BODLVL_1V9_gc = (0x06<<0), /* 1.8 V */
1083  BODLVL_2V1_gc = (0x05<<0), /* 2.0 V */
1084  BODLVL_2V4_gc = (0x04<<0), /* 2.2 V */
1085  BODLVL_2V6_gc = (0x03<<0), /* 2.4 V */
1086  BODLVL_2V9_gc = (0x02<<0), /* 2.7 V */
1087  BODLVL_3V2_gc = (0x01<<0), /* 2.9 V */
1088 } BODLVL_t;
1089 
1090 
1091 /*
1092 --------------------------------------------------------------------------
1093 AC - Analog Comparator
1094 --------------------------------------------------------------------------
1095 */
1096 
1097 /* Analog Comparator */
1098 typedef struct AC_struct
1099 {
1100  register8_t AC0CTRL; /* Comparator 0 Control */
1101  register8_t AC1CTRL; /* Comparator 1 Control */
1102  register8_t AC0MUXCTRL; /* Comparator 0 MUX Control */
1103  register8_t AC1MUXCTRL; /* Comparator 1 MUX Control */
1104  register8_t CTRLA; /* Control Register A */
1105  register8_t CTRLB; /* Control Register B */
1106  register8_t WINCTRL; /* Window Mode Control */
1107  register8_t STATUS; /* Status */
1108 } AC_t;
1109 
1110 /* Interrupt mode */
1111 typedef enum AC_INTMODE_enum
1112 {
1113  AC_INTMODE_BOTHEDGES_gc = (0x00<<6), /* Interrupt on both edges */
1114  AC_INTMODE_FALLING_gc = (0x02<<6), /* Interrupt on falling edge */
1115  AC_INTMODE_RISING_gc = (0x03<<6), /* Interrupt on rising edge */
1116 } AC_INTMODE_t;
1117 
1118 /* Interrupt level */
1119 typedef enum AC_INTLVL_enum
1120 {
1121  AC_INTLVL_OFF_gc = (0x00<<4), /* Interrupt disabled */
1122  AC_INTLVL_LO_gc = (0x01<<4), /* Low level */
1123  AC_INTLVL_MED_gc = (0x02<<4), /* Medium level */
1124  AC_INTLVL_HI_gc = (0x03<<4), /* High level */
1125 } AC_INTLVL_t;
1126 
1127 /* Hysteresis mode selection */
1128 typedef enum AC_HYSMODE_enum
1129 {
1130  AC_HYSMODE_NO_gc = (0x00<<1), /* No hysteresis */
1131  AC_HYSMODE_SMALL_gc = (0x01<<1), /* Small hysteresis */
1132  AC_HYSMODE_LARGE_gc = (0x02<<1), /* Large hysteresis */
1133 } AC_HYSMODE_t;
1134 
1135 /* Positive input multiplexer selection */
1136 typedef enum AC_MUXPOS_enum
1137 {
1138  AC_MUXPOS_PIN0_gc = (0x00<<3), /* Pin 0 */
1139  AC_MUXPOS_PIN1_gc = (0x01<<3), /* Pin 1 */
1140  AC_MUXPOS_PIN2_gc = (0x02<<3), /* Pin 2 */
1141  AC_MUXPOS_PIN3_gc = (0x03<<3), /* Pin 3 */
1142  AC_MUXPOS_PIN4_gc = (0x04<<3), /* Pin 4 */
1143  AC_MUXPOS_PIN5_gc = (0x05<<3), /* Pin 5 */
1144  AC_MUXPOS_PIN6_gc = (0x06<<3), /* Pin 6 */
1145  AC_MUXPOS_DAC_gc = (0x07<<3), /* DAC output */
1146 } AC_MUXPOS_t;
1147 
1148 /* Negative input multiplexer selection */
1149 typedef enum AC_MUXNEG_enum
1150 {
1151  AC_MUXNEG_PIN0_gc = (0x00<<0), /* Pin 0 */
1152  AC_MUXNEG_PIN1_gc = (0x01<<0), /* Pin 1 */
1153  AC_MUXNEG_PIN3_gc = (0x02<<0), /* Pin 3 */
1154  AC_MUXNEG_PIN5_gc = (0x03<<0), /* Pin 5 */
1155  AC_MUXNEG_PIN7_gc = (0x04<<0), /* Pin 7 */
1156  AC_MUXNEG_DAC_gc = (0x05<<0), /* DAC output */
1157  AC_MUXNEG_BANDGAP_gc = (0x06<<0), /* Bandgap Reference */
1158  AC_MUXNEG_SCALER_gc = (0x07<<0), /* Internal voltage scaler */
1159 } AC_MUXNEG_t;
1160 
1161 /* Windows interrupt mode */
1162 typedef enum AC_WINTMODE_enum
1163 {
1164  AC_WINTMODE_ABOVE_gc = (0x00<<2), /* Interrupt on above window */
1165  AC_WINTMODE_INSIDE_gc = (0x01<<2), /* Interrupt on inside window */
1166  AC_WINTMODE_BELOW_gc = (0x02<<2), /* Interrupt on below window */
1167  AC_WINTMODE_OUTSIDE_gc = (0x03<<2), /* Interrupt on outside window */
1168 } AC_WINTMODE_t;
1169 
1170 /* Window interrupt level */
1171 typedef enum AC_WINTLVL_enum
1172 {
1173  AC_WINTLVL_OFF_gc = (0x00<<0), /* Interrupt disabled */
1174  AC_WINTLVL_LO_gc = (0x01<<0), /* Low priority */
1175  AC_WINTLVL_MED_gc = (0x02<<0), /* Medium priority */
1176  AC_WINTLVL_HI_gc = (0x03<<0), /* High priority */
1177 } AC_WINTLVL_t;
1178 
1179 /* Window mode state */
1180 typedef enum AC_WSTATE_enum
1181 {
1182  AC_WSTATE_ABOVE_gc = (0x00<<6), /* Signal above window */
1183  AC_WSTATE_INSIDE_gc = (0x01<<6), /* Signal inside window */
1184  AC_WSTATE_BELOW_gc = (0x02<<6), /* Signal below window */
1185 } AC_WSTATE_t;
1186 
1187 
1188 /*
1189 --------------------------------------------------------------------------
1190 ADC - Analog/Digital Converter
1191 --------------------------------------------------------------------------
1192 */
1193 
1194 /* ADC Channel */
1195 typedef struct ADC_CH_struct
1196 {
1197  register8_t CTRL; /* Control Register */
1198  register8_t MUXCTRL; /* MUX Control */
1199  register8_t INTCTRL; /* Channel Interrupt Control */
1200  register8_t INTFLAGS; /* Interrupt Flags */
1201  _WORDREGISTER(RES); /* Channel Result */
1202  register8_t reserved_0x6;
1203  register8_t reserved_0x7;
1204 } ADC_CH_t;
1205 
1206 /*
1207 --------------------------------------------------------------------------
1208 ADC - Analog/Digital Converter
1209 --------------------------------------------------------------------------
1210 */
1211 
1212 /* Analog-to-Digital Converter */
1213 typedef struct ADC_struct
1214 {
1215  register8_t CTRLA; /* Control Register A */
1216  register8_t CTRLB; /* Control Register B */
1217  register8_t REFCTRL; /* Reference Control */
1218  register8_t EVCTRL; /* Event Control */
1219  register8_t PRESCALER; /* Clock Prescaler */
1220  register8_t CALCTRL; /* Calibration Control Register */
1221  register8_t INTFLAGS; /* Interrupt Flags */
1222  register8_t reserved_0x07;
1223  register8_t reserved_0x08;
1224  register8_t reserved_0x09;
1225  register8_t reserved_0x0A;
1226  register8_t reserved_0x0B;
1227  _WORDREGISTER(CAL); /* Calibration Value */
1228  register8_t reserved_0x0E;
1229  register8_t reserved_0x0F;
1230  _WORDREGISTER(CH0RES); /* Channel 0 Result */
1231  _WORDREGISTER(CH1RES); /* Channel 1 Result */
1232  _WORDREGISTER(CH2RES); /* Channel 2 Result */
1233  _WORDREGISTER(CH3RES); /* Channel 3 Result */
1234  _WORDREGISTER(CMP); /* Compare Value */
1235  register8_t reserved_0x1A;
1236  register8_t reserved_0x1B;
1237  register8_t reserved_0x1C;
1238  register8_t reserved_0x1D;
1239  register8_t reserved_0x1E;
1240  register8_t reserved_0x1F;
1241  ADC_CH_t CH0; /* ADC Channel 0 */
1242  ADC_CH_t CH1; /* ADC Channel 1 */
1243  ADC_CH_t CH2; /* ADC Channel 2 */
1244  ADC_CH_t CH3; /* ADC Channel 3 */
1245 } ADC_t;
1246 
1247 /* Positive input multiplexer selection */
1248 typedef enum ADC_CH_MUXPOS_enum
1249 {
1250  ADC_CH_MUXPOS_PIN0_gc = (0x00<<3), /* Input pin 0 */
1251  ADC_CH_MUXPOS_PIN1_gc = (0x01<<3), /* Input pin 1 */
1252  ADC_CH_MUXPOS_PIN2_gc = (0x02<<3), /* Input pin 2 */
1253  ADC_CH_MUXPOS_PIN3_gc = (0x03<<3), /* Input pin 3 */
1254  ADC_CH_MUXPOS_PIN4_gc = (0x04<<3), /* Input pin 4 */
1255  ADC_CH_MUXPOS_PIN5_gc = (0x05<<3), /* Input pin 5 */
1256  ADC_CH_MUXPOS_PIN6_gc = (0x06<<3), /* Input pin 6 */
1257  ADC_CH_MUXPOS_PIN7_gc = (0x07<<3), /* Input pin 7 */
1258 } ADC_CH_MUXPOS_t;
1259 
1260 /* Internal input multiplexer selections */
1261 typedef enum ADC_CH_MUXINT_enum
1262 {
1263  ADC_CH_MUXINT_TEMP_gc = (0x00<<3), /* Temperature Reference */
1264  ADC_CH_MUXINT_BANDGAP_gc = (0x01<<3), /* Bandgap Reference */
1265  ADC_CH_MUXINT_SCALEDVCC_gc = (0x02<<3), /* 1/10 scaled VCC */
1266  ADC_CH_MUXINT_DAC_gc = (0x03<<3), /* DAC output */
1267 } ADC_CH_MUXINT_t;
1268 
1269 /* Negative input multiplexer selection */
1270 typedef enum ADC_CH_MUXNEG_enum
1271 {
1272  ADC_CH_MUXNEG_PIN0_gc = (0x00<<0), /* Input pin 0 */
1273  ADC_CH_MUXNEG_PIN1_gc = (0x01<<0), /* Input pin 1 */
1274  ADC_CH_MUXNEG_PIN2_gc = (0x02<<0), /* Input pin 2 */
1275  ADC_CH_MUXNEG_PIN3_gc = (0x03<<0), /* Input pin 3 */
1276  ADC_CH_MUXNEG_PIN4_gc = (0x04<<0), /* Input pin 4 */
1277  ADC_CH_MUXNEG_PIN5_gc = (0x05<<0), /* Input pin 5 */
1278  ADC_CH_MUXNEG_PIN6_gc = (0x06<<0), /* Input pin 6 */
1279  ADC_CH_MUXNEG_PIN7_gc = (0x07<<0), /* Input pin 7 */
1280 } ADC_CH_MUXNEG_t;
1281 
1282 /* Input mode */
1283 typedef enum ADC_CH_INPUTMODE_enum
1284 {
1285  ADC_CH_INPUTMODE_INTERNAL_gc = (0x00<<0), /* Internal inputs, no gain */
1286  ADC_CH_INPUTMODE_SINGLEENDED_gc = (0x01<<0), /* Single-ended input, no gain */
1287  ADC_CH_INPUTMODE_DIFF_gc = (0x02<<0), /* Differential input, no gain */
1288  ADC_CH_INPUTMODE_DIFFWGAIN_gc = (0x03<<0), /* Differential input, with gain */
1289 } ADC_CH_INPUTMODE_t;
1290 
1291 /* Gain factor */
1292 typedef enum ADC_CH_GAIN_enum
1293 {
1294  ADC_CH_GAIN_1X_gc = (0x00<<2), /* 1x gain */
1295  ADC_CH_GAIN_2X_gc = (0x01<<2), /* 2x gain */
1296  ADC_CH_GAIN_4X_gc = (0x02<<2), /* 4x gain */
1297  ADC_CH_GAIN_8X_gc = (0x03<<2), /* 8x gain */
1298  ADC_CH_GAIN_16X_gc = (0x04<<2), /* 16x gain */
1299  ADC_CH_GAIN_32X_gc = (0x05<<2), /* 32x gain */
1300  ADC_CH_GAIN_64X_gc = (0x06<<2), /* 64x gain */
1301 } ADC_CH_GAIN_t;
1302 
1303 /* Conversion result resolution */
1304 typedef enum ADC_RESOLUTION_enum
1305 {
1306  ADC_RESOLUTION_12BIT_gc = (0x00<<1), /* 12-bit right-adjusted result */
1307  ADC_RESOLUTION_8BIT_gc = (0x02<<1), /* 8-bit right-adjusted result */
1308  ADC_RESOLUTION_LEFT12BIT_gc = (0x03<<1), /* 12-bit left-adjusted result */
1309 } ADC_RESOLUTION_t;
1310 
1311 /* Voltage reference selection */
1312 typedef enum ADC_REFSEL_enum
1313 {
1314  ADC_REFSEL_INT1V_gc = (0x00<<4), /* Internal 1V */
1315  ADC_REFSEL_VCC_gc = (0x01<<4), /* Internal VCC / 1.6V */
1316  ADC_REFSEL_AREFA_gc = (0x02<<4), /* External reference on PORT A */
1317  ADC_REFSEL_AREFB_gc = (0x03<<4), /* External reference on PORT B */
1318 } ADC_REFSEL_t;
1319 
1320 /* Channel sweep selection */
1321 typedef enum ADC_SWEEP_enum
1322 {
1323  ADC_SWEEP_0_gc = (0x00<<6), /* ADC Channel 0 */
1324  ADC_SWEEP_01_gc = (0x01<<6), /* ADC Channel 0,1 */
1325  ADC_SWEEP_012_gc = (0x02<<6), /* ADC Channel 0,1,2 */
1326  ADC_SWEEP_0123_gc = (0x03<<6), /* ADC Channel 0,1,2,3 */
1327 } ADC_SWEEP_t;
1328 
1329 /* Event channel input selection */
1330 typedef enum ADC_EVSEL_enum
1331 {
1332  ADC_EVSEL_0123_gc = (0x00<<3), /* Event Channel 0,1,2,3 */
1333  ADC_EVSEL_1234_gc = (0x01<<3), /* Event Channel 1,2,3,4 */
1334  ADC_EVSEL_2345_gc = (0x02<<3), /* Event Channel 2,3,4,5 */
1335  ADC_EVSEL_3456_gc = (0x03<<3), /* Event Channel 3,4,5,6 */
1336  ADC_EVSEL_4567_gc = (0x04<<3), /* Event Channel 4,5,6,7 */
1337  ADC_EVSEL_567_gc = (0x05<<3), /* Event Channel 5,6,7 */
1338  ADC_EVSEL_67_gc = (0x06<<3), /* Event Channel 6,7 */
1339  ADC_EVSEL_7_gc = (0x07<<3), /* Event Channel 7 */
1340 } ADC_EVSEL_t;
1341 
1342 /* Event action selection */
1343 typedef enum ADC_EVACT_enum
1344 {
1345  ADC_EVACT_NONE_gc = (0x00<<0), /* No event action */
1346  ADC_EVACT_CH0_gc = (0x01<<0), /* First event triggers channel 0 */
1347  ADC_EVACT_CH01_gc = (0x02<<0), /* First two events trigger channel 0,1 */
1348  ADC_EVACT_CH012_gc = (0x03<<0), /* First three events trigger channel 0,1,2 */
1349  ADC_EVACT_CH0123_gc = (0x04<<0), /* Events trigger channel 0,1,2,3 */
1350  ADC_EVACT_SWEEP_gc = (0x05<<0), /* First event triggers sweep */
1351  ADC_EVACT_SYNCHSWEEP_gc = (0x06<<0), /* First event triggers synchronized sweep */
1352 } ADC_EVACT_t;
1353 
1354 /* Interupt mode */
1355 typedef enum ADC_CH_INTMODE_enum
1356 {
1357  ADC_CH_INTMODE_COMPLETE_gc = (0x00<<2), /* Interrupt on conversion complete */
1358  ADC_CH_INTMODE_BELOW_gc = (0x01<<2), /* Interrupt on result below compare value */
1359  ADC_CH_INTMODE_ABOVE_gc = (0x03<<2), /* Interrupt on result above compare value */
1360 } ADC_CH_INTMODE_t;
1361 
1362 /* Interrupt level */
1363 typedef enum ADC_CH_INTLVL_enum
1364 {
1365  ADC_CH_INTLVL_OFF_gc = (0x00<<0), /* Interrupt disabled */
1366  ADC_CH_INTLVL_LO_gc = (0x01<<0), /* Low level */
1367  ADC_CH_INTLVL_MED_gc = (0x02<<0), /* Medium level */
1368  ADC_CH_INTLVL_HI_gc = (0x03<<0), /* High level */
1369 } ADC_CH_INTLVL_t;
1370 
1371 /* DMA request selection */
1372 typedef enum ADC_DMASEL_enum
1373 {
1374  ADC_DMASEL_OFF_gc = (0x00<<6), /* Combined DMA request OFF */
1375  ADC_DMASEL_CH01_gc = (0x01<<6), /* ADC Channel 0 or 1 */
1376  ADC_DMASEL_CH012_gc = (0x02<<6), /* ADC Channel 0 or 1 or 2 */
1377  ADC_DMASEL_CH0123_gc = (0x03<<6), /* ADC Channel 0 or 1 or 2 or 3 */
1378 } ADC_DMASEL_t;
1379 
1380 /* Clock prescaler */
1381 typedef enum ADC_PRESCALER_enum
1382 {
1383  ADC_PRESCALER_DIV4_gc = (0x00<<0), /* Divide clock by 4 */
1384  ADC_PRESCALER_DIV8_gc = (0x01<<0), /* Divide clock by 8 */
1385  ADC_PRESCALER_DIV16_gc = (0x02<<0), /* Divide clock by 16 */
1386  ADC_PRESCALER_DIV32_gc = (0x03<<0), /* Divide clock by 32 */
1387  ADC_PRESCALER_DIV64_gc = (0x04<<0), /* Divide clock by 64 */
1388  ADC_PRESCALER_DIV128_gc = (0x05<<0), /* Divide clock by 128 */
1389  ADC_PRESCALER_DIV256_gc = (0x06<<0), /* Divide clock by 256 */
1390  ADC_PRESCALER_DIV512_gc = (0x07<<0), /* Divide clock by 512 */
1391 } ADC_PRESCALER_t;
1392 
1393 
1394 /*
1395 --------------------------------------------------------------------------
1396 DAC - Digital/Analog Converter
1397 --------------------------------------------------------------------------
1398 */
1399 
1400 /* Digital-to-Analog Converter */
1401 typedef struct DAC_struct
1402 {
1403  register8_t CTRLA; /* Control Register A */
1404  register8_t CTRLB; /* Control Register B */
1405  register8_t CTRLC; /* Control Register C */
1406  register8_t EVCTRL; /* Event Input Control */
1407  register8_t TIMCTRL; /* Timing Control */
1408  register8_t STATUS; /* Status */
1409  register8_t reserved_0x06;
1410  register8_t reserved_0x07;
1411  register8_t GAINCAL; /* Gain Calibration */
1412  register8_t OFFSETCAL; /* Offset Calibration */
1413  register8_t reserved_0x0A;
1414  register8_t reserved_0x0B;
1415  register8_t reserved_0x0C;
1416  register8_t reserved_0x0D;
1417  register8_t reserved_0x0E;
1418  register8_t reserved_0x0F;
1419  register8_t reserved_0x10;
1420  register8_t reserved_0x11;
1421  register8_t reserved_0x12;
1422  register8_t reserved_0x13;
1423  register8_t reserved_0x14;
1424  register8_t reserved_0x15;
1425  register8_t reserved_0x16;
1426  register8_t reserved_0x17;
1427  _WORDREGISTER(CH0DATA); /* Channel 0 Data */
1428  _WORDREGISTER(CH1DATA); /* Channel 1 Data */
1429 } DAC_t;
1430 
1431 /* Output channel selection */
1432 typedef enum DAC_CHSEL_enum
1433 {
1434  DAC_CHSEL_SINGLE_gc = (0x00<<5), /* Single channel operation (Channel A only) */
1435  DAC_CHSEL_DUAL_gc = (0x02<<5), /* Dual channel operation (S/H on both channels) */
1436 } DAC_CHSEL_t;
1437 
1438 /* Reference voltage selection */
1439 typedef enum DAC_REFSEL_enum
1440 {
1441  DAC_REFSEL_INT1V_gc = (0x00<<3), /* Internal 1V */
1442  DAC_REFSEL_AVCC_gc = (0x01<<3), /* Analog supply voltage */
1443  DAC_REFSEL_AREFA_gc = (0x02<<3), /* External reference on AREF on PORTA */
1444  DAC_REFSEL_AREFB_gc = (0x03<<3), /* External reference on AREF on PORTB */
1445 } DAC_REFSEL_t;
1446 
1447 /* Event channel selection */
1448 typedef enum DAC_EVSEL_enum
1449 {
1450  DAC_EVSEL_0_gc = (0x00<<0), /* Event Channel 0 */
1451  DAC_EVSEL_1_gc = (0x01<<0), /* Event Channel 1 */
1452  DAC_EVSEL_2_gc = (0x02<<0), /* Event Channel 2 */
1453  DAC_EVSEL_3_gc = (0x03<<0), /* Event Channel 3 */
1454  DAC_EVSEL_4_gc = (0x04<<0), /* Event Channel 4 */
1455  DAC_EVSEL_5_gc = (0x05<<0), /* Event Channel 5 */
1456  DAC_EVSEL_6_gc = (0x06<<0), /* Event Channel 6 */
1457  DAC_EVSEL_7_gc = (0x07<<0), /* Event Channel 7 */
1458 } DAC_EVSEL_t;
1459 
1460 /* Conversion interval */
1461 typedef enum DAC_CONINTVAL_enum
1462 {
1463  DAC_CONINTVAL_1CLK_gc = (0x00<<4), /* 1 CLK / 2 CLK in S/H mode */
1464  DAC_CONINTVAL_2CLK_gc = (0x01<<4), /* 2 CLK / 3 CLK in S/H mode */
1465  DAC_CONINTVAL_4CLK_gc = (0x02<<4), /* 4 CLK / 6 CLK in S/H mode */
1466  DAC_CONINTVAL_8CLK_gc = (0x03<<4), /* 8 CLK / 12 CLK in S/H mode */
1467  DAC_CONINTVAL_16CLK_gc = (0x04<<4), /* 16 CLK / 24 CLK in S/H mode */
1468  DAC_CONINTVAL_32CLK_gc = (0x05<<4), /* 32 CLK / 48 CLK in S/H mode */
1469  DAC_CONINTVAL_64CLK_gc = (0x06<<4), /* 64 CLK / 96 CLK in S/H mode */
1470  DAC_CONINTVAL_128CLK_gc = (0x07<<4), /* 128 CLK / 192 CLK in S/H mode */
1471 } DAC_CONINTVAL_t;
1472 
1473 /* Refresh rate */
1474 typedef enum DAC_REFRESH_enum
1475 {
1476  DAC_REFRESH_16CLK_gc = (0x00<<0), /* 16 CLK */
1477  DAC_REFRESH_32CLK_gc = (0x01<<0), /* 32 CLK */
1478  DAC_REFRESH_64CLK_gc = (0x02<<0), /* 64 CLK */
1479  DAC_REFRESH_128CLK_gc = (0x03<<0), /* 128 CLK */
1480  DAC_REFRESH_256CLK_gc = (0x04<<0), /* 256 CLK */
1481  DAC_REFRESH_512CLK_gc = (0x05<<0), /* 512 CLK */
1482  DAC_REFRESH_1024CLK_gc = (0x06<<0), /* 1024 CLK */
1483  DAC_REFRESH_2048CLK_gc = (0x07<<0), /* 2048 CLK */
1484  DAC_REFRESH_4086CLK_gc = (0x08<<0), /* 4096 CLK */
1485  DAC_REFRESH_8192CLK_gc = (0x09<<0), /* 8192 CLK */
1486  DAC_REFRESH_16384CLK_gc = (0x0A<<0), /* 16384 CLK */
1487  DAC_REFRESH_32768CLK_gc = (0x0B<<0), /* 32768 CLK */
1488  DAC_REFRESH_65536CLK_gc = (0x0C<<0), /* 65536 CLK */
1489  DAC_REFRESH_OFF_gc = (0x0F<<0), /* Auto refresh OFF */
1490 } DAC_REFRESH_t;
1491 
1492 
1493 /*
1494 --------------------------------------------------------------------------
1495 RTC - Real-Time Clounter
1496 --------------------------------------------------------------------------
1497 */
1498 
1499 /* Real-Time Counter */
1500 typedef struct RTC_struct
1501 {
1502  register8_t CTRL; /* Control Register */
1503  register8_t STATUS; /* Status Register */
1504  register8_t INTCTRL; /* Interrupt Control Register */
1505  register8_t INTFLAGS; /* Interrupt Flags */
1506  register8_t TEMP; /* Temporary register */
1507  register8_t reserved_0x05;
1508  register8_t reserved_0x06;
1509  register8_t reserved_0x07;
1510  _WORDREGISTER(CNT); /* Count Register */
1511  _WORDREGISTER(PER); /* Period Register */
1512  _WORDREGISTER(COMP); /* Compare Register */
1513 } RTC_t;
1514 
1515 /* Prescaler Factor */
1516 typedef enum RTC_PRESCALER_enum
1517 {
1518  RTC_PRESCALER_OFF_gc = (0x00<<0), /* RTC Off */
1519  RTC_PRESCALER_DIV1_gc = (0x01<<0), /* RTC Clock */
1520  RTC_PRESCALER_DIV2_gc = (0x02<<0), /* RTC Clock / 2 */
1521  RTC_PRESCALER_DIV8_gc = (0x03<<0), /* RTC Clock / 8 */
1522  RTC_PRESCALER_DIV16_gc = (0x04<<0), /* RTC Clock / 16 */
1523  RTC_PRESCALER_DIV64_gc = (0x05<<0), /* RTC Clock / 64 */
1524  RTC_PRESCALER_DIV256_gc = (0x06<<0), /* RTC Clock / 256 */
1525  RTC_PRESCALER_DIV1024_gc = (0x07<<0), /* RTC Clock / 1024 */
1526 } RTC_PRESCALER_t;
1527 
1528 /* Compare Interrupt level */
1529 typedef enum RTC_COMPINTLVL_enum
1530 {
1531  RTC_COMPINTLVL_OFF_gc = (0x00<<2), /* Interrupt Disabled */
1532  RTC_COMPINTLVL_LO_gc = (0x01<<2), /* Low Level */
1533  RTC_COMPINTLVL_MED_gc = (0x02<<2), /* Medium Level */
1534  RTC_COMPINTLVL_HI_gc = (0x03<<2), /* High Level */
1535 } RTC_COMPINTLVL_t;
1536 
1537 /* Overflow Interrupt level */
1538 typedef enum RTC_OVFINTLVL_enum
1539 {
1540  RTC_OVFINTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */
1541  RTC_OVFINTLVL_LO_gc = (0x01<<0), /* Low Level */
1542  RTC_OVFINTLVL_MED_gc = (0x02<<0), /* Medium Level */
1543  RTC_OVFINTLVL_HI_gc = (0x03<<0), /* High Level */
1544 } RTC_OVFINTLVL_t;
1545 
1546 
1547 /*
1548 --------------------------------------------------------------------------
1549 EBI - External Bus Interface
1550 --------------------------------------------------------------------------
1551 */
1552 
1553 /* EBI Chip Select Module */
1554 typedef struct EBI_CS_struct
1555 {
1556  register8_t CTRLA; /* Chip Select Control Register A */
1557  register8_t CTRLB; /* Chip Select Control Register B */
1558  _WORDREGISTER(BASEADDR); /* Chip Select Base Address */
1559 } EBI_CS_t;
1560 
1561 /*
1562 --------------------------------------------------------------------------
1563 EBI - External Bus Interface
1564 --------------------------------------------------------------------------
1565 */
1566 
1567 /* External Bus Interface */
1568 typedef struct EBI_struct
1569 {
1570  register8_t CTRL; /* Control */
1571  register8_t SDRAMCTRLA; /* SDRAM Control Register A */
1572  register8_t reserved_0x02;
1573  register8_t reserved_0x03;
1574  _WORDREGISTER(REFRESH); /* SDRAM Refresh Period */
1575  _WORDREGISTER(INITDLY); /* SDRAM Initialization Delay */
1576  register8_t SDRAMCTRLB; /* SDRAM Control Register B */
1577  register8_t SDRAMCTRLC; /* SDRAM Control Register C */
1578  register8_t reserved_0x0A;
1579  register8_t reserved_0x0B;
1580  register8_t reserved_0x0C;
1581  register8_t reserved_0x0D;
1582  register8_t reserved_0x0E;
1583  register8_t reserved_0x0F;
1584  EBI_CS_t CS0; /* Chip Select 0 */
1585  EBI_CS_t CS1; /* Chip Select 1 */
1586  EBI_CS_t CS2; /* Chip Select 2 */
1587  EBI_CS_t CS3; /* Chip Select 3 */
1588 } EBI_t;
1589 
1590 /* Chip Select adress space */
1591 typedef enum EBI_CS_ASPACE_enum
1592 {
1593  EBI_CS_ASPACE_256B_gc = (0x00<<2), /* 256 bytes */
1594  EBI_CS_ASPACE_512B_gc = (0x01<<2), /* 512 bytes */
1595  EBI_CS_ASPACE_1KB_gc = (0x02<<2), /* 1K bytes */
1596  EBI_CS_ASPACE_2KB_gc = (0x03<<2), /* 2K bytes */
1597  EBI_CS_ASPACE_4KB_gc = (0x04<<2), /* 4K bytes */
1598  EBI_CS_ASPACE_8KB_gc = (0x05<<2), /* 8K bytes */
1599  EBI_CS_ASPACE_16KB_gc = (0x06<<2), /* 16K bytes */
1600  EBI_CS_ASPACE_32KB_gc = (0x07<<2), /* 32K bytes */
1601  EBI_CS_ASPACE_64KB_gc = (0x08<<2), /* 64K bytes */
1602  EBI_CS_ASPACE_128KB_gc = (0x09<<2), /* 128K bytes */
1603  EBI_CS_ASPACE_256KB_gc = (0x0A<<2), /* 256K bytes */
1604  EBI_CS_ASPACE_512KB_gc = (0x0B<<2), /* 512K bytes */
1605  EBI_CS_ASPACE_1MB_gc = (0x0C<<2), /* 1M bytes */
1606  EBI_CS_ASPACE_2MB_gc = (0x0D<<2), /* 2M bytes */
1607  EBI_CS_ASPACE_4MB_gc = (0x0E<<2), /* 4M bytes */
1608  EBI_CS_ASPACE_8MB_gc = (0x0F<<2), /* 8M bytes */
1609  EBI_CS_ASPACE_16M_gc = (0x10<<2), /* 16M bytes */
1610 } EBI_CS_ASPACE_t;
1611 
1612 /* */
1613 typedef enum EBI_CS_SRWS_enum
1614 {
1615  EBI_CS_SRWS_0CLK_gc = (0x00<<0), /* 0 cycles */
1616  EBI_CS_SRWS_1CLK_gc = (0x01<<0), /* 1 cycle */
1617  EBI_CS_SRWS_2CLK_gc = (0x02<<0), /* 2 cycles */
1618  EBI_CS_SRWS_3CLK_gc = (0x03<<0), /* 3 cycles */
1619  EBI_CS_SRWS_4CLK_gc = (0x04<<0), /* 4 cycles */
1620  EBI_CS_SRWS_5CLK_gc = (0x05<<0), /* 5 cycle */
1621  EBI_CS_SRWS_6CLK_gc = (0x06<<0), /* 6 cycles */
1622  EBI_CS_SRWS_7CLK_gc = (0x07<<0), /* 7 cycles */
1623 } EBI_CS_SRWS_t;
1624 
1625 /* Chip Select address mode */
1626 typedef enum EBI_CS_MODE_enum
1627 {
1628  EBI_CS_MODE_DISABLED_gc = (0x00<<0), /* Chip Select Disabled */
1629  EBI_CS_MODE_SRAM_gc = (0x01<<0), /* Chip Select in SRAM mode */
1630  EBI_CS_MODE_LPC_gc = (0x02<<0), /* Chip Select in SRAM LPC mode */
1631  EBI_CS_MODE_SDRAM_gc = (0x03<<0), /* Chip Select in SDRAM mode */
1632 } EBI_CS_MODE_t;
1633 
1634 /* Chip Select SDRAM mode */
1635 typedef enum EBI_CS_SDMODE_enum
1636 {
1637  EBI_CS_SDMODE_NORMAL_gc = (0x00<<0), /* Normal mode */
1638  EBI_CS_SDMODE_LOAD_gc = (0x01<<0), /* Load Mode Register command mode */
1639 } EBI_CS_SDMODE_t;
1640 
1641 /* */
1642 typedef enum EBI_SDDATAW_enum
1643 {
1644  EBI_SDDATAW_4BIT_gc = (0x00<<6), /* 4-bit data bus */
1645  EBI_SDDATAW_8BIT_gc = (0x01<<6), /* 8-bit data bus */
1646 } EBI_SDDATAW_t;
1647 
1648 /* */
1649 typedef enum EBI_LPCMODE_enum
1650 {
1651  EBI_LPCMODE_ALE1_gc = (0x00<<4), /* Data muxed with addr byte 0 */
1652  EBI_LPCMODE_ALE12_gc = (0x02<<4), /* Data muxed with addr byte 0 and 1 */
1653 } EBI_LPCMODE_t;
1654 
1655 /* */
1656 typedef enum EBI_SRMODE_enum
1657 {
1658  EBI_SRMODE_ALE1_gc = (0x00<<2), /* Addr byte 0 muxed with 1 */
1659  EBI_SRMODE_ALE2_gc = (0x01<<2), /* Addr byte 0 muxed with 2 */
1660  EBI_SRMODE_ALE12_gc = (0x02<<2), /* Addr byte 0 muxed with 1 and 2 */
1661  EBI_SRMODE_NOALE_gc = (0x03<<2), /* No addr muxing */
1662 } EBI_SRMODE_t;
1663 
1664 /* */
1665 typedef enum EBI_IFMODE_enum
1666 {
1667  EBI_IFMODE_DISABLED_gc = (0x00<<0), /* EBI Disabled */
1668  EBI_IFMODE_3PORT_gc = (0x01<<0), /* 3-port mode */
1669  EBI_IFMODE_4PORT_gc = (0x02<<0), /* 4-port mode */
1670  EBI_IFMODE_2PORT_gc = (0x03<<0), /* 2-port mode */
1671 } EBI_IFMODE_t;
1672 
1673 /* */
1674 typedef enum EBI_SDCOL_enum
1675 {
1676  EBI_SDCOL_8BIT_gc = (0x00<<0), /* 8 column bits */
1677  EBI_SDCOL_9BIT_gc = (0x01<<0), /* 9 column bits */
1678  EBI_SDCOL_10BIT_gc = (0x02<<0), /* 10 column bits */
1679  EBI_SDCOL_11BIT_gc = (0x03<<0), /* 11 column bits */
1680 } EBI_SDCOL_t;
1681 
1682 /* */
1683 typedef enum EBI_MRDLY_enum
1684 {
1685  EBI_MRDLY_0CLK_gc = (0x00<<6), /* 0 cycles */
1686  EBI_MRDLY_1CLK_gc = (0x01<<6), /* 1 cycle */
1687  EBI_MRDLY_2CLK_gc = (0x02<<6), /* 2 cycles */
1688  EBI_MRDLY_3CLK_gc = (0x03<<6), /* 3 cycles */
1689 } EBI_MRDLY_t;
1690 
1691 /* */
1692 typedef enum EBI_ROWCYCDLY_enum
1693 {
1694  EBI_ROWCYCDLY_0CLK_gc = (0x00<<3), /* 0 cycles */
1695  EBI_ROWCYCDLY_1CLK_gc = (0x01<<3), /* 1 cycle */
1696  EBI_ROWCYCDLY_2CLK_gc = (0x02<<3), /* 2 cycles */
1697  EBI_ROWCYCDLY_3CLK_gc = (0x03<<3), /* 3 cycles */
1698  EBI_ROWCYCDLY_4CLK_gc = (0x04<<3), /* 4 cycles */
1699  EBI_ROWCYCDLY_5CLK_gc = (0x05<<3), /* 5 cycle */
1700  EBI_ROWCYCDLY_6CLK_gc = (0x06<<3), /* 6 cycles */
1701  EBI_ROWCYCDLY_7CLK_gc = (0x07<<3), /* 7 cycles */
1702 } EBI_ROWCYCDLY_t;
1703 
1704 /* */
1705 typedef enum EBI_RPDLY_enum
1706 {
1707  EBI_RPDLY_0CLK_gc = (0x00<<0), /* 0 cycles */
1708  EBI_RPDLY_1CLK_gc = (0x01<<0), /* 1 cycle */
1709  EBI_RPDLY_2CLK_gc = (0x02<<0), /* 2 cycles */
1710  EBI_RPDLY_3CLK_gc = (0x03<<0), /* 3 cycles */
1711  EBI_RPDLY_4CLK_gc = (0x04<<0), /* 4 cycles */
1712  EBI_RPDLY_5CLK_gc = (0x05<<0), /* 5 cycle */
1713  EBI_RPDLY_6CLK_gc = (0x06<<0), /* 6 cycles */
1714  EBI_RPDLY_7CLK_gc = (0x07<<0), /* 7 cycles */
1715 } EBI_RPDLY_t;
1716 
1717 /* */
1718 typedef enum EBI_WRDLY_enum
1719 {
1720  EBI_WRDLY_0CLK_gc = (0x00<<6), /* 0 cycles */
1721  EBI_WRDLY_1CLK_gc = (0x01<<6), /* 1 cycle */
1722  EBI_WRDLY_2CLK_gc = (0x02<<6), /* 2 cycles */
1723  EBI_WRDLY_3CLK_gc = (0x03<<6), /* 3 cycles */
1724 } EBI_WRDLY_t;
1725 
1726 /* */
1727 typedef enum EBI_ESRDLY_enum
1728 {
1729  EBI_ESRDLY_0CLK_gc = (0x00<<3), /* 0 cycles */
1730  EBI_ESRDLY_1CLK_gc = (0x01<<3), /* 1 cycle */
1731  EBI_ESRDLY_2CLK_gc = (0x02<<3), /* 2 cycles */
1732  EBI_ESRDLY_3CLK_gc = (0x03<<3), /* 3 cycles */
1733  EBI_ESRDLY_4CLK_gc = (0x04<<3), /* 4 cycles */
1734  EBI_ESRDLY_5CLK_gc = (0x05<<3), /* 5 cycle */
1735  EBI_ESRDLY_6CLK_gc = (0x06<<3), /* 6 cycles */
1736  EBI_ESRDLY_7CLK_gc = (0x07<<3), /* 7 cycles */
1737 } EBI_ESRDLY_t;
1738 
1739 /* */
1740 typedef enum EBI_ROWCOLDLY_enum
1741 {
1742  EBI_ROWCOLDLY_0CLK_gc = (0x00<<0), /* 0 cycles */
1743  EBI_ROWCOLDLY_1CLK_gc = (0x01<<0), /* 1 cycle */
1744  EBI_ROWCOLDLY_2CLK_gc = (0x02<<0), /* 2 cycles */
1745  EBI_ROWCOLDLY_3CLK_gc = (0x03<<0), /* 3 cycles */
1746  EBI_ROWCOLDLY_4CLK_gc = (0x04<<0), /* 4 cycles */
1747  EBI_ROWCOLDLY_5CLK_gc = (0x05<<0), /* 5 cycle */
1748  EBI_ROWCOLDLY_6CLK_gc = (0x06<<0), /* 6 cycles */
1749  EBI_ROWCOLDLY_7CLK_gc = (0x07<<0), /* 7 cycles */
1750 } EBI_ROWCOLDLY_t;
1751 
1752 
1753 /*
1754 --------------------------------------------------------------------------
1755 TWI - Two-Wire Interface
1756 --------------------------------------------------------------------------
1757 */
1758 
1759 /* */
1760 typedef struct TWI_MASTER_struct
1761 {
1762  register8_t CTRLA; /* Control Register A */
1763  register8_t CTRLB; /* Control Register B */
1764  register8_t CTRLC; /* Control Register C */
1765  register8_t STATUS; /* Status Register */
1766  register8_t BAUD; /* Baurd Rate Control Register */
1767  register8_t ADDR; /* Address Register */
1768  register8_t DATA; /* Data Register */
1769 } TWI_MASTER_t;
1770 
1771 /*
1772 --------------------------------------------------------------------------
1773 TWI - Two-Wire Interface
1774 --------------------------------------------------------------------------
1775 */
1776 
1777 /* */
1778 typedef struct TWI_SLAVE_struct
1779 {
1780  register8_t CTRLA; /* Control Register A */
1781  register8_t CTRLB; /* Control Register B */
1782  register8_t STATUS; /* Status Register */
1783  register8_t ADDR; /* Address Register */
1784  register8_t DATA; /* Data Register */
1785  register8_t ADDRMASK; /* Address Mask Register */
1786 } TWI_SLAVE_t;
1787 
1788 /*
1789 --------------------------------------------------------------------------
1790 TWI - Two-Wire Interface
1791 --------------------------------------------------------------------------
1792 */
1793 
1794 /* Two-Wire Interface */
1795 typedef struct TWI_struct
1796 {
1797  register8_t CTRL; /* TWI Common Control Register */
1798  TWI_MASTER_t MASTER; /* TWI master module */
1799  TWI_SLAVE_t SLAVE; /* TWI slave module */
1800 } TWI_t;
1801 
1802 /* Master Interrupt Level */
1803 typedef enum TWI_MASTER_INTLVL_enum
1804 {
1805  TWI_MASTER_INTLVL_OFF_gc = (0x00<<6), /* Interrupt Disabled */
1806  TWI_MASTER_INTLVL_LO_gc = (0x01<<6), /* Low Level */
1807  TWI_MASTER_INTLVL_MED_gc = (0x02<<6), /* Medium Level */
1808  TWI_MASTER_INTLVL_HI_gc = (0x03<<6), /* High Level */
1809 } TWI_MASTER_INTLVL_t;
1810 
1811 /* Inactive Timeout */
1812 typedef enum TWI_MASTER_TIMEOUT_enum
1813 {
1814  TWI_MASTER_TIMEOUT_DISABLED_gc = (0x00<<2), /* Bus Timeout Disabled */
1815  TWI_MASTER_TIMEOUT_50US_gc = (0x01<<2), /* 50 Microseconds */
1816  TWI_MASTER_TIMEOUT_100US_gc = (0x02<<2), /* 100 Microseconds */
1817  TWI_MASTER_TIMEOUT_200US_gc = (0x03<<2), /* 200 Microseconds */
1818 } TWI_MASTER_TIMEOUT_t;
1819 
1820 /* Master Command */
1821 typedef enum TWI_MASTER_CMD_enum
1822 {
1823  TWI_MASTER_CMD_NOACT_gc = (0x00<<0), /* No Action */
1824  TWI_MASTER_CMD_REPSTART_gc = (0x01<<0), /* Issue Repeated Start Condition */
1825  TWI_MASTER_CMD_RECVTRANS_gc = (0x02<<0), /* Receive or Transmit Data */
1826  TWI_MASTER_CMD_STOP_gc = (0x03<<0), /* Issue Stop Condition */
1827 } TWI_MASTER_CMD_t;
1828 
1829 /* Master Bus State */
1830 typedef enum TWI_MASTER_BUSSTATE_enum
1831 {
1832  TWI_MASTER_BUSSTATE_UNKNOWN_gc = (0x00<<0), /* Unknown Bus State */
1833  TWI_MASTER_BUSSTATE_IDLE_gc = (0x01<<0), /* Bus is Idle */
1834  TWI_MASTER_BUSSTATE_OWNER_gc = (0x02<<0), /* This Module Controls The Bus */
1835  TWI_MASTER_BUSSTATE_BUSY_gc = (0x03<<0), /* The Bus is Busy */
1836 } TWI_MASTER_BUSSTATE_t;
1837 
1838 /* Slave Interrupt Level */
1839 typedef enum TWI_SLAVE_INTLVL_enum
1840 {
1841  TWI_SLAVE_INTLVL_OFF_gc = (0x00<<6), /* Interrupt Disabled */
1842  TWI_SLAVE_INTLVL_LO_gc = (0x01<<6), /* Low Level */
1843  TWI_SLAVE_INTLVL_MED_gc = (0x02<<6), /* Medium Level */
1844  TWI_SLAVE_INTLVL_HI_gc = (0x03<<6), /* High Level */
1845 } TWI_SLAVE_INTLVL_t;
1846 
1847 /* Slave Command */
1848 typedef enum TWI_SLAVE_CMD_enum
1849 {
1850  TWI_SLAVE_CMD_NOACT_gc = (0x00<<0), /* No Action */
1851  TWI_SLAVE_CMD_COMPTRANS_gc = (0x02<<0), /* Used To Complete a Transaction */
1852  TWI_SLAVE_CMD_RESPONSE_gc = (0x03<<0), /* Used in Response to Address/Data Interrupt */
1853 } TWI_SLAVE_CMD_t;
1854 
1855 
1856 /*
1857 --------------------------------------------------------------------------
1858 PORT - Port Configuration
1859 --------------------------------------------------------------------------
1860 */
1861 
1862 /* I/O port Configuration */
1863 typedef struct PORTCFG_struct
1864 {
1865  register8_t MPCMASK; /* Multi-pin Configuration Mask */
1866  register8_t reserved_0x01;
1867  register8_t VPCTRLA; /* Virtual Port Control Register A */
1868  register8_t VPCTRLB; /* Virtual Port Control Register B */
1869  register8_t CLKEVOUT; /* Clock and Event Out Register */
1870 } PORTCFG_t;
1871 
1872 /*
1873 --------------------------------------------------------------------------
1874 PORT - Port Configuration
1875 --------------------------------------------------------------------------
1876 */
1877 
1878 /* Virtual Port */
1879 typedef struct VPORT_struct
1880 {
1881  register8_t DIR; /* I/O Port Data Direction */
1882  register8_t OUT; /* I/O Port Output */
1883  register8_t IN; /* I/O Port Input */
1884  register8_t INTFLAGS; /* Interrupt Flag Register */
1885 } VPORT_t;
1886 
1887 /*
1888 --------------------------------------------------------------------------
1889 PORT - Port Configuration
1890 --------------------------------------------------------------------------
1891 */
1892 
1893 /* I/O Ports */
1894 typedef struct PORT_struct
1895 {
1896  register8_t DIR; /* I/O Port Data Direction */
1897  register8_t DIRSET; /* I/O Port Data Direction Set */
1898  register8_t DIRCLR; /* I/O Port Data Direction Clear */
1899  register8_t DIRTGL; /* I/O Port Data Direction Toggle */
1900  register8_t OUT; /* I/O Port Output */
1901  register8_t OUTSET; /* I/O Port Output Set */
1902  register8_t OUTCLR; /* I/O Port Output Clear */
1903  register8_t OUTTGL; /* I/O Port Output Toggle */
1904  register8_t IN; /* I/O port Input */
1905  register8_t INTCTRL; /* Interrupt Control Register */
1906  register8_t INT0MASK; /* Port Interrupt 0 Mask */
1907  register8_t INT1MASK; /* Port Interrupt 1 Mask */
1908  register8_t INTFLAGS; /* Interrupt Flag Register */
1909  register8_t reserved_0x0D;
1910  register8_t reserved_0x0E;
1911  register8_t reserved_0x0F;
1912  register8_t PIN0CTRL; /* Pin 0 Control Register */
1913  register8_t PIN1CTRL; /* Pin 1 Control Register */
1914  register8_t PIN2CTRL; /* Pin 2 Control Register */
1915  register8_t PIN3CTRL; /* Pin 3 Control Register */
1916  register8_t PIN4CTRL; /* Pin 4 Control Register */
1917  register8_t PIN5CTRL; /* Pin 5 Control Register */
1918  register8_t PIN6CTRL; /* Pin 6 Control Register */
1919  register8_t PIN7CTRL; /* Pin 7 Control Register */
1920 } PORT_t;
1921 
1922 /* Virtual Port 0 Mapping */
1923 typedef enum PORTCFG_VP0MAP_enum
1924 {
1925  PORTCFG_VP0MAP_PORTA_gc = (0x00<<0), /* Mapped To PORTA */
1926  PORTCFG_VP0MAP_PORTB_gc = (0x01<<0), /* Mapped To PORTB */
1927  PORTCFG_VP0MAP_PORTC_gc = (0x02<<0), /* Mapped To PORTC */
1928  PORTCFG_VP0MAP_PORTD_gc = (0x03<<0), /* Mapped To PORTD */
1929  PORTCFG_VP0MAP_PORTE_gc = (0x04<<0), /* Mapped To PORTE */
1930  PORTCFG_VP0MAP_PORTF_gc = (0x05<<0), /* Mapped To PORTF */
1931  PORTCFG_VP0MAP_PORTG_gc = (0x06<<0), /* Mapped To PORTG */
1932  PORTCFG_VP0MAP_PORTH_gc = (0x07<<0), /* Mapped To PORTH */
1933  PORTCFG_VP0MAP_PORTJ_gc = (0x08<<0), /* Mapped To PORTJ */
1934  PORTCFG_VP0MAP_PORTK_gc = (0x09<<0), /* Mapped To PORTK */
1935  PORTCFG_VP0MAP_PORTL_gc = (0x0A<<0), /* Mapped To PORTL */
1936  PORTCFG_VP0MAP_PORTM_gc = (0x0B<<0), /* Mapped To PORTM */
1937  PORTCFG_VP0MAP_PORTN_gc = (0x0C<<0), /* Mapped To PORTN */
1938  PORTCFG_VP0MAP_PORTP_gc = (0x0D<<0), /* Mapped To PORTP */
1939  PORTCFG_VP0MAP_PORTQ_gc = (0x0E<<0), /* Mapped To PORTQ */
1940  PORTCFG_VP0MAP_PORTR_gc = (0x0F<<0), /* Mapped To PORTR */
1941 } PORTCFG_VP0MAP_t;
1942 
1943 /* Virtual Port 1 Mapping */
1944 typedef enum PORTCFG_VP1MAP_enum
1945 {
1946  PORTCFG_VP1MAP_PORTA_gc = (0x00<<4), /* Mapped To PORTA */
1947  PORTCFG_VP1MAP_PORTB_gc = (0x01<<4), /* Mapped To PORTB */
1948  PORTCFG_VP1MAP_PORTC_gc = (0x02<<4), /* Mapped To PORTC */
1949  PORTCFG_VP1MAP_PORTD_gc = (0x03<<4), /* Mapped To PORTD */
1950  PORTCFG_VP1MAP_PORTE_gc = (0x04<<4), /* Mapped To PORTE */
1951  PORTCFG_VP1MAP_PORTF_gc = (0x05<<4), /* Mapped To PORTF */
1952  PORTCFG_VP1MAP_PORTG_gc = (0x06<<4), /* Mapped To PORTG */
1953  PORTCFG_VP1MAP_PORTH_gc = (0x07<<4), /* Mapped To PORTH */
1954  PORTCFG_VP1MAP_PORTJ_gc = (0x08<<4), /* Mapped To PORTJ */
1955  PORTCFG_VP1MAP_PORTK_gc = (0x09<<4), /* Mapped To PORTK */
1956  PORTCFG_VP1MAP_PORTL_gc = (0x0A<<4), /* Mapped To PORTL */
1957  PORTCFG_VP1MAP_PORTM_gc = (0x0B<<4), /* Mapped To PORTM */
1958  PORTCFG_VP1MAP_PORTN_gc = (0x0C<<4), /* Mapped To PORTN */
1959  PORTCFG_VP1MAP_PORTP_gc = (0x0D<<4), /* Mapped To PORTP */
1960  PORTCFG_VP1MAP_PORTQ_gc = (0x0E<<4), /* Mapped To PORTQ */
1961  PORTCFG_VP1MAP_PORTR_gc = (0x0F<<4), /* Mapped To PORTR */
1962 } PORTCFG_VP1MAP_t;
1963 
1964 /* Virtual Port 2 Mapping */
1965 typedef enum PORTCFG_VP2MAP_enum
1966 {
1967  PORTCFG_VP2MAP_PORTA_gc = (0x00<<0), /* Mapped To PORTA */
1968  PORTCFG_VP2MAP_PORTB_gc = (0x01<<0), /* Mapped To PORTB */
1969  PORTCFG_VP2MAP_PORTC_gc = (0x02<<0), /* Mapped To PORTC */
1970  PORTCFG_VP2MAP_PORTD_gc = (0x03<<0), /* Mapped To PORTD */
1971  PORTCFG_VP2MAP_PORTE_gc = (0x04<<0), /* Mapped To PORTE */
1972  PORTCFG_VP2MAP_PORTF_gc = (0x05<<0), /* Mapped To PORTF */
1973  PORTCFG_VP2MAP_PORTG_gc = (0x06<<0), /* Mapped To PORTG */
1974  PORTCFG_VP2MAP_PORTH_gc = (0x07<<0), /* Mapped To PORTH */
1975  PORTCFG_VP2MAP_PORTJ_gc = (0x08<<0), /* Mapped To PORTJ */
1976  PORTCFG_VP2MAP_PORTK_gc = (0x09<<0), /* Mapped To PORTK */
1977  PORTCFG_VP2MAP_PORTL_gc = (0x0A<<0), /* Mapped To PORTL */
1978  PORTCFG_VP2MAP_PORTM_gc = (0x0B<<0), /* Mapped To PORTM */
1979  PORTCFG_VP2MAP_PORTN_gc = (0x0C<<0), /* Mapped To PORTN */
1980  PORTCFG_VP2MAP_PORTP_gc = (0x0D<<0), /* Mapped To PORTP */
1981  PORTCFG_VP2MAP_PORTQ_gc = (0x0E<<0), /* Mapped To PORTQ */
1982  PORTCFG_VP2MAP_PORTR_gc = (0x0F<<0), /* Mapped To PORTR */
1983 } PORTCFG_VP2MAP_t;
1984 
1985 /* Virtual Port 3 Mapping */
1986 typedef enum PORTCFG_VP3MAP_enum
1987 {
1988  PORTCFG_VP3MAP_PORTA_gc = (0x00<<4), /* Mapped To PORTA */
1989  PORTCFG_VP3MAP_PORTB_gc = (0x01<<4), /* Mapped To PORTB */
1990  PORTCFG_VP3MAP_PORTC_gc = (0x02<<4), /* Mapped To PORTC */
1991  PORTCFG_VP3MAP_PORTD_gc = (0x03<<4), /* Mapped To PORTD */
1992  PORTCFG_VP3MAP_PORTE_gc = (0x04<<4), /* Mapped To PORTE */
1993  PORTCFG_VP3MAP_PORTF_gc = (0x05<<4), /* Mapped To PORTF */
1994  PORTCFG_VP3MAP_PORTG_gc = (0x06<<4), /* Mapped To PORTG */
1995  PORTCFG_VP3MAP_PORTH_gc = (0x07<<4), /* Mapped To PORTH */
1996  PORTCFG_VP3MAP_PORTJ_gc = (0x08<<4), /* Mapped To PORTJ */
1997  PORTCFG_VP3MAP_PORTK_gc = (0x09<<4), /* Mapped To PORTK */
1998  PORTCFG_VP3MAP_PORTL_gc = (0x0A<<4), /* Mapped To PORTL */
1999  PORTCFG_VP3MAP_PORTM_gc = (0x0B<<4), /* Mapped To PORTM */
2000  PORTCFG_VP3MAP_PORTN_gc = (0x0C<<4), /* Mapped To PORTN */
2001  PORTCFG_VP3MAP_PORTP_gc = (0x0D<<4), /* Mapped To PORTP */
2002  PORTCFG_VP3MAP_PORTQ_gc = (0x0E<<4), /* Mapped To PORTQ */
2003  PORTCFG_VP3MAP_PORTR_gc = (0x0F<<4), /* Mapped To PORTR */
2004 } PORTCFG_VP3MAP_t;
2005 
2006 /* Clock Output Port */
2007 typedef enum PORTCFG_CLKOUT_enum
2008 {
2009  PORTCFG_CLKOUT_OFF_gc = (0x00<<0), /* Clock Output Disabled */
2010  PORTCFG_CLKOUT_PC7_gc = (0x01<<0), /* Clock Output on Port C pin 7 */
2011  PORTCFG_CLKOUT_PD7_gc = (0x02<<0), /* Clock Output on Port D pin 7 */
2012  PORTCFG_CLKOUT_PE7_gc = (0x03<<0), /* Clock Output on Port E pin 7 */
2013 } PORTCFG_CLKOUT_t;
2014 
2015 /* Event Output Port */
2016 typedef enum PORTCFG_EVOUT_enum
2017 {
2018  PORTCFG_EVOUT_OFF_gc = (0x00<<4), /* Event Output Disabled */
2019  PORTCFG_EVOUT_PC7_gc = (0x01<<4), /* Event Channel 7 Output on Port C pin 7 */
2020  PORTCFG_EVOUT_PD7_gc = (0x02<<4), /* Event Channel 7 Output on Port D pin 7 */
2021  PORTCFG_EVOUT_PE7_gc = (0x03<<4), /* Event Channel 7 Output on Port E pin 7 */
2022 } PORTCFG_EVOUT_t;
2023 
2024 /* Port Interrupt 0 Level */
2025 typedef enum PORT_INT0LVL_enum
2026 {
2027  PORT_INT0LVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */
2028  PORT_INT0LVL_LO_gc = (0x01<<0), /* Low Level */
2029  PORT_INT0LVL_MED_gc = (0x02<<0), /* Medium Level */
2030  PORT_INT0LVL_HI_gc = (0x03<<0), /* High Level */
2031 } PORT_INT0LVL_t;
2032 
2033 /* Port Interrupt 1 Level */
2034 typedef enum PORT_INT1LVL_enum
2035 {
2036  PORT_INT1LVL_OFF_gc = (0x00<<2), /* Interrupt Disabled */
2037  PORT_INT1LVL_LO_gc = (0x01<<2), /* Low Level */
2038  PORT_INT1LVL_MED_gc = (0x02<<2), /* Medium Level */
2039  PORT_INT1LVL_HI_gc = (0x03<<2), /* High Level */
2040 } PORT_INT1LVL_t;
2041 
2042 /* Output/Pull Configuration */
2043 typedef enum PORT_OPC_enum
2044 {
2045  PORT_OPC_TOTEM_gc = (0x00<<3), /* Totempole */
2046  PORT_OPC_BUSKEEPER_gc = (0x01<<3), /* Totempole w/ Bus keeper on Input and Output */
2047  PORT_OPC_PULLDOWN_gc = (0x02<<3), /* Totempole w/ Pull-down on Input */
2048  PORT_OPC_PULLUP_gc = (0x03<<3), /* Totempole w/ Pull-up on Input */
2049  PORT_OPC_WIREDOR_gc = (0x04<<3), /* Wired OR */
2050  PORT_OPC_WIREDAND_gc = (0x05<<3), /* Wired AND */
2051  PORT_OPC_WIREDORPULL_gc = (0x06<<3), /* Wired OR w/ Pull-down */
2052  PORT_OPC_WIREDANDPULL_gc = (0x07<<3), /* Wired AND w/ Pull-up */
2053 } PORT_OPC_t;
2054 
2055 /* Input/Sense Configuration */
2056 typedef enum PORT_ISC_enum
2057 {
2058  PORT_ISC_BOTHEDGES_gc = (0x00<<0), /* Sense Both Edges */
2059  PORT_ISC_RISING_gc = (0x01<<0), /* Sense Rising Edge */
2060  PORT_ISC_FALLING_gc = (0x02<<0), /* Sense Falling Edge */
2061  PORT_ISC_LEVEL_gc = (0x03<<0), /* Sense Level (Transparent For Events) */
2062  PORT_ISC_INPUT_DISABLE_gc = (0x07<<0), /* Disable Digital Input Buffer */
2063 } PORT_ISC_t;
2064 
2065 
2066 /*
2067 --------------------------------------------------------------------------
2068 TC - 16-bit Timer/Counter With PWM
2069 --------------------------------------------------------------------------
2070 */
2071 
2072 /* 16-bit Timer/Counter 0 */
2073 typedef struct TC0_struct
2074 {
2075  register8_t CTRLA; /* Control Register A */
2076  register8_t CTRLB; /* Control Register B */
2077  register8_t CTRLC; /* Control register C */
2078  register8_t CTRLD; /* Control Register D */
2079  register8_t CTRLE; /* Control Register E */
2080  register8_t reserved_0x05;
2081  register8_t INTCTRLA; /* Interrupt Control Register A */
2082  register8_t INTCTRLB; /* Interrupt Control Register B */
2083  register8_t CTRLFCLR; /* Control Register F Clear */
2084  register8_t CTRLFSET; /* Control Register F Set */
2085  register8_t CTRLGCLR; /* Control Register G Clear */
2086  register8_t CTRLGSET; /* Control Register G Set */
2087  register8_t INTFLAGS; /* Interrupt Flag Register */
2088  register8_t reserved_0x0D;
2089  register8_t reserved_0x0E;
2090  register8_t TEMP; /* Temporary Register For 16-bit Access */
2091  register8_t reserved_0x10;
2092  register8_t reserved_0x11;
2093  register8_t reserved_0x12;
2094  register8_t reserved_0x13;
2095  register8_t reserved_0x14;
2096  register8_t reserved_0x15;
2097  register8_t reserved_0x16;
2098  register8_t reserved_0x17;
2099  register8_t reserved_0x18;
2100  register8_t reserved_0x19;
2101  register8_t reserved_0x1A;
2102  register8_t reserved_0x1B;
2103  register8_t reserved_0x1C;
2104  register8_t reserved_0x1D;
2105  register8_t reserved_0x1E;
2106  register8_t reserved_0x1F;
2107  _WORDREGISTER(CNT); /* Count */
2108  register8_t reserved_0x22;
2109  register8_t reserved_0x23;
2110  register8_t reserved_0x24;
2111  register8_t reserved_0x25;
2112  _WORDREGISTER(PER); /* Period */
2113  _WORDREGISTER(CCA); /* Compare or Capture A */
2114  _WORDREGISTER(CCB); /* Compare or Capture B */
2115  _WORDREGISTER(CCC); /* Compare or Capture C */
2116  _WORDREGISTER(CCD); /* Compare or Capture D */
2117  register8_t reserved_0x30;
2118  register8_t reserved_0x31;
2119  register8_t reserved_0x32;
2120  register8_t reserved_0x33;
2121  register8_t reserved_0x34;
2122  register8_t reserved_0x35;
2123  _WORDREGISTER(PERBUF); /* Period Buffer */
2124  _WORDREGISTER(CCABUF); /* Compare Or Capture A Buffer */
2125  _WORDREGISTER(CCBBUF); /* Compare Or Capture B Buffer */
2126  _WORDREGISTER(CCCBUF); /* Compare Or Capture C Buffer */
2127  _WORDREGISTER(CCDBUF); /* Compare Or Capture D Buffer */
2128 } TC0_t;
2129 
2130 /*
2131 --------------------------------------------------------------------------
2132 TC - 16-bit Timer/Counter With PWM
2133 --------------------------------------------------------------------------
2134 */
2135 
2136 /* 16-bit Timer/Counter 1 */
2137 typedef struct TC1_struct
2138 {
2139  register8_t CTRLA; /* Control Register A */
2140  register8_t CTRLB; /* Control Register B */
2141  register8_t CTRLC; /* Control register C */
2142  register8_t CTRLD; /* Control Register D */
2143  register8_t CTRLE; /* Control Register E */
2144  register8_t reserved_0x05;
2145  register8_t INTCTRLA; /* Interrupt Control Register A */
2146  register8_t INTCTRLB; /* Interrupt Control Register B */
2147  register8_t CTRLFCLR; /* Control Register F Clear */
2148  register8_t CTRLFSET; /* Control Register F Set */
2149  register8_t CTRLGCLR; /* Control Register G Clear */
2150  register8_t CTRLGSET; /* Control Register G Set */
2151  register8_t INTFLAGS; /* Interrupt Flag Register */
2152  register8_t reserved_0x0D;
2153  register8_t reserved_0x0E;
2154  register8_t TEMP; /* Temporary Register For 16-bit Access */
2155  register8_t reserved_0x10;
2156  register8_t reserved_0x11;
2157  register8_t reserved_0x12;
2158  register8_t reserved_0x13;
2159  register8_t reserved_0x14;
2160  register8_t reserved_0x15;
2161  register8_t reserved_0x16;
2162  register8_t reserved_0x17;
2163  register8_t reserved_0x18;
2164  register8_t reserved_0x19;
2165  register8_t reserved_0x1A;
2166  register8_t reserved_0x1B;
2167  register8_t reserved_0x1C;
2168  register8_t reserved_0x1D;
2169  register8_t reserved_0x1E;
2170  register8_t reserved_0x1F;
2171  _WORDREGISTER(CNT); /* Count */
2172  register8_t reserved_0x22;
2173  register8_t reserved_0x23;
2174  register8_t reserved_0x24;
2175  register8_t reserved_0x25;
2176  _WORDREGISTER(PER); /* Period */
2177  _WORDREGISTER(CCA); /* Compare or Capture A */
2178  _WORDREGISTER(CCB); /* Compare or Capture B */
2179  register8_t reserved_0x2C;
2180  register8_t reserved_0x2D;
2181  register8_t reserved_0x2E;
2182  register8_t reserved_0x2F;
2183  register8_t reserved_0x30;
2184  register8_t reserved_0x31;
2185  register8_t reserved_0x32;
2186  register8_t reserved_0x33;
2187  register8_t reserved_0x34;
2188  register8_t reserved_0x35;
2189  _WORDREGISTER(PERBUF); /* Period Buffer */
2190  _WORDREGISTER(CCABUF); /* Compare Or Capture A Buffer */
2191  _WORDREGISTER(CCBBUF); /* Compare Or Capture B Buffer */
2192 } TC1_t;
2193 
2194 /*
2195 --------------------------------------------------------------------------
2196 TC - 16-bit Timer/Counter With PWM
2197 --------------------------------------------------------------------------
2198 */
2199 
2200 /* Advanced Waveform Extension */
2201 typedef struct AWEX_struct
2202 {
2203  register8_t CTRL; /* Control Register */
2204  register8_t reserved_0x01;
2205  register8_t FDEVMASK; /* Fault Detection Event Mask */
2206  register8_t FDCTRL; /* Fault Detection Control Register */
2207  register8_t STATUS; /* Status Register */
2208  register8_t reserved_0x05;
2209  register8_t DTBOTH; /* Dead Time Both Sides */
2210  register8_t DTBOTHBUF; /* Dead Time Both Sides Buffer */
2211  register8_t DTLS; /* Dead Time Low Side */
2212  register8_t DTHS; /* Dead Time High Side */
2213  register8_t DTLSBUF; /* Dead Time Low Side Buffer */
2214  register8_t DTHSBUF; /* Dead Time High Side Buffer */
2215  register8_t OUTOVEN; /* Output Override Enable */
2216 } AWEX_t;
2217 
2218 /*
2219 --------------------------------------------------------------------------
2220 TC - 16-bit Timer/Counter With PWM
2221 --------------------------------------------------------------------------
2222 */
2223 
2224 /* High-Resolution Extension */
2225 typedef struct HIRES_struct
2226 {
2227  register8_t CTRL; /* Control Register */
2228 } HIRES_t;
2229 
2230 /* Clock Selection */
2231 typedef enum TC_CLKSEL_enum
2232 {
2233  TC_CLKSEL_OFF_gc = (0x00<<0), /* Timer Off */
2234  TC_CLKSEL_DIV1_gc = (0x01<<0), /* System Clock */
2235  TC_CLKSEL_DIV2_gc = (0x02<<0), /* System Clock / 2 */
2236  TC_CLKSEL_DIV4_gc = (0x03<<0), /* System Clock / 4 */
2237  TC_CLKSEL_DIV8_gc = (0x04<<0), /* System Clock / 8 */
2238  TC_CLKSEL_DIV64_gc = (0x05<<0), /* System Clock / 64 */
2239  TC_CLKSEL_DIV256_gc = (0x06<<0), /* System Clock / 256 */
2240  TC_CLKSEL_DIV1024_gc = (0x07<<0), /* System Clock / 1024 */
2241  TC_CLKSEL_EVCH0_gc = (0x08<<0), /* Event Channel 0 */
2242  TC_CLKSEL_EVCH1_gc = (0x09<<0), /* Event Channel 1 */
2243  TC_CLKSEL_EVCH2_gc = (0x0A<<0), /* Event Channel 2 */
2244  TC_CLKSEL_EVCH3_gc = (0x0B<<0), /* Event Channel 3 */
2245  TC_CLKSEL_EVCH4_gc = (0x0C<<0), /* Event Channel 4 */
2246  TC_CLKSEL_EVCH5_gc = (0x0D<<0), /* Event Channel 5 */
2247  TC_CLKSEL_EVCH6_gc = (0x0E<<0), /* Event Channel 6 */
2248  TC_CLKSEL_EVCH7_gc = (0x0F<<0), /* Event Channel 7 */
2249 } TC_CLKSEL_t;
2250 
2251 /* Waveform Generation Mode */
2252 typedef enum TC_WGMODE_enum
2253 {
2254  TC_WGMODE_NORMAL_gc = (0x00<<0), /* Normal Mode */
2255  TC_WGMODE_FRQ_gc = (0x01<<0), /* Frequency Generation Mode */
2256  TC_WGMODE_SS_gc = (0x03<<0), /* Single Slope */
2257  TC_WGMODE_DS_T_gc = (0x05<<0), /* Dual Slope, Update on TOP */
2258  TC_WGMODE_DS_TB_gc = (0x06<<0), /* Dual Slope, Update on TOP and BOTTOM */
2259  TC_WGMODE_DS_B_gc = (0x07<<0), /* Dual Slope, Update on BOTTOM */
2260 } TC_WGMODE_t;
2261 
2262 /* Event Action */
2263 typedef enum TC_EVACT_enum
2264 {
2265  TC_EVACT_OFF_gc = (0x00<<5), /* No Event Action */
2266  TC_EVACT_CAPT_gc = (0x01<<5), /* Input Capture */
2267  TC_EVACT_UPDOWN_gc = (0x02<<5), /* Externally Controlled Up/Down Count */
2268  TC_EVACT_QDEC_gc = (0x03<<5), /* Quadrature Decode */
2269  TC_EVACT_RESTART_gc = (0x04<<5), /* Restart */
2270  TC_EVACT_FRW_gc = (0x05<<5), /* Frequency Capture */
2271  TC_EVACT_PW_gc = (0x06<<5), /* Pulse-width Capture */
2272 } TC_EVACT_t;
2273 
2274 /* Event Selection */
2275 typedef enum TC_EVSEL_enum
2276 {
2277  TC_EVSEL_OFF_gc = (0x00<<0), /* No Event Source */
2278  TC_EVSEL_CH0_gc = (0x08<<0), /* Event Channel 0 */
2279  TC_EVSEL_CH1_gc = (0x09<<0), /* Event Channel 1 */
2280  TC_EVSEL_CH2_gc = (0x0A<<0), /* Event Channel 2 */
2281  TC_EVSEL_CH3_gc = (0x0B<<0), /* Event Channel 3 */
2282  TC_EVSEL_CH4_gc = (0x0C<<0), /* Event Channel 4 */
2283  TC_EVSEL_CH5_gc = (0x0D<<0), /* Event Channel 5 */
2284  TC_EVSEL_CH6_gc = (0x0E<<0), /* Event Channel 6 */
2285  TC_EVSEL_CH7_gc = (0x0F<<0), /* Event Channel 7 */
2286 } TC_EVSEL_t;
2287 
2288 /* Error Interrupt Level */
2289 typedef enum TC_ERRINTLVL_enum
2290 {
2291  TC_ERRINTLVL_OFF_gc = (0x00<<2), /* Interrupt Disabled */
2292  TC_ERRINTLVL_LO_gc = (0x01<<2), /* Low Level */
2293  TC_ERRINTLVL_MED_gc = (0x02<<2), /* Medium Level */
2294  TC_ERRINTLVL_HI_gc = (0x03<<2), /* High Level */
2295 } TC_ERRINTLVL_t;
2296 
2297 /* Overflow Interrupt Level */
2298 typedef enum TC_OVFINTLVL_enum
2299 {
2300  TC_OVFINTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */
2301  TC_OVFINTLVL_LO_gc = (0x01<<0), /* Low Level */
2302  TC_OVFINTLVL_MED_gc = (0x02<<0), /* Medium Level */
2303  TC_OVFINTLVL_HI_gc = (0x03<<0), /* High Level */
2304 } TC_OVFINTLVL_t;
2305 
2306 /* Compare or Capture D Interrupt Level */
2307 typedef enum TC_CCDINTLVL_enum
2308 {
2309  TC_CCDINTLVL_OFF_gc = (0x00<<6), /* Interrupt Disabled */
2310  TC_CCDINTLVL_LO_gc = (0x01<<6), /* Low Level */
2311  TC_CCDINTLVL_MED_gc = (0x02<<6), /* Medium Level */
2312  TC_CCDINTLVL_HI_gc = (0x03<<6), /* High Level */
2313 } TC_CCDINTLVL_t;
2314 
2315 /* Compare or Capture C Interrupt Level */
2316 typedef enum TC_CCCINTLVL_enum
2317 {
2318  TC_CCCINTLVL_OFF_gc = (0x00<<4), /* Interrupt Disabled */
2319  TC_CCCINTLVL_LO_gc = (0x01<<4), /* Low Level */
2320  TC_CCCINTLVL_MED_gc = (0x02<<4), /* Medium Level */
2321  TC_CCCINTLVL_HI_gc = (0x03<<4), /* High Level */
2322 } TC_CCCINTLVL_t;
2323 
2324 /* Compare or Capture B Interrupt Level */
2325 typedef enum TC_CCBINTLVL_enum
2326 {
2327  TC_CCBINTLVL_OFF_gc = (0x00<<2), /* Interrupt Disabled */
2328  TC_CCBINTLVL_LO_gc = (0x01<<2), /* Low Level */
2329  TC_CCBINTLVL_MED_gc = (0x02<<2), /* Medium Level */
2330  TC_CCBINTLVL_HI_gc = (0x03<<2), /* High Level */
2331 } TC_CCBINTLVL_t;
2332 
2333 /* Compare or Capture A Interrupt Level */
2334 typedef enum TC_CCAINTLVL_enum
2335 {
2336  TC_CCAINTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */
2337  TC_CCAINTLVL_LO_gc = (0x01<<0), /* Low Level */
2338  TC_CCAINTLVL_MED_gc = (0x02<<0), /* Medium Level */
2339  TC_CCAINTLVL_HI_gc = (0x03<<0), /* High Level */
2340 } TC_CCAINTLVL_t;
2341 
2342 /* Timer/Counter Command */
2343 typedef enum TC_CMD_enum
2344 {
2345  TC_CMD_NONE_gc = (0x00<<2), /* No Command */
2346  TC_CMD_UPDATE_gc = (0x01<<2), /* Force Update */
2347  TC_CMD_RESTART_gc = (0x02<<2), /* Force Restart */
2348  TC_CMD_RESET_gc = (0x03<<2), /* Force Hard Reset */
2349 } TC_CMD_t;
2350 
2351 /* Fault Detect Action */
2352 typedef enum AWEX_FDACT_enum
2353 {
2354  AWEX_FDACT_NONE_gc = (0x00<<0), /* No Fault Protection */
2355  AWEX_FDACT_CLEAROE_gc = (0x01<<0), /* Clear Output Enable Bits */
2356  AWEX_FDACT_CLEARDIR_gc = (0x03<<0), /* Clear I/O Port Direction Bits */
2357 } AWEX_FDACT_t;
2358 
2359 /* High Resolution Enable */
2360 typedef enum HIRES_HREN_enum
2361 {
2362  HIRES_HREN_NONE_gc = (0x00<<0), /* No Fault Protection */
2363  HIRES_HREN_TC0_gc = (0x01<<0), /* Enable High Resolution on Timer/Counter 0 */
2364  HIRES_HREN_TC1_gc = (0x02<<0), /* Enable High Resolution on Timer/Counter 1 */
2365  HIRES_HREN_BOTH_gc = (0x03<<0), /* Enable High Resolution both Timer/Counters */
2366 } HIRES_HREN_t;
2367 
2368 
2369 /*
2370 --------------------------------------------------------------------------
2371 USART - Universal Asynchronous Receiver-Transmitter
2372 --------------------------------------------------------------------------
2373 */
2374 
2375 /* Universal Synchronous/Asynchronous Receiver/Transmitter */
2376 typedef struct USART_struct
2377 {
2378  register8_t DATA; /* Data Register */
2379  register8_t STATUS; /* Status Register */
2380  register8_t reserved_0x02;
2381  register8_t CTRLA; /* Control Register A */
2382  register8_t CTRLB; /* Control Register B */
2383  register8_t CTRLC; /* Control Register C */
2384  register8_t BAUDCTRLA; /* Baud Rate Control Register A */
2385  register8_t BAUDCTRLB; /* Baud Rate Control Register B */
2386 } USART_t;
2387 
2388 /* Receive Complete Interrupt level */
2389 typedef enum USART_RXCINTLVL_enum
2390 {
2391  USART_RXCINTLVL_OFF_gc = (0x00<<4), /* Interrupt Disabled */
2392  USART_RXCINTLVL_LO_gc = (0x01<<4), /* Low Level */
2393  USART_RXCINTLVL_MED_gc = (0x02<<4), /* Medium Level */
2394  USART_RXCINTLVL_HI_gc = (0x03<<4), /* High Level */
2395 } USART_RXCINTLVL_t;
2396 
2397 /* Transmit Complete Interrupt level */
2398 typedef enum USART_TXCINTLVL_enum
2399 {
2400  USART_TXCINTLVL_OFF_gc = (0x00<<2), /* Interrupt Disabled */
2401  USART_TXCINTLVL_LO_gc = (0x01<<2), /* Low Level */
2402  USART_TXCINTLVL_MED_gc = (0x02<<2), /* Medium Level */
2403  USART_TXCINTLVL_HI_gc = (0x03<<2), /* High Level */
2404 } USART_TXCINTLVL_t;
2405 
2406 /* Data Register Empty Interrupt level */
2407 typedef enum USART_DREINTLVL_enum
2408 {
2409  USART_DREINTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */
2410  USART_DREINTLVL_LO_gc = (0x01<<0), /* Low Level */
2411  USART_DREINTLVL_MED_gc = (0x02<<0), /* Medium Level */
2412  USART_DREINTLVL_HI_gc = (0x03<<0), /* High Level */
2413 } USART_DREINTLVL_t;
2414 
2415 /* Character Size */
2416 typedef enum USART_CHSIZE_enum
2417 {
2418  USART_CHSIZE_5BIT_gc = (0x00<<0), /* Character size: 5 bit */
2419  USART_CHSIZE_6BIT_gc = (0x01<<0), /* Character size: 6 bit */
2420  USART_CHSIZE_7BIT_gc = (0x02<<0), /* Character size: 7 bit */
2421  USART_CHSIZE_8BIT_gc = (0x03<<0), /* Character size: 8 bit */
2422  USART_CHSIZE_9BIT_gc = (0x07<<0), /* Character size: 9 bit */
2423 } USART_CHSIZE_t;
2424 
2425 /* Communication Mode */
2426 typedef enum USART_CMODE_enum
2427 {
2428  USART_CMODE_ASYNCHRONOUS_gc = (0x00<<6), /* Asynchronous Mode */
2429  USART_CMODE_SYNCHRONOUS_gc = (0x01<<6), /* Synchronous Mode */
2430  USART_CMODE_IRDA_gc = (0x02<<6), /* IrDA Mode */
2431  USART_CMODE_MSPI_gc = (0x03<<6), /* Master SPI Mode */
2432 } USART_CMODE_t;
2433 
2434 /* Parity Mode */
2435 typedef enum USART_PMODE_enum
2436 {
2437  USART_PMODE_DISABLED_gc = (0x00<<4), /* No Parity */
2438  USART_PMODE_EVEN_gc = (0x02<<4), /* Even Parity */
2439  USART_PMODE_ODD_gc = (0x03<<4), /* Odd Parity */
2440 } USART_PMODE_t;
2441 
2442 
2443 /*
2444 --------------------------------------------------------------------------
2445 SPI - Serial Peripheral Interface
2446 --------------------------------------------------------------------------
2447 */
2448 
2449 /* Serial Peripheral Interface */
2450 typedef struct SPI_struct
2451 {
2452  register8_t CTRL; /* Control Register */
2453  register8_t INTCTRL; /* Interrupt Control Register */
2454  register8_t STATUS; /* Status Register */
2455  register8_t DATA; /* Data Register */
2456 } SPI_t;
2457 
2458 /* SPI Mode */
2459 typedef enum SPI_MODE_enum
2460 {
2461  SPI_MODE_0_gc = (0x00<<2), /* SPI Mode 0 */
2462  SPI_MODE_1_gc = (0x01<<2), /* SPI Mode 1 */
2463  SPI_MODE_2_gc = (0x02<<2), /* SPI Mode 2 */
2464  SPI_MODE_3_gc = (0x03<<2), /* SPI Mode 3 */
2465 } SPI_MODE_t;
2466 
2467 /* Prescaler setting */
2468 typedef enum SPI_PRESCALER_enum
2469 {
2470  SPI_PRESCALER_DIV4_gc = (0x00<<0), /* System Clock / 4 */
2471  SPI_PRESCALER_DIV16_gc = (0x01<<0), /* System Clock / 16 */
2472  SPI_PRESCALER_DIV64_gc = (0x02<<0), /* System Clock / 64 */
2473  SPI_PRESCALER_DIV128_gc = (0x03<<0), /* System Clock / 128 */
2474 } SPI_PRESCALER_t;
2475 
2476 /* Interrupt level */
2477 typedef enum SPI_INTLVL_enum
2478 {
2479  SPI_INTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */
2480  SPI_INTLVL_LO_gc = (0x01<<0), /* Low Level */
2481  SPI_INTLVL_MED_gc = (0x02<<0), /* Medium Level */
2482  SPI_INTLVL_HI_gc = (0x03<<0), /* High Level */
2483 } SPI_INTLVL_t;
2484 
2485 
2486 /*
2487 --------------------------------------------------------------------------
2488 IRCOM - IR Communication Module
2489 --------------------------------------------------------------------------
2490 */
2491 
2492 /* IR Communication Module */
2493 typedef struct IRCOM_struct
2494 {
2495  register8_t CTRL; /* Control Register */
2496  register8_t TXPLCTRL; /* IrDA Transmitter Pulse Length Control Register */
2497  register8_t RXPLCTRL; /* IrDA Receiver Pulse Length Control Register */
2498 } IRCOM_t;
2499 
2500 /* Event channel selection */
2501 typedef enum IRDA_EVSEL_enum
2502 {
2503  IRDA_EVSEL_OFF_gc = (0x00<<0), /* No Event Source */
2504  IRDA_EVSEL_0_gc = (0x08<<0), /* Event Channel 0 */
2505  IRDA_EVSEL_1_gc = (0x09<<0), /* Event Channel 1 */
2506  IRDA_EVSEL_2_gc = (0x0A<<0), /* Event Channel 2 */
2507  IRDA_EVSEL_3_gc = (0x0B<<0), /* Event Channel 3 */
2508  IRDA_EVSEL_4_gc = (0x0C<<0), /* Event Channel 4 */
2509  IRDA_EVSEL_5_gc = (0x0D<<0), /* Event Channel 5 */
2510  IRDA_EVSEL_6_gc = (0x0E<<0), /* Event Channel 6 */
2511  IRDA_EVSEL_7_gc = (0x0F<<0), /* Event Channel 7 */
2512 } IRDA_EVSEL_t;
2513 
2514 
2515 /*
2516 --------------------------------------------------------------------------
2517 AES - AES Module
2518 --------------------------------------------------------------------------
2519 */
2520 
2521 /* AES Module */
2522 typedef struct AES_struct
2523 {
2524  register8_t CTRL; /* AES Control Register */
2525  register8_t STATUS; /* AES Status Register */
2526  register8_t STATE; /* AES State Register */
2527  register8_t KEY; /* AES Key Register */
2528  register8_t INTCTRL; /* AES Interrupt Control Register */
2529 } AES_t;
2530 
2531 /* Interrupt level */
2532 typedef enum AES_INTLVL_enum
2533 {
2534  AES_INTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */
2535  AES_INTLVL_LO_gc = (0x01<<0), /* Low Level */
2536  AES_INTLVL_MED_gc = (0x02<<0), /* Medium Level */
2537  AES_INTLVL_HI_gc = (0x03<<0), /* High Level */
2538 } AES_INTLVL_t;
2539 
2540 
2541 
2542 /*
2543 ==========================================================================
2544 IO Module Instances. Mapped to memory.
2545 ==========================================================================
2546 */
2547 
2548 #define GPIO (*(GPIO_t *) 0x0000) /* General Purpose IO Registers */
2549 #define VPORT0 (*(VPORT_t *) 0x0010) /* Virtual Port 0 */
2550 #define VPORT1 (*(VPORT_t *) 0x0014) /* Virtual Port 1 */
2551 #define VPORT2 (*(VPORT_t *) 0x0018) /* Virtual Port 2 */
2552 #define VPORT3 (*(VPORT_t *) 0x001C) /* Virtual Port 3 */
2553 #define OCD (*(OCD_t *) 0x002E) /* On-Chip Debug System */
2554 #define CPU (*(CPU_t *) 0x0030) /* CPU Registers */
2555 #define CLK (*(CLK_t *) 0x0040) /* Clock System */
2556 #define SLEEP (*(SLEEP_t *) 0x0048) /* Sleep Controller */
2557 #define OSC (*(OSC_t *) 0x0050) /* Oscillator Control */
2558 #define DFLLRC32M (*(DFLL_t *) 0x0060) /* DFLL for 32MHz RC Oscillator */
2559 #define DFLLRC2M (*(DFLL_t *) 0x0068) /* DFLL for 2MHz RC Oscillator */
2560 #define PR (*(PR_t *) 0x0070) /* Power Reduction */
2561 #define RST (*(RST_t *) 0x0078) /* Reset Controller */
2562 #define WDT (*(WDT_t *) 0x0080) /* Watch-Dog Timer */
2563 #define MCU (*(MCU_t *) 0x0090) /* MCU Control */
2564 #define PMIC (*(PMIC_t *) 0x00A0) /* Programmable Interrupt Controller */
2565 #define PORTCFG (*(PORTCFG_t *) 0x00B0) /* Port Configuration */
2566 #define AES (*(AES_t *) 0x00C0) /* AES Crypto Module */
2567 #define DMA (*(DMA_t *) 0x0100) /* DMA Controller */
2568 #define EVSYS (*(EVSYS_t *) 0x0180) /* Event System */
2569 #define NVM (*(NVM_t *) 0x01C0) /* Non Volatile Memory Controller */
2570 #define ADCA (*(ADC_t *) 0x0200) /* Analog to Digital Converter A */
2571 #define DACB (*(DAC_t *) 0x0320) /* Digital to Analog Converter B */
2572 #define ACA (*(AC_t *) 0x0380) /* Analog Comparator A */
2573 #define RTC (*(RTC_t *) 0x0400) /* Real-Time Counter */
2574 #define TWIC (*(TWI_t *) 0x0480) /* Two-Wire Interface C */
2575 #define TWIE (*(TWI_t *) 0x04A0) /* Two-Wire Interface E */
2576 #define PORTA (*(PORT_t *) 0x0600) /* Port A */
2577 #define PORTB (*(PORT_t *) 0x0620) /* Port B */
2578 #define PORTC (*(PORT_t *) 0x0640) /* Port C */
2579 #define PORTD (*(PORT_t *) 0x0660) /* Port D */
2580 #define PORTE (*(PORT_t *) 0x0680) /* Port E */
2581 #define PORTR (*(PORT_t *) 0x07E0) /* Port R */
2582 #define TCC0 (*(TC0_t *) 0x0800) /* Timer/Counter C0 */
2583 #define TCC1 (*(TC1_t *) 0x0840) /* Timer/Counter C1 */
2584 #define AWEXC (*(AWEX_t *) 0x0880) /* Advanced Waveform Extension C */
2585 #define HIRESC (*(HIRES_t *) 0x0890) /* High-Resolution Extension C */
2586 #define USARTC0 (*(USART_t *) 0x08A0) /* Universal Asynchronous Receiver-Transmitter C0 */
2587 #define USARTC1 (*(USART_t *) 0x08B0) /* Universal Asynchronous Receiver-Transmitter C1 */
2588 #define SPIC (*(SPI_t *) 0x08C0) /* Serial Peripheral Interface C */
2589 #define IRCOM (*(IRCOM_t *) 0x08F8) /* IR Communication Module */
2590 #define TCD0 (*(TC0_t *) 0x0900) /* Timer/Counter D0 */
2591 #define TCD1 (*(TC1_t *) 0x0940) /* Timer/Counter D1 */
2592 #define HIRESD (*(HIRES_t *) 0x0990) /* High-Resolution Extension D */
2593 #define USARTD0 (*(USART_t *) 0x09A0) /* Universal Asynchronous Receiver-Transmitter D0 */
2594 #define USARTD1 (*(USART_t *) 0x09B0) /* Universal Asynchronous Receiver-Transmitter D1 */
2595 #define SPID (*(SPI_t *) 0x09C0) /* Serial Peripheral Interface D */
2596 #define TCE0 (*(TC0_t *) 0x0A00) /* Timer/Counter E0 */
2597 #define HIRESE (*(HIRES_t *) 0x0A90) /* High-Resolution Extension E */
2598 #define USARTE0 (*(USART_t *) 0x0AA0) /* Universal Asynchronous Receiver-Transmitter E0 */
2599 
2600 
2601 #endif /* !defined (__ASSEMBLER__) */
2602 
2603 
2604 /* ========== Flattened fully qualified IO register names ========== */
2605 
2606 /* GPIO - General Purpose IO Registers */
2607 #define GPIO_GPIO0 _SFR_MEM8(0x0000)
2608 #define GPIO_GPIO1 _SFR_MEM8(0x0001)
2609 #define GPIO_GPIO2 _SFR_MEM8(0x0002)
2610 #define GPIO_GPIO3 _SFR_MEM8(0x0003)
2611 #define GPIO_GPIO4 _SFR_MEM8(0x0004)
2612 #define GPIO_GPIO5 _SFR_MEM8(0x0005)
2613 #define GPIO_GPIO6 _SFR_MEM8(0x0006)
2614 #define GPIO_GPIO7 _SFR_MEM8(0x0007)
2615 #define GPIO_GPIO8 _SFR_MEM8(0x0008)
2616 #define GPIO_GPIO9 _SFR_MEM8(0x0009)
2617 #define GPIO_GPIOA _SFR_MEM8(0x000A)
2618 #define GPIO_GPIOB _SFR_MEM8(0x000B)
2619 #define GPIO_GPIOC _SFR_MEM8(0x000C)
2620 #define GPIO_GPIOD _SFR_MEM8(0x000D)
2621 #define GPIO_GPIOE _SFR_MEM8(0x000E)
2622 #define GPIO_GPIOF _SFR_MEM8(0x000F)
2623 
2624 /* VPORT0 - Virtual Port 0 */
2625 #define VPORT0_DIR _SFR_MEM8(0x0010)
2626 #define VPORT0_OUT _SFR_MEM8(0x0011)
2627 #define VPORT0_IN _SFR_MEM8(0x0012)
2628 #define VPORT0_INTFLAGS _SFR_MEM8(0x0013)
2629 
2630 /* VPORT1 - Virtual Port 1 */
2631 #define VPORT1_DIR _SFR_MEM8(0x0014)
2632 #define VPORT1_OUT _SFR_MEM8(0x0015)
2633 #define VPORT1_IN _SFR_MEM8(0x0016)
2634 #define VPORT1_INTFLAGS _SFR_MEM8(0x0017)
2635 
2636 /* VPORT2 - Virtual Port 2 */
2637 #define VPORT2_DIR _SFR_MEM8(0x0018)
2638 #define VPORT2_OUT _SFR_MEM8(0x0019)
2639 #define VPORT2_IN _SFR_MEM8(0x001A)
2640 #define VPORT2_INTFLAGS _SFR_MEM8(0x001B)
2641 
2642 /* VPORT3 - Virtual Port 3 */
2643 #define VPORT3_DIR _SFR_MEM8(0x001C)
2644 #define VPORT3_OUT _SFR_MEM8(0x001D)
2645 #define VPORT3_IN _SFR_MEM8(0x001E)
2646 #define VPORT3_INTFLAGS _SFR_MEM8(0x001F)
2647 
2648 /* OCD - On-Chip Debug System */
2649 #define OCD_OCDR0 _SFR_MEM8(0x002E)
2650 #define OCD_OCDR1 _SFR_MEM8(0x002F)
2651 
2652 /* CPU - CPU Registers */
2653 #define CPU_CCP _SFR_MEM8(0x0034)
2654 #define CPU_RAMPD _SFR_MEM8(0x0038)
2655 #define CPU_RAMPX _SFR_MEM8(0x0039)
2656 #define CPU_RAMPY _SFR_MEM8(0x003A)
2657 #define CPU_RAMPZ _SFR_MEM8(0x003B)
2658 #define CPU_EIND _SFR_MEM8(0x003C)
2659 #define CPU_SPL _SFR_MEM8(0x003D)
2660 #define CPU_SPH _SFR_MEM8(0x003E)
2661 #define CPU_SREG _SFR_MEM8(0x003F)
2662 
2663 /* CLK - Clock System */
2664 #define CLK_CTRL _SFR_MEM8(0x0040)
2665 #define CLK_PSCTRL _SFR_MEM8(0x0041)
2666 #define CLK_LOCK _SFR_MEM8(0x0042)
2667 #define CLK_RTCCTRL _SFR_MEM8(0x0043)
2668 
2669 /* SLEEP - Sleep Controller */
2670 #define SLEEP_CTRL _SFR_MEM8(0x0048)
2671 
2672 /* OSC - Oscillator Control */
2673 #define OSC_CTRL _SFR_MEM8(0x0050)
2674 #define OSC_STATUS _SFR_MEM8(0x0051)
2675 #define OSC_XOSCCTRL _SFR_MEM8(0x0052)
2676 #define OSC_XOSCFAIL _SFR_MEM8(0x0053)
2677 #define OSC_RC32KCAL _SFR_MEM8(0x0054)
2678 #define OSC_PLLCTRL _SFR_MEM8(0x0055)
2679 #define OSC_DFLLCTRL _SFR_MEM8(0x0056)
2680 
2681 /* DFLLRC32M - DFLL for 32MHz RC Oscillator */
2682 #define DFLLRC32M_CTRL _SFR_MEM8(0x0060)
2683 #define DFLLRC32M_CALA _SFR_MEM8(0x0062)
2684 #define DFLLRC32M_CALB _SFR_MEM8(0x0063)
2685 #define DFLLRC32M_COMP0 _SFR_MEM8(0x0064)
2686 #define DFLLRC32M_COMP1 _SFR_MEM8(0x0065)
2687 #define DFLLRC32M_COMP2 _SFR_MEM8(0x0066)
2688 
2689 /* DFLLRC2M - DFLL for 2MHz RC Oscillator */
2690 #define DFLLRC2M_CTRL _SFR_MEM8(0x0068)
2691 #define DFLLRC2M_CALA _SFR_MEM8(0x006A)
2692 #define DFLLRC2M_CALB _SFR_MEM8(0x006B)
2693 #define DFLLRC2M_COMP0 _SFR_MEM8(0x006C)
2694 #define DFLLRC2M_COMP1 _SFR_MEM8(0x006D)
2695 #define DFLLRC2M_COMP2 _SFR_MEM8(0x006E)
2696 
2697 /* PR - Power Reduction */
2698 #define PR_PRGEN _SFR_MEM8(0x0070)
2699 #define PR_PRPA _SFR_MEM8(0x0071)
2700 #define PR_PRPB _SFR_MEM8(0x0072)
2701 #define PR_PRPC _SFR_MEM8(0x0073)
2702 #define PR_PRPD _SFR_MEM8(0x0074)
2703 #define PR_PRPE _SFR_MEM8(0x0075)
2704 #define PR_PRPF _SFR_MEM8(0x0076)
2705 
2706 /* RST - Reset Controller */
2707 #define RST_STATUS _SFR_MEM8(0x0078)
2708 #define RST_CTRL _SFR_MEM8(0x0079)
2709 
2710 /* WDT - Watch-Dog Timer */
2711 #define WDT_CTRL _SFR_MEM8(0x0080)
2712 #define WDT_WINCTRL _SFR_MEM8(0x0081)
2713 #define WDT_STATUS _SFR_MEM8(0x0082)
2714 
2715 /* MCU - MCU Control */
2716 #define MCU_DEVID0 _SFR_MEM8(0x0090)
2717 #define MCU_DEVID1 _SFR_MEM8(0x0091)
2718 #define MCU_DEVID2 _SFR_MEM8(0x0092)
2719 #define MCU_REVID _SFR_MEM8(0x0093)
2720 #define MCU_JTAGUID _SFR_MEM8(0x0094)
2721 #define MCU_MCUCR _SFR_MEM8(0x0096)
2722 #define MCU_EVSYSLOCK _SFR_MEM8(0x0098)
2723 #define MCU_AWEXLOCK _SFR_MEM8(0x0099)
2724 
2725 /* PMIC - Programmable Interrupt Controller */
2726 #define PMIC_STATUS _SFR_MEM8(0x00A0)
2727 #define PMIC_INTPRI _SFR_MEM8(0x00A1)
2728 #define PMIC_CTRL _SFR_MEM8(0x00A2)
2729 
2730 /* PORTCFG - Port Configuration */
2731 #define PORTCFG_MPCMASK _SFR_MEM8(0x00B0)
2732 #define PORTCFG_VPCTRLA _SFR_MEM8(0x00B2)
2733 #define PORTCFG_VPCTRLB _SFR_MEM8(0x00B3)
2734 #define PORTCFG_CLKEVOUT _SFR_MEM8(0x00B4)
2735 
2736 /* AES - AES Crypto Module */
2737 #define AES_CTRL _SFR_MEM8(0x00C0)
2738 #define AES_STATUS _SFR_MEM8(0x00C1)
2739 #define AES_STATE _SFR_MEM8(0x00C2)
2740 #define AES_KEY _SFR_MEM8(0x00C3)
2741 #define AES_INTCTRL _SFR_MEM8(0x00C4)
2742 
2743 /* DMA - DMA Controller */
2744 #define DMA_CTRL _SFR_MEM8(0x0100)
2745 #define DMA_INTFLAGS _SFR_MEM8(0x0103)
2746 #define DMA_STATUS _SFR_MEM8(0x0104)
2747 #define DMA_TEMP _SFR_MEM16(0x0106)
2748 #define DMA_CH0_CTRLA _SFR_MEM8(0x0110)
2749 #define DMA_CH0_CTRLB _SFR_MEM8(0x0111)
2750 #define DMA_CH0_ADDRCTRL _SFR_MEM8(0x0112)
2751 #define DMA_CH0_TRIGSRC _SFR_MEM8(0x0113)
2752 #define DMA_CH0_TRFCNT _SFR_MEM16(0x0114)
2753 #define DMA_CH0_REPCNT _SFR_MEM8(0x0116)
2754 #define DMA_CH0_SRCADDR0 _SFR_MEM8(0x0118)
2755 #define DMA_CH0_SRCADDR1 _SFR_MEM8(0x0119)
2756 #define DMA_CH0_SRCADDR2 _SFR_MEM8(0x011A)
2757 #define DMA_CH0_DESTADDR0 _SFR_MEM8(0x011C)
2758 #define DMA_CH0_DESTADDR1 _SFR_MEM8(0x011D)
2759 #define DMA_CH0_DESTADDR2 _SFR_MEM8(0x011E)
2760 #define DMA_CH1_CTRLA _SFR_MEM8(0x0120)
2761 #define DMA_CH1_CTRLB _SFR_MEM8(0x0121)
2762 #define DMA_CH1_ADDRCTRL _SFR_MEM8(0x0122)
2763 #define DMA_CH1_TRIGSRC _SFR_MEM8(0x0123)
2764 #define DMA_CH1_TRFCNT _SFR_MEM16(0x0124)
2765 #define DMA_CH1_REPCNT _SFR_MEM8(0x0126)
2766 #define DMA_CH1_SRCADDR0 _SFR_MEM8(0x0128)
2767 #define DMA_CH1_SRCADDR1 _SFR_MEM8(0x0129)
2768 #define DMA_CH1_SRCADDR2 _SFR_MEM8(0x012A)
2769 #define DMA_CH1_DESTADDR0 _SFR_MEM8(0x012C)
2770 #define DMA_CH1_DESTADDR1 _SFR_MEM8(0x012D)
2771 #define DMA_CH1_DESTADDR2 _SFR_MEM8(0x012E)
2772 #define DMA_CH2_CTRLA _SFR_MEM8(0x0130)
2773 #define DMA_CH2_CTRLB _SFR_MEM8(0x0131)
2774 #define DMA_CH2_ADDRCTRL _SFR_MEM8(0x0132)
2775 #define DMA_CH2_TRIGSRC _SFR_MEM8(0x0133)
2776 #define DMA_CH2_TRFCNT _SFR_MEM16(0x0134)
2777 #define DMA_CH2_REPCNT _SFR_MEM8(0x0136)
2778 #define DMA_CH2_SRCADDR0 _SFR_MEM8(0x0138)
2779 #define DMA_CH2_SRCADDR1 _SFR_MEM8(0x0139)
2780 #define DMA_CH2_SRCADDR2 _SFR_MEM8(0x013A)
2781 #define DMA_CH2_DESTADDR0 _SFR_MEM8(0x013C)
2782 #define DMA_CH2_DESTADDR1 _SFR_MEM8(0x013D)
2783 #define DMA_CH2_DESTADDR2 _SFR_MEM8(0x013E)
2784 #define DMA_CH3_CTRLA _SFR_MEM8(0x0140)
2785 #define DMA_CH3_CTRLB _SFR_MEM8(0x0141)
2786 #define DMA_CH3_ADDRCTRL _SFR_MEM8(0x0142)
2787 #define DMA_CH3_TRIGSRC _SFR_MEM8(0x0143)
2788 #define DMA_CH3_TRFCNT _SFR_MEM16(0x0144)
2789 #define DMA_CH3_REPCNT _SFR_MEM8(0x0146)
2790 #define DMA_CH3_SRCADDR0 _SFR_MEM8(0x0148)
2791 #define DMA_CH3_SRCADDR1 _SFR_MEM8(0x0149)
2792 #define DMA_CH3_SRCADDR2 _SFR_MEM8(0x014A)
2793 #define DMA_CH3_DESTADDR0 _SFR_MEM8(0x014C)
2794 #define DMA_CH3_DESTADDR1 _SFR_MEM8(0x014D)
2795 #define DMA_CH3_DESTADDR2 _SFR_MEM8(0x014E)
2796 
2797 /* EVSYS - Event System */
2798 #define EVSYS_CH0MUX _SFR_MEM8(0x0180)
2799 #define EVSYS_CH1MUX _SFR_MEM8(0x0181)
2800 #define EVSYS_CH2MUX _SFR_MEM8(0x0182)
2801 #define EVSYS_CH3MUX _SFR_MEM8(0x0183)
2802 #define EVSYS_CH4MUX _SFR_MEM8(0x0184)
2803 #define EVSYS_CH5MUX _SFR_MEM8(0x0185)
2804 #define EVSYS_CH6MUX _SFR_MEM8(0x0186)
2805 #define EVSYS_CH7MUX _SFR_MEM8(0x0187)
2806 #define EVSYS_CH0CTRL _SFR_MEM8(0x0188)
2807 #define EVSYS_CH1CTRL _SFR_MEM8(0x0189)
2808 #define EVSYS_CH2CTRL _SFR_MEM8(0x018A)
2809 #define EVSYS_CH3CTRL _SFR_MEM8(0x018B)
2810 #define EVSYS_CH4CTRL _SFR_MEM8(0x018C)
2811 #define EVSYS_CH5CTRL _SFR_MEM8(0x018D)
2812 #define EVSYS_CH6CTRL _SFR_MEM8(0x018E)
2813 #define EVSYS_CH7CTRL _SFR_MEM8(0x018F)
2814 #define EVSYS_STROBE _SFR_MEM8(0x0190)
2815 #define EVSYS_DATA _SFR_MEM8(0x0191)
2816 
2817 /* NVM - Non Volatile Memory Controller */
2818 #define NVM_ADDR0 _SFR_MEM8(0x01C0)
2819 #define NVM_ADDR1 _SFR_MEM8(0x01C1)
2820 #define NVM_ADDR2 _SFR_MEM8(0x01C2)
2821 #define NVM_DATA0 _SFR_MEM8(0x01C4)
2822 #define NVM_DATA1 _SFR_MEM8(0x01C5)
2823 #define NVM_DATA2 _SFR_MEM8(0x01C6)
2824 #define NVM_CMD _SFR_MEM8(0x01CA)
2825 #define NVM_CTRLA _SFR_MEM8(0x01CB)
2826 #define NVM_CTRLB _SFR_MEM8(0x01CC)
2827 #define NVM_INTCTRL _SFR_MEM8(0x01CD)
2828 #define NVM_STATUS _SFR_MEM8(0x01CF)
2829 #define NVM_LOCKBITS _SFR_MEM8(0x01D0)
2830 
2831 /* ADCA - Analog to Digital Converter A */
2832 #define ADCA_CTRLA _SFR_MEM8(0x0200)
2833 #define ADCA_CTRLB _SFR_MEM8(0x0201)
2834 #define ADCA_REFCTRL _SFR_MEM8(0x0202)
2835 #define ADCA_EVCTRL _SFR_MEM8(0x0203)
2836 #define ADCA_PRESCALER _SFR_MEM8(0x0204)
2837 #define ADCA_CALCTRL _SFR_MEM8(0x0205)
2838 #define ADCA_INTFLAGS _SFR_MEM8(0x0206)
2839 #define ADCA_CAL _SFR_MEM16(0x020C)
2840 #define ADCA_CH0RES _SFR_MEM16(0x0210)
2841 #define ADCA_CH1RES _SFR_MEM16(0x0212)
2842 #define ADCA_CH2RES _SFR_MEM16(0x0214)
2843 #define ADCA_CH3RES _SFR_MEM16(0x0216)
2844 #define ADCA_CMP _SFR_MEM16(0x0218)
2845 #define ADCA_CH0_CTRL _SFR_MEM8(0x0220)
2846 #define ADCA_CH0_MUXCTRL _SFR_MEM8(0x0221)
2847 #define ADCA_CH0_INTCTRL _SFR_MEM8(0x0222)
2848 #define ADCA_CH0_INTFLAGS _SFR_MEM8(0x0223)
2849 #define ADCA_CH0_RES _SFR_MEM16(0x0224)
2850 #define ADCA_CH1_CTRL _SFR_MEM8(0x0228)
2851 #define ADCA_CH1_MUXCTRL _SFR_MEM8(0x0229)
2852 #define ADCA_CH1_INTCTRL _SFR_MEM8(0x022A)
2853 #define ADCA_CH1_INTFLAGS _SFR_MEM8(0x022B)
2854 #define ADCA_CH1_RES _SFR_MEM16(0x022C)
2855 #define ADCA_CH2_CTRL _SFR_MEM8(0x0230)
2856 #define ADCA_CH2_MUXCTRL _SFR_MEM8(0x0231)
2857 #define ADCA_CH2_INTCTRL _SFR_MEM8(0x0232)
2858 #define ADCA_CH2_INTFLAGS _SFR_MEM8(0x0233)
2859 #define ADCA_CH2_RES _SFR_MEM16(0x0234)
2860 #define ADCA_CH3_CTRL _SFR_MEM8(0x0238)
2861 #define ADCA_CH3_MUXCTRL _SFR_MEM8(0x0239)
2862 #define ADCA_CH3_INTCTRL _SFR_MEM8(0x023A)
2863 #define ADCA_CH3_INTFLAGS _SFR_MEM8(0x023B)
2864 #define ADCA_CH3_RES _SFR_MEM16(0x023C)
2865 
2866 /* DACB - Digital to Analog Converter B */
2867 #define DACB_CTRLA _SFR_MEM8(0x0320)
2868 #define DACB_CTRLB _SFR_MEM8(0x0321)
2869 #define DACB_CTRLC _SFR_MEM8(0x0322)
2870 #define DACB_EVCTRL _SFR_MEM8(0x0323)
2871 #define DACB_TIMCTRL _SFR_MEM8(0x0324)
2872 #define DACB_STATUS _SFR_MEM8(0x0325)
2873 #define DACB_GAINCAL _SFR_MEM8(0x0328)
2874 #define DACB_OFFSETCAL _SFR_MEM8(0x0329)
2875 #define DACB_CH0DATA _SFR_MEM16(0x0338)
2876 #define DACB_CH1DATA _SFR_MEM16(0x033A)
2877 
2878 /* ACA - Analog Comparator A */
2879 #define ACA_AC0CTRL _SFR_MEM8(0x0380)
2880 #define ACA_AC1CTRL _SFR_MEM8(0x0381)
2881 #define ACA_AC0MUXCTRL _SFR_MEM8(0x0382)
2882 #define ACA_AC1MUXCTRL _SFR_MEM8(0x0383)
2883 #define ACA_CTRLA _SFR_MEM8(0x0384)
2884 #define ACA_CTRLB _SFR_MEM8(0x0385)
2885 #define ACA_WINCTRL _SFR_MEM8(0x0386)
2886 #define ACA_STATUS _SFR_MEM8(0x0387)
2887 
2888 /* RTC - Real-Time Counter */
2889 #define RTC_CTRL _SFR_MEM8(0x0400)
2890 #define RTC_STATUS _SFR_MEM8(0x0401)
2891 #define RTC_INTCTRL _SFR_MEM8(0x0402)
2892 #define RTC_INTFLAGS _SFR_MEM8(0x0403)
2893 #define RTC_TEMP _SFR_MEM8(0x0404)
2894 #define RTC_CNT _SFR_MEM16(0x0408)
2895 #define RTC_PER _SFR_MEM16(0x040A)
2896 #define RTC_COMP _SFR_MEM16(0x040C)
2897 
2898 /* TWIC - Two-Wire Interface C */
2899 #define TWIC_CTRL _SFR_MEM8(0x0480)
2900 #define TWIC_MASTER_CTRLA _SFR_MEM8(0x0481)
2901 #define TWIC_MASTER_CTRLB _SFR_MEM8(0x0482)
2902 #define TWIC_MASTER_CTRLC _SFR_MEM8(0x0483)
2903 #define TWIC_MASTER_STATUS _SFR_MEM8(0x0484)
2904 #define TWIC_MASTER_BAUD _SFR_MEM8(0x0485)
2905 #define TWIC_MASTER_ADDR _SFR_MEM8(0x0486)
2906 #define TWIC_MASTER_DATA _SFR_MEM8(0x0487)
2907 #define TWIC_SLAVE_CTRLA _SFR_MEM8(0x0488)
2908 #define TWIC_SLAVE_CTRLB _SFR_MEM8(0x0489)
2909 #define TWIC_SLAVE_STATUS _SFR_MEM8(0x048A)
2910 #define TWIC_SLAVE_ADDR _SFR_MEM8(0x048B)
2911 #define TWIC_SLAVE_DATA _SFR_MEM8(0x048C)
2912 #define TWIC_SLAVE_ADDRMASK _SFR_MEM8(0x048D)
2913 
2914 /* TWIE - Two-Wire Interface E */
2915 #define TWIE_CTRL _SFR_MEM8(0x04A0)
2916 #define TWIE_MASTER_CTRLA _SFR_MEM8(0x04A1)
2917 #define TWIE_MASTER_CTRLB _SFR_MEM8(0x04A2)
2918 #define TWIE_MASTER_CTRLC _SFR_MEM8(0x04A3)
2919 #define TWIE_MASTER_STATUS _SFR_MEM8(0x04A4)
2920 #define TWIE_MASTER_BAUD _SFR_MEM8(0x04A5)
2921 #define TWIE_MASTER_ADDR _SFR_MEM8(0x04A6)
2922 #define TWIE_MASTER_DATA _SFR_MEM8(0x04A7)
2923 #define TWIE_SLAVE_CTRLA _SFR_MEM8(0x04A8)
2924 #define TWIE_SLAVE_CTRLB _SFR_MEM8(0x04A9)
2925 #define TWIE_SLAVE_STATUS _SFR_MEM8(0x04AA)
2926 #define TWIE_SLAVE_ADDR _SFR_MEM8(0x04AB)
2927 #define TWIE_SLAVE_DATA _SFR_MEM8(0x04AC)
2928 #define TWIE_SLAVE_ADDRMASK _SFR_MEM8(0x04AD)
2929 
2930 /* PORTA - Port A */
2931 #define PORTA_DIR _SFR_MEM8(0x0600)
2932 #define PORTA_DIRSET _SFR_MEM8(0x0601)
2933 #define PORTA_DIRCLR _SFR_MEM8(0x0602)
2934 #define PORTA_DIRTGL _SFR_MEM8(0x0603)
2935 #define PORTA_OUT _SFR_MEM8(0x0604)
2936 #define PORTA_OUTSET _SFR_MEM8(0x0605)
2937 #define PORTA_OUTCLR _SFR_MEM8(0x0606)
2938 #define PORTA_OUTTGL _SFR_MEM8(0x0607)
2939 #define PORTA_IN _SFR_MEM8(0x0608)
2940 #define PORTA_INTCTRL _SFR_MEM8(0x0609)
2941 #define PORTA_INT0MASK _SFR_MEM8(0x060A)
2942 #define PORTA_INT1MASK _SFR_MEM8(0x060B)
2943 #define PORTA_INTFLAGS _SFR_MEM8(0x060C)
2944 #define PORTA_PIN0CTRL _SFR_MEM8(0x0610)
2945 #define PORTA_PIN1CTRL _SFR_MEM8(0x0611)
2946 #define PORTA_PIN2CTRL _SFR_MEM8(0x0612)
2947 #define PORTA_PIN3CTRL _SFR_MEM8(0x0613)
2948 #define PORTA_PIN4CTRL _SFR_MEM8(0x0614)
2949 #define PORTA_PIN5CTRL _SFR_MEM8(0x0615)
2950 #define PORTA_PIN6CTRL _SFR_MEM8(0x0616)
2951 #define PORTA_PIN7CTRL _SFR_MEM8(0x0617)
2952 
2953 /* PORTB - Port B */
2954 #define PORTB_DIR _SFR_MEM8(0x0620)
2955 #define PORTB_DIRSET _SFR_MEM8(0x0621)
2956 #define PORTB_DIRCLR _SFR_MEM8(0x0622)
2957 #define PORTB_DIRTGL _SFR_MEM8(0x0623)
2958 #define PORTB_OUT _SFR_MEM8(0x0624)
2959 #define PORTB_OUTSET _SFR_MEM8(0x0625)
2960 #define PORTB_OUTCLR _SFR_MEM8(0x0626)
2961 #define PORTB_OUTTGL _SFR_MEM8(0x0627)
2962 #define PORTB_IN _SFR_MEM8(0x0628)
2963 #define PORTB_INTCTRL _SFR_MEM8(0x0629)
2964 #define PORTB_INT0MASK _SFR_MEM8(0x062A)
2965 #define PORTB_INT1MASK _SFR_MEM8(0x062B)
2966 #define PORTB_INTFLAGS _SFR_MEM8(0x062C)
2967 #define PORTB_PIN0CTRL _SFR_MEM8(0x0630)
2968 #define PORTB_PIN1CTRL _SFR_MEM8(0x0631)
2969 #define PORTB_PIN2CTRL _SFR_MEM8(0x0632)
2970 #define PORTB_PIN3CTRL _SFR_MEM8(0x0633)
2971 #define PORTB_PIN4CTRL _SFR_MEM8(0x0634)
2972 #define PORTB_PIN5CTRL _SFR_MEM8(0x0635)
2973 #define PORTB_PIN6CTRL _SFR_MEM8(0x0636)
2974 #define PORTB_PIN7CTRL _SFR_MEM8(0x0637)
2975 
2976 /* PORTC - Port C */
2977 #define PORTC_DIR _SFR_MEM8(0x0640)
2978 #define PORTC_DIRSET _SFR_MEM8(0x0641)
2979 #define PORTC_DIRCLR _SFR_MEM8(0x0642)
2980 #define PORTC_DIRTGL _SFR_MEM8(0x0643)
2981 #define PORTC_OUT _SFR_MEM8(0x0644)
2982 #define PORTC_OUTSET _SFR_MEM8(0x0645)
2983 #define PORTC_OUTCLR _SFR_MEM8(0x0646)
2984 #define PORTC_OUTTGL _SFR_MEM8(0x0647)
2985 #define PORTC_IN _SFR_MEM8(0x0648)
2986 #define PORTC_INTCTRL _SFR_MEM8(0x0649)
2987 #define PORTC_INT0MASK _SFR_MEM8(0x064A)
2988 #define PORTC_INT1MASK _SFR_MEM8(0x064B)
2989 #define PORTC_INTFLAGS _SFR_MEM8(0x064C)
2990 #define PORTC_PIN0CTRL _SFR_MEM8(0x0650)
2991 #define PORTC_PIN1CTRL _SFR_MEM8(0x0651)
2992 #define PORTC_PIN2CTRL _SFR_MEM8(0x0652)
2993 #define PORTC_PIN3CTRL _SFR_MEM8(0x0653)
2994 #define PORTC_PIN4CTRL _SFR_MEM8(0x0654)
2995 #define PORTC_PIN5CTRL _SFR_MEM8(0x0655)
2996 #define PORTC_PIN6CTRL _SFR_MEM8(0x0656)
2997 #define PORTC_PIN7CTRL _SFR_MEM8(0x0657)
2998 
2999 /* PORTD - Port D */
3000 #define PORTD_DIR _SFR_MEM8(0x0660)
3001 #define PORTD_DIRSET _SFR_MEM8(0x0661)
3002 #define PORTD_DIRCLR _SFR_MEM8(0x0662)
3003 #define PORTD_DIRTGL _SFR_MEM8(0x0663)
3004 #define PORTD_OUT _SFR_MEM8(0x0664)
3005 #define PORTD_OUTSET _SFR_MEM8(0x0665)
3006 #define PORTD_OUTCLR _SFR_MEM8(0x0666)
3007 #define PORTD_OUTTGL _SFR_MEM8(0x0667)
3008 #define PORTD_IN _SFR_MEM8(0x0668)
3009 #define PORTD_INTCTRL _SFR_MEM8(0x0669)
3010 #define PORTD_INT0MASK _SFR_MEM8(0x066A)
3011 #define PORTD_INT1MASK _SFR_MEM8(0x066B)
3012 #define PORTD_INTFLAGS _SFR_MEM8(0x066C)
3013 #define PORTD_PIN0CTRL _SFR_MEM8(0x0670)
3014 #define PORTD_PIN1CTRL _SFR_MEM8(0x0671)
3015 #define PORTD_PIN2CTRL _SFR_MEM8(0x0672)
3016 #define PORTD_PIN3CTRL _SFR_MEM8(0x0673)
3017 #define PORTD_PIN4CTRL _SFR_MEM8(0x0674)
3018 #define PORTD_PIN5CTRL _SFR_MEM8(0x0675)
3019 #define PORTD_PIN6CTRL _SFR_MEM8(0x0676)
3020 #define PORTD_PIN7CTRL _SFR_MEM8(0x0677)
3021 
3022 /* PORTE - Port E */
3023 #define PORTE_DIR _SFR_MEM8(0x0680)
3024 #define PORTE_DIRSET _SFR_MEM8(0x0681)
3025 #define PORTE_DIRCLR _SFR_MEM8(0x0682)
3026 #define PORTE_DIRTGL _SFR_MEM8(0x0683)
3027 #define PORTE_OUT _SFR_MEM8(0x0684)
3028 #define PORTE_OUTSET _SFR_MEM8(0x0685)
3029 #define PORTE_OUTCLR _SFR_MEM8(0x0686)
3030 #define PORTE_OUTTGL _SFR_MEM8(0x0687)
3031 #define PORTE_IN _SFR_MEM8(0x0688)
3032 #define PORTE_INTCTRL _SFR_MEM8(0x0689)
3033 #define PORTE_INT0MASK _SFR_MEM8(0x068A)
3034 #define PORTE_INT1MASK _SFR_MEM8(0x068B)
3035 #define PORTE_INTFLAGS _SFR_MEM8(0x068C)
3036 #define PORTE_PIN0CTRL _SFR_MEM8(0x0690)
3037 #define PORTE_PIN1CTRL _SFR_MEM8(0x0691)
3038 #define PORTE_PIN2CTRL _SFR_MEM8(0x0692)
3039 #define PORTE_PIN3CTRL _SFR_MEM8(0x0693)
3040 #define PORTE_PIN4CTRL _SFR_MEM8(0x0694)
3041 #define PORTE_PIN5CTRL _SFR_MEM8(0x0695)
3042 #define PORTE_PIN6CTRL _SFR_MEM8(0x0696)
3043 #define PORTE_PIN7CTRL _SFR_MEM8(0x0697)
3044 
3045 /* PORTR - Port R */
3046 #define PORTR_DIR _SFR_MEM8(0x07E0)
3047 #define PORTR_DIRSET _SFR_MEM8(0x07E1)
3048 #define PORTR_DIRCLR _SFR_MEM8(0x07E2)
3049 #define PORTR_DIRTGL _SFR_MEM8(0x07E3)
3050 #define PORTR_OUT _SFR_MEM8(0x07E4)
3051 #define PORTR_OUTSET _SFR_MEM8(0x07E5)
3052 #define PORTR_OUTCLR _SFR_MEM8(0x07E6)
3053 #define PORTR_OUTTGL _SFR_MEM8(0x07E7)
3054 #define PORTR_IN _SFR_MEM8(0x07E8)
3055 #define PORTR_INTCTRL _SFR_MEM8(0x07E9)
3056 #define PORTR_INT0MASK _SFR_MEM8(0x07EA)
3057 #define PORTR_INT1MASK _SFR_MEM8(0x07EB)
3058 #define PORTR_INTFLAGS _SFR_MEM8(0x07EC)
3059 #define PORTR_PIN0CTRL _SFR_MEM8(0x07F0)
3060 #define PORTR_PIN1CTRL _SFR_MEM8(0x07F1)
3061 #define PORTR_PIN2CTRL _SFR_MEM8(0x07F2)
3062 #define PORTR_PIN3CTRL _SFR_MEM8(0x07F3)
3063 #define PORTR_PIN4CTRL _SFR_MEM8(0x07F4)
3064 #define PORTR_PIN5CTRL _SFR_MEM8(0x07F5)
3065 #define PORTR_PIN6CTRL _SFR_MEM8(0x07F6)
3066 #define PORTR_PIN7CTRL _SFR_MEM8(0x07F7)
3067 
3068 /* TCC0 - Timer/Counter C0 */
3069 #define TCC0_CTRLA _SFR_MEM8(0x0800)
3070 #define TCC0_CTRLB _SFR_MEM8(0x0801)
3071 #define TCC0_CTRLC _SFR_MEM8(0x0802)
3072 #define TCC0_CTRLD _SFR_MEM8(0x0803)
3073 #define TCC0_CTRLE _SFR_MEM8(0x0804)
3074 #define TCC0_INTCTRLA _SFR_MEM8(0x0806)
3075 #define TCC0_INTCTRLB _SFR_MEM8(0x0807)
3076 #define TCC0_CTRLFCLR _SFR_MEM8(0x0808)
3077 #define TCC0_CTRLFSET _SFR_MEM8(0x0809)
3078 #define TCC0_CTRLGCLR _SFR_MEM8(0x080A)
3079 #define TCC0_CTRLGSET _SFR_MEM8(0x080B)
3080 #define TCC0_INTFLAGS _SFR_MEM8(0x080C)
3081 #define TCC0_TEMP _SFR_MEM8(0x080F)
3082 #define TCC0_CNT _SFR_MEM16(0x0820)
3083 #define TCC0_PER _SFR_MEM16(0x0826)
3084 #define TCC0_CCA _SFR_MEM16(0x0828)
3085 #define TCC0_CCB _SFR_MEM16(0x082A)
3086 #define TCC0_CCC _SFR_MEM16(0x082C)
3087 #define TCC0_CCD _SFR_MEM16(0x082E)
3088 #define TCC0_PERBUF _SFR_MEM16(0x0836)
3089 #define TCC0_CCABUF _SFR_MEM16(0x0838)
3090 #define TCC0_CCBBUF _SFR_MEM16(0x083A)
3091 #define TCC0_CCCBUF _SFR_MEM16(0x083C)
3092 #define TCC0_CCDBUF _SFR_MEM16(0x083E)
3093 
3094 /* TCC1 - Timer/Counter C1 */
3095 #define TCC1_CTRLA _SFR_MEM8(0x0840)
3096 #define TCC1_CTRLB _SFR_MEM8(0x0841)
3097 #define TCC1_CTRLC _SFR_MEM8(0x0842)
3098 #define TCC1_CTRLD _SFR_MEM8(0x0843)
3099 #define TCC1_CTRLE _SFR_MEM8(0x0844)
3100 #define TCC1_INTCTRLA _SFR_MEM8(0x0846)
3101 #define TCC1_INTCTRLB _SFR_MEM8(0x0847)
3102 #define TCC1_CTRLFCLR _SFR_MEM8(0x0848)
3103 #define TCC1_CTRLFSET _SFR_MEM8(0x0849)
3104 #define TCC1_CTRLGCLR _SFR_MEM8(0x084A)
3105 #define TCC1_CTRLGSET _SFR_MEM8(0x084B)
3106 #define TCC1_INTFLAGS _SFR_MEM8(0x084C)
3107 #define TCC1_TEMP _SFR_MEM8(0x084F)
3108 #define TCC1_CNT _SFR_MEM16(0x0860)
3109 #define TCC1_PER _SFR_MEM16(0x0866)
3110 #define TCC1_CCA _SFR_MEM16(0x0868)
3111 #define TCC1_CCB _SFR_MEM16(0x086A)
3112 #define TCC1_PERBUF _SFR_MEM16(0x0876)
3113 #define TCC1_CCABUF _SFR_MEM16(0x0878)
3114 #define TCC1_CCBBUF _SFR_MEM16(0x087A)
3115 
3116 /* AWEXC - Advanced Waveform Extension C */
3117 #define AWEXC_CTRL _SFR_MEM8(0x0880)
3118 #define AWEXC_FDEVMASK _SFR_MEM8(0x0882)
3119 #define AWEXC_FDCTRL _SFR_MEM8(0x0883)
3120 #define AWEXC_STATUS _SFR_MEM8(0x0884)
3121 #define AWEXC_DTBOTH _SFR_MEM8(0x0886)
3122 #define AWEXC_DTBOTHBUF _SFR_MEM8(0x0887)
3123 #define AWEXC_DTLS _SFR_MEM8(0x0888)
3124 #define AWEXC_DTHS _SFR_MEM8(0x0889)
3125 #define AWEXC_DTLSBUF _SFR_MEM8(0x088A)
3126 #define AWEXC_DTHSBUF _SFR_MEM8(0x088B)
3127 #define AWEXC_OUTOVEN _SFR_MEM8(0x088C)
3128 
3129 /* HIRESC - High-Resolution Extension C */
3130 #define HIRESC_CTRL _SFR_MEM8(0x0890)
3131 
3132 /* USARTC0 - Universal Asynchronous Receiver-Transmitter C0 */
3133 #define USARTC0_DATA _SFR_MEM8(0x08A0)
3134 #define USARTC0_STATUS _SFR_MEM8(0x08A1)
3135 #define USARTC0_CTRLA _SFR_MEM8(0x08A3)
3136 #define USARTC0_CTRLB _SFR_MEM8(0x08A4)
3137 #define USARTC0_CTRLC _SFR_MEM8(0x08A5)
3138 #define USARTC0_BAUDCTRLA _SFR_MEM8(0x08A6)
3139 #define USARTC0_BAUDCTRLB _SFR_MEM8(0x08A7)
3140 
3141 /* USARTC1 - Universal Asynchronous Receiver-Transmitter C1 */
3142 #define USARTC1_DATA _SFR_MEM8(0x08B0)
3143 #define USARTC1_STATUS _SFR_MEM8(0x08B1)
3144 #define USARTC1_CTRLA _SFR_MEM8(0x08B3)
3145 #define USARTC1_CTRLB _SFR_MEM8(0x08B4)
3146 #define USARTC1_CTRLC _SFR_MEM8(0x08B5)
3147 #define USARTC1_BAUDCTRLA _SFR_MEM8(0x08B6)
3148 #define USARTC1_BAUDCTRLB _SFR_MEM8(0x08B7)
3149 
3150 /* SPIC - Serial Peripheral Interface C */
3151 #define SPIC_CTRL _SFR_MEM8(0x08C0)
3152 #define SPIC_INTCTRL _SFR_MEM8(0x08C1)
3153 #define SPIC_STATUS _SFR_MEM8(0x08C2)
3154 #define SPIC_DATA _SFR_MEM8(0x08C3)
3155 
3156 /* IRCOM - IR Communication Module */
3157 #define IRCOM_CTRL _SFR_MEM8(0x08F8)
3158 #define IRCOM_TXPLCTRL _SFR_MEM8(0x08F9)
3159 #define IRCOM_RXPLCTRL _SFR_MEM8(0x08FA)
3160 
3161 /* TCD0 - Timer/Counter D0 */
3162 #define TCD0_CTRLA _SFR_MEM8(0x0900)
3163 #define TCD0_CTRLB _SFR_MEM8(0x0901)
3164 #define TCD0_CTRLC _SFR_MEM8(0x0902)
3165 #define TCD0_CTRLD _SFR_MEM8(0x0903)
3166 #define TCD0_CTRLE _SFR_MEM8(0x0904)
3167 #define TCD0_INTCTRLA _SFR_MEM8(0x0906)
3168 #define TCD0_INTCTRLB _SFR_MEM8(0x0907)
3169 #define TCD0_CTRLFCLR _SFR_MEM8(0x0908)
3170 #define TCD0_CTRLFSET _SFR_MEM8(0x0909)
3171 #define TCD0_CTRLGCLR _SFR_MEM8(0x090A)
3172 #define TCD0_CTRLGSET _SFR_MEM8(0x090B)
3173 #define TCD0_INTFLAGS _SFR_MEM8(0x090C)
3174 #define TCD0_TEMP _SFR_MEM8(0x090F)
3175 #define TCD0_CNT _SFR_MEM16(0x0920)
3176 #define TCD0_PER _SFR_MEM16(0x0926)
3177 #define TCD0_CCA _SFR_MEM16(0x0928)
3178 #define TCD0_CCB _SFR_MEM16(0x092A)
3179 #define TCD0_CCC _SFR_MEM16(0x092C)
3180 #define TCD0_CCD _SFR_MEM16(0x092E)
3181 #define TCD0_PERBUF _SFR_MEM16(0x0936)
3182 #define TCD0_CCABUF _SFR_MEM16(0x0938)
3183 #define TCD0_CCBBUF _SFR_MEM16(0x093A)
3184 #define TCD0_CCCBUF _SFR_MEM16(0x093C)
3185 #define TCD0_CCDBUF _SFR_MEM16(0x093E)
3186 
3187 /* TCD1 - Timer/Counter D1 */
3188 #define TCD1_CTRLA _SFR_MEM8(0x0940)
3189 #define TCD1_CTRLB _SFR_MEM8(0x0941)
3190 #define TCD1_CTRLC _SFR_MEM8(0x0942)
3191 #define TCD1_CTRLD _SFR_MEM8(0x0943)
3192 #define TCD1_CTRLE _SFR_MEM8(0x0944)
3193 #define TCD1_INTCTRLA _SFR_MEM8(0x0946)
3194 #define TCD1_INTCTRLB _SFR_MEM8(0x0947)
3195 #define TCD1_CTRLFCLR _SFR_MEM8(0x0948)
3196 #define TCD1_CTRLFSET _SFR_MEM8(0x0949)
3197 #define TCD1_CTRLGCLR _SFR_MEM8(0x094A)
3198 #define TCD1_CTRLGSET _SFR_MEM8(0x094B)
3199 #define TCD1_INTFLAGS _SFR_MEM8(0x094C)
3200 #define TCD1_TEMP _SFR_MEM8(0x094F)
3201 #define TCD1_CNT _SFR_MEM16(0x0960)
3202 #define TCD1_PER _SFR_MEM16(0x0966)
3203 #define TCD1_CCA _SFR_MEM16(0x0968)
3204 #define TCD1_CCB _SFR_MEM16(0x096A)
3205 #define TCD1_PERBUF _SFR_MEM16(0x0976)
3206 #define TCD1_CCABUF _SFR_MEM16(0x0978)
3207 #define TCD1_CCBBUF _SFR_MEM16(0x097A)
3208 
3209 /* HIRESD - High-Resolution Extension D */
3210 #define HIRESD_CTRL _SFR_MEM8(0x0990)
3211 
3212 /* USARTD0 - Universal Asynchronous Receiver-Transmitter D0 */
3213 #define USARTD0_DATA _SFR_MEM8(0x09A0)
3214 #define USARTD0_STATUS _SFR_MEM8(0x09A1)
3215 #define USARTD0_CTRLA _SFR_MEM8(0x09A3)
3216 #define USARTD0_CTRLB _SFR_MEM8(0x09A4)
3217 #define USARTD0_CTRLC _SFR_MEM8(0x09A5)
3218 #define USARTD0_BAUDCTRLA _SFR_MEM8(0x09A6)
3219 #define USARTD0_BAUDCTRLB _SFR_MEM8(0x09A7)
3220 
3221 /* USARTD1 - Universal Asynchronous Receiver-Transmitter D1 */
3222 #define USARTD1_DATA _SFR_MEM8(0x09B0)
3223 #define USARTD1_STATUS _SFR_MEM8(0x09B1)
3224 #define USARTD1_CTRLA _SFR_MEM8(0x09B3)
3225 #define USARTD1_CTRLB _SFR_MEM8(0x09B4)
3226 #define USARTD1_CTRLC _SFR_MEM8(0x09B5)
3227 #define USARTD1_BAUDCTRLA _SFR_MEM8(0x09B6)
3228 #define USARTD1_BAUDCTRLB _SFR_MEM8(0x09B7)
3229 
3230 /* SPID - Serial Peripheral Interface D */
3231 #define SPID_CTRL _SFR_MEM8(0x09C0)
3232 #define SPID_INTCTRL _SFR_MEM8(0x09C1)
3233 #define SPID_STATUS _SFR_MEM8(0x09C2)
3234 #define SPID_DATA _SFR_MEM8(0x09C3)
3235 
3236 /* TCE0 - Timer/Counter E0 */
3237 #define TCE0_CTRLA _SFR_MEM8(0x0A00)
3238 #define TCE0_CTRLB _SFR_MEM8(0x0A01)
3239 #define TCE0_CTRLC _SFR_MEM8(0x0A02)
3240 #define TCE0_CTRLD _SFR_MEM8(0x0A03)
3241 #define TCE0_CTRLE _SFR_MEM8(0x0A04)
3242 #define TCE0_INTCTRLA _SFR_MEM8(0x0A06)
3243 #define TCE0_INTCTRLB _SFR_MEM8(0x0A07)
3244 #define TCE0_CTRLFCLR _SFR_MEM8(0x0A08)
3245 #define TCE0_CTRLFSET _SFR_MEM8(0x0A09)
3246 #define TCE0_CTRLGCLR _SFR_MEM8(0x0A0A)
3247 #define TCE0_CTRLGSET _SFR_MEM8(0x0A0B)
3248 #define TCE0_INTFLAGS _SFR_MEM8(0x0A0C)
3249 #define TCE0_TEMP _SFR_MEM8(0x0A0F)
3250 #define TCE0_CNT _SFR_MEM16(0x0A20)
3251 #define TCE0_PER _SFR_MEM16(0x0A26)
3252 #define TCE0_CCA _SFR_MEM16(0x0A28)
3253 #define TCE0_CCB _SFR_MEM16(0x0A2A)
3254 #define TCE0_CCC _SFR_MEM16(0x0A2C)
3255 #define TCE0_CCD _SFR_MEM16(0x0A2E)
3256 #define TCE0_PERBUF _SFR_MEM16(0x0A36)
3257 #define TCE0_CCABUF _SFR_MEM16(0x0A38)
3258 #define TCE0_CCBBUF _SFR_MEM16(0x0A3A)
3259 #define TCE0_CCCBUF _SFR_MEM16(0x0A3C)
3260 #define TCE0_CCDBUF _SFR_MEM16(0x0A3E)
3261 
3262 /* HIRESE - High-Resolution Extension E */
3263 #define HIRESE_CTRL _SFR_MEM8(0x0A90)
3264 
3265 /* USARTE0 - Universal Asynchronous Receiver-Transmitter E0 */
3266 #define USARTE0_DATA _SFR_MEM8(0x0AA0)
3267 #define USARTE0_STATUS _SFR_MEM8(0x0AA1)
3268 #define USARTE0_CTRLA _SFR_MEM8(0x0AA3)
3269 #define USARTE0_CTRLB _SFR_MEM8(0x0AA4)
3270 #define USARTE0_CTRLC _SFR_MEM8(0x0AA5)
3271 #define USARTE0_BAUDCTRLA _SFR_MEM8(0x0AA6)
3272 #define USARTE0_BAUDCTRLB _SFR_MEM8(0x0AA7)
3273 
3274 
3275 
3276 /*================== Bitfield Definitions ================== */
3277 
3278 /* XOCD - On-Chip Debug System */
3279 /* OCD.OCDR1 bit masks and bit positions */
3280 #define OCD_OCDRD_bm 0x01 /* OCDR Dirty bit mask. */
3281 #define OCD_OCDRD_bp 0 /* OCDR Dirty bit position. */
3282 
3283 
3284 /* CPU - CPU */
3285 /* CPU.CCP bit masks and bit positions */
3286 #define CPU_CCP_gm 0xFF /* CCP signature group mask. */
3287 #define CPU_CCP_gp 0 /* CCP signature group position. */
3288 #define CPU_CCP0_bm (1<<0) /* CCP signature bit 0 mask. */
3289 #define CPU_CCP0_bp 0 /* CCP signature bit 0 position. */
3290 #define CPU_CCP1_bm (1<<1) /* CCP signature bit 1 mask. */
3291 #define CPU_CCP1_bp 1 /* CCP signature bit 1 position. */
3292 #define CPU_CCP2_bm (1<<2) /* CCP signature bit 2 mask. */
3293 #define CPU_CCP2_bp 2 /* CCP signature bit 2 position. */
3294 #define CPU_CCP3_bm (1<<3) /* CCP signature bit 3 mask. */
3295 #define CPU_CCP3_bp 3 /* CCP signature bit 3 position. */
3296 #define CPU_CCP4_bm (1<<4) /* CCP signature bit 4 mask. */
3297 #define CPU_CCP4_bp 4 /* CCP signature bit 4 position. */
3298 #define CPU_CCP5_bm (1<<5) /* CCP signature bit 5 mask. */
3299 #define CPU_CCP5_bp 5 /* CCP signature bit 5 position. */
3300 #define CPU_CCP6_bm (1<<6) /* CCP signature bit 6 mask. */
3301 #define CPU_CCP6_bp 6 /* CCP signature bit 6 position. */
3302 #define CPU_CCP7_bm (1<<7) /* CCP signature bit 7 mask. */
3303 #define CPU_CCP7_bp 7 /* CCP signature bit 7 position. */
3304 
3305 
3306 /* CPU.SREG bit masks and bit positions */
3307 #define CPU_I_bm 0x80 /* Global Interrupt Enable Flag bit mask. */
3308 #define CPU_I_bp 7 /* Global Interrupt Enable Flag bit position. */
3309 
3310 #define CPU_T_bm 0x40 /* Transfer Bit bit mask. */
3311 #define CPU_T_bp 6 /* Transfer Bit bit position. */
3312 
3313 #define CPU_H_bm 0x20 /* Half Carry Flag bit mask. */
3314 #define CPU_H_bp 5 /* Half Carry Flag bit position. */
3315 
3316 #define CPU_S_bm 0x10 /* N Exclusive Or V Flag bit mask. */
3317 #define CPU_S_bp 4 /* N Exclusive Or V Flag bit position. */
3318 
3319 #define CPU_V_bm 0x08 /* Two's Complement Overflow Flag bit mask. */
3320 #define CPU_V_bp 3 /* Two's Complement Overflow Flag bit position. */
3321 
3322 #define CPU_N_bm 0x04 /* Negative Flag bit mask. */
3323 #define CPU_N_bp 2 /* Negative Flag bit position. */
3324 
3325 #define CPU_Z_bm 0x02 /* Zero Flag bit mask. */
3326 #define CPU_Z_bp 1 /* Zero Flag bit position. */
3327 
3328 #define CPU_C_bm 0x01 /* Carry Flag bit mask. */
3329 #define CPU_C_bp 0 /* Carry Flag bit position. */
3330 
3331 
3332 /* CLK - Clock System */
3333 /* CLK.CTRL bit masks and bit positions */
3334 #define CLK_SCLKSEL_gm 0x07 /* System Clock Selection group mask. */
3335 #define CLK_SCLKSEL_gp 0 /* System Clock Selection group position. */
3336 #define CLK_SCLKSEL0_bm (1<<0) /* System Clock Selection bit 0 mask. */
3337 #define CLK_SCLKSEL0_bp 0 /* System Clock Selection bit 0 position. */
3338 #define CLK_SCLKSEL1_bm (1<<1) /* System Clock Selection bit 1 mask. */
3339 #define CLK_SCLKSEL1_bp 1 /* System Clock Selection bit 1 position. */
3340 #define CLK_SCLKSEL2_bm (1<<2) /* System Clock Selection bit 2 mask. */
3341 #define CLK_SCLKSEL2_bp 2 /* System Clock Selection bit 2 position. */
3342 
3343 
3344 /* CLK.PSCTRL bit masks and bit positions */
3345 #define CLK_PSADIV_gm 0x7C /* Prescaler A Division Factor group mask. */
3346 #define CLK_PSADIV_gp 2 /* Prescaler A Division Factor group position. */
3347 #define CLK_PSADIV0_bm (1<<2) /* Prescaler A Division Factor bit 0 mask. */
3348 #define CLK_PSADIV0_bp 2 /* Prescaler A Division Factor bit 0 position. */
3349 #define CLK_PSADIV1_bm (1<<3) /* Prescaler A Division Factor bit 1 mask. */
3350 #define CLK_PSADIV1_bp 3 /* Prescaler A Division Factor bit 1 position. */
3351 #define CLK_PSADIV2_bm (1<<4) /* Prescaler A Division Factor bit 2 mask. */
3352 #define CLK_PSADIV2_bp 4 /* Prescaler A Division Factor bit 2 position. */
3353 #define CLK_PSADIV3_bm (1<<5) /* Prescaler A Division Factor bit 3 mask. */
3354 #define CLK_PSADIV3_bp 5 /* Prescaler A Division Factor bit 3 position. */
3355 #define CLK_PSADIV4_bm (1<<6) /* Prescaler A Division Factor bit 4 mask. */
3356 #define CLK_PSADIV4_bp 6 /* Prescaler A Division Factor bit 4 position. */
3357 
3358 #define CLK_PSBCDIV_gm 0x03 /* Prescaler B and C Division factor group mask. */
3359 #define CLK_PSBCDIV_gp 0 /* Prescaler B and C Division factor group position. */
3360 #define CLK_PSBCDIV0_bm (1<<0) /* Prescaler B and C Division factor bit 0 mask. */
3361 #define CLK_PSBCDIV0_bp 0 /* Prescaler B and C Division factor bit 0 position. */
3362 #define CLK_PSBCDIV1_bm (1<<1) /* Prescaler B and C Division factor bit 1 mask. */
3363 #define CLK_PSBCDIV1_bp 1 /* Prescaler B and C Division factor bit 1 position. */
3364 
3365 
3366 /* CLK.LOCK bit masks and bit positions */
3367 #define CLK_LOCK_bm 0x01 /* Clock System Lock bit mask. */
3368 #define CLK_LOCK_bp 0 /* Clock System Lock bit position. */
3369 
3370 
3371 /* CLK.RTCCTRL bit masks and bit positions */
3372 #define CLK_RTCSRC_gm 0x0E /* Clock Source group mask. */
3373 #define CLK_RTCSRC_gp 1 /* Clock Source group position. */
3374 #define CLK_RTCSRC0_bm (1<<1) /* Clock Source bit 0 mask. */
3375 #define CLK_RTCSRC0_bp 1 /* Clock Source bit 0 position. */
3376 #define CLK_RTCSRC1_bm (1<<2) /* Clock Source bit 1 mask. */
3377 #define CLK_RTCSRC1_bp 2 /* Clock Source bit 1 position. */
3378 #define CLK_RTCSRC2_bm (1<<3) /* Clock Source bit 2 mask. */
3379 #define CLK_RTCSRC2_bp 3 /* Clock Source bit 2 position. */
3380 
3381 #define CLK_RTCEN_bm 0x01 /* RTC Clock Source Enable bit mask. */
3382 #define CLK_RTCEN_bp 0 /* RTC Clock Source Enable bit position. */
3383 
3384 
3385 /* PR.PRGEN bit masks and bit positions */
3386 #define PR_AES_bm 0x10 /* AES bit mask. */
3387 #define PR_AES_bp 4 /* AES bit position. */
3388 
3389 #define PR_EBI_bm 0x08 /* External Bus Interface bit mask. */
3390 #define PR_EBI_bp 3 /* External Bus Interface bit position. */
3391 
3392 #define PR_RTC_bm 0x04 /* Real-time Counter bit mask. */
3393 #define PR_RTC_bp 2 /* Real-time Counter bit position. */
3394 
3395 #define PR_EVSYS_bm 0x02 /* Event System bit mask. */
3396 #define PR_EVSYS_bp 1 /* Event System bit position. */
3397 
3398 #define PR_DMA_bm 0x01 /* DMA-Controller bit mask. */
3399 #define PR_DMA_bp 0 /* DMA-Controller bit position. */
3400 
3401 
3402 /* PR.PRPA bit masks and bit positions */
3403 #define PR_DAC_bm 0x04 /* Port A DAC bit mask. */
3404 #define PR_DAC_bp 2 /* Port A DAC bit position. */
3405 
3406 #define PR_ADC_bm 0x02 /* Port A ADC bit mask. */
3407 #define PR_ADC_bp 1 /* Port A ADC bit position. */
3408 
3409 #define PR_AC_bm 0x01 /* Port A Analog Comparator bit mask. */
3410 #define PR_AC_bp 0 /* Port A Analog Comparator bit position. */
3411 
3412 
3413 /* PR.PRPB bit masks and bit positions */
3414 /* PR_DAC_bm Predefined. */
3415 /* PR_DAC_bp Predefined. */
3416 
3417 /* PR_ADC_bm Predefined. */
3418 /* PR_ADC_bp Predefined. */
3419 
3420 /* PR_AC_bm Predefined. */
3421 /* PR_AC_bp Predefined. */
3422 
3423 
3424 /* PR.PRPC bit masks and bit positions */
3425 #define PR_TWI_bm 0x40 /* Port C Two-wire Interface bit mask. */
3426 #define PR_TWI_bp 6 /* Port C Two-wire Interface bit position. */
3427 
3428 #define PR_USART1_bm 0x20 /* Port C USART1 bit mask. */
3429 #define PR_USART1_bp 5 /* Port C USART1 bit position. */
3430 
3431 #define PR_USART0_bm 0x10 /* Port C USART0 bit mask. */
3432 #define PR_USART0_bp 4 /* Port C USART0 bit position. */
3433 
3434 #define PR_SPI_bm 0x08 /* Port C SPI bit mask. */
3435 #define PR_SPI_bp 3 /* Port C SPI bit position. */
3436 
3437 #define PR_HIRES_bm 0x04 /* Port C AWEX bit mask. */
3438 #define PR_HIRES_bp 2 /* Port C AWEX bit position. */
3439 
3440 #define PR_TC1_bm 0x02 /* Port C Timer/Counter1 bit mask. */
3441 #define PR_TC1_bp 1 /* Port C Timer/Counter1 bit position. */
3442 
3443 #define PR_TC0_bm 0x01 /* Port C Timer/Counter0 bit mask. */
3444 #define PR_TC0_bp 0 /* Port C Timer/Counter0 bit position. */
3445 
3446 
3447 /* PR.PRPD bit masks and bit positions */
3448 /* PR_TWI_bm Predefined. */
3449 /* PR_TWI_bp Predefined. */
3450 
3451 /* PR_USART1_bm Predefined. */
3452 /* PR_USART1_bp Predefined. */
3453 
3454 /* PR_USART0_bm Predefined. */
3455 /* PR_USART0_bp Predefined. */
3456 
3457 /* PR_SPI_bm Predefined. */
3458 /* PR_SPI_bp Predefined. */
3459 
3460 /* PR_HIRES_bm Predefined. */
3461 /* PR_HIRES_bp Predefined. */
3462 
3463 /* PR_TC1_bm Predefined. */
3464 /* PR_TC1_bp Predefined. */
3465 
3466 /* PR_TC0_bm Predefined. */
3467 /* PR_TC0_bp Predefined. */
3468 
3469 
3470 /* PR.PRPE bit masks and bit positions */
3471 /* PR_TWI_bm Predefined. */
3472 /* PR_TWI_bp Predefined. */
3473 
3474 /* PR_USART1_bm Predefined. */
3475 /* PR_USART1_bp Predefined. */
3476 
3477 /* PR_USART0_bm Predefined. */
3478 /* PR_USART0_bp Predefined. */
3479 
3480 /* PR_SPI_bm Predefined. */
3481 /* PR_SPI_bp Predefined. */
3482 
3483 /* PR_HIRES_bm Predefined. */
3484 /* PR_HIRES_bp Predefined. */
3485 
3486 /* PR_TC1_bm Predefined. */
3487 /* PR_TC1_bp Predefined. */
3488 
3489 /* PR_TC0_bm Predefined. */
3490 /* PR_TC0_bp Predefined. */
3491 
3492 
3493 /* PR.PRPF bit masks and bit positions */
3494 /* PR_TWI_bm Predefined. */
3495 /* PR_TWI_bp Predefined. */
3496 
3497 /* PR_USART1_bm Predefined. */
3498 /* PR_USART1_bp Predefined. */
3499 
3500 /* PR_USART0_bm Predefined. */
3501 /* PR_USART0_bp Predefined. */
3502 
3503 /* PR_SPI_bm Predefined. */
3504 /* PR_SPI_bp Predefined. */
3505 
3506 /* PR_HIRES_bm Predefined. */
3507 /* PR_HIRES_bp Predefined. */
3508 
3509 /* PR_TC1_bm Predefined. */
3510 /* PR_TC1_bp Predefined. */
3511 
3512 /* PR_TC0_bm Predefined. */
3513 /* PR_TC0_bp Predefined. */
3514 
3515 
3516 /* SLEEP - Sleep Controller */
3517 /* SLEEP.CTRL bit masks and bit positions */
3518 #define SLEEP_SMODE_gm 0x0E /* Sleep Mode group mask. */
3519 #define SLEEP_SMODE_gp 1 /* Sleep Mode group position. */
3520 #define SLEEP_SMODE0_bm (1<<1) /* Sleep Mode bit 0 mask. */
3521 #define SLEEP_SMODE0_bp 1 /* Sleep Mode bit 0 position. */
3522 #define SLEEP_SMODE1_bm (1<<2) /* Sleep Mode bit 1 mask. */
3523 #define SLEEP_SMODE1_bp 2 /* Sleep Mode bit 1 position. */
3524 #define SLEEP_SMODE2_bm (1<<3) /* Sleep Mode bit 2 mask. */
3525 #define SLEEP_SMODE2_bp 3 /* Sleep Mode bit 2 position. */
3526 
3527 #define SLEEP_SEN_bm 0x01 /* Sleep Enable bit mask. */
3528 #define SLEEP_SEN_bp 0 /* Sleep Enable bit position. */
3529 
3530 
3531 /* OSC - Oscillator */
3532 /* OSC.CTRL bit masks and bit positions */
3533 #define OSC_PLLEN_bm 0x10 /* PLL Enable bit mask. */
3534 #define OSC_PLLEN_bp 4 /* PLL Enable bit position. */
3535 
3536 #define OSC_XOSCEN_bm 0x08 /* External Oscillator Enable bit mask. */
3537 #define OSC_XOSCEN_bp 3 /* External Oscillator Enable bit position. */
3538 
3539 #define OSC_RC32KEN_bm 0x04 /* Internal 32kHz RC Oscillator Enable bit mask. */
3540 #define OSC_RC32KEN_bp 2 /* Internal 32kHz RC Oscillator Enable bit position. */
3541 
3542 #define OSC_RC32MEN_bm 0x02 /* Internal 32MHz RC Oscillator Enable bit mask. */
3543 #define OSC_RC32MEN_bp 1 /* Internal 32MHz RC Oscillator Enable bit position. */
3544 
3545 #define OSC_RC2MEN_bm 0x01 /* Internal 2MHz RC Oscillator Enable bit mask. */
3546 #define OSC_RC2MEN_bp 0 /* Internal 2MHz RC Oscillator Enable bit position. */
3547 
3548 
3549 /* OSC.STATUS bit masks and bit positions */
3550 #define OSC_PLLRDY_bm 0x10 /* PLL Ready bit mask. */
3551 #define OSC_PLLRDY_bp 4 /* PLL Ready bit position. */
3552 
3553 #define OSC_XOSCRDY_bm 0x08 /* External Oscillator Ready bit mask. */
3554 #define OSC_XOSCRDY_bp 3 /* External Oscillator Ready bit position. */
3555 
3556 #define OSC_RC32KRDY_bm 0x04 /* Internal 32kHz RC Oscillator Ready bit mask. */
3557 #define OSC_RC32KRDY_bp 2 /* Internal 32kHz RC Oscillator Ready bit position. */
3558 
3559 #define OSC_RC32MRDY_bm 0x02 /* Internal 32MHz RC Oscillator Ready bit mask. */
3560 #define OSC_RC32MRDY_bp 1 /* Internal 32MHz RC Oscillator Ready bit position. */
3561 
3562 #define OSC_RC2MRDY_bm 0x01 /* Internal 2MHz RC Oscillator Ready bit mask. */
3563 #define OSC_RC2MRDY_bp 0 /* Internal 2MHz RC Oscillator Ready bit position. */
3564 
3565 
3566 /* OSC.XOSCCTRL bit masks and bit positions */
3567 #define OSC_FRQRANGE_gm 0xC0 /* Frequency Range group mask. */
3568 #define OSC_FRQRANGE_gp 6 /* Frequency Range group position. */
3569 #define OSC_FRQRANGE0_bm (1<<6) /* Frequency Range bit 0 mask. */
3570 #define OSC_FRQRANGE0_bp 6 /* Frequency Range bit 0 position. */
3571 #define OSC_FRQRANGE1_bm (1<<7) /* Frequency Range bit 1 mask. */
3572 #define OSC_FRQRANGE1_bp 7 /* Frequency Range bit 1 position. */
3573 
3574 #define OSC_X32KLPM_bm 0x20 /* 32kHz XTAL OSC Low-power Mode bit mask. */
3575 #define OSC_X32KLPM_bp 5 /* 32kHz XTAL OSC Low-power Mode bit position. */
3576 
3577 #define OSC_XOSCSEL_gm 0x0F /* External Oscillator Selection and Startup Time group mask. */
3578 #define OSC_XOSCSEL_gp 0 /* External Oscillator Selection and Startup Time group position. */
3579 #define OSC_XOSCSEL0_bm (1<<0) /* External Oscillator Selection and Startup Time bit 0 mask. */
3580 #define OSC_XOSCSEL0_bp 0 /* External Oscillator Selection and Startup Time bit 0 position. */
3581 #define OSC_XOSCSEL1_bm (1<<1) /* External Oscillator Selection and Startup Time bit 1 mask. */
3582 #define OSC_XOSCSEL1_bp 1 /* External Oscillator Selection and Startup Time bit 1 position. */
3583 #define OSC_XOSCSEL2_bm (1<<2) /* External Oscillator Selection and Startup Time bit 2 mask. */
3584 #define OSC_XOSCSEL2_bp 2 /* External Oscillator Selection and Startup Time bit 2 position. */
3585 #define OSC_XOSCSEL3_bm (1<<3) /* External Oscillator Selection and Startup Time bit 3 mask. */
3586 #define OSC_XOSCSEL3_bp 3 /* External Oscillator Selection and Startup Time bit 3 position. */
3587 
3588 
3589 /* OSC.XOSCFAIL bit masks and bit positions */
3590 #define OSC_XOSCFDIF_bm 0x02 /* Failure Detection Interrupt Flag bit mask. */
3591 #define OSC_XOSCFDIF_bp 1 /* Failure Detection Interrupt Flag bit position. */
3592 
3593 #define OSC_XOSCFDEN_bm 0x01 /* Failure Detection Enable bit mask. */
3594 #define OSC_XOSCFDEN_bp 0 /* Failure Detection Enable bit position. */
3595 
3596 
3597 /* OSC.PLLCTRL bit masks and bit positions */
3598 #define OSC_PLLSRC_gm 0xC0 /* Clock Source group mask. */
3599 #define OSC_PLLSRC_gp 6 /* Clock Source group position. */
3600 #define OSC_PLLSRC0_bm (1<<6) /* Clock Source bit 0 mask. */
3601 #define OSC_PLLSRC0_bp 6 /* Clock Source bit 0 position. */
3602 #define OSC_PLLSRC1_bm (1<<7) /* Clock Source bit 1 mask. */
3603 #define OSC_PLLSRC1_bp 7 /* Clock Source bit 1 position. */
3604 
3605 #define OSC_PLLFAC_gm 0x1F /* Multiplication Factor group mask. */
3606 #define OSC_PLLFAC_gp 0 /* Multiplication Factor group position. */
3607 #define OSC_PLLFAC0_bm (1<<0) /* Multiplication Factor bit 0 mask. */
3608 #define OSC_PLLFAC0_bp 0 /* Multiplication Factor bit 0 position. */
3609 #define OSC_PLLFAC1_bm (1<<1) /* Multiplication Factor bit 1 mask. */
3610 #define OSC_PLLFAC1_bp 1 /* Multiplication Factor bit 1 position. */
3611 #define OSC_PLLFAC2_bm (1<<2) /* Multiplication Factor bit 2 mask. */
3612 #define OSC_PLLFAC2_bp 2 /* Multiplication Factor bit 2 position. */
3613 #define OSC_PLLFAC3_bm (1<<3) /* Multiplication Factor bit 3 mask. */
3614 #define OSC_PLLFAC3_bp 3 /* Multiplication Factor bit 3 position. */
3615 #define OSC_PLLFAC4_bm (1<<4) /* Multiplication Factor bit 4 mask. */
3616 #define OSC_PLLFAC4_bp 4 /* Multiplication Factor bit 4 position. */
3617 
3618 
3619 /* OSC.DFLLCTRL bit masks and bit positions */
3620 #define OSC_RC32MCREF_bm 0x02 /* 32MHz Calibration Reference bit mask. */
3621 #define OSC_RC32MCREF_bp 1 /* 32MHz Calibration Reference bit position. */
3622 
3623 #define OSC_RC2MCREF_bm 0x01 /* 2MHz Calibration Reference bit mask. */
3624 #define OSC_RC2MCREF_bp 0 /* 2MHz Calibration Reference bit position. */
3625 
3626 
3627 /* DFLL - DFLL */
3628 /* DFLL.CTRL bit masks and bit positions */
3629 #define DFLL_ENABLE_bm 0x01 /* DFLL Enable bit mask. */
3630 #define DFLL_ENABLE_bp 0 /* DFLL Enable bit position. */
3631 
3632 
3633 /* DFLL.CALA bit masks and bit positions */
3634 #define DFLL_CALL_gm 0x7F /* DFLL Calibration bits [6:0] group mask. */
3635 #define DFLL_CALL_gp 0 /* DFLL Calibration bits [6:0] group position. */
3636 #define DFLL_CALL0_bm (1<<0) /* DFLL Calibration bits [6:0] bit 0 mask. */
3637 #define DFLL_CALL0_bp 0 /* DFLL Calibration bits [6:0] bit 0 position. */
3638 #define DFLL_CALL1_bm (1<<1) /* DFLL Calibration bits [6:0] bit 1 mask. */
3639 #define DFLL_CALL1_bp 1 /* DFLL Calibration bits [6:0] bit 1 position. */
3640 #define DFLL_CALL2_bm (1<<2) /* DFLL Calibration bits [6:0] bit 2 mask. */
3641 #define DFLL_CALL2_bp 2 /* DFLL Calibration bits [6:0] bit 2 position. */
3642 #define DFLL_CALL3_bm (1<<3) /* DFLL Calibration bits [6:0] bit 3 mask. */
3643 #define DFLL_CALL3_bp 3 /* DFLL Calibration bits [6:0] bit 3 position. */
3644 #define DFLL_CALL4_bm (1<<4) /* DFLL Calibration bits [6:0] bit 4 mask. */
3645 #define DFLL_CALL4_bp 4 /* DFLL Calibration bits [6:0] bit 4 position. */
3646 #define DFLL_CALL5_bm (1<<5) /* DFLL Calibration bits [6:0] bit 5 mask. */
3647 #define DFLL_CALL5_bp 5 /* DFLL Calibration bits [6:0] bit 5 position. */
3648 #define DFLL_CALL6_bm (1<<6) /* DFLL Calibration bits [6:0] bit 6 mask. */
3649 #define DFLL_CALL6_bp 6 /* DFLL Calibration bits [6:0] bit 6 position. */
3650 
3651 
3652 /* DFLL.CALB bit masks and bit positions */
3653 #define DFLL_CALH_gm 0x3F /* DFLL Calibration bits [12:7] group mask. */
3654 #define DFLL_CALH_gp 0 /* DFLL Calibration bits [12:7] group position. */
3655 #define DFLL_CALH0_bm (1<<0) /* DFLL Calibration bits [12:7] bit 0 mask. */
3656 #define DFLL_CALH0_bp 0 /* DFLL Calibration bits [12:7] bit 0 position. */
3657 #define DFLL_CALH1_bm (1<<1) /* DFLL Calibration bits [12:7] bit 1 mask. */
3658 #define DFLL_CALH1_bp 1 /* DFLL Calibration bits [12:7] bit 1 position. */
3659 #define DFLL_CALH2_bm (1<<2) /* DFLL Calibration bits [12:7] bit 2 mask. */
3660 #define DFLL_CALH2_bp 2 /* DFLL Calibration bits [12:7] bit 2 position. */
3661 #define DFLL_CALH3_bm (1<<3) /* DFLL Calibration bits [12:7] bit 3 mask. */
3662 #define DFLL_CALH3_bp 3 /* DFLL Calibration bits [12:7] bit 3 position. */
3663 #define DFLL_CALH4_bm (1<<4) /* DFLL Calibration bits [12:7] bit 4 mask. */
3664 #define DFLL_CALH4_bp 4 /* DFLL Calibration bits [12:7] bit 4 position. */
3665 #define DFLL_CALH5_bm (1<<5) /* DFLL Calibration bits [12:7] bit 5 mask. */
3666 #define DFLL_CALH5_bp 5 /* DFLL Calibration bits [12:7] bit 5 position. */
3667 
3668 
3669 /* RST - Reset */
3670 /* RST.STATUS bit masks and bit positions */
3671 #define RST_SDRF_bm 0x40 /* Spike Detection Reset Flag bit mask. */
3672 #define RST_SDRF_bp 6 /* Spike Detection Reset Flag bit position. */
3673 
3674 #define RST_SRF_bm 0x20 /* Software Reset Flag bit mask. */
3675 #define RST_SRF_bp 5 /* Software Reset Flag bit position. */
3676 
3677 #define RST_PDIRF_bm 0x10 /* Programming and Debug Interface Interface Reset Flag bit mask. */
3678 #define RST_PDIRF_bp 4 /* Programming and Debug Interface Interface Reset Flag bit position. */
3679 
3680 #define RST_WDRF_bm 0x08 /* Watchdog Reset Flag bit mask. */
3681 #define RST_WDRF_bp 3 /* Watchdog Reset Flag bit position. */
3682 
3683 #define RST_BORF_bm 0x04 /* Brown-out Reset Flag bit mask. */
3684 #define RST_BORF_bp 2 /* Brown-out Reset Flag bit position. */
3685 
3686 #define RST_EXTRF_bm 0x02 /* External Reset Flag bit mask. */
3687 #define RST_EXTRF_bp 1 /* External Reset Flag bit position. */
3688 
3689 #define RST_PORF_bm 0x01 /* Power-on Reset Flag bit mask. */
3690 #define RST_PORF_bp 0 /* Power-on Reset Flag bit position. */
3691 
3692 
3693 /* RST.CTRL bit masks and bit positions */
3694 #define RST_SWRST_bm 0x01 /* Software Reset bit mask. */
3695 #define RST_SWRST_bp 0 /* Software Reset bit position. */
3696 
3697 
3698 /* WDT - Watch-Dog Timer */
3699 /* WDT.CTRL bit masks and bit positions */
3700 #define WDT_PER_gm 0x3C /* Period group mask. */
3701 #define WDT_PER_gp 2 /* Period group position. */
3702 #define WDT_PER0_bm (1<<2) /* Period bit 0 mask. */
3703 #define WDT_PER0_bp 2 /* Period bit 0 position. */
3704 #define WDT_PER1_bm (1<<3) /* Period bit 1 mask. */
3705 #define WDT_PER1_bp 3 /* Period bit 1 position. */
3706 #define WDT_PER2_bm (1<<4) /* Period bit 2 mask. */
3707 #define WDT_PER2_bp 4 /* Period bit 2 position. */
3708 #define WDT_PER3_bm (1<<5) /* Period bit 3 mask. */
3709 #define WDT_PER3_bp 5 /* Period bit 3 position. */
3710 
3711 #define WDT_ENABLE_bm 0x02 /* Enable bit mask. */
3712 #define WDT_ENABLE_bp 1 /* Enable bit position. */
3713 
3714 #define WDT_CEN_bm 0x01 /* Change Enable bit mask. */
3715 #define WDT_CEN_bp 0 /* Change Enable bit position. */
3716 
3717 
3718 /* WDT.WINCTRL bit masks and bit positions */
3719 #define WDT_WPER_gm 0x3C /* Windowed Mode Period group mask. */
3720 #define WDT_WPER_gp 2 /* Windowed Mode Period group position. */
3721 #define WDT_WPER0_bm (1<<2) /* Windowed Mode Period bit 0 mask. */
3722 #define WDT_WPER0_bp 2 /* Windowed Mode Period bit 0 position. */
3723 #define WDT_WPER1_bm (1<<3) /* Windowed Mode Period bit 1 mask. */
3724 #define WDT_WPER1_bp 3 /* Windowed Mode Period bit 1 position. */
3725 #define WDT_WPER2_bm (1<<4) /* Windowed Mode Period bit 2 mask. */
3726 #define WDT_WPER2_bp 4 /* Windowed Mode Period bit 2 position. */
3727 #define WDT_WPER3_bm (1<<5) /* Windowed Mode Period bit 3 mask. */
3728 #define WDT_WPER3_bp 5 /* Windowed Mode Period bit 3 position. */
3729 
3730 #define WDT_WEN_bm 0x02 /* Windowed Mode Enable bit mask. */
3731 #define WDT_WEN_bp 1 /* Windowed Mode Enable bit position. */
3732 
3733 #define WDT_WCEN_bm 0x01 /* Windowed Mode Change Enable bit mask. */
3734 #define WDT_WCEN_bp 0 /* Windowed Mode Change Enable bit position. */
3735 
3736 
3737 /* WDT.STATUS bit masks and bit positions */
3738 #define WDT_SYNCBUSY_bm 0x01 /* Syncronization busy bit mask. */
3739 #define WDT_SYNCBUSY_bp 0 /* Syncronization busy bit position. */
3740 
3741 
3742 /* MCU - MCU Control */
3743 /* MCU.MCUCR bit masks and bit positions */
3744 #define MCU_JTAGD_bm 0x01 /* JTAG Disable bit mask. */
3745 #define MCU_JTAGD_bp 0 /* JTAG Disable bit position. */
3746 
3747 
3748 /* MCU.EVSYSLOCK bit masks and bit positions */
3749 #define MCU_EVSYS1LOCK_bm 0x10 /* Event Channel 4-7 Lock bit mask. */
3750 #define MCU_EVSYS1LOCK_bp 4 /* Event Channel 4-7 Lock bit position. */
3751 
3752 #define MCU_EVSYS0LOCK_bm 0x01 /* Event Channel 0-3 Lock bit mask. */
3753 #define MCU_EVSYS0LOCK_bp 0 /* Event Channel 0-3 Lock bit position. */
3754 
3755 
3756 /* MCU.AWEXLOCK bit masks and bit positions */
3757 #define MCU_AWEXELOCK_bm 0x04 /* AWeX on T/C E0 Lock bit mask. */
3758 #define MCU_AWEXELOCK_bp 2 /* AWeX on T/C E0 Lock bit position. */
3759 
3760 #define MCU_AWEXCLOCK_bm 0x01 /* AWeX on T/C C0 Lock bit mask. */
3761 #define MCU_AWEXCLOCK_bp 0 /* AWeX on T/C C0 Lock bit position. */
3762 
3763 
3764 /* PMIC - Programmable Multi-level Interrupt Controller */
3765 /* PMIC.STATUS bit masks and bit positions */
3766 #define PMIC_NMIEX_bm 0x80 /* Non-maskable Interrupt Executing bit mask. */
3767 #define PMIC_NMIEX_bp 7 /* Non-maskable Interrupt Executing bit position. */
3768 
3769 #define PMIC_HILVLEX_bm 0x04 /* High Level Interrupt Executing bit mask. */
3770 #define PMIC_HILVLEX_bp 2 /* High Level Interrupt Executing bit position. */
3771 
3772 #define PMIC_MEDLVLEX_bm 0x02 /* Medium Level Interrupt Executing bit mask. */
3773 #define PMIC_MEDLVLEX_bp 1 /* Medium Level Interrupt Executing bit position. */
3774 
3775 #define PMIC_LOLVLEX_bm 0x01 /* Low Level Interrupt Executing bit mask. */
3776 #define PMIC_LOLVLEX_bp 0 /* Low Level Interrupt Executing bit position. */
3777 
3778 
3779 /* PMIC.CTRL bit masks and bit positions */
3780 #define PMIC_RREN_bm 0x80 /* Round-Robin Priority Enable bit mask. */
3781 #define PMIC_RREN_bp 7 /* Round-Robin Priority Enable bit position. */
3782 
3783 #define PMIC_IVSEL_bm 0x40 /* Interrupt Vector Select bit mask. */
3784 #define PMIC_IVSEL_bp 6 /* Interrupt Vector Select bit position. */
3785 
3786 #define PMIC_HILVLEN_bm 0x04 /* High Level Enable bit mask. */
3787 #define PMIC_HILVLEN_bp 2 /* High Level Enable bit position. */
3788 
3789 #define PMIC_MEDLVLEN_bm 0x02 /* Medium Level Enable bit mask. */
3790 #define PMIC_MEDLVLEN_bp 1 /* Medium Level Enable bit position. */
3791 
3792 #define PMIC_LOLVLEN_bm 0x01 /* Low Level Enable bit mask. */
3793 #define PMIC_LOLVLEN_bp 0 /* Low Level Enable bit position. */
3794 
3795 
3796 /* DMA - DMA Controller */
3797 /* DMA_CH.CTRLA bit masks and bit positions */
3798 #define DMA_CH_ENABLE_bm 0x80 /* Channel Enable bit mask. */
3799 #define DMA_CH_ENABLE_bp 7 /* Channel Enable bit position. */
3800 
3801 #define DMA_CH_RESET_bm 0x40 /* Channel Software Reset bit mask. */
3802 #define DMA_CH_RESET_bp 6 /* Channel Software Reset bit position. */
3803 
3804 #define DMA_CH_REPEAT_bm 0x20 /* Channel Repeat Mode bit mask. */
3805 #define DMA_CH_REPEAT_bp 5 /* Channel Repeat Mode bit position. */
3806 
3807 #define DMA_CH_TRFREQ_bm 0x10 /* Channel Transfer Request bit mask. */
3808 #define DMA_CH_TRFREQ_bp 4 /* Channel Transfer Request bit position. */
3809 
3810 #define DMA_CH_SINGLE_bm 0x04 /* Channel Single Shot Data Transfer bit mask. */
3811 #define DMA_CH_SINGLE_bp 2 /* Channel Single Shot Data Transfer bit position. */
3812 
3813 #define DMA_CH_BURSTLEN_gm 0x03 /* Channel Transfer Mode group mask. */
3814 #define DMA_CH_BURSTLEN_gp 0 /* Channel Transfer Mode group position. */
3815 #define DMA_CH_BURSTLEN0_bm (1<<0) /* Channel Transfer Mode bit 0 mask. */
3816 #define DMA_CH_BURSTLEN0_bp 0 /* Channel Transfer Mode bit 0 position. */
3817 #define DMA_CH_BURSTLEN1_bm (1<<1) /* Channel Transfer Mode bit 1 mask. */
3818 #define DMA_CH_BURSTLEN1_bp 1 /* Channel Transfer Mode bit 1 position. */
3819 
3820 
3821 /* DMA_CH.CTRLB bit masks and bit positions */
3822 #define DMA_CH_CHBUSY_bm 0x80 /* Block Transfer Busy bit mask. */
3823 #define DMA_CH_CHBUSY_bp 7 /* Block Transfer Busy bit position. */
3824 
3825 #define DMA_CH_CHPEND_bm 0x40 /* Block Transfer Pending bit mask. */
3826 #define DMA_CH_CHPEND_bp 6 /* Block Transfer Pending bit position. */
3827 
3828 #define DMA_CH_ERRIF_bm 0x20 /* Block Transfer Error Interrupt Flag bit mask. */
3829 #define DMA_CH_ERRIF_bp 5 /* Block Transfer Error Interrupt Flag bit position. */
3830 
3831 #define DMA_CH_TRNIF_bm 0x10 /* Transaction Complete Interrup Flag bit mask. */
3832 #define DMA_CH_TRNIF_bp 4 /* Transaction Complete Interrup Flag bit position. */
3833 
3834 #define DMA_CH_ERRINTLVL_gm 0x0C /* Transfer Error Interrupt Level group mask. */
3835 #define DMA_CH_ERRINTLVL_gp 2 /* Transfer Error Interrupt Level group position. */
3836 #define DMA_CH_ERRINTLVL0_bm (1<<2) /* Transfer Error Interrupt Level bit 0 mask. */
3837 #define DMA_CH_ERRINTLVL0_bp 2 /* Transfer Error Interrupt Level bit 0 position. */
3838 #define DMA_CH_ERRINTLVL1_bm (1<<3) /* Transfer Error Interrupt Level bit 1 mask. */
3839 #define DMA_CH_ERRINTLVL1_bp 3 /* Transfer Error Interrupt Level bit 1 position. */
3840 
3841 #define DMA_CH_TRNINTLVL_gm 0x03 /* Transaction Complete Interrupt Level group mask. */
3842 #define DMA_CH_TRNINTLVL_gp 0 /* Transaction Complete Interrupt Level group position. */
3843 #define DMA_CH_TRNINTLVL0_bm (1<<0) /* Transaction Complete Interrupt Level bit 0 mask. */
3844 #define DMA_CH_TRNINTLVL0_bp 0 /* Transaction Complete Interrupt Level bit 0 position. */
3845 #define DMA_CH_TRNINTLVL1_bm (1<<1) /* Transaction Complete Interrupt Level bit 1 mask. */
3846 #define DMA_CH_TRNINTLVL1_bp 1 /* Transaction Complete Interrupt Level bit 1 position. */
3847 
3848 
3849 /* DMA_CH.ADDRCTRL bit masks and bit positions */
3850 #define DMA_CH_SRCRELOAD_gm 0xC0 /* Channel Source Address Reload group mask. */
3851 #define DMA_CH_SRCRELOAD_gp 6 /* Channel Source Address Reload group position. */
3852 #define DMA_CH_SRCRELOAD0_bm (1<<6) /* Channel Source Address Reload bit 0 mask. */
3853 #define DMA_CH_SRCRELOAD0_bp 6 /* Channel Source Address Reload bit 0 position. */
3854 #define DMA_CH_SRCRELOAD1_bm (1<<7) /* Channel Source Address Reload bit 1 mask. */
3855 #define DMA_CH_SRCRELOAD1_bp 7 /* Channel Source Address Reload bit 1 position. */
3856 
3857 #define DMA_CH_SRCDIR_gm 0x30 /* Channel Source Address Mode group mask. */
3858 #define DMA_CH_SRCDIR_gp 4 /* Channel Source Address Mode group position. */
3859 #define DMA_CH_SRCDIR0_bm (1<<4) /* Channel Source Address Mode bit 0 mask. */
3860 #define DMA_CH_SRCDIR0_bp 4 /* Channel Source Address Mode bit 0 position. */
3861 #define DMA_CH_SRCDIR1_bm (1<<5) /* Channel Source Address Mode bit 1 mask. */
3862 #define DMA_CH_SRCDIR1_bp 5 /* Channel Source Address Mode bit 1 position. */
3863 
3864 #define DMA_CH_DESTRELOAD_gm 0x0C /* Channel Destination Address Reload group mask. */
3865 #define DMA_CH_DESTRELOAD_gp 2 /* Channel Destination Address Reload group position. */
3866 #define DMA_CH_DESTRELOAD0_bm (1<<2) /* Channel Destination Address Reload bit 0 mask. */
3867 #define DMA_CH_DESTRELOAD0_bp 2 /* Channel Destination Address Reload bit 0 position. */
3868 #define DMA_CH_DESTRELOAD1_bm (1<<3) /* Channel Destination Address Reload bit 1 mask. */
3869 #define DMA_CH_DESTRELOAD1_bp 3 /* Channel Destination Address Reload bit 1 position. */
3870 
3871 #define DMA_CH_DESTDIR_gm 0x03 /* Channel Destination Address Mode group mask. */
3872 #define DMA_CH_DESTDIR_gp 0 /* Channel Destination Address Mode group position. */
3873 #define DMA_CH_DESTDIR0_bm (1<<0) /* Channel Destination Address Mode bit 0 mask. */
3874 #define DMA_CH_DESTDIR0_bp 0 /* Channel Destination Address Mode bit 0 position. */
3875 #define DMA_CH_DESTDIR1_bm (1<<1) /* Channel Destination Address Mode bit 1 mask. */
3876 #define DMA_CH_DESTDIR1_bp 1 /* Channel Destination Address Mode bit 1 position. */
3877 
3878 
3879 /* DMA_CH.TRIGSRC bit masks and bit positions */
3880 #define DMA_CH_TRIGSRC_gm 0xFF /* Channel Trigger Source group mask. */
3881 #define DMA_CH_TRIGSRC_gp 0 /* Channel Trigger Source group position. */
3882 #define DMA_CH_TRIGSRC0_bm (1<<0) /* Channel Trigger Source bit 0 mask. */
3883 #define DMA_CH_TRIGSRC0_bp 0 /* Channel Trigger Source bit 0 position. */
3884 #define DMA_CH_TRIGSRC1_bm (1<<1) /* Channel Trigger Source bit 1 mask. */
3885 #define DMA_CH_TRIGSRC1_bp 1 /* Channel Trigger Source bit 1 position. */
3886 #define DMA_CH_TRIGSRC2_bm (1<<2) /* Channel Trigger Source bit 2 mask. */
3887 #define DMA_CH_TRIGSRC2_bp 2 /* Channel Trigger Source bit 2 position. */
3888 #define DMA_CH_TRIGSRC3_bm (1<<3) /* Channel Trigger Source bit 3 mask. */
3889 #define DMA_CH_TRIGSRC3_bp 3 /* Channel Trigger Source bit 3 position. */
3890 #define DMA_CH_TRIGSRC4_bm (1<<4) /* Channel Trigger Source bit 4 mask. */
3891 #define DMA_CH_TRIGSRC4_bp 4 /* Channel Trigger Source bit 4 position. */
3892 #define DMA_CH_TRIGSRC5_bm (1<<5) /* Channel Trigger Source bit 5 mask. */
3893 #define DMA_CH_TRIGSRC5_bp 5 /* Channel Trigger Source bit 5 position. */
3894 #define DMA_CH_TRIGSRC6_bm (1<<6) /* Channel Trigger Source bit 6 mask. */
3895 #define DMA_CH_TRIGSRC6_bp 6 /* Channel Trigger Source bit 6 position. */
3896 #define DMA_CH_TRIGSRC7_bm (1<<7) /* Channel Trigger Source bit 7 mask. */
3897 #define DMA_CH_TRIGSRC7_bp 7 /* Channel Trigger Source bit 7 position. */
3898 
3899 
3900 /* DMA.CTRL bit masks and bit positions */
3901 #define DMA_ENABLE_bm 0x80 /* Enable bit mask. */
3902 #define DMA_ENABLE_bp 7 /* Enable bit position. */
3903 
3904 #define DMA_RESET_bm 0x40 /* Software Reset bit mask. */
3905 #define DMA_RESET_bp 6 /* Software Reset bit position. */
3906 
3907 #define DMA_DBUFMODE_gm 0x0C /* Double Buffering Mode group mask. */
3908 #define DMA_DBUFMODE_gp 2 /* Double Buffering Mode group position. */
3909 #define DMA_DBUFMODE0_bm (1<<2) /* Double Buffering Mode bit 0 mask. */
3910 #define DMA_DBUFMODE0_bp 2 /* Double Buffering Mode bit 0 position. */
3911 #define DMA_DBUFMODE1_bm (1<<3) /* Double Buffering Mode bit 1 mask. */
3912 #define DMA_DBUFMODE1_bp 3 /* Double Buffering Mode bit 1 position. */
3913 
3914 #define DMA_PRIMODE_gm 0x03 /* Channel Priority Mode group mask. */
3915 #define DMA_PRIMODE_gp 0 /* Channel Priority Mode group position. */
3916 #define DMA_PRIMODE0_bm (1<<0) /* Channel Priority Mode bit 0 mask. */
3917 #define DMA_PRIMODE0_bp 0 /* Channel Priority Mode bit 0 position. */
3918 #define DMA_PRIMODE1_bm (1<<1) /* Channel Priority Mode bit 1 mask. */
3919 #define DMA_PRIMODE1_bp 1 /* Channel Priority Mode bit 1 position. */
3920 
3921 
3922 /* DMA.INTFLAGS bit masks and bit positions */
3923 #define DMA_CH3ERRIF_bm 0x80 /* Channel 3 Block Transfer Error Interrupt Flag bit mask. */
3924 #define DMA_CH3ERRIF_bp 7 /* Channel 3 Block Transfer Error Interrupt Flag bit position. */
3925 
3926 #define DMA_CH2ERRIF_bm 0x40 /* Channel 2 Block Transfer Error Interrupt Flag bit mask. */
3927 #define DMA_CH2ERRIF_bp 6 /* Channel 2 Block Transfer Error Interrupt Flag bit position. */
3928 
3929 #define DMA_CH1ERRIF_bm 0x20 /* Channel 1 Block Transfer Error Interrupt Flag bit mask. */
3930 #define DMA_CH1ERRIF_bp 5 /* Channel 1 Block Transfer Error Interrupt Flag bit position. */
3931 
3932 #define DMA_CH0ERRIF_bm 0x10 /* Channel 0 Block Transfer Error Interrupt Flag bit mask. */
3933 #define DMA_CH0ERRIF_bp 4 /* Channel 0 Block Transfer Error Interrupt Flag bit position. */
3934 
3935 #define DMA_CH3TRNIF_bm 0x08 /* Channel 3 Transaction Complete Interrupt Flag bit mask. */
3936 #define DMA_CH3TRNIF_bp 3 /* Channel 3 Transaction Complete Interrupt Flag bit position. */
3937 
3938 #define DMA_CH2TRNIF_bm 0x04 /* Channel 2 Transaction Complete Interrupt Flag bit mask. */
3939 #define DMA_CH2TRNIF_bp 2 /* Channel 2 Transaction Complete Interrupt Flag bit position. */
3940 
3941 #define DMA_CH1TRNIF_bm 0x02 /* Channel 1 Transaction Complete Interrupt Flag bit mask. */
3942 #define DMA_CH1TRNIF_bp 1 /* Channel 1 Transaction Complete Interrupt Flag bit position. */
3943 
3944 #define DMA_CH0TRNIF_bm 0x01 /* Channel 0 Transaction Complete Interrupt Flag bit mask. */
3945 #define DMA_CH0TRNIF_bp 0 /* Channel 0 Transaction Complete Interrupt Flag bit position. */
3946 
3947 
3948 /* DMA.STATUS bit masks and bit positions */
3949 #define DMA_CH3BUSY_bm 0x80 /* Channel 3 Block Transfer Busy bit mask. */
3950 #define DMA_CH3BUSY_bp 7 /* Channel 3 Block Transfer Busy bit position. */
3951 
3952 #define DMA_CH2BUSY_bm 0x40 /* Channel 2 Block Transfer Busy bit mask. */
3953 #define DMA_CH2BUSY_bp 6 /* Channel 2 Block Transfer Busy bit position. */
3954 
3955 #define DMA_CH1BUSY_bm 0x20 /* Channel 1 Block Transfer Busy bit mask. */
3956 #define DMA_CH1BUSY_bp 5 /* Channel 1 Block Transfer Busy bit position. */
3957 
3958 #define DMA_CH0BUSY_bm 0x10 /* Channel 0 Block Transfer Busy bit mask. */
3959 #define DMA_CH0BUSY_bp 4 /* Channel 0 Block Transfer Busy bit position. */
3960 
3961 #define DMA_CH3PEND_bm 0x08 /* Channel 3 Block Transfer Pending bit mask. */
3962 #define DMA_CH3PEND_bp 3 /* Channel 3 Block Transfer Pending bit position. */
3963 
3964 #define DMA_CH2PEND_bm 0x04 /* Channel 2 Block Transfer Pending bit mask. */
3965 #define DMA_CH2PEND_bp 2 /* Channel 2 Block Transfer Pending bit position. */
3966 
3967 #define DMA_CH1PEND_bm 0x02 /* Channel 1 Block Transfer Pending bit mask. */
3968 #define DMA_CH1PEND_bp 1 /* Channel 1 Block Transfer Pending bit position. */
3969 
3970 #define DMA_CH0PEND_bm 0x01 /* Channel 0 Block Transfer Pending bit mask. */
3971 #define DMA_CH0PEND_bp 0 /* Channel 0 Block Transfer Pending bit position. */
3972 
3973 
3974 /* EVSYS - Event System */
3975 /* EVSYS.CH0MUX bit masks and bit positions */
3976 #define EVSYS_CHMUX_gm 0xFF /* Event Channel 0 Multiplexer group mask. */
3977 #define EVSYS_CHMUX_gp 0 /* Event Channel 0 Multiplexer group position. */
3978 #define EVSYS_CHMUX0_bm (1<<0) /* Event Channel 0 Multiplexer bit 0 mask. */
3979 #define EVSYS_CHMUX0_bp 0 /* Event Channel 0 Multiplexer bit 0 position. */
3980 #define EVSYS_CHMUX1_bm (1<<1) /* Event Channel 0 Multiplexer bit 1 mask. */
3981 #define EVSYS_CHMUX1_bp 1 /* Event Channel 0 Multiplexer bit 1 position. */
3982 #define EVSYS_CHMUX2_bm (1<<2) /* Event Channel 0 Multiplexer bit 2 mask. */
3983 #define EVSYS_CHMUX2_bp 2 /* Event Channel 0 Multiplexer bit 2 position. */
3984 #define EVSYS_CHMUX3_bm (1<<3) /* Event Channel 0 Multiplexer bit 3 mask. */
3985 #define EVSYS_CHMUX3_bp 3 /* Event Channel 0 Multiplexer bit 3 position. */
3986 #define EVSYS_CHMUX4_bm (1<<4) /* Event Channel 0 Multiplexer bit 4 mask. */
3987 #define EVSYS_CHMUX4_bp 4 /* Event Channel 0 Multiplexer bit 4 position. */
3988 #define EVSYS_CHMUX5_bm (1<<5) /* Event Channel 0 Multiplexer bit 5 mask. */
3989 #define EVSYS_CHMUX5_bp 5 /* Event Channel 0 Multiplexer bit 5 position. */
3990 #define EVSYS_CHMUX6_bm (1<<6) /* Event Channel 0 Multiplexer bit 6 mask. */
3991 #define EVSYS_CHMUX6_bp 6 /* Event Channel 0 Multiplexer bit 6 position. */
3992 #define EVSYS_CHMUX7_bm (1<<7) /* Event Channel 0 Multiplexer bit 7 mask. */
3993 #define EVSYS_CHMUX7_bp 7 /* Event Channel 0 Multiplexer bit 7 position. */
3994 
3995 
3996 /* EVSYS.CH1MUX bit masks and bit positions */
3997 /* EVSYS_CHMUX_gm Predefined. */
3998 /* EVSYS_CHMUX_gp Predefined. */
3999 /* EVSYS_CHMUX0_bm Predefined. */
4000 /* EVSYS_CHMUX0_bp Predefined. */
4001 /* EVSYS_CHMUX1_bm Predefined. */
4002 /* EVSYS_CHMUX1_bp Predefined. */
4003 /* EVSYS_CHMUX2_bm Predefined. */
4004 /* EVSYS_CHMUX2_bp Predefined. */
4005 /* EVSYS_CHMUX3_bm Predefined. */
4006 /* EVSYS_CHMUX3_bp Predefined. */
4007 /* EVSYS_CHMUX4_bm Predefined. */
4008 /* EVSYS_CHMUX4_bp Predefined. */
4009 /* EVSYS_CHMUX5_bm Predefined. */
4010 /* EVSYS_CHMUX5_bp Predefined. */
4011 /* EVSYS_CHMUX6_bm Predefined. */
4012 /* EVSYS_CHMUX6_bp Predefined. */
4013 /* EVSYS_CHMUX7_bm Predefined. */
4014 /* EVSYS_CHMUX7_bp Predefined. */
4015 
4016 
4017 /* EVSYS.CH2MUX bit masks and bit positions */
4018 /* EVSYS_CHMUX_gm Predefined. */
4019 /* EVSYS_CHMUX_gp Predefined. */
4020 /* EVSYS_CHMUX0_bm Predefined. */
4021 /* EVSYS_CHMUX0_bp Predefined. */
4022 /* EVSYS_CHMUX1_bm Predefined. */
4023 /* EVSYS_CHMUX1_bp Predefined. */
4024 /* EVSYS_CHMUX2_bm Predefined. */
4025 /* EVSYS_CHMUX2_bp Predefined. */
4026 /* EVSYS_CHMUX3_bm Predefined. */
4027 /* EVSYS_CHMUX3_bp Predefined. */
4028 /* EVSYS_CHMUX4_bm Predefined. */
4029 /* EVSYS_CHMUX4_bp Predefined. */
4030 /* EVSYS_CHMUX5_bm Predefined. */
4031 /* EVSYS_CHMUX5_bp Predefined. */
4032 /* EVSYS_CHMUX6_bm Predefined. */
4033 /* EVSYS_CHMUX6_bp Predefined. */
4034 /* EVSYS_CHMUX7_bm Predefined. */
4035 /* EVSYS_CHMUX7_bp Predefined. */
4036 
4037 
4038 /* EVSYS.CH3MUX bit masks and bit positions */
4039 /* EVSYS_CHMUX_gm Predefined. */
4040 /* EVSYS_CHMUX_gp Predefined. */
4041 /* EVSYS_CHMUX0_bm Predefined. */
4042 /* EVSYS_CHMUX0_bp Predefined. */
4043 /* EVSYS_CHMUX1_bm Predefined. */
4044 /* EVSYS_CHMUX1_bp Predefined. */
4045 /* EVSYS_CHMUX2_bm Predefined. */
4046 /* EVSYS_CHMUX2_bp Predefined. */
4047 /* EVSYS_CHMUX3_bm Predefined. */
4048 /* EVSYS_CHMUX3_bp Predefined. */
4049 /* EVSYS_CHMUX4_bm Predefined. */
4050 /* EVSYS_CHMUX4_bp Predefined. */
4051 /* EVSYS_CHMUX5_bm Predefined. */
4052 /* EVSYS_CHMUX5_bp Predefined. */
4053 /* EVSYS_CHMUX6_bm Predefined. */
4054 /* EVSYS_CHMUX6_bp Predefined. */
4055 /* EVSYS_CHMUX7_bm Predefined. */
4056 /* EVSYS_CHMUX7_bp Predefined. */
4057 
4058 
4059 /* EVSYS.CH4MUX bit masks and bit positions */
4060 /* EVSYS_CHMUX_gm Predefined. */
4061 /* EVSYS_CHMUX_gp Predefined. */
4062 /* EVSYS_CHMUX0_bm Predefined. */
4063 /* EVSYS_CHMUX0_bp Predefined. */
4064 /* EVSYS_CHMUX1_bm Predefined. */
4065 /* EVSYS_CHMUX1_bp Predefined. */
4066 /* EVSYS_CHMUX2_bm Predefined. */
4067 /* EVSYS_CHMUX2_bp Predefined. */
4068 /* EVSYS_CHMUX3_bm Predefined. */
4069 /* EVSYS_CHMUX3_bp Predefined. */
4070 /* EVSYS_CHMUX4_bm Predefined. */
4071 /* EVSYS_CHMUX4_bp Predefined. */
4072 /* EVSYS_CHMUX5_bm Predefined. */
4073 /* EVSYS_CHMUX5_bp Predefined. */
4074 /* EVSYS_CHMUX6_bm Predefined. */
4075 /* EVSYS_CHMUX6_bp Predefined. */
4076 /* EVSYS_CHMUX7_bm Predefined. */
4077 /* EVSYS_CHMUX7_bp Predefined. */
4078 
4079 
4080 /* EVSYS.CH5MUX bit masks and bit positions */
4081 /* EVSYS_CHMUX_gm Predefined. */
4082 /* EVSYS_CHMUX_gp Predefined. */
4083 /* EVSYS_CHMUX0_bm Predefined. */
4084 /* EVSYS_CHMUX0_bp Predefined. */
4085 /* EVSYS_CHMUX1_bm Predefined. */
4086 /* EVSYS_CHMUX1_bp Predefined. */
4087 /* EVSYS_CHMUX2_bm Predefined. */
4088 /* EVSYS_CHMUX2_bp Predefined. */
4089 /* EVSYS_CHMUX3_bm Predefined. */
4090 /* EVSYS_CHMUX3_bp Predefined. */
4091 /* EVSYS_CHMUX4_bm Predefined. */
4092 /* EVSYS_CHMUX4_bp Predefined. */
4093 /* EVSYS_CHMUX5_bm Predefined. */
4094 /* EVSYS_CHMUX5_bp Predefined. */
4095 /* EVSYS_CHMUX6_bm Predefined. */
4096 /* EVSYS_CHMUX6_bp Predefined. */
4097 /* EVSYS_CHMUX7_bm Predefined. */
4098 /* EVSYS_CHMUX7_bp Predefined. */
4099 
4100 
4101 /* EVSYS.CH6MUX bit masks and bit positions */
4102 /* EVSYS_CHMUX_gm Predefined. */
4103 /* EVSYS_CHMUX_gp Predefined. */
4104 /* EVSYS_CHMUX0_bm Predefined. */
4105 /* EVSYS_CHMUX0_bp Predefined. */
4106 /* EVSYS_CHMUX1_bm Predefined. */
4107 /* EVSYS_CHMUX1_bp Predefined. */
4108 /* EVSYS_CHMUX2_bm Predefined. */
4109 /* EVSYS_CHMUX2_bp Predefined. */
4110 /* EVSYS_CHMUX3_bm Predefined. */
4111 /* EVSYS_CHMUX3_bp Predefined. */
4112 /* EVSYS_CHMUX4_bm Predefined. */
4113 /* EVSYS_CHMUX4_bp Predefined. */
4114 /* EVSYS_CHMUX5_bm Predefined. */
4115 /* EVSYS_CHMUX5_bp Predefined. */
4116 /* EVSYS_CHMUX6_bm Predefined. */
4117 /* EVSYS_CHMUX6_bp Predefined. */
4118 /* EVSYS_CHMUX7_bm Predefined. */
4119 /* EVSYS_CHMUX7_bp Predefined. */
4120 
4121 
4122 /* EVSYS.CH7MUX bit masks and bit positions */
4123 /* EVSYS_CHMUX_gm Predefined. */
4124 /* EVSYS_CHMUX_gp Predefined. */
4125 /* EVSYS_CHMUX0_bm Predefined. */
4126 /* EVSYS_CHMUX0_bp Predefined. */
4127 /* EVSYS_CHMUX1_bm Predefined. */
4128 /* EVSYS_CHMUX1_bp Predefined. */
4129 /* EVSYS_CHMUX2_bm Predefined. */
4130 /* EVSYS_CHMUX2_bp Predefined. */
4131 /* EVSYS_CHMUX3_bm Predefined. */
4132 /* EVSYS_CHMUX3_bp Predefined. */
4133 /* EVSYS_CHMUX4_bm Predefined. */
4134 /* EVSYS_CHMUX4_bp Predefined. */
4135 /* EVSYS_CHMUX5_bm Predefined. */
4136 /* EVSYS_CHMUX5_bp Predefined. */
4137 /* EVSYS_CHMUX6_bm Predefined. */
4138 /* EVSYS_CHMUX6_bp Predefined. */
4139 /* EVSYS_CHMUX7_bm Predefined. */
4140 /* EVSYS_CHMUX7_bp Predefined. */
4141 
4142 
4143 /* EVSYS.CH0CTRL bit masks and bit positions */
4144 #define EVSYS_QDIRM_gm 0x60 /* Quadrature Decoder Index Recognition Mode group mask. */
4145 #define EVSYS_QDIRM_gp 5 /* Quadrature Decoder Index Recognition Mode group position. */
4146 #define EVSYS_QDIRM0_bm (1<<5) /* Quadrature Decoder Index Recognition Mode bit 0 mask. */
4147 #define EVSYS_QDIRM0_bp 5 /* Quadrature Decoder Index Recognition Mode bit 0 position. */
4148 #define EVSYS_QDIRM1_bm (1<<6) /* Quadrature Decoder Index Recognition Mode bit 1 mask. */
4149 #define EVSYS_QDIRM1_bp 6 /* Quadrature Decoder Index Recognition Mode bit 1 position. */
4150 
4151 #define EVSYS_QDIEN_bm 0x10 /* Quadrature Decoder Index Enable bit mask. */
4152 #define EVSYS_QDIEN_bp 4 /* Quadrature Decoder Index Enable bit position. */
4153 
4154 #define EVSYS_QDEN_bm 0x08 /* Quadrature Decoder Enable bit mask. */
4155 #define EVSYS_QDEN_bp 3 /* Quadrature Decoder Enable bit position. */
4156 
4157 #define EVSYS_DIGFILT_gm 0x07 /* Digital Filter group mask. */
4158 #define EVSYS_DIGFILT_gp 0 /* Digital Filter group position. */
4159 #define EVSYS_DIGFILT0_bm (1<<0) /* Digital Filter bit 0 mask. */
4160 #define EVSYS_DIGFILT0_bp 0 /* Digital Filter bit 0 position. */
4161 #define EVSYS_DIGFILT1_bm (1<<1) /* Digital Filter bit 1 mask. */
4162 #define EVSYS_DIGFILT1_bp 1 /* Digital Filter bit 1 position. */
4163 #define EVSYS_DIGFILT2_bm (1<<2) /* Digital Filter bit 2 mask. */
4164 #define EVSYS_DIGFILT2_bp 2 /* Digital Filter bit 2 position. */
4165 
4166 
4167 /* EVSYS.CH1CTRL bit masks and bit positions */
4168 /* EVSYS_DIGFILT_gm Predefined. */
4169 /* EVSYS_DIGFILT_gp Predefined. */
4170 /* EVSYS_DIGFILT0_bm Predefined. */
4171 /* EVSYS_DIGFILT0_bp Predefined. */
4172 /* EVSYS_DIGFILT1_bm Predefined. */
4173 /* EVSYS_DIGFILT1_bp Predefined. */
4174 /* EVSYS_DIGFILT2_bm Predefined. */
4175 /* EVSYS_DIGFILT2_bp Predefined. */
4176 
4177 
4178 /* EVSYS.CH2CTRL bit masks and bit positions */
4179 /* EVSYS_QDIRM_gm Predefined. */
4180 /* EVSYS_QDIRM_gp Predefined. */
4181 /* EVSYS_QDIRM0_bm Predefined. */
4182 /* EVSYS_QDIRM0_bp Predefined. */
4183 /* EVSYS_QDIRM1_bm Predefined. */
4184 /* EVSYS_QDIRM1_bp Predefined. */
4185 
4186 /* EVSYS_QDIEN_bm Predefined. */
4187 /* EVSYS_QDIEN_bp Predefined. */
4188 
4189 /* EVSYS_QDEN_bm Predefined. */
4190 /* EVSYS_QDEN_bp Predefined. */
4191 
4192 /* EVSYS_DIGFILT_gm Predefined. */
4193 /* EVSYS_DIGFILT_gp Predefined. */
4194 /* EVSYS_DIGFILT0_bm Predefined. */
4195 /* EVSYS_DIGFILT0_bp Predefined. */
4196 /* EVSYS_DIGFILT1_bm Predefined. */
4197 /* EVSYS_DIGFILT1_bp Predefined. */
4198 /* EVSYS_DIGFILT2_bm Predefined. */
4199 /* EVSYS_DIGFILT2_bp Predefined. */
4200 
4201 
4202 /* EVSYS.CH3CTRL bit masks and bit positions */
4203 /* EVSYS_DIGFILT_gm Predefined. */
4204 /* EVSYS_DIGFILT_gp Predefined. */
4205 /* EVSYS_DIGFILT0_bm Predefined. */
4206 /* EVSYS_DIGFILT0_bp Predefined. */
4207 /* EVSYS_DIGFILT1_bm Predefined. */
4208 /* EVSYS_DIGFILT1_bp Predefined. */
4209 /* EVSYS_DIGFILT2_bm Predefined. */
4210 /* EVSYS_DIGFILT2_bp Predefined. */
4211 
4212 
4213 /* EVSYS.CH4CTRL bit masks and bit positions */
4214 /* EVSYS_QDIRM_gm Predefined. */
4215 /* EVSYS_QDIRM_gp Predefined. */
4216 /* EVSYS_QDIRM0_bm Predefined. */
4217 /* EVSYS_QDIRM0_bp Predefined. */
4218 /* EVSYS_QDIRM1_bm Predefined. */
4219 /* EVSYS_QDIRM1_bp Predefined. */
4220 
4221 /* EVSYS_QDIEN_bm Predefined. */
4222 /* EVSYS_QDIEN_bp Predefined. */
4223 
4224 /* EVSYS_QDEN_bm Predefined. */
4225 /* EVSYS_QDEN_bp Predefined. */
4226 
4227 /* EVSYS_DIGFILT_gm Predefined. */
4228 /* EVSYS_DIGFILT_gp Predefined. */
4229 /* EVSYS_DIGFILT0_bm Predefined. */
4230 /* EVSYS_DIGFILT0_bp Predefined. */
4231 /* EVSYS_DIGFILT1_bm Predefined. */
4232 /* EVSYS_DIGFILT1_bp Predefined. */
4233 /* EVSYS_DIGFILT2_bm Predefined. */
4234 /* EVSYS_DIGFILT2_bp Predefined. */
4235 
4236 
4237 /* EVSYS.CH5CTRL bit masks and bit positions */
4238 /* EVSYS_DIGFILT_gm Predefined. */
4239 /* EVSYS_DIGFILT_gp Predefined. */
4240 /* EVSYS_DIGFILT0_bm Predefined. */
4241 /* EVSYS_DIGFILT0_bp Predefined. */
4242 /* EVSYS_DIGFILT1_bm Predefined. */
4243 /* EVSYS_DIGFILT1_bp Predefined. */
4244 /* EVSYS_DIGFILT2_bm Predefined. */
4245 /* EVSYS_DIGFILT2_bp Predefined. */
4246 
4247 
4248 /* EVSYS.CH6CTRL bit masks and bit positions */
4249 /* EVSYS_DIGFILT_gm Predefined. */
4250 /* EVSYS_DIGFILT_gp Predefined. */
4251 /* EVSYS_DIGFILT0_bm Predefined. */
4252 /* EVSYS_DIGFILT0_bp Predefined. */
4253 /* EVSYS_DIGFILT1_bm Predefined. */
4254 /* EVSYS_DIGFILT1_bp Predefined. */
4255 /* EVSYS_DIGFILT2_bm Predefined. */
4256 /* EVSYS_DIGFILT2_bp Predefined. */
4257 
4258 
4259 /* EVSYS.CH7CTRL bit masks and bit positions */
4260 /* EVSYS_DIGFILT_gm Predefined. */
4261 /* EVSYS_DIGFILT_gp Predefined. */
4262 /* EVSYS_DIGFILT0_bm Predefined. */
4263 /* EVSYS_DIGFILT0_bp Predefined. */
4264 /* EVSYS_DIGFILT1_bm Predefined. */
4265 /* EVSYS_DIGFILT1_bp Predefined. */
4266 /* EVSYS_DIGFILT2_bm Predefined. */
4267 /* EVSYS_DIGFILT2_bp Predefined. */
4268 
4269 
4270 /* NVM - Non Volatile Memory Controller */
4271 /* NVM.CMD bit masks and bit positions */
4272 #define NVM_CMD_gm 0xFF /* Command group mask. */
4273 #define NVM_CMD_gp 0 /* Command group position. */
4274 #define NVM_CMD0_bm (1<<0) /* Command bit 0 mask. */
4275 #define NVM_CMD0_bp 0 /* Command bit 0 position. */
4276 #define NVM_CMD1_bm (1<<1) /* Command bit 1 mask. */
4277 #define NVM_CMD1_bp 1 /* Command bit 1 position. */
4278 #define NVM_CMD2_bm (1<<2) /* Command bit 2 mask. */
4279 #define NVM_CMD2_bp 2 /* Command bit 2 position. */
4280 #define NVM_CMD3_bm (1<<3) /* Command bit 3 mask. */
4281 #define NVM_CMD3_bp 3 /* Command bit 3 position. */
4282 #define NVM_CMD4_bm (1<<4) /* Command bit 4 mask. */
4283 #define NVM_CMD4_bp 4 /* Command bit 4 position. */
4284 #define NVM_CMD5_bm (1<<5) /* Command bit 5 mask. */
4285 #define NVM_CMD5_bp 5 /* Command bit 5 position. */
4286 #define NVM_CMD6_bm (1<<6) /* Command bit 6 mask. */
4287 #define NVM_CMD6_bp 6 /* Command bit 6 position. */
4288 #define NVM_CMD7_bm (1<<7) /* Command bit 7 mask. */
4289 #define NVM_CMD7_bp 7 /* Command bit 7 position. */
4290 
4291 
4292 /* NVM.CTRLA bit masks and bit positions */
4293 #define NVM_CMDEX_bm 0x01 /* Command Execute bit mask. */
4294 #define NVM_CMDEX_bp 0 /* Command Execute bit position. */
4295 
4296 
4297 /* NVM.CTRLB bit masks and bit positions */
4298 #define NVM_EEMAPEN_bm 0x08 /* EEPROM Mapping Enable bit mask. */
4299 #define NVM_EEMAPEN_bp 3 /* EEPROM Mapping Enable bit position. */
4300 
4301 #define NVM_FPRM_bm 0x04 /* Flash Power Reduction Enable bit mask. */
4302 #define NVM_FPRM_bp 2 /* Flash Power Reduction Enable bit position. */
4303 
4304 #define NVM_EPRM_bm 0x02 /* EEPROM Power Reduction Enable bit mask. */
4305 #define NVM_EPRM_bp 1 /* EEPROM Power Reduction Enable bit position. */
4306 
4307 #define NVM_SPMLOCK_bm 0x01 /* SPM Lock bit mask. */
4308 #define NVM_SPMLOCK_bp 0 /* SPM Lock bit position. */
4309 
4310 
4311 /* NVM.INTCTRL bit masks and bit positions */
4312 #define NVM_SPMLVL_gm 0x0C /* SPM Interrupt Level group mask. */
4313 #define NVM_SPMLVL_gp 2 /* SPM Interrupt Level group position. */
4314 #define NVM_SPMLVL0_bm (1<<2) /* SPM Interrupt Level bit 0 mask. */
4315 #define NVM_SPMLVL0_bp 2 /* SPM Interrupt Level bit 0 position. */
4316 #define NVM_SPMLVL1_bm (1<<3) /* SPM Interrupt Level bit 1 mask. */
4317 #define NVM_SPMLVL1_bp 3 /* SPM Interrupt Level bit 1 position. */
4318 
4319 #define NVM_EELVL_gm 0x03 /* EEPROM Interrupt Level group mask. */
4320 #define NVM_EELVL_gp 0 /* EEPROM Interrupt Level group position. */
4321 #define NVM_EELVL0_bm (1<<0) /* EEPROM Interrupt Level bit 0 mask. */
4322 #define NVM_EELVL0_bp 0 /* EEPROM Interrupt Level bit 0 position. */
4323 #define NVM_EELVL1_bm (1<<1) /* EEPROM Interrupt Level bit 1 mask. */
4324 #define NVM_EELVL1_bp 1 /* EEPROM Interrupt Level bit 1 position. */
4325 
4326 
4327 /* NVM.STATUS bit masks and bit positions */
4328 #define NVM_NVMBUSY_bm 0x80 /* Non-volatile Memory Busy bit mask. */
4329 #define NVM_NVMBUSY_bp 7 /* Non-volatile Memory Busy bit position. */
4330 
4331 #define NVM_FBUSY_bm 0x40 /* Flash Memory Busy bit mask. */
4332 #define NVM_FBUSY_bp 6 /* Flash Memory Busy bit position. */
4333 
4334 #define NVM_EELOAD_bm 0x02 /* EEPROM Page Buffer Active Loading bit mask. */
4335 #define NVM_EELOAD_bp 1 /* EEPROM Page Buffer Active Loading bit position. */
4336 
4337 #define NVM_FLOAD_bm 0x01 /* Flash Page Buffer Active Loading bit mask. */
4338 #define NVM_FLOAD_bp 0 /* Flash Page Buffer Active Loading bit position. */
4339 
4340 
4341 /* NVM.LOCKBITS bit masks and bit positions */
4342 #define NVM_BLBB_gm 0xC0 /* Boot Lock Bits - Boot Section group mask. */
4343 #define NVM_BLBB_gp 6 /* Boot Lock Bits - Boot Section group position. */
4344 #define NVM_BLBB0_bm (1<<6) /* Boot Lock Bits - Boot Section bit 0 mask. */
4345 #define NVM_BLBB0_bp 6 /* Boot Lock Bits - Boot Section bit 0 position. */
4346 #define NVM_BLBB1_bm (1<<7) /* Boot Lock Bits - Boot Section bit 1 mask. */
4347 #define NVM_BLBB1_bp 7 /* Boot Lock Bits - Boot Section bit 1 position. */
4348 
4349 #define NVM_BLBA_gm 0x30 /* Boot Lock Bits - Application Section group mask. */
4350 #define NVM_BLBA_gp 4 /* Boot Lock Bits - Application Section group position. */
4351 #define NVM_BLBA0_bm (1<<4) /* Boot Lock Bits - Application Section bit 0 mask. */
4352 #define NVM_BLBA0_bp 4 /* Boot Lock Bits - Application Section bit 0 position. */
4353 #define NVM_BLBA1_bm (1<<5) /* Boot Lock Bits - Application Section bit 1 mask. */
4354 #define NVM_BLBA1_bp 5 /* Boot Lock Bits - Application Section bit 1 position. */
4355 
4356 #define NVM_BLBAT_gm 0x0C /* Boot Lock Bits - Application Table group mask. */
4357 #define NVM_BLBAT_gp 2 /* Boot Lock Bits - Application Table group position. */
4358 #define NVM_BLBAT0_bm (1<<2) /* Boot Lock Bits - Application Table bit 0 mask. */
4359 #define NVM_BLBAT0_bp 2 /* Boot Lock Bits - Application Table bit 0 position. */
4360 #define NVM_BLBAT1_bm (1<<3) /* Boot Lock Bits - Application Table bit 1 mask. */
4361 #define NVM_BLBAT1_bp 3 /* Boot Lock Bits - Application Table bit 1 position. */
4362 
4363 #define NVM_LB_gm 0x03 /* Lock Bits group mask. */
4364 #define NVM_LB_gp 0 /* Lock Bits group position. */
4365 #define NVM_LB0_bm (1<<0) /* Lock Bits bit 0 mask. */
4366 #define NVM_LB0_bp 0 /* Lock Bits bit 0 position. */
4367 #define NVM_LB1_bm (1<<1) /* Lock Bits bit 1 mask. */
4368 #define NVM_LB1_bp 1 /* Lock Bits bit 1 position. */
4369 
4370 
4371 /* NVM_LOCKBITS.LOCKBITS bit masks and bit positions */
4372 #define NVM_LOCKBITS_BLBB_gm 0xC0 /* Boot Lock Bits - Boot Section group mask. */
4373 #define NVM_LOCKBITS_BLBB_gp 6 /* Boot Lock Bits - Boot Section group position. */
4374 #define NVM_LOCKBITS_BLBB0_bm (1<<6) /* Boot Lock Bits - Boot Section bit 0 mask. */
4375 #define NVM_LOCKBITS_BLBB0_bp 6 /* Boot Lock Bits - Boot Section bit 0 position. */
4376 #define NVM_LOCKBITS_BLBB1_bm (1<<7) /* Boot Lock Bits - Boot Section bit 1 mask. */
4377 #define NVM_LOCKBITS_BLBB1_bp 7 /* Boot Lock Bits - Boot Section bit 1 position. */
4378 
4379 #define NVM_LOCKBITS_BLBA_gm 0x30 /* Boot Lock Bits - Application Section group mask. */
4380 #define NVM_LOCKBITS_BLBA_gp 4 /* Boot Lock Bits - Application Section group position. */
4381 #define NVM_LOCKBITS_BLBA0_bm (1<<4) /* Boot Lock Bits - Application Section bit 0 mask. */
4382 #define NVM_LOCKBITS_BLBA0_bp 4 /* Boot Lock Bits - Application Section bit 0 position. */
4383 #define NVM_LOCKBITS_BLBA1_bm (1<<5) /* Boot Lock Bits - Application Section bit 1 mask. */
4384 #define NVM_LOCKBITS_BLBA1_bp 5 /* Boot Lock Bits - Application Section bit 1 position. */
4385 
4386 #define NVM_LOCKBITS_BLBAT_gm 0x0C /* Boot Lock Bits - Application Table group mask. */
4387 #define NVM_LOCKBITS_BLBAT_gp 2 /* Boot Lock Bits - Application Table group position. */
4388 #define NVM_LOCKBITS_BLBAT0_bm (1<<2) /* Boot Lock Bits - Application Table bit 0 mask. */
4389 #define NVM_LOCKBITS_BLBAT0_bp 2 /* Boot Lock Bits - Application Table bit 0 position. */
4390 #define NVM_LOCKBITS_BLBAT1_bm (1<<3) /* Boot Lock Bits - Application Table bit 1 mask. */
4391 #define NVM_LOCKBITS_BLBAT1_bp 3 /* Boot Lock Bits - Application Table bit 1 position. */
4392 
4393 #define NVM_LOCKBITS_LB_gm 0x03 /* Lock Bits group mask. */
4394 #define NVM_LOCKBITS_LB_gp 0 /* Lock Bits group position. */
4395 #define NVM_LOCKBITS_LB0_bm (1<<0) /* Lock Bits bit 0 mask. */
4396 #define NVM_LOCKBITS_LB0_bp 0 /* Lock Bits bit 0 position. */
4397 #define NVM_LOCKBITS_LB1_bm (1<<1) /* Lock Bits bit 1 mask. */
4398 #define NVM_LOCKBITS_LB1_bp 1 /* Lock Bits bit 1 position. */
4399 
4400 
4401 /* NVM_FUSES.FUSEBYTE0 bit masks and bit positions */
4402 #define NVM_FUSES_USERID_gm 0xFF /* User ID group mask. */
4403 #define NVM_FUSES_USERID_gp 0 /* User ID group position. */
4404 #define NVM_FUSES_USERID0_bm (1<<0) /* User ID bit 0 mask. */
4405 #define NVM_FUSES_USERID0_bp 0 /* User ID bit 0 position. */
4406 #define NVM_FUSES_USERID1_bm (1<<1) /* User ID bit 1 mask. */
4407 #define NVM_FUSES_USERID1_bp 1 /* User ID bit 1 position. */
4408 #define NVM_FUSES_USERID2_bm (1<<2) /* User ID bit 2 mask. */
4409 #define NVM_FUSES_USERID2_bp 2 /* User ID bit 2 position. */
4410 #define NVM_FUSES_USERID3_bm (1<<3) /* User ID bit 3 mask. */
4411 #define NVM_FUSES_USERID3_bp 3 /* User ID bit 3 position. */
4412 #define NVM_FUSES_USERID4_bm (1<<4) /* User ID bit 4 mask. */
4413 #define NVM_FUSES_USERID4_bp 4 /* User ID bit 4 position. */
4414 #define NVM_FUSES_USERID5_bm (1<<5) /* User ID bit 5 mask. */
4415 #define NVM_FUSES_USERID5_bp 5 /* User ID bit 5 position. */
4416 #define NVM_FUSES_USERID6_bm (1<<6) /* User ID bit 6 mask. */
4417 #define NVM_FUSES_USERID6_bp 6 /* User ID bit 6 position. */
4418 #define NVM_FUSES_USERID7_bm (1<<7) /* User ID bit 7 mask. */
4419 #define NVM_FUSES_USERID7_bp 7 /* User ID bit 7 position. */
4420 
4421 
4422 /* NVM_FUSES.FUSEBYTE1 bit masks and bit positions */
4423 #define NVM_FUSES_WDWP_gm 0xF0 /* Watchdog Window Timeout Period group mask. */
4424 #define NVM_FUSES_WDWP_gp 4 /* Watchdog Window Timeout Period group position. */
4425 #define NVM_FUSES_WDWP0_bm (1<<4) /* Watchdog Window Timeout Period bit 0 mask. */
4426 #define NVM_FUSES_WDWP0_bp 4 /* Watchdog Window Timeout Period bit 0 position. */
4427 #define NVM_FUSES_WDWP1_bm (1<<5) /* Watchdog Window Timeout Period bit 1 mask. */
4428 #define NVM_FUSES_WDWP1_bp 5 /* Watchdog Window Timeout Period bit 1 position. */
4429 #define NVM_FUSES_WDWP2_bm (1<<6) /* Watchdog Window Timeout Period bit 2 mask. */
4430 #define NVM_FUSES_WDWP2_bp 6 /* Watchdog Window Timeout Period bit 2 position. */
4431 #define NVM_FUSES_WDWP3_bm (1<<7) /* Watchdog Window Timeout Period bit 3 mask. */
4432 #define NVM_FUSES_WDWP3_bp 7 /* Watchdog Window Timeout Period bit 3 position. */
4433 
4434 #define NVM_FUSES_WDP_gm 0x0F /* Watchdog Timeout Period group mask. */
4435 #define NVM_FUSES_WDP_gp 0 /* Watchdog Timeout Period group position. */
4436 #define NVM_FUSES_WDP0_bm (1<<0) /* Watchdog Timeout Period bit 0 mask. */
4437 #define NVM_FUSES_WDP0_bp 0 /* Watchdog Timeout Period bit 0 position. */
4438 #define NVM_FUSES_WDP1_bm (1<<1) /* Watchdog Timeout Period bit 1 mask. */
4439 #define NVM_FUSES_WDP1_bp 1 /* Watchdog Timeout Period bit 1 position. */
4440 #define NVM_FUSES_WDP2_bm (1<<2) /* Watchdog Timeout Period bit 2 mask. */
4441 #define NVM_FUSES_WDP2_bp 2 /* Watchdog Timeout Period bit 2 position. */
4442 #define NVM_FUSES_WDP3_bm (1<<3) /* Watchdog Timeout Period bit 3 mask. */
4443 #define NVM_FUSES_WDP3_bp 3 /* Watchdog Timeout Period bit 3 position. */
4444 
4445 
4446 /* NVM_FUSES.FUSEBYTE2 bit masks and bit positions */
4447 #define NVM_FUSES_DVSDON_bm 0x80 /* Spike Detector Enable bit mask. */
4448 #define NVM_FUSES_DVSDON_bp 7 /* Spike Detector Enable bit position. */
4449 
4450 #define NVM_FUSES_BOOTRST_bm 0x40 /* Boot Loader Section Reset Vector bit mask. */
4451 #define NVM_FUSES_BOOTRST_bp 6 /* Boot Loader Section Reset Vector bit position. */
4452 
4453 #define NVM_FUSES_BODPD_gm 0x03 /* BOD Operation in Power-Down Mode group mask. */
4454 #define NVM_FUSES_BODPD_gp 0 /* BOD Operation in Power-Down Mode group position. */
4455 #define NVM_FUSES_BODPD0_bm (1<<0) /* BOD Operation in Power-Down Mode bit 0 mask. */
4456 #define NVM_FUSES_BODPD0_bp 0 /* BOD Operation in Power-Down Mode bit 0 position. */
4457 #define NVM_FUSES_BODPD1_bm (1<<1) /* BOD Operation in Power-Down Mode bit 1 mask. */
4458 #define NVM_FUSES_BODPD1_bp 1 /* BOD Operation in Power-Down Mode bit 1 position. */
4459 
4460 
4461 /* NVM_FUSES.FUSEBYTE4 bit masks and bit positions */
4462 #define NVM_FUSES_SUT_gm 0x0C /* Start-up Time group mask. */
4463 #define NVM_FUSES_SUT_gp 2 /* Start-up Time group position. */
4464 #define NVM_FUSES_SUT0_bm (1<<2) /* Start-up Time bit 0 mask. */
4465 #define NVM_FUSES_SUT0_bp 2 /* Start-up Time bit 0 position. */
4466 #define NVM_FUSES_SUT1_bm (1<<3) /* Start-up Time bit 1 mask. */
4467 #define NVM_FUSES_SUT1_bp 3 /* Start-up Time bit 1 position. */
4468 
4469 #define NVM_FUSES_WDLOCK_bm 0x02 /* Watchdog Timer Lock bit mask. */
4470 #define NVM_FUSES_WDLOCK_bp 1 /* Watchdog Timer Lock bit position. */
4471 
4472 
4473 /* NVM_FUSES.FUSEBYTE5 bit masks and bit positions */
4474 #define NVM_FUSES_BODACT_gm 0x30 /* BOD Operation in Active Mode group mask. */
4475 #define NVM_FUSES_BODACT_gp 4 /* BOD Operation in Active Mode group position. */
4476 #define NVM_FUSES_BODACT0_bm (1<<4) /* BOD Operation in Active Mode bit 0 mask. */
4477 #define NVM_FUSES_BODACT0_bp 4 /* BOD Operation in Active Mode bit 0 position. */
4478 #define NVM_FUSES_BODACT1_bm (1<<5) /* BOD Operation in Active Mode bit 1 mask. */
4479 #define NVM_FUSES_BODACT1_bp 5 /* BOD Operation in Active Mode bit 1 position. */
4480 
4481 #define NVM_FUSES_EESAVE_bm 0x08 /* Preserve EEPROM Through Chip Erase bit mask. */
4482 #define NVM_FUSES_EESAVE_bp 3 /* Preserve EEPROM Through Chip Erase bit position. */
4483 
4484 #define NVM_FUSES_BODLVL_gm 0x07 /* Brown Out Detection Voltage Level group mask. */
4485 #define NVM_FUSES_BODLVL_gp 0 /* Brown Out Detection Voltage Level group position. */
4486 #define NVM_FUSES_BODLVL0_bm (1<<0) /* Brown Out Detection Voltage Level bit 0 mask. */
4487 #define NVM_FUSES_BODLVL0_bp 0 /* Brown Out Detection Voltage Level bit 0 position. */
4488 #define NVM_FUSES_BODLVL1_bm (1<<1) /* Brown Out Detection Voltage Level bit 1 mask. */
4489 #define NVM_FUSES_BODLVL1_bp 1 /* Brown Out Detection Voltage Level bit 1 position. */
4490 #define NVM_FUSES_BODLVL2_bm (1<<2) /* Brown Out Detection Voltage Level bit 2 mask. */
4491 #define NVM_FUSES_BODLVL2_bp 2 /* Brown Out Detection Voltage Level bit 2 position. */
4492 
4493 
4494 /* AC - Analog Comparator */
4495 /* AC.AC0CTRL bit masks and bit positions */
4496 #define AC_INTMODE_gm 0xC0 /* Interrupt Mode group mask. */
4497 #define AC_INTMODE_gp 6 /* Interrupt Mode group position. */
4498 #define AC_INTMODE0_bm (1<<6) /* Interrupt Mode bit 0 mask. */
4499 #define AC_INTMODE0_bp 6 /* Interrupt Mode bit 0 position. */
4500 #define AC_INTMODE1_bm (1<<7) /* Interrupt Mode bit 1 mask. */
4501 #define AC_INTMODE1_bp 7 /* Interrupt Mode bit 1 position. */
4502 
4503 #define AC_INTLVL_gm 0x30 /* Interrupt Level group mask. */
4504 #define AC_INTLVL_gp 4 /* Interrupt Level group position. */
4505 #define AC_INTLVL0_bm (1<<4) /* Interrupt Level bit 0 mask. */
4506 #define AC_INTLVL0_bp 4 /* Interrupt Level bit 0 position. */
4507 #define AC_INTLVL1_bm (1<<5) /* Interrupt Level bit 1 mask. */
4508 #define AC_INTLVL1_bp 5 /* Interrupt Level bit 1 position. */
4509 
4510 #define AC_HSMODE_bm 0x08 /* High-speed Mode bit mask. */
4511 #define AC_HSMODE_bp 3 /* High-speed Mode bit position. */
4512 
4513 #define AC_HYSMODE_gm 0x06 /* Hysteresis Mode group mask. */
4514 #define AC_HYSMODE_gp 1 /* Hysteresis Mode group position. */
4515 #define AC_HYSMODE0_bm (1<<1) /* Hysteresis Mode bit 0 mask. */
4516 #define AC_HYSMODE0_bp 1 /* Hysteresis Mode bit 0 position. */
4517 #define AC_HYSMODE1_bm (1<<2) /* Hysteresis Mode bit 1 mask. */
4518 #define AC_HYSMODE1_bp 2 /* Hysteresis Mode bit 1 position. */
4519 
4520 #define AC_ENABLE_bm 0x01 /* Enable bit mask. */
4521 #define AC_ENABLE_bp 0 /* Enable bit position. */
4522 
4523 
4524 /* AC.AC1CTRL bit masks and bit positions */
4525 /* AC_INTMODE_gm Predefined. */
4526 /* AC_INTMODE_gp Predefined. */
4527 /* AC_INTMODE0_bm Predefined. */
4528 /* AC_INTMODE0_bp Predefined. */
4529 /* AC_INTMODE1_bm Predefined. */
4530 /* AC_INTMODE1_bp Predefined. */
4531 
4532 /* AC_INTLVL_gm Predefined. */
4533 /* AC_INTLVL_gp Predefined. */
4534 /* AC_INTLVL0_bm Predefined. */
4535 /* AC_INTLVL0_bp Predefined. */
4536 /* AC_INTLVL1_bm Predefined. */
4537 /* AC_INTLVL1_bp Predefined. */
4538 
4539 /* AC_HSMODE_bm Predefined. */
4540 /* AC_HSMODE_bp Predefined. */
4541 
4542 /* AC_HYSMODE_gm Predefined. */
4543 /* AC_HYSMODE_gp Predefined. */
4544 /* AC_HYSMODE0_bm Predefined. */
4545 /* AC_HYSMODE0_bp Predefined. */
4546 /* AC_HYSMODE1_bm Predefined. */
4547 /* AC_HYSMODE1_bp Predefined. */
4548 
4549 /* AC_ENABLE_bm Predefined. */
4550 /* AC_ENABLE_bp Predefined. */
4551 
4552 
4553 /* AC.AC0MUXCTRL bit masks and bit positions */
4554 #define AC_MUXPOS_gm 0x38 /* MUX Positive Input group mask. */
4555 #define AC_MUXPOS_gp 3 /* MUX Positive Input group position. */
4556 #define AC_MUXPOS0_bm (1<<3) /* MUX Positive Input bit 0 mask. */
4557 #define AC_MUXPOS0_bp 3 /* MUX Positive Input bit 0 position. */
4558 #define AC_MUXPOS1_bm (1<<4) /* MUX Positive Input bit 1 mask. */
4559 #define AC_MUXPOS1_bp 4 /* MUX Positive Input bit 1 position. */
4560 #define AC_MUXPOS2_bm (1<<5) /* MUX Positive Input bit 2 mask. */
4561 #define AC_MUXPOS2_bp 5 /* MUX Positive Input bit 2 position. */
4562 
4563 #define AC_MUXNEG_gm 0x07 /* MUX Negative Input group mask. */
4564 #define AC_MUXNEG_gp 0 /* MUX Negative Input group position. */
4565 #define AC_MUXNEG0_bm (1<<0) /* MUX Negative Input bit 0 mask. */
4566 #define AC_MUXNEG0_bp 0 /* MUX Negative Input bit 0 position. */
4567 #define AC_MUXNEG1_bm (1<<1) /* MUX Negative Input bit 1 mask. */
4568 #define AC_MUXNEG1_bp 1 /* MUX Negative Input bit 1 position. */
4569 #define AC_MUXNEG2_bm (1<<2) /* MUX Negative Input bit 2 mask. */
4570 #define AC_MUXNEG2_bp 2 /* MUX Negative Input bit 2 position. */
4571 
4572 
4573 /* AC.AC1MUXCTRL bit masks and bit positions */
4574 /* AC_MUXPOS_gm Predefined. */
4575 /* AC_MUXPOS_gp Predefined. */
4576 /* AC_MUXPOS0_bm Predefined. */
4577 /* AC_MUXPOS0_bp Predefined. */
4578 /* AC_MUXPOS1_bm Predefined. */
4579 /* AC_MUXPOS1_bp Predefined. */
4580 /* AC_MUXPOS2_bm Predefined. */
4581 /* AC_MUXPOS2_bp Predefined. */
4582 
4583 /* AC_MUXNEG_gm Predefined. */
4584 /* AC_MUXNEG_gp Predefined. */
4585 /* AC_MUXNEG0_bm Predefined. */
4586 /* AC_MUXNEG0_bp Predefined. */
4587 /* AC_MUXNEG1_bm Predefined. */
4588 /* AC_MUXNEG1_bp Predefined. */
4589 /* AC_MUXNEG2_bm Predefined. */
4590 /* AC_MUXNEG2_bp Predefined. */
4591 
4592 
4593 /* AC.CTRLA bit masks and bit positions */
4594 #define AC_AC0OUT_bm 0x01 /* Comparator 0 Output Enable bit mask. */
4595 #define AC_AC0OUT_bp 0 /* Comparator 0 Output Enable bit position. */
4596 
4597 
4598 /* AC.CTRLB bit masks and bit positions */
4599 #define AC_SCALEFAC_gm 0x3F /* VCC Voltage Scaler Factor group mask. */
4600 #define AC_SCALEFAC_gp 0 /* VCC Voltage Scaler Factor group position. */
4601 #define AC_SCALEFAC0_bm (1<<0) /* VCC Voltage Scaler Factor bit 0 mask. */
4602 #define AC_SCALEFAC0_bp 0 /* VCC Voltage Scaler Factor bit 0 position. */
4603 #define AC_SCALEFAC1_bm (1<<1) /* VCC Voltage Scaler Factor bit 1 mask. */
4604 #define AC_SCALEFAC1_bp 1 /* VCC Voltage Scaler Factor bit 1 position. */
4605 #define AC_SCALEFAC2_bm (1<<2) /* VCC Voltage Scaler Factor bit 2 mask. */
4606 #define AC_SCALEFAC2_bp 2 /* VCC Voltage Scaler Factor bit 2 position. */
4607 #define AC_SCALEFAC3_bm (1<<3) /* VCC Voltage Scaler Factor bit 3 mask. */
4608 #define AC_SCALEFAC3_bp 3 /* VCC Voltage Scaler Factor bit 3 position. */
4609 #define AC_SCALEFAC4_bm (1<<4) /* VCC Voltage Scaler Factor bit 4 mask. */
4610 #define AC_SCALEFAC4_bp 4 /* VCC Voltage Scaler Factor bit 4 position. */
4611 #define AC_SCALEFAC5_bm (1<<5) /* VCC Voltage Scaler Factor bit 5 mask. */
4612 #define AC_SCALEFAC5_bp 5 /* VCC Voltage Scaler Factor bit 5 position. */
4613 
4614 
4615 /* AC.WINCTRL bit masks and bit positions */
4616 #define AC_WEN_bm 0x10 /* Window Mode Enable bit mask. */
4617 #define AC_WEN_bp 4 /* Window Mode Enable bit position. */
4618 
4619 #define AC_WINTMODE_gm 0x0C /* Window Interrupt Mode group mask. */
4620 #define AC_WINTMODE_gp 2 /* Window Interrupt Mode group position. */
4621 #define AC_WINTMODE0_bm (1<<2) /* Window Interrupt Mode bit 0 mask. */
4622 #define AC_WINTMODE0_bp 2 /* Window Interrupt Mode bit 0 position. */
4623 #define AC_WINTMODE1_bm (1<<3) /* Window Interrupt Mode bit 1 mask. */
4624 #define AC_WINTMODE1_bp 3 /* Window Interrupt Mode bit 1 position. */
4625 
4626 #define AC_WINTLVL_gm 0x03 /* Window Interrupt Level group mask. */
4627 #define AC_WINTLVL_gp 0 /* Window Interrupt Level group position. */
4628 #define AC_WINTLVL0_bm (1<<0) /* Window Interrupt Level bit 0 mask. */
4629 #define AC_WINTLVL0_bp 0 /* Window Interrupt Level bit 0 position. */
4630 #define AC_WINTLVL1_bm (1<<1) /* Window Interrupt Level bit 1 mask. */
4631 #define AC_WINTLVL1_bp 1 /* Window Interrupt Level bit 1 position. */
4632 
4633 
4634 /* AC.STATUS bit masks and bit positions */
4635 #define AC_WSTATE_gm 0xC0 /* Window Mode State group mask. */
4636 #define AC_WSTATE_gp 6 /* Window Mode State group position. */
4637 #define AC_WSTATE0_bm (1<<6) /* Window Mode State bit 0 mask. */
4638 #define AC_WSTATE0_bp 6 /* Window Mode State bit 0 position. */
4639 #define AC_WSTATE1_bm (1<<7) /* Window Mode State bit 1 mask. */
4640 #define AC_WSTATE1_bp 7 /* Window Mode State bit 1 position. */
4641 
4642 #define AC_AC1STATE_bm 0x20 /* Comparator 1 State bit mask. */
4643 #define AC_AC1STATE_bp 5 /* Comparator 1 State bit position. */
4644 
4645 #define AC_AC0STATE_bm 0x10 /* Comparator 0 State bit mask. */
4646 #define AC_AC0STATE_bp 4 /* Comparator 0 State bit position. */
4647 
4648 #define AC_WIF_bm 0x04 /* Window Mode Interrupt Flag bit mask. */
4649 #define AC_WIF_bp 2 /* Window Mode Interrupt Flag bit position. */
4650 
4651 #define AC_AC1IF_bm 0x02 /* Comparator 1 Interrupt Flag bit mask. */
4652 #define AC_AC1IF_bp 1 /* Comparator 1 Interrupt Flag bit position. */
4653 
4654 #define AC_AC0IF_bm 0x01 /* Comparator 0 Interrupt Flag bit mask. */
4655 #define AC_AC0IF_bp 0 /* Comparator 0 Interrupt Flag bit position. */
4656 
4657 
4658 /* ADC - Analog/Digital Converter */
4659 /* ADC_CH.CTRL bit masks and bit positions */
4660 #define ADC_CH_START_bm 0x80 /* Channel Start Conversion bit mask. */
4661 #define ADC_CH_START_bp 7 /* Channel Start Conversion bit position. */
4662 
4663 #define ADC_CH_GAINFAC_gm 0x1C /* Gain Factor group mask. */
4664 #define ADC_CH_GAINFAC_gp 2 /* Gain Factor group position. */
4665 #define ADC_CH_GAINFAC0_bm (1<<2) /* Gain Factor bit 0 mask. */
4666 #define ADC_CH_GAINFAC0_bp 2 /* Gain Factor bit 0 position. */
4667 #define ADC_CH_GAINFAC1_bm (1<<3) /* Gain Factor bit 1 mask. */
4668 #define ADC_CH_GAINFAC1_bp 3 /* Gain Factor bit 1 position. */
4669 #define ADC_CH_GAINFAC2_bm (1<<4) /* Gain Factor bit 2 mask. */
4670 #define ADC_CH_GAINFAC2_bp 4 /* Gain Factor bit 2 position. */
4671 
4672 #define ADC_CH_INPUTMODE_gm 0x03 /* Input Mode Select group mask. */
4673 #define ADC_CH_INPUTMODE_gp 0 /* Input Mode Select group position. */
4674 #define ADC_CH_INPUTMODE0_bm (1<<0) /* Input Mode Select bit 0 mask. */
4675 #define ADC_CH_INPUTMODE0_bp 0 /* Input Mode Select bit 0 position. */
4676 #define ADC_CH_INPUTMODE1_bm (1<<1) /* Input Mode Select bit 1 mask. */
4677 #define ADC_CH_INPUTMODE1_bp 1 /* Input Mode Select bit 1 position. */
4678 
4679 
4680 /* ADC_CH.MUXCTRL bit masks and bit positions */
4681 #define ADC_CH_MUXPOS_gm 0x78 /* Positive Input Select group mask. */
4682 #define ADC_CH_MUXPOS_gp 3 /* Positive Input Select group position. */
4683 #define ADC_CH_MUXPOS0_bm (1<<3) /* Positive Input Select bit 0 mask. */
4684 #define ADC_CH_MUXPOS0_bp 3 /* Positive Input Select bit 0 position. */
4685 #define ADC_CH_MUXPOS1_bm (1<<4) /* Positive Input Select bit 1 mask. */
4686 #define ADC_CH_MUXPOS1_bp 4 /* Positive Input Select bit 1 position. */
4687 #define ADC_CH_MUXPOS2_bm (1<<5) /* Positive Input Select bit 2 mask. */
4688 #define ADC_CH_MUXPOS2_bp 5 /* Positive Input Select bit 2 position. */
4689 #define ADC_CH_MUXPOS3_bm (1<<6) /* Positive Input Select bit 3 mask. */
4690 #define ADC_CH_MUXPOS3_bp 6 /* Positive Input Select bit 3 position. */
4691 
4692 #define ADC_CH_MUXINT_gm 0x78 /* Internal Input Select group mask. */
4693 #define ADC_CH_MUXINT_gp 3 /* Internal Input Select group position. */
4694 #define ADC_CH_MUXINT0_bm (1<<3) /* Internal Input Select bit 0 mask. */
4695 #define ADC_CH_MUXINT0_bp 3 /* Internal Input Select bit 0 position. */
4696 #define ADC_CH_MUXINT1_bm (1<<4) /* Internal Input Select bit 1 mask. */
4697 #define ADC_CH_MUXINT1_bp 4 /* Internal Input Select bit 1 position. */
4698 #define ADC_CH_MUXINT2_bm (1<<5) /* Internal Input Select bit 2 mask. */
4699 #define ADC_CH_MUXINT2_bp 5 /* Internal Input Select bit 2 position. */
4700 #define ADC_CH_MUXINT3_bm (1<<6) /* Internal Input Select bit 3 mask. */
4701 #define ADC_CH_MUXINT3_bp 6 /* Internal Input Select bit 3 position. */
4702 
4703 #define ADC_CH_MUXNEG_gm 0x03 /* Negative Input Select group mask. */
4704 #define ADC_CH_MUXNEG_gp 0 /* Negative Input Select group position. */
4705 #define ADC_CH_MUXNEG0_bm (1<<0) /* Negative Input Select bit 0 mask. */
4706 #define ADC_CH_MUXNEG0_bp 0 /* Negative Input Select bit 0 position. */
4707 #define ADC_CH_MUXNEG1_bm (1<<1) /* Negative Input Select bit 1 mask. */
4708 #define ADC_CH_MUXNEG1_bp 1 /* Negative Input Select bit 1 position. */
4709 
4710 
4711 /* ADC_CH.INTCTRL bit masks and bit positions */
4712 #define ADC_CH_INTMODE_gm 0x0C /* Interrupt Mode group mask. */
4713 #define ADC_CH_INTMODE_gp 2 /* Interrupt Mode group position. */
4714 #define ADC_CH_INTMODE0_bm (1<<2) /* Interrupt Mode bit 0 mask. */
4715 #define ADC_CH_INTMODE0_bp 2 /* Interrupt Mode bit 0 position. */
4716 #define ADC_CH_INTMODE1_bm (1<<3) /* Interrupt Mode bit 1 mask. */
4717 #define ADC_CH_INTMODE1_bp 3 /* Interrupt Mode bit 1 position. */
4718 
4719 #define ADC_CH_INTLVL_gm 0x03 /* Interrupt Level group mask. */
4720 #define ADC_CH_INTLVL_gp 0 /* Interrupt Level group position. */
4721 #define ADC_CH_INTLVL0_bm (1<<0) /* Interrupt Level bit 0 mask. */
4722 #define ADC_CH_INTLVL0_bp 0 /* Interrupt Level bit 0 position. */
4723 #define ADC_CH_INTLVL1_bm (1<<1) /* Interrupt Level bit 1 mask. */
4724 #define ADC_CH_INTLVL1_bp 1 /* Interrupt Level bit 1 position. */
4725 
4726 
4727 /* ADC_CH.INTFLAGS bit masks and bit positions */
4728 #define ADC_CH_CHIF_bm 0x01 /* Channel Interrupt Flag bit mask. */
4729 #define ADC_CH_CHIF_bp 0 /* Channel Interrupt Flag bit position. */
4730 
4731 
4732 /* ADC.CTRLA bit masks and bit positions */
4733 #define ADC_DMASEL_gm 0xC0 /* DMA Selection group mask. */
4734 #define ADC_DMASEL_gp 6 /* DMA Selection group position. */
4735 #define ADC_DMASEL0_bm (1<<6) /* DMA Selection bit 0 mask. */
4736 #define ADC_DMASEL0_bp 6 /* DMA Selection bit 0 position. */
4737 #define ADC_DMASEL1_bm (1<<7) /* DMA Selection bit 1 mask. */
4738 #define ADC_DMASEL1_bp 7 /* DMA Selection bit 1 position. */
4739 
4740 #define ADC_CH3START_bm 0x20 /* Channel 3 Start Conversion bit mask. */
4741 #define ADC_CH3START_bp 5 /* Channel 3 Start Conversion bit position. */
4742 
4743 #define ADC_CH2START_bm 0x10 /* Channel 2 Start Conversion bit mask. */
4744 #define ADC_CH2START_bp 4 /* Channel 2 Start Conversion bit position. */
4745 
4746 #define ADC_CH1START_bm 0x08 /* Channel 1 Start Conversion bit mask. */
4747 #define ADC_CH1START_bp 3 /* Channel 1 Start Conversion bit position. */
4748 
4749 #define ADC_CH0START_bm 0x04 /* Channel 0 Start Conversion bit mask. */
4750 #define ADC_CH0START_bp 2 /* Channel 0 Start Conversion bit position. */
4751 
4752 #define ADC_FLUSH_bm 0x02 /* Flush Pipeline bit mask. */
4753 #define ADC_FLUSH_bp 1 /* Flush Pipeline bit position. */
4754 
4755 #define ADC_ENABLE_bm 0x01 /* Enable ADC bit mask. */
4756 #define ADC_ENABLE_bp 0 /* Enable ADC bit position. */
4757 
4758 
4759 /* ADC.CTRLB bit masks and bit positions */
4760 #define ADC_CONMODE_bm 0x10 /* Conversion Mode bit mask. */
4761 #define ADC_CONMODE_bp 4 /* Conversion Mode bit position. */
4762 
4763 #define ADC_FREERUN_bm 0x08 /* Free Running Mode Enable bit mask. */
4764 #define ADC_FREERUN_bp 3 /* Free Running Mode Enable bit position. */
4765 
4766 #define ADC_RESOLUTION_gm 0x06 /* Result Resolution group mask. */
4767 #define ADC_RESOLUTION_gp 1 /* Result Resolution group position. */
4768 #define ADC_RESOLUTION0_bm (1<<1) /* Result Resolution bit 0 mask. */
4769 #define ADC_RESOLUTION0_bp 1 /* Result Resolution bit 0 position. */
4770 #define ADC_RESOLUTION1_bm (1<<2) /* Result Resolution bit 1 mask. */
4771 #define ADC_RESOLUTION1_bp 2 /* Result Resolution bit 1 position. */
4772 
4773 
4774 /* ADC.REFCTRL bit masks and bit positions */
4775 #define ADC_REFSEL_gm 0x30 /* Reference Selection group mask. */
4776 #define ADC_REFSEL_gp 4 /* Reference Selection group position. */
4777 #define ADC_REFSEL0_bm (1<<4) /* Reference Selection bit 0 mask. */
4778 #define ADC_REFSEL0_bp 4 /* Reference Selection bit 0 position. */
4779 #define ADC_REFSEL1_bm (1<<5) /* Reference Selection bit 1 mask. */
4780 #define ADC_REFSEL1_bp 5 /* Reference Selection bit 1 position. */
4781 
4782 #define ADC_BANDGAP_bm 0x02 /* Bandgap enable bit mask. */
4783 #define ADC_BANDGAP_bp 1 /* Bandgap enable bit position. */
4784 
4785 #define ADC_TEMPREF_bm 0x01 /* Temperature Reference Enable bit mask. */
4786 #define ADC_TEMPREF_bp 0 /* Temperature Reference Enable bit position. */
4787 
4788 
4789 /* ADC.EVCTRL bit masks and bit positions */
4790 #define ADC_SWEEP_gm 0xC0 /* Channel Sweep Selection group mask. */
4791 #define ADC_SWEEP_gp 6 /* Channel Sweep Selection group position. */
4792 #define ADC_SWEEP0_bm (1<<6) /* Channel Sweep Selection bit 0 mask. */
4793 #define ADC_SWEEP0_bp 6 /* Channel Sweep Selection bit 0 position. */
4794 #define ADC_SWEEP1_bm (1<<7) /* Channel Sweep Selection bit 1 mask. */
4795 #define ADC_SWEEP1_bp 7 /* Channel Sweep Selection bit 1 position. */
4796 
4797 #define ADC_EVSEL_gm 0x38 /* Event Input Select group mask. */
4798 #define ADC_EVSEL_gp 3 /* Event Input Select group position. */
4799 #define ADC_EVSEL0_bm (1<<3) /* Event Input Select bit 0 mask. */
4800 #define ADC_EVSEL0_bp 3 /* Event Input Select bit 0 position. */
4801 #define ADC_EVSEL1_bm (1<<4) /* Event Input Select bit 1 mask. */
4802 #define ADC_EVSEL1_bp 4 /* Event Input Select bit 1 position. */
4803 #define ADC_EVSEL2_bm (1<<5) /* Event Input Select bit 2 mask. */
4804 #define ADC_EVSEL2_bp 5 /* Event Input Select bit 2 position. */
4805 
4806 #define ADC_EVACT_gm 0x07 /* Event Action Select group mask. */
4807 #define ADC_EVACT_gp 0 /* Event Action Select group position. */
4808 #define ADC_EVACT0_bm (1<<0) /* Event Action Select bit 0 mask. */
4809 #define ADC_EVACT0_bp 0 /* Event Action Select bit 0 position. */
4810 #define ADC_EVACT1_bm (1<<1) /* Event Action Select bit 1 mask. */
4811 #define ADC_EVACT1_bp 1 /* Event Action Select bit 1 position. */
4812 #define ADC_EVACT2_bm (1<<2) /* Event Action Select bit 2 mask. */
4813 #define ADC_EVACT2_bp 2 /* Event Action Select bit 2 position. */
4814 
4815 
4816 /* ADC.PRESCALER bit masks and bit positions */
4817 #define ADC_PRESCALER_gm 0x07 /* Clock Prescaler Selection group mask. */
4818 #define ADC_PRESCALER_gp 0 /* Clock Prescaler Selection group position. */
4819 #define ADC_PRESCALER0_bm (1<<0) /* Clock Prescaler Selection bit 0 mask. */
4820 #define ADC_PRESCALER0_bp 0 /* Clock Prescaler Selection bit 0 position. */
4821 #define ADC_PRESCALER1_bm (1<<1) /* Clock Prescaler Selection bit 1 mask. */
4822 #define ADC_PRESCALER1_bp 1 /* Clock Prescaler Selection bit 1 position. */
4823 #define ADC_PRESCALER2_bm (1<<2) /* Clock Prescaler Selection bit 2 mask. */
4824 #define ADC_PRESCALER2_bp 2 /* Clock Prescaler Selection bit 2 position. */
4825 
4826 
4827 /* ADC.CALCTRL bit masks and bit positions */
4828 #define ADC_CAL_bm 0x01 /* ADC Calibration Start bit mask. */
4829 #define ADC_CAL_bp 0 /* ADC Calibration Start bit position. */
4830 
4831 
4832 /* ADC.INTFLAGS bit masks and bit positions */
4833 #define ADC_CH3IF_bm 0x08 /* Channel 3 Interrupt Flag bit mask. */
4834 #define ADC_CH3IF_bp 3 /* Channel 3 Interrupt Flag bit position. */
4835 
4836 #define ADC_CH2IF_bm 0x04 /* Channel 2 Interrupt Flag bit mask. */
4837 #define ADC_CH2IF_bp 2 /* Channel 2 Interrupt Flag bit position. */
4838 
4839 #define ADC_CH1IF_bm 0x02 /* Channel 1 Interrupt Flag bit mask. */
4840 #define ADC_CH1IF_bp 1 /* Channel 1 Interrupt Flag bit position. */
4841 
4842 #define ADC_CH0IF_bm 0x01 /* Channel 0 Interrupt Flag bit mask. */
4843 #define ADC_CH0IF_bp 0 /* Channel 0 Interrupt Flag bit position. */
4844 
4845 
4846 /* DAC - Digital/Analog Converter */
4847 /* DAC.CTRLA bit masks and bit positions */
4848 #define DAC_IDOEN_bm 0x10 /* Internal Output Enable bit mask. */
4849 #define DAC_IDOEN_bp 4 /* Internal Output Enable bit position. */
4850 
4851 #define DAC_CH1EN_bm 0x08 /* Channel 1 Output Enable bit mask. */
4852 #define DAC_CH1EN_bp 3 /* Channel 1 Output Enable bit position. */
4853 
4854 #define DAC_CH0EN_bm 0x04 /* Channel 0 Output Enable bit mask. */
4855 #define DAC_CH0EN_bp 2 /* Channel 0 Output Enable bit position. */
4856 
4857 #define DAC_LPMODE_bm 0x02 /* Low Power Mode bit mask. */
4858 #define DAC_LPMODE_bp 1 /* Low Power Mode bit position. */
4859 
4860 #define DAC_ENABLE_bm 0x01 /* Enable bit mask. */
4861 #define DAC_ENABLE_bp 0 /* Enable bit position. */
4862 
4863 
4864 /* DAC.CTRLB bit masks and bit positions */
4865 #define DAC_CHSEL_gm 0x60 /* Channel Select group mask. */
4866 #define DAC_CHSEL_gp 5 /* Channel Select group position. */
4867 #define DAC_CHSEL0_bm (1<<5) /* Channel Select bit 0 mask. */
4868 #define DAC_CHSEL0_bp 5 /* Channel Select bit 0 position. */
4869 #define DAC_CHSEL1_bm (1<<6) /* Channel Select bit 1 mask. */
4870 #define DAC_CHSEL1_bp 6 /* Channel Select bit 1 position. */
4871 
4872 #define DAC_CH1TRIG_bm 0x02 /* Channel 1 Event Trig Enable bit mask. */
4873 #define DAC_CH1TRIG_bp 1 /* Channel 1 Event Trig Enable bit position. */
4874 
4875 #define DAC_CH0TRIG_bm 0x01 /* Channel 0 Event Trig Enable bit mask. */
4876 #define DAC_CH0TRIG_bp 0 /* Channel 0 Event Trig Enable bit position. */
4877 
4878 
4879 /* DAC.CTRLC bit masks and bit positions */
4880 #define DAC_REFSEL_gm 0x18 /* Reference Select group mask. */
4881 #define DAC_REFSEL_gp 3 /* Reference Select group position. */
4882 #define DAC_REFSEL0_bm (1<<3) /* Reference Select bit 0 mask. */
4883 #define DAC_REFSEL0_bp 3 /* Reference Select bit 0 position. */
4884 #define DAC_REFSEL1_bm (1<<4) /* Reference Select bit 1 mask. */
4885 #define DAC_REFSEL1_bp 4 /* Reference Select bit 1 position. */
4886 
4887 #define DAC_LEFTADJ_bm 0x01 /* Left-adjust Result bit mask. */
4888 #define DAC_LEFTADJ_bp 0 /* Left-adjust Result bit position. */
4889 
4890 
4891 /* DAC.EVCTRL bit masks and bit positions */
4892 #define DAC_EVSEL_gm 0x07 /* Event Input Selection group mask. */
4893 #define DAC_EVSEL_gp 0 /* Event Input Selection group position. */
4894 #define DAC_EVSEL0_bm (1<<0) /* Event Input Selection bit 0 mask. */
4895 #define DAC_EVSEL0_bp 0 /* Event Input Selection bit 0 position. */
4896 #define DAC_EVSEL1_bm (1<<1) /* Event Input Selection bit 1 mask. */
4897 #define DAC_EVSEL1_bp 1 /* Event Input Selection bit 1 position. */
4898 #define DAC_EVSEL2_bm (1<<2) /* Event Input Selection bit 2 mask. */
4899 #define DAC_EVSEL2_bp 2 /* Event Input Selection bit 2 position. */
4900 
4901 
4902 /* DAC.TIMCTRL bit masks and bit positions */
4903 #define DAC_CONINTVAL_gm 0x70 /* Conversion Intercal group mask. */
4904 #define DAC_CONINTVAL_gp 4 /* Conversion Intercal group position. */
4905 #define DAC_CONINTVAL0_bm (1<<4) /* Conversion Intercal bit 0 mask. */
4906 #define DAC_CONINTVAL0_bp 4 /* Conversion Intercal bit 0 position. */
4907 #define DAC_CONINTVAL1_bm (1<<5) /* Conversion Intercal bit 1 mask. */
4908 #define DAC_CONINTVAL1_bp 5 /* Conversion Intercal bit 1 position. */
4909 #define DAC_CONINTVAL2_bm (1<<6) /* Conversion Intercal bit 2 mask. */
4910 #define DAC_CONINTVAL2_bp 6 /* Conversion Intercal bit 2 position. */
4911 
4912 #define DAC_REFRESH_gm 0x0F /* Refresh Timing Control group mask. */
4913 #define DAC_REFRESH_gp 0 /* Refresh Timing Control group position. */
4914 #define DAC_REFRESH0_bm (1<<0) /* Refresh Timing Control bit 0 mask. */
4915 #define DAC_REFRESH0_bp 0 /* Refresh Timing Control bit 0 position. */
4916 #define DAC_REFRESH1_bm (1<<1) /* Refresh Timing Control bit 1 mask. */
4917 #define DAC_REFRESH1_bp 1 /* Refresh Timing Control bit 1 position. */
4918 #define DAC_REFRESH2_bm (1<<2) /* Refresh Timing Control bit 2 mask. */
4919 #define DAC_REFRESH2_bp 2 /* Refresh Timing Control bit 2 position. */
4920 #define DAC_REFRESH3_bm (1<<3) /* Refresh Timing Control bit 3 mask. */
4921 #define DAC_REFRESH3_bp 3 /* Refresh Timing Control bit 3 position. */
4922 
4923 
4924 /* DAC.STATUS bit masks and bit positions */
4925 #define DAC_CH1DRE_bm 0x02 /* Channel 1 Data Register Empty bit mask. */
4926 #define DAC_CH1DRE_bp 1 /* Channel 1 Data Register Empty bit position. */
4927 
4928 #define DAC_CH0DRE_bm 0x01 /* Channel 0 Data Register Empty bit mask. */
4929 #define DAC_CH0DRE_bp 0 /* Channel 0 Data Register Empty bit position. */
4930 
4931 
4932 /* RTC - Real-Time Clounter */
4933 /* RTC.CTRL bit masks and bit positions */
4934 #define RTC_PRESCALER_gm 0x07 /* Prescaling Factor group mask. */
4935 #define RTC_PRESCALER_gp 0 /* Prescaling Factor group position. */
4936 #define RTC_PRESCALER0_bm (1<<0) /* Prescaling Factor bit 0 mask. */
4937 #define RTC_PRESCALER0_bp 0 /* Prescaling Factor bit 0 position. */
4938 #define RTC_PRESCALER1_bm (1<<1) /* Prescaling Factor bit 1 mask. */
4939 #define RTC_PRESCALER1_bp 1 /* Prescaling Factor bit 1 position. */
4940 #define RTC_PRESCALER2_bm (1<<2) /* Prescaling Factor bit 2 mask. */
4941 #define RTC_PRESCALER2_bp 2 /* Prescaling Factor bit 2 position. */
4942 
4943 
4944 /* RTC.STATUS bit masks and bit positions */
4945 #define RTC_SYNCBUSY_bm 0x01 /* Synchronization Busy Flag bit mask. */
4946 #define RTC_SYNCBUSY_bp 0 /* Synchronization Busy Flag bit position. */
4947 
4948 
4949 /* RTC.INTCTRL bit masks and bit positions */
4950 #define RTC_COMPINTLVL_gm 0x0C /* Compare Match Interrupt Level group mask. */
4951 #define RTC_COMPINTLVL_gp 2 /* Compare Match Interrupt Level group position. */
4952 #define RTC_COMPINTLVL0_bm (1<<2) /* Compare Match Interrupt Level bit 0 mask. */
4953 #define RTC_COMPINTLVL0_bp 2 /* Compare Match Interrupt Level bit 0 position. */
4954 #define RTC_COMPINTLVL1_bm (1<<3) /* Compare Match Interrupt Level bit 1 mask. */
4955 #define RTC_COMPINTLVL1_bp 3 /* Compare Match Interrupt Level bit 1 position. */
4956 
4957 #define RTC_OVFINTLVL_gm 0x03 /* Overflow Interrupt Level group mask. */
4958 #define RTC_OVFINTLVL_gp 0 /* Overflow Interrupt Level group position. */
4959 #define RTC_OVFINTLVL0_bm (1<<0) /* Overflow Interrupt Level bit 0 mask. */
4960 #define RTC_OVFINTLVL0_bp 0 /* Overflow Interrupt Level bit 0 position. */
4961 #define RTC_OVFINTLVL1_bm (1<<1) /* Overflow Interrupt Level bit 1 mask. */
4962 #define RTC_OVFINTLVL1_bp 1 /* Overflow Interrupt Level bit 1 position. */
4963 
4964 
4965 /* RTC.INTFLAGS bit masks and bit positions */
4966 #define RTC_COMPIF_bm 0x02 /* Compare Match Interrupt Flag bit mask. */
4967 #define RTC_COMPIF_bp 1 /* Compare Match Interrupt Flag bit position. */
4968 
4969 #define RTC_OVFIF_bm 0x01 /* Overflow Interrupt Flag bit mask. */
4970 #define RTC_OVFIF_bp 0 /* Overflow Interrupt Flag bit position. */
4971 
4972 
4973 /* EBI - External Bus Interface */
4974 /* EBI_CS.CTRLA bit masks and bit positions */
4975 #define EBI_CS_ASPACE_gm 0x7C /* Address Space group mask. */
4976 #define EBI_CS_ASPACE_gp 2 /* Address Space group position. */
4977 #define EBI_CS_ASPACE0_bm (1<<2) /* Address Space bit 0 mask. */
4978 #define EBI_CS_ASPACE0_bp 2 /* Address Space bit 0 position. */
4979 #define EBI_CS_ASPACE1_bm (1<<3) /* Address Space bit 1 mask. */
4980 #define EBI_CS_ASPACE1_bp 3 /* Address Space bit 1 position. */
4981 #define EBI_CS_ASPACE2_bm (1<<4) /* Address Space bit 2 mask. */
4982 #define EBI_CS_ASPACE2_bp 4 /* Address Space bit 2 position. */
4983 #define EBI_CS_ASPACE3_bm (1<<5) /* Address Space bit 3 mask. */
4984 #define EBI_CS_ASPACE3_bp 5 /* Address Space bit 3 position. */
4985 #define EBI_CS_ASPACE4_bm (1<<6) /* Address Space bit 4 mask. */
4986 #define EBI_CS_ASPACE4_bp 6 /* Address Space bit 4 position. */
4987 
4988 #define EBI_CS_MODE_gm 0x03 /* Memory Mode group mask. */
4989 #define EBI_CS_MODE_gp 0 /* Memory Mode group position. */
4990 #define EBI_CS_MODE0_bm (1<<0) /* Memory Mode bit 0 mask. */
4991 #define EBI_CS_MODE0_bp 0 /* Memory Mode bit 0 position. */
4992 #define EBI_CS_MODE1_bm (1<<1) /* Memory Mode bit 1 mask. */
4993 #define EBI_CS_MODE1_bp 1 /* Memory Mode bit 1 position. */
4994 
4995 
4996 /* EBI_CS.CTRLB bit masks and bit positions */
4997 #define EBI_CS_SRWS_gm 0x07 /* SRAM Wait State Cycles group mask. */
4998 #define EBI_CS_SRWS_gp 0 /* SRAM Wait State Cycles group position. */
4999 #define EBI_CS_SRWS0_bm (1<<0) /* SRAM Wait State Cycles bit 0 mask. */
5000 #define EBI_CS_SRWS0_bp 0 /* SRAM Wait State Cycles bit 0 position. */
5001 #define EBI_CS_SRWS1_bm (1<<1) /* SRAM Wait State Cycles bit 1 mask. */
5002 #define EBI_CS_SRWS1_bp 1 /* SRAM Wait State Cycles bit 1 position. */
5003 #define EBI_CS_SRWS2_bm (1<<2) /* SRAM Wait State Cycles bit 2 mask. */
5004 #define EBI_CS_SRWS2_bp 2 /* SRAM Wait State Cycles bit 2 position. */
5005 
5006 #define EBI_CS_SDINITDONE_bm 0x80 /* SDRAM Initialization Done bit mask. */
5007 #define EBI_CS_SDINITDONE_bp 7 /* SDRAM Initialization Done bit position. */
5008 
5009 #define EBI_CS_SDSREN_bm 0x04 /* SDRAM Self-refresh Enable bit mask. */
5010 #define EBI_CS_SDSREN_bp 2 /* SDRAM Self-refresh Enable bit position. */
5011 
5012 #define EBI_CS_SDMODE_gm 0x03 /* SDRAM Mode group mask. */
5013 #define EBI_CS_SDMODE_gp 0 /* SDRAM Mode group position. */
5014 #define EBI_CS_SDMODE0_bm (1<<0) /* SDRAM Mode bit 0 mask. */
5015 #define EBI_CS_SDMODE0_bp 0 /* SDRAM Mode bit 0 position. */
5016 #define EBI_CS_SDMODE1_bm (1<<1) /* SDRAM Mode bit 1 mask. */
5017 #define EBI_CS_SDMODE1_bp 1 /* SDRAM Mode bit 1 position. */
5018 
5019 
5020 /* EBI.CTRL bit masks and bit positions */
5021 #define EBI_SDDATAW_gm 0xC0 /* SDRAM Data Width Setting group mask. */
5022 #define EBI_SDDATAW_gp 6 /* SDRAM Data Width Setting group position. */
5023 #define EBI_SDDATAW0_bm (1<<6) /* SDRAM Data Width Setting bit 0 mask. */
5024 #define EBI_SDDATAW0_bp 6 /* SDRAM Data Width Setting bit 0 position. */
5025 #define EBI_SDDATAW1_bm (1<<7) /* SDRAM Data Width Setting bit 1 mask. */
5026 #define EBI_SDDATAW1_bp 7 /* SDRAM Data Width Setting bit 1 position. */
5027 
5028 #define EBI_LPCMODE_gm 0x30 /* SRAM LPC Mode group mask. */
5029 #define EBI_LPCMODE_gp 4 /* SRAM LPC Mode group position. */
5030 #define EBI_LPCMODE0_bm (1<<4) /* SRAM LPC Mode bit 0 mask. */
5031 #define EBI_LPCMODE0_bp 4 /* SRAM LPC Mode bit 0 position. */
5032 #define EBI_LPCMODE1_bm (1<<5) /* SRAM LPC Mode bit 1 mask. */
5033 #define EBI_LPCMODE1_bp 5 /* SRAM LPC Mode bit 1 position. */
5034 
5035 #define EBI_SRMODE_gm 0x0C /* SRAM Mode group mask. */
5036 #define EBI_SRMODE_gp 2 /* SRAM Mode group position. */
5037 #define EBI_SRMODE0_bm (1<<2) /* SRAM Mode bit 0 mask. */
5038 #define EBI_SRMODE0_bp 2 /* SRAM Mode bit 0 position. */
5039 #define EBI_SRMODE1_bm (1<<3) /* SRAM Mode bit 1 mask. */
5040 #define EBI_SRMODE1_bp 3 /* SRAM Mode bit 1 position. */
5041 
5042 #define EBI_IFMODE_gm 0x03 /* Interface Mode group mask. */
5043 #define EBI_IFMODE_gp 0 /* Interface Mode group position. */
5044 #define EBI_IFMODE0_bm (1<<0) /* Interface Mode bit 0 mask. */
5045 #define EBI_IFMODE0_bp 0 /* Interface Mode bit 0 position. */
5046 #define EBI_IFMODE1_bm (1<<1) /* Interface Mode bit 1 mask. */
5047 #define EBI_IFMODE1_bp 1 /* Interface Mode bit 1 position. */
5048 
5049 
5050 /* EBI.SDRAMCTRLA bit masks and bit positions */
5051 #define EBI_SDCAS_bm 0x08 /* SDRAM CAS Latency Setting bit mask. */
5052 #define EBI_SDCAS_bp 3 /* SDRAM CAS Latency Setting bit position. */
5053 
5054 #define EBI_SDROW_bm 0x04 /* SDRAM ROW Bits Setting bit mask. */
5055 #define EBI_SDROW_bp 2 /* SDRAM ROW Bits Setting bit position. */
5056 
5057 #define EBI_SDCOL_gm 0x03 /* SDRAM Column Bits Setting group mask. */
5058 #define EBI_SDCOL_gp 0 /* SDRAM Column Bits Setting group position. */
5059 #define EBI_SDCOL0_bm (1<<0) /* SDRAM Column Bits Setting bit 0 mask. */
5060 #define EBI_SDCOL0_bp 0 /* SDRAM Column Bits Setting bit 0 position. */
5061 #define EBI_SDCOL1_bm (1<<1) /* SDRAM Column Bits Setting bit 1 mask. */
5062 #define EBI_SDCOL1_bp 1 /* SDRAM Column Bits Setting bit 1 position. */
5063 
5064 
5065 /* EBI.SDRAMCTRLB bit masks and bit positions */
5066 #define EBI_MRDLY_gm 0xC0 /* SDRAM Mode Register Delay group mask. */
5067 #define EBI_MRDLY_gp 6 /* SDRAM Mode Register Delay group position. */
5068 #define EBI_MRDLY0_bm (1<<6) /* SDRAM Mode Register Delay bit 0 mask. */
5069 #define EBI_MRDLY0_bp 6 /* SDRAM Mode Register Delay bit 0 position. */
5070 #define EBI_MRDLY1_bm (1<<7) /* SDRAM Mode Register Delay bit 1 mask. */
5071 #define EBI_MRDLY1_bp 7 /* SDRAM Mode Register Delay bit 1 position. */
5072 
5073 #define EBI_ROWCYCDLY_gm 0x38 /* SDRAM Row Cycle Delay group mask. */
5074 #define EBI_ROWCYCDLY_gp 3 /* SDRAM Row Cycle Delay group position. */
5075 #define EBI_ROWCYCDLY0_bm (1<<3) /* SDRAM Row Cycle Delay bit 0 mask. */
5076 #define EBI_ROWCYCDLY0_bp 3 /* SDRAM Row Cycle Delay bit 0 position. */
5077 #define EBI_ROWCYCDLY1_bm (1<<4) /* SDRAM Row Cycle Delay bit 1 mask. */
5078 #define EBI_ROWCYCDLY1_bp 4 /* SDRAM Row Cycle Delay bit 1 position. */
5079 #define EBI_ROWCYCDLY2_bm (1<<5) /* SDRAM Row Cycle Delay bit 2 mask. */
5080 #define EBI_ROWCYCDLY2_bp 5 /* SDRAM Row Cycle Delay bit 2 position. */
5081 
5082 #define EBI_RPDLY_gm 0x07 /* SDRAM Row-to-Precharge Delay group mask. */
5083 #define EBI_RPDLY_gp 0 /* SDRAM Row-to-Precharge Delay group position. */
5084 #define EBI_RPDLY0_bm (1<<0) /* SDRAM Row-to-Precharge Delay bit 0 mask. */
5085 #define EBI_RPDLY0_bp 0 /* SDRAM Row-to-Precharge Delay bit 0 position. */
5086 #define EBI_RPDLY1_bm (1<<1) /* SDRAM Row-to-Precharge Delay bit 1 mask. */
5087 #define EBI_RPDLY1_bp 1 /* SDRAM Row-to-Precharge Delay bit 1 position. */
5088 #define EBI_RPDLY2_bm (1<<2) /* SDRAM Row-to-Precharge Delay bit 2 mask. */
5089 #define EBI_RPDLY2_bp 2 /* SDRAM Row-to-Precharge Delay bit 2 position. */
5090 
5091 
5092 /* EBI.SDRAMCTRLC bit masks and bit positions */
5093 #define EBI_WRDLY_gm 0xC0 /* SDRAM Write Recovery Delay group mask. */
5094 #define EBI_WRDLY_gp 6 /* SDRAM Write Recovery Delay group position. */
5095 #define EBI_WRDLY0_bm (1<<6) /* SDRAM Write Recovery Delay bit 0 mask. */
5096 #define EBI_WRDLY0_bp 6 /* SDRAM Write Recovery Delay bit 0 position. */
5097 #define EBI_WRDLY1_bm (1<<7) /* SDRAM Write Recovery Delay bit 1 mask. */
5098 #define EBI_WRDLY1_bp 7 /* SDRAM Write Recovery Delay bit 1 position. */
5099 
5100 #define EBI_ESRDLY_gm 0x38 /* SDRAM Exit-Self-refresh-to-Active Delay group mask. */
5101 #define EBI_ESRDLY_gp 3 /* SDRAM Exit-Self-refresh-to-Active Delay group position. */
5102 #define EBI_ESRDLY0_bm (1<<3) /* SDRAM Exit-Self-refresh-to-Active Delay bit 0 mask. */
5103 #define EBI_ESRDLY0_bp 3 /* SDRAM Exit-Self-refresh-to-Active Delay bit 0 position. */
5104 #define EBI_ESRDLY1_bm (1<<4) /* SDRAM Exit-Self-refresh-to-Active Delay bit 1 mask. */
5105 #define EBI_ESRDLY1_bp 4 /* SDRAM Exit-Self-refresh-to-Active Delay bit 1 position. */
5106 #define EBI_ESRDLY2_bm (1<<5) /* SDRAM Exit-Self-refresh-to-Active Delay bit 2 mask. */
5107 #define EBI_ESRDLY2_bp 5 /* SDRAM Exit-Self-refresh-to-Active Delay bit 2 position. */
5108 
5109 #define EBI_ROWCOLDLY_gm 0x07 /* SDRAM Row-to-Column Delay group mask. */
5110 #define EBI_ROWCOLDLY_gp 0 /* SDRAM Row-to-Column Delay group position. */
5111 #define EBI_ROWCOLDLY0_bm (1<<0) /* SDRAM Row-to-Column Delay bit 0 mask. */
5112 #define EBI_ROWCOLDLY0_bp 0 /* SDRAM Row-to-Column Delay bit 0 position. */
5113 #define EBI_ROWCOLDLY1_bm (1<<1) /* SDRAM Row-to-Column Delay bit 1 mask. */
5114 #define EBI_ROWCOLDLY1_bp 1 /* SDRAM Row-to-Column Delay bit 1 position. */
5115 #define EBI_ROWCOLDLY2_bm (1<<2) /* SDRAM Row-to-Column Delay bit 2 mask. */
5116 #define EBI_ROWCOLDLY2_bp 2 /* SDRAM Row-to-Column Delay bit 2 position. */
5117 
5118 
5119 /* TWI - Two-Wire Interface */
5120 /* TWI_MASTER.CTRLA bit masks and bit positions */
5121 #define TWI_MASTER_INTLVL_gm 0xC0 /* Interrupt Level group mask. */
5122 #define TWI_MASTER_INTLVL_gp 6 /* Interrupt Level group position. */
5123 #define TWI_MASTER_INTLVL0_bm (1<<6) /* Interrupt Level bit 0 mask. */
5124 #define TWI_MASTER_INTLVL0_bp 6 /* Interrupt Level bit 0 position. */
5125 #define TWI_MASTER_INTLVL1_bm (1<<7) /* Interrupt Level bit 1 mask. */
5126 #define TWI_MASTER_INTLVL1_bp 7 /* Interrupt Level bit 1 position. */
5127 
5128 #define TWI_MASTER_RIEN_bm 0x20 /* Read Interrupt Enable bit mask. */
5129 #define TWI_MASTER_RIEN_bp 5 /* Read Interrupt Enable bit position. */
5130 
5131 #define TWI_MASTER_WIEN_bm 0x10 /* Write Interrupt Enable bit mask. */
5132 #define TWI_MASTER_WIEN_bp 4 /* Write Interrupt Enable bit position. */
5133 
5134 #define TWI_MASTER_ENABLE_bm 0x08 /* Enable TWI Master bit mask. */
5135 #define TWI_MASTER_ENABLE_bp 3 /* Enable TWI Master bit position. */
5136 
5137 
5138 /* TWI_MASTER.CTRLB bit masks and bit positions */
5139 #define TWI_MASTER_TIMEOUT_gm 0x0C /* Inactive Bus Timeout group mask. */
5140 #define TWI_MASTER_TIMEOUT_gp 2 /* Inactive Bus Timeout group position. */
5141 #define TWI_MASTER_TIMEOUT0_bm (1<<2) /* Inactive Bus Timeout bit 0 mask. */
5142 #define TWI_MASTER_TIMEOUT0_bp 2 /* Inactive Bus Timeout bit 0 position. */
5143 #define TWI_MASTER_TIMEOUT1_bm (1<<3) /* Inactive Bus Timeout bit 1 mask. */
5144 #define TWI_MASTER_TIMEOUT1_bp 3 /* Inactive Bus Timeout bit 1 position. */
5145 
5146 #define TWI_MASTER_QCEN_bm 0x02 /* Quick Command Enable bit mask. */
5147 #define TWI_MASTER_QCEN_bp 1 /* Quick Command Enable bit position. */
5148 
5149 #define TWI_MASTER_SMEN_bm 0x01 /* Smart Mode Enable bit mask. */
5150 #define TWI_MASTER_SMEN_bp 0 /* Smart Mode Enable bit position. */
5151 
5152 
5153 /* TWI_MASTER.CTRLC bit masks and bit positions */
5154 #define TWI_MASTER_ACKACT_bm 0x04 /* Acknowledge Action bit mask. */
5155 #define TWI_MASTER_ACKACT_bp 2 /* Acknowledge Action bit position. */
5156 
5157 #define TWI_MASTER_CMD_gm 0x03 /* Command group mask. */
5158 #define TWI_MASTER_CMD_gp 0 /* Command group position. */
5159 #define TWI_MASTER_CMD0_bm (1<<0) /* Command bit 0 mask. */
5160 #define TWI_MASTER_CMD0_bp 0 /* Command bit 0 position. */
5161 #define TWI_MASTER_CMD1_bm (1<<1) /* Command bit 1 mask. */
5162 #define TWI_MASTER_CMD1_bp 1 /* Command bit 1 position. */
5163 
5164 
5165 /* TWI_MASTER.STATUS bit masks and bit positions */
5166 #define TWI_MASTER_RIF_bm 0x80 /* Read Interrupt Flag bit mask. */
5167 #define TWI_MASTER_RIF_bp 7 /* Read Interrupt Flag bit position. */
5168 
5169 #define TWI_MASTER_WIF_bm 0x40 /* Write Interrupt Flag bit mask. */
5170 #define TWI_MASTER_WIF_bp 6 /* Write Interrupt Flag bit position. */
5171 
5172 #define TWI_MASTER_CLKHOLD_bm 0x20 /* Clock Hold bit mask. */
5173 #define TWI_MASTER_CLKHOLD_bp 5 /* Clock Hold bit position. */
5174 
5175 #define TWI_MASTER_RXACK_bm 0x10 /* Received Acknowledge bit mask. */
5176 #define TWI_MASTER_RXACK_bp 4 /* Received Acknowledge bit position. */
5177 
5178 #define TWI_MASTER_ARBLOST_bm 0x08 /* Arbitration Lost bit mask. */
5179 #define TWI_MASTER_ARBLOST_bp 3 /* Arbitration Lost bit position. */
5180 
5181 #define TWI_MASTER_BUSERR_bm 0x04 /* Bus Error bit mask. */
5182 #define TWI_MASTER_BUSERR_bp 2 /* Bus Error bit position. */
5183 
5184 #define TWI_MASTER_BUSSTATE_gm 0x03 /* Bus State group mask. */
5185 #define TWI_MASTER_BUSSTATE_gp 0 /* Bus State group position. */
5186 #define TWI_MASTER_BUSSTATE0_bm (1<<0) /* Bus State bit 0 mask. */
5187 #define TWI_MASTER_BUSSTATE0_bp 0 /* Bus State bit 0 position. */
5188 #define TWI_MASTER_BUSSTATE1_bm (1<<1) /* Bus State bit 1 mask. */
5189 #define TWI_MASTER_BUSSTATE1_bp 1 /* Bus State bit 1 position. */
5190 
5191 
5192 /* TWI_SLAVE.CTRLA bit masks and bit positions */
5193 #define TWI_SLAVE_INTLVL_gm 0xC0 /* Interrupt Level group mask. */
5194 #define TWI_SLAVE_INTLVL_gp 6 /* Interrupt Level group position. */
5195 #define TWI_SLAVE_INTLVL0_bm (1<<6) /* Interrupt Level bit 0 mask. */
5196 #define TWI_SLAVE_INTLVL0_bp 6 /* Interrupt Level bit 0 position. */
5197 #define TWI_SLAVE_INTLVL1_bm (1<<7) /* Interrupt Level bit 1 mask. */
5198 #define TWI_SLAVE_INTLVL1_bp 7 /* Interrupt Level bit 1 position. */
5199 
5200 #define TWI_SLAVE_DIEN_bm 0x20 /* Data Interrupt Enable bit mask. */
5201 #define TWI_SLAVE_DIEN_bp 5 /* Data Interrupt Enable bit position. */
5202 
5203 #define TWI_SLAVE_APIEN_bm 0x10 /* Address/Stop Interrupt Enable bit mask. */
5204 #define TWI_SLAVE_APIEN_bp 4 /* Address/Stop Interrupt Enable bit position. */
5205 
5206 #define TWI_SLAVE_ENABLE_bm 0x08 /* Enable TWI Slave bit mask. */
5207 #define TWI_SLAVE_ENABLE_bp 3 /* Enable TWI Slave bit position. */
5208 
5209 #define TWI_SLAVE_PIEN_bm 0x04 /* Stop Interrupt Enable bit mask. */
5210 #define TWI_SLAVE_PIEN_bp 2 /* Stop Interrupt Enable bit position. */
5211 
5212 #define TWI_SLAVE_PMEN_bm 0x02 /* Promiscuous Mode Enable bit mask. */
5213 #define TWI_SLAVE_PMEN_bp 1 /* Promiscuous Mode Enable bit position. */
5214 
5215 #define TWI_SLAVE_SMEN_bm 0x01 /* Smart Mode Enable bit mask. */
5216 #define TWI_SLAVE_SMEN_bp 0 /* Smart Mode Enable bit position. */
5217 
5218 
5219 /* TWI_SLAVE.CTRLB bit masks and bit positions */
5220 #define TWI_SLAVE_ACKACT_bm 0x04 /* Acknowledge Action bit mask. */
5221 #define TWI_SLAVE_ACKACT_bp 2 /* Acknowledge Action bit position. */
5222 
5223 #define TWI_SLAVE_CMD_gm 0x03 /* Command group mask. */
5224 #define TWI_SLAVE_CMD_gp 0 /* Command group position. */
5225 #define TWI_SLAVE_CMD0_bm (1<<0) /* Command bit 0 mask. */
5226 #define TWI_SLAVE_CMD0_bp 0 /* Command bit 0 position. */
5227 #define TWI_SLAVE_CMD1_bm (1<<1) /* Command bit 1 mask. */
5228 #define TWI_SLAVE_CMD1_bp 1 /* Command bit 1 position. */
5229 
5230 
5231 /* TWI_SLAVE.STATUS bit masks and bit positions */
5232 #define TWI_SLAVE_DIF_bm 0x80 /* Data Interrupt Flag bit mask. */
5233 #define TWI_SLAVE_DIF_bp 7 /* Data Interrupt Flag bit position. */
5234 
5235 #define TWI_SLAVE_APIF_bm 0x40 /* Address/Stop Interrupt Flag bit mask. */
5236 #define TWI_SLAVE_APIF_bp 6 /* Address/Stop Interrupt Flag bit position. */
5237 
5238 #define TWI_SLAVE_CLKHOLD_bm 0x20 /* Clock Hold bit mask. */
5239 #define TWI_SLAVE_CLKHOLD_bp 5 /* Clock Hold bit position. */
5240 
5241 #define TWI_SLAVE_RXACK_bm 0x10 /* Received Acknowledge bit mask. */
5242 #define TWI_SLAVE_RXACK_bp 4 /* Received Acknowledge bit position. */
5243 
5244 #define TWI_SLAVE_COLL_bm 0x08 /* Collision bit mask. */
5245 #define TWI_SLAVE_COLL_bp 3 /* Collision bit position. */
5246 
5247 #define TWI_SLAVE_BUSERR_bm 0x04 /* Bus Error bit mask. */
5248 #define TWI_SLAVE_BUSERR_bp 2 /* Bus Error bit position. */
5249 
5250 #define TWI_SLAVE_DIR_bm 0x02 /* Read/Write Direction bit mask. */
5251 #define TWI_SLAVE_DIR_bp 1 /* Read/Write Direction bit position. */
5252 
5253 #define TWI_SLAVE_AP_bm 0x01 /* Slave Address or Stop bit mask. */
5254 #define TWI_SLAVE_AP_bp 0 /* Slave Address or Stop bit position. */
5255 
5256 
5257 /* TWI_SLAVE.ADDRMASK bit masks and bit positions */
5258 #define TWI_SLAVE_ADDRMASK_gm 0xFE /* Address Mask group mask. */
5259 #define TWI_SLAVE_ADDRMASK_gp 1 /* Address Mask group position. */
5260 #define TWI_SLAVE_ADDRMASK0_bm (1<<1) /* Address Mask bit 0 mask. */
5261 #define TWI_SLAVE_ADDRMASK0_bp 1 /* Address Mask bit 0 position. */
5262 #define TWI_SLAVE_ADDRMASK1_bm (1<<2) /* Address Mask bit 1 mask. */
5263 #define TWI_SLAVE_ADDRMASK1_bp 2 /* Address Mask bit 1 position. */
5264 #define TWI_SLAVE_ADDRMASK2_bm (1<<3) /* Address Mask bit 2 mask. */
5265 #define TWI_SLAVE_ADDRMASK2_bp 3 /* Address Mask bit 2 position. */
5266 #define TWI_SLAVE_ADDRMASK3_bm (1<<4) /* Address Mask bit 3 mask. */
5267 #define TWI_SLAVE_ADDRMASK3_bp 4 /* Address Mask bit 3 position. */
5268 #define TWI_SLAVE_ADDRMASK4_bm (1<<5) /* Address Mask bit 4 mask. */
5269 #define TWI_SLAVE_ADDRMASK4_bp 5 /* Address Mask bit 4 position. */
5270 #define TWI_SLAVE_ADDRMASK5_bm (1<<6) /* Address Mask bit 5 mask. */
5271 #define TWI_SLAVE_ADDRMASK5_bp 6 /* Address Mask bit 5 position. */
5272 #define TWI_SLAVE_ADDRMASK6_bm (1<<7) /* Address Mask bit 6 mask. */
5273 #define TWI_SLAVE_ADDRMASK6_bp 7 /* Address Mask bit 6 position. */
5274 
5275 #define TWI_SLAVE_ADDREN_bm 0x01 /* Address Enable bit mask. */
5276 #define TWI_SLAVE_ADDREN_bp 0 /* Address Enable bit position. */
5277 
5278 
5279 /* TWI.CTRL bit masks and bit positions */
5280 #define TWI_SDAHOLD_bm 0x02 /* SDA Hold Time Enable bit mask. */
5281 #define TWI_SDAHOLD_bp 1 /* SDA Hold Time Enable bit position. */
5282 
5283 #define TWI_EDIEN_bm 0x01 /* External Driver Interface Enable bit mask. */
5284 #define TWI_EDIEN_bp 0 /* External Driver Interface Enable bit position. */
5285 
5286 
5287 /* PORT - Port Configuration */
5288 /* PORTCFG.VPCTRLA bit masks and bit positions */
5289 #define PORTCFG_VP1MAP_gm 0xF0 /* Virtual Port 1 Mapping group mask. */
5290 #define PORTCFG_VP1MAP_gp 4 /* Virtual Port 1 Mapping group position. */
5291 #define PORTCFG_VP1MAP0_bm (1<<4) /* Virtual Port 1 Mapping bit 0 mask. */
5292 #define PORTCFG_VP1MAP0_bp 4 /* Virtual Port 1 Mapping bit 0 position. */
5293 #define PORTCFG_VP1MAP1_bm (1<<5) /* Virtual Port 1 Mapping bit 1 mask. */
5294 #define PORTCFG_VP1MAP1_bp 5 /* Virtual Port 1 Mapping bit 1 position. */
5295 #define PORTCFG_VP1MAP2_bm (1<<6) /* Virtual Port 1 Mapping bit 2 mask. */
5296 #define PORTCFG_VP1MAP2_bp 6 /* Virtual Port 1 Mapping bit 2 position. */
5297 #define PORTCFG_VP1MAP3_bm (1<<7) /* Virtual Port 1 Mapping bit 3 mask. */
5298 #define PORTCFG_VP1MAP3_bp 7 /* Virtual Port 1 Mapping bit 3 position. */
5299 
5300 #define PORTCFG_VP0MAP_gm 0x0F /* Virtual Port 0 Mapping group mask. */
5301 #define PORTCFG_VP0MAP_gp 0 /* Virtual Port 0 Mapping group position. */
5302 #define PORTCFG_VP0MAP0_bm (1<<0) /* Virtual Port 0 Mapping bit 0 mask. */
5303 #define PORTCFG_VP0MAP0_bp 0 /* Virtual Port 0 Mapping bit 0 position. */
5304 #define PORTCFG_VP0MAP1_bm (1<<1) /* Virtual Port 0 Mapping bit 1 mask. */
5305 #define PORTCFG_VP0MAP1_bp 1 /* Virtual Port 0 Mapping bit 1 position. */
5306 #define PORTCFG_VP0MAP2_bm (1<<2) /* Virtual Port 0 Mapping bit 2 mask. */
5307 #define PORTCFG_VP0MAP2_bp 2 /* Virtual Port 0 Mapping bit 2 position. */
5308 #define PORTCFG_VP0MAP3_bm (1<<3) /* Virtual Port 0 Mapping bit 3 mask. */
5309 #define PORTCFG_VP0MAP3_bp 3 /* Virtual Port 0 Mapping bit 3 position. */
5310 
5311 
5312 /* PORTCFG.VPCTRLB bit masks and bit positions */
5313 #define PORTCFG_VP3MAP_gm 0xF0 /* Virtual Port 3 Mapping group mask. */
5314 #define PORTCFG_VP3MAP_gp 4 /* Virtual Port 3 Mapping group position. */
5315 #define PORTCFG_VP3MAP0_bm (1<<4) /* Virtual Port 3 Mapping bit 0 mask. */
5316 #define PORTCFG_VP3MAP0_bp 4 /* Virtual Port 3 Mapping bit 0 position. */
5317 #define PORTCFG_VP3MAP1_bm (1<<5) /* Virtual Port 3 Mapping bit 1 mask. */
5318 #define PORTCFG_VP3MAP1_bp 5 /* Virtual Port 3 Mapping bit 1 position. */
5319 #define PORTCFG_VP3MAP2_bm (1<<6) /* Virtual Port 3 Mapping bit 2 mask. */
5320 #define PORTCFG_VP3MAP2_bp 6 /* Virtual Port 3 Mapping bit 2 position. */
5321 #define PORTCFG_VP3MAP3_bm (1<<7) /* Virtual Port 3 Mapping bit 3 mask. */
5322 #define PORTCFG_VP3MAP3_bp 7 /* Virtual Port 3 Mapping bit 3 position. */
5323 
5324 #define PORTCFG_VP2MAP_gm 0x0F /* Virtual Port 2 Mapping group mask. */
5325 #define PORTCFG_VP2MAP_gp 0 /* Virtual Port 2 Mapping group position. */
5326 #define PORTCFG_VP2MAP0_bm (1<<0) /* Virtual Port 2 Mapping bit 0 mask. */
5327 #define PORTCFG_VP2MAP0_bp 0 /* Virtual Port 2 Mapping bit 0 position. */
5328 #define PORTCFG_VP2MAP1_bm (1<<1) /* Virtual Port 2 Mapping bit 1 mask. */
5329 #define PORTCFG_VP2MAP1_bp 1 /* Virtual Port 2 Mapping bit 1 position. */
5330 #define PORTCFG_VP2MAP2_bm (1<<2) /* Virtual Port 2 Mapping bit 2 mask. */
5331 #define PORTCFG_VP2MAP2_bp 2 /* Virtual Port 2 Mapping bit 2 position. */
5332 #define PORTCFG_VP2MAP3_bm (1<<3) /* Virtual Port 2 Mapping bit 3 mask. */
5333 #define PORTCFG_VP2MAP3_bp 3 /* Virtual Port 2 Mapping bit 3 position. */
5334 
5335 
5336 /* PORTCFG.CLKEVOUT bit masks and bit positions */
5337 #define PORTCFG_CLKOUT_gm 0x03 /* Clock Output Port group mask. */
5338 #define PORTCFG_CLKOUT_gp 0 /* Clock Output Port group position. */
5339 #define PORTCFG_CLKOUT0_bm (1<<0) /* Clock Output Port bit 0 mask. */
5340 #define PORTCFG_CLKOUT0_bp 0 /* Clock Output Port bit 0 position. */
5341 #define PORTCFG_CLKOUT1_bm (1<<1) /* Clock Output Port bit 1 mask. */
5342 #define PORTCFG_CLKOUT1_bp 1 /* Clock Output Port bit 1 position. */
5343 
5344 #define PORTCFG_EVOUT_gm 0x30 /* Event Output Port group mask. */
5345 #define PORTCFG_EVOUT_gp 4 /* Event Output Port group position. */
5346 #define PORTCFG_EVOUT0_bm (1<<4) /* Event Output Port bit 0 mask. */
5347 #define PORTCFG_EVOUT0_bp 4 /* Event Output Port bit 0 position. */
5348 #define PORTCFG_EVOUT1_bm (1<<5) /* Event Output Port bit 1 mask. */
5349 #define PORTCFG_EVOUT1_bp 5 /* Event Output Port bit 1 position. */
5350 
5351 
5352 /* VPORT.INTFLAGS bit masks and bit positions */
5353 #define VPORT_INT1IF_bm 0x02 /* Port Interrupt 1 Flag bit mask. */
5354 #define VPORT_INT1IF_bp 1 /* Port Interrupt 1 Flag bit position. */
5355 
5356 #define VPORT_INT0IF_bm 0x01 /* Port Interrupt 0 Flag bit mask. */
5357 #define VPORT_INT0IF_bp 0 /* Port Interrupt 0 Flag bit position. */
5358 
5359 
5360 /* PORT.INTCTRL bit masks and bit positions */
5361 #define PORT_INT1LVL_gm 0x0C /* Port Interrupt 1 Level group mask. */
5362 #define PORT_INT1LVL_gp 2 /* Port Interrupt 1 Level group position. */
5363 #define PORT_INT1LVL0_bm (1<<2) /* Port Interrupt 1 Level bit 0 mask. */
5364 #define PORT_INT1LVL0_bp 2 /* Port Interrupt 1 Level bit 0 position. */
5365 #define PORT_INT1LVL1_bm (1<<3) /* Port Interrupt 1 Level bit 1 mask. */
5366 #define PORT_INT1LVL1_bp 3 /* Port Interrupt 1 Level bit 1 position. */
5367 
5368 #define PORT_INT0LVL_gm 0x03 /* Port Interrupt 0 Level group mask. */
5369 #define PORT_INT0LVL_gp 0 /* Port Interrupt 0 Level group position. */
5370 #define PORT_INT0LVL0_bm (1<<0) /* Port Interrupt 0 Level bit 0 mask. */
5371 #define PORT_INT0LVL0_bp 0 /* Port Interrupt 0 Level bit 0 position. */
5372 #define PORT_INT0LVL1_bm (1<<1) /* Port Interrupt 0 Level bit 1 mask. */
5373 #define PORT_INT0LVL1_bp 1 /* Port Interrupt 0 Level bit 1 position. */
5374 
5375 
5376 /* PORT.INTFLAGS bit masks and bit positions */
5377 #define PORT_INT1IF_bm 0x02 /* Port Interrupt 1 Flag bit mask. */
5378 #define PORT_INT1IF_bp 1 /* Port Interrupt 1 Flag bit position. */
5379 
5380 #define PORT_INT0IF_bm 0x01 /* Port Interrupt 0 Flag bit mask. */
5381 #define PORT_INT0IF_bp 0 /* Port Interrupt 0 Flag bit position. */
5382 
5383 
5384 /* PORT.PIN0CTRL bit masks and bit positions */
5385 #define PORT_SRLEN_bm 0x80 /* Slew Rate Enable bit mask. */
5386 #define PORT_SRLEN_bp 7 /* Slew Rate Enable bit position. */
5387 
5388 #define PORT_INVEN_bm 0x40 /* Inverted I/O Enable bit mask. */
5389 #define PORT_INVEN_bp 6 /* Inverted I/O Enable bit position. */
5390 
5391 #define PORT_OPC_gm 0x38 /* Output/Pull Configuration group mask. */
5392 #define PORT_OPC_gp 3 /* Output/Pull Configuration group position. */
5393 #define PORT_OPC0_bm (1<<3) /* Output/Pull Configuration bit 0 mask. */
5394 #define PORT_OPC0_bp 3 /* Output/Pull Configuration bit 0 position. */
5395 #define PORT_OPC1_bm (1<<4) /* Output/Pull Configuration bit 1 mask. */
5396 #define PORT_OPC1_bp 4 /* Output/Pull Configuration bit 1 position. */
5397 #define PORT_OPC2_bm (1<<5) /* Output/Pull Configuration bit 2 mask. */
5398 #define PORT_OPC2_bp 5 /* Output/Pull Configuration bit 2 position. */
5399 
5400 #define PORT_ISC_gm 0x07 /* Input/Sense Configuration group mask. */
5401 #define PORT_ISC_gp 0 /* Input/Sense Configuration group position. */
5402 #define PORT_ISC0_bm (1<<0) /* Input/Sense Configuration bit 0 mask. */
5403 #define PORT_ISC0_bp 0 /* Input/Sense Configuration bit 0 position. */
5404 #define PORT_ISC1_bm (1<<1) /* Input/Sense Configuration bit 1 mask. */
5405 #define PORT_ISC1_bp 1 /* Input/Sense Configuration bit 1 position. */
5406 #define PORT_ISC2_bm (1<<2) /* Input/Sense Configuration bit 2 mask. */
5407 #define PORT_ISC2_bp 2 /* Input/Sense Configuration bit 2 position. */
5408 
5409 
5410 /* PORT.PIN1CTRL bit masks and bit positions */
5411 /* PORT_SRLEN_bm Predefined. */
5412 /* PORT_SRLEN_bp Predefined. */
5413 
5414 /* PORT_INVEN_bm Predefined. */
5415 /* PORT_INVEN_bp Predefined. */
5416 
5417 /* PORT_OPC_gm Predefined. */
5418 /* PORT_OPC_gp Predefined. */
5419 /* PORT_OPC0_bm Predefined. */
5420 /* PORT_OPC0_bp Predefined. */
5421 /* PORT_OPC1_bm Predefined. */
5422 /* PORT_OPC1_bp Predefined. */
5423 /* PORT_OPC2_bm Predefined. */
5424 /* PORT_OPC2_bp Predefined. */
5425 
5426 /* PORT_ISC_gm Predefined. */
5427 /* PORT_ISC_gp Predefined. */
5428 /* PORT_ISC0_bm Predefined. */
5429 /* PORT_ISC0_bp Predefined. */
5430 /* PORT_ISC1_bm Predefined. */
5431 /* PORT_ISC1_bp Predefined. */
5432 /* PORT_ISC2_bm Predefined. */
5433 /* PORT_ISC2_bp Predefined. */
5434 
5435 
5436 /* PORT.PIN2CTRL bit masks and bit positions */
5437 /* PORT_SRLEN_bm Predefined. */
5438 /* PORT_SRLEN_bp Predefined. */
5439 
5440 /* PORT_INVEN_bm Predefined. */
5441 /* PORT_INVEN_bp Predefined. */
5442 
5443 /* PORT_OPC_gm Predefined. */
5444 /* PORT_OPC_gp Predefined. */
5445 /* PORT_OPC0_bm Predefined. */
5446 /* PORT_OPC0_bp Predefined. */
5447 /* PORT_OPC1_bm Predefined. */
5448 /* PORT_OPC1_bp Predefined. */
5449 /* PORT_OPC2_bm Predefined. */
5450 /* PORT_OPC2_bp Predefined. */
5451 
5452 /* PORT_ISC_gm Predefined. */
5453 /* PORT_ISC_gp Predefined. */
5454 /* PORT_ISC0_bm Predefined. */
5455 /* PORT_ISC0_bp Predefined. */
5456 /* PORT_ISC1_bm Predefined. */
5457 /* PORT_ISC1_bp Predefined. */
5458 /* PORT_ISC2_bm Predefined. */
5459 /* PORT_ISC2_bp Predefined. */
5460 
5461 
5462 /* PORT.PIN3CTRL bit masks and bit positions */
5463 /* PORT_SRLEN_bm Predefined. */
5464 /* PORT_SRLEN_bp Predefined. */
5465 
5466 /* PORT_INVEN_bm Predefined. */
5467 /* PORT_INVEN_bp Predefined. */
5468 
5469 /* PORT_OPC_gm Predefined. */
5470 /* PORT_OPC_gp Predefined. */
5471 /* PORT_OPC0_bm Predefined. */
5472 /* PORT_OPC0_bp Predefined. */
5473 /* PORT_OPC1_bm Predefined. */
5474 /* PORT_OPC1_bp Predefined. */
5475 /* PORT_OPC2_bm Predefined. */
5476 /* PORT_OPC2_bp Predefined. */
5477 
5478 /* PORT_ISC_gm Predefined. */
5479 /* PORT_ISC_gp Predefined. */
5480 /* PORT_ISC0_bm Predefined. */
5481 /* PORT_ISC0_bp Predefined. */
5482 /* PORT_ISC1_bm Predefined. */
5483 /* PORT_ISC1_bp Predefined. */
5484 /* PORT_ISC2_bm Predefined. */
5485 /* PORT_ISC2_bp Predefined. */
5486 
5487 
5488 /* PORT.PIN4CTRL bit masks and bit positions */
5489 /* PORT_SRLEN_bm Predefined. */
5490 /* PORT_SRLEN_bp Predefined. */
5491 
5492 /* PORT_INVEN_bm Predefined. */
5493 /* PORT_INVEN_bp Predefined. */
5494 
5495 /* PORT_OPC_gm Predefined. */
5496 /* PORT_OPC_gp Predefined. */
5497 /* PORT_OPC0_bm Predefined. */
5498 /* PORT_OPC0_bp Predefined. */
5499 /* PORT_OPC1_bm Predefined. */
5500 /* PORT_OPC1_bp Predefined. */
5501 /* PORT_OPC2_bm Predefined. */
5502 /* PORT_OPC2_bp Predefined. */
5503 
5504 /* PORT_ISC_gm Predefined. */
5505 /* PORT_ISC_gp Predefined. */
5506 /* PORT_ISC0_bm Predefined. */
5507 /* PORT_ISC0_bp Predefined. */
5508 /* PORT_ISC1_bm Predefined. */
5509 /* PORT_ISC1_bp Predefined. */
5510 /* PORT_ISC2_bm Predefined. */
5511 /* PORT_ISC2_bp Predefined. */
5512 
5513 
5514 /* PORT.PIN5CTRL bit masks and bit positions */
5515 /* PORT_SRLEN_bm Predefined. */
5516 /* PORT_SRLEN_bp Predefined. */
5517 
5518 /* PORT_INVEN_bm Predefined. */
5519 /* PORT_INVEN_bp Predefined. */
5520 
5521 /* PORT_OPC_gm Predefined. */
5522 /* PORT_OPC_gp Predefined. */
5523 /* PORT_OPC0_bm Predefined. */
5524 /* PORT_OPC0_bp Predefined. */
5525 /* PORT_OPC1_bm Predefined. */
5526 /* PORT_OPC1_bp Predefined. */
5527 /* PORT_OPC2_bm Predefined. */
5528 /* PORT_OPC2_bp Predefined. */
5529 
5530 /* PORT_ISC_gm Predefined. */
5531 /* PORT_ISC_gp Predefined. */
5532 /* PORT_ISC0_bm Predefined. */
5533 /* PORT_ISC0_bp Predefined. */
5534 /* PORT_ISC1_bm Predefined. */
5535 /* PORT_ISC1_bp Predefined. */
5536 /* PORT_ISC2_bm Predefined. */
5537 /* PORT_ISC2_bp Predefined. */
5538 
5539 
5540 /* PORT.PIN6CTRL bit masks and bit positions */
5541 /* PORT_SRLEN_bm Predefined. */
5542 /* PORT_SRLEN_bp Predefined. */
5543 
5544 /* PORT_INVEN_bm Predefined. */
5545 /* PORT_INVEN_bp Predefined. */
5546 
5547 /* PORT_OPC_gm Predefined. */
5548 /* PORT_OPC_gp Predefined. */
5549 /* PORT_OPC0_bm Predefined. */
5550 /* PORT_OPC0_bp Predefined. */
5551 /* PORT_OPC1_bm Predefined. */
5552 /* PORT_OPC1_bp Predefined. */
5553 /* PORT_OPC2_bm Predefined. */
5554 /* PORT_OPC2_bp Predefined. */
5555 
5556 /* PORT_ISC_gm Predefined. */
5557 /* PORT_ISC_gp Predefined. */
5558 /* PORT_ISC0_bm Predefined. */
5559 /* PORT_ISC0_bp Predefined. */
5560 /* PORT_ISC1_bm Predefined. */
5561 /* PORT_ISC1_bp Predefined. */
5562 /* PORT_ISC2_bm Predefined. */
5563 /* PORT_ISC2_bp Predefined. */
5564 
5565 
5566 /* PORT.PIN7CTRL bit masks and bit positions */
5567 /* PORT_SRLEN_bm Predefined. */
5568 /* PORT_SRLEN_bp Predefined. */
5569 
5570 /* PORT_INVEN_bm Predefined. */
5571 /* PORT_INVEN_bp Predefined. */
5572 
5573 /* PORT_OPC_gm Predefined. */
5574 /* PORT_OPC_gp Predefined. */
5575 /* PORT_OPC0_bm Predefined. */
5576 /* PORT_OPC0_bp Predefined. */
5577 /* PORT_OPC1_bm Predefined. */
5578 /* PORT_OPC1_bp Predefined. */
5579 /* PORT_OPC2_bm Predefined. */
5580 /* PORT_OPC2_bp Predefined. */
5581 
5582 /* PORT_ISC_gm Predefined. */
5583 /* PORT_ISC_gp Predefined. */
5584 /* PORT_ISC0_bm Predefined. */
5585 /* PORT_ISC0_bp Predefined. */
5586 /* PORT_ISC1_bm Predefined. */
5587 /* PORT_ISC1_bp Predefined. */
5588 /* PORT_ISC2_bm Predefined. */
5589 /* PORT_ISC2_bp Predefined. */
5590 
5591 
5592 /* TC - 16-bit Timer/Counter With PWM */
5593 /* TC0.CTRLA bit masks and bit positions */
5594 #define TC0_CLKSEL_gm 0x0F /* Clock Selection group mask. */
5595 #define TC0_CLKSEL_gp 0 /* Clock Selection group position. */
5596 #define TC0_CLKSEL0_bm (1<<0) /* Clock Selection bit 0 mask. */
5597 #define TC0_CLKSEL0_bp 0 /* Clock Selection bit 0 position. */
5598 #define TC0_CLKSEL1_bm (1<<1) /* Clock Selection bit 1 mask. */
5599 #define TC0_CLKSEL1_bp 1 /* Clock Selection bit 1 position. */
5600 #define TC0_CLKSEL2_bm (1<<2) /* Clock Selection bit 2 mask. */
5601 #define TC0_CLKSEL2_bp 2 /* Clock Selection bit 2 position. */
5602 #define TC0_CLKSEL3_bm (1<<3) /* Clock Selection bit 3 mask. */
5603 #define TC0_CLKSEL3_bp 3 /* Clock Selection bit 3 position. */
5604 
5605 
5606 /* TC0.CTRLB bit masks and bit positions */
5607 #define TC0_CCDEN_bm 0x80 /* Compare or Capture D Enable bit mask. */
5608 #define TC0_CCDEN_bp 7 /* Compare or Capture D Enable bit position. */
5609 
5610 #define TC0_CCCEN_bm 0x40 /* Compare or Capture C Enable bit mask. */
5611 #define TC0_CCCEN_bp 6 /* Compare or Capture C Enable bit position. */
5612 
5613 #define TC0_CCBEN_bm 0x20 /* Compare or Capture B Enable bit mask. */
5614 #define TC0_CCBEN_bp 5 /* Compare or Capture B Enable bit position. */
5615 
5616 #define TC0_CCAEN_bm 0x10 /* Compare or Capture A Enable bit mask. */
5617 #define TC0_CCAEN_bp 4 /* Compare or Capture A Enable bit position. */
5618 
5619 #define TC0_WGMODE_gm 0x07 /* Waveform generation mode group mask. */
5620 #define TC0_WGMODE_gp 0 /* Waveform generation mode group position. */
5621 #define TC0_WGMODE0_bm (1<<0) /* Waveform generation mode bit 0 mask. */
5622 #define TC0_WGMODE0_bp 0 /* Waveform generation mode bit 0 position. */
5623 #define TC0_WGMODE1_bm (1<<1) /* Waveform generation mode bit 1 mask. */
5624 #define TC0_WGMODE1_bp 1 /* Waveform generation mode bit 1 position. */
5625 #define TC0_WGMODE2_bm (1<<2) /* Waveform generation mode bit 2 mask. */
5626 #define TC0_WGMODE2_bp 2 /* Waveform generation mode bit 2 position. */
5627 
5628 
5629 /* TC0.CTRLC bit masks and bit positions */
5630 #define TC0_CMPD_bm 0x08 /* Compare D Output Value bit mask. */
5631 #define TC0_CMPD_bp 3 /* Compare D Output Value bit position. */
5632 
5633 #define TC0_CMPC_bm 0x04 /* Compare C Output Value bit mask. */
5634 #define TC0_CMPC_bp 2 /* Compare C Output Value bit position. */
5635 
5636 #define TC0_CMPB_bm 0x02 /* Compare B Output Value bit mask. */
5637 #define TC0_CMPB_bp 1 /* Compare B Output Value bit position. */
5638 
5639 #define TC0_CMPA_bm 0x01 /* Compare A Output Value bit mask. */
5640 #define TC0_CMPA_bp 0 /* Compare A Output Value bit position. */
5641 
5642 
5643 /* TC0.CTRLD bit masks and bit positions */
5644 #define TC0_EVACT_gm 0xE0 /* Event Action group mask. */
5645 #define TC0_EVACT_gp 5 /* Event Action group position. */
5646 #define TC0_EVACT0_bm (1<<5) /* Event Action bit 0 mask. */
5647 #define TC0_EVACT0_bp 5 /* Event Action bit 0 position. */
5648 #define TC0_EVACT1_bm (1<<6) /* Event Action bit 1 mask. */
5649 #define TC0_EVACT1_bp 6 /* Event Action bit 1 position. */
5650 #define TC0_EVACT2_bm (1<<7) /* Event Action bit 2 mask. */
5651 #define TC0_EVACT2_bp 7 /* Event Action bit 2 position. */
5652 
5653 #define TC0_EVDLY_bm 0x10 /* Event Delay bit mask. */
5654 #define TC0_EVDLY_bp 4 /* Event Delay bit position. */
5655 
5656 #define TC0_EVSEL_gm 0x0F /* Event Source Select group mask. */
5657 #define TC0_EVSEL_gp 0 /* Event Source Select group position. */
5658 #define TC0_EVSEL0_bm (1<<0) /* Event Source Select bit 0 mask. */
5659 #define TC0_EVSEL0_bp 0 /* Event Source Select bit 0 position. */
5660 #define TC0_EVSEL1_bm (1<<1) /* Event Source Select bit 1 mask. */
5661 #define TC0_EVSEL1_bp 1 /* Event Source Select bit 1 position. */
5662 #define TC0_EVSEL2_bm (1<<2) /* Event Source Select bit 2 mask. */
5663 #define TC0_EVSEL2_bp 2 /* Event Source Select bit 2 position. */
5664 #define TC0_EVSEL3_bm (1<<3) /* Event Source Select bit 3 mask. */
5665 #define TC0_EVSEL3_bp 3 /* Event Source Select bit 3 position. */
5666 
5667 
5668 /* TC0.CTRLE bit masks and bit positions */
5669 #define TC0_DTHM_bm 0x02 /* Dead Time Hold Mode bit mask. */
5670 #define TC0_DTHM_bp 1 /* Dead Time Hold Mode bit position. */
5671 
5672 #define TC0_BYTEM_bm 0x01 /* Byte Mode bit mask. */
5673 #define TC0_BYTEM_bp 0 /* Byte Mode bit position. */
5674 
5675 
5676 /* TC0.INTCTRLA bit masks and bit positions */
5677 #define TC0_ERRINTLVL_gm 0x0C /* Error Interrupt Level group mask. */
5678 #define TC0_ERRINTLVL_gp 2 /* Error Interrupt Level group position. */
5679 #define TC0_ERRINTLVL0_bm (1<<2) /* Error Interrupt Level bit 0 mask. */
5680 #define TC0_ERRINTLVL0_bp 2 /* Error Interrupt Level bit 0 position. */
5681 #define TC0_ERRINTLVL1_bm (1<<3) /* Error Interrupt Level bit 1 mask. */
5682 #define TC0_ERRINTLVL1_bp 3 /* Error Interrupt Level bit 1 position. */
5683 
5684 #define TC0_OVFINTLVL_gm 0x03 /* Overflow interrupt level group mask. */
5685 #define TC0_OVFINTLVL_gp 0 /* Overflow interrupt level group position. */
5686 #define TC0_OVFINTLVL0_bm (1<<0) /* Overflow interrupt level bit 0 mask. */
5687 #define TC0_OVFINTLVL0_bp 0 /* Overflow interrupt level bit 0 position. */
5688 #define TC0_OVFINTLVL1_bm (1<<1) /* Overflow interrupt level bit 1 mask. */
5689 #define TC0_OVFINTLVL1_bp 1 /* Overflow interrupt level bit 1 position. */
5690 
5691 
5692 /* TC0.INTCTRLB bit masks and bit positions */
5693 #define TC0_CCDINTLVL_gm 0xC0 /* Compare or Capture D Interrupt Level group mask. */
5694 #define TC0_CCDINTLVL_gp 6 /* Compare or Capture D Interrupt Level group position. */
5695 #define TC0_CCDINTLVL0_bm (1<<6) /* Compare or Capture D Interrupt Level bit 0 mask. */
5696 #define TC0_CCDINTLVL0_bp 6 /* Compare or Capture D Interrupt Level bit 0 position. */
5697 #define TC0_CCDINTLVL1_bm (1<<7) /* Compare or Capture D Interrupt Level bit 1 mask. */
5698 #define TC0_CCDINTLVL1_bp 7 /* Compare or Capture D Interrupt Level bit 1 position. */
5699 
5700 #define TC0_CCCINTLVL_gm 0x30 /* Compare or Capture C Interrupt Level group mask. */
5701 #define TC0_CCCINTLVL_gp 4 /* Compare or Capture C Interrupt Level group position. */
5702 #define TC0_CCCINTLVL0_bm (1<<4) /* Compare or Capture C Interrupt Level bit 0 mask. */
5703 #define TC0_CCCINTLVL0_bp 4 /* Compare or Capture C Interrupt Level bit 0 position. */
5704 #define TC0_CCCINTLVL1_bm (1<<5) /* Compare or Capture C Interrupt Level bit 1 mask. */
5705 #define TC0_CCCINTLVL1_bp 5 /* Compare or Capture C Interrupt Level bit 1 position. */
5706 
5707 #define TC0_CCBINTLVL_gm 0x0C /* Compare or Capture B Interrupt Level group mask. */
5708 #define TC0_CCBINTLVL_gp 2 /* Compare or Capture B Interrupt Level group position. */
5709 #define TC0_CCBINTLVL0_bm (1<<2) /* Compare or Capture B Interrupt Level bit 0 mask. */
5710 #define TC0_CCBINTLVL0_bp 2 /* Compare or Capture B Interrupt Level bit 0 position. */
5711 #define TC0_CCBINTLVL1_bm (1<<3) /* Compare or Capture B Interrupt Level bit 1 mask. */
5712 #define TC0_CCBINTLVL1_bp 3 /* Compare or Capture B Interrupt Level bit 1 position. */
5713 
5714 #define TC0_CCAINTLVL_gm 0x03 /* Compare or Capture A Interrupt Level group mask. */
5715 #define TC0_CCAINTLVL_gp 0 /* Compare or Capture A Interrupt Level group position. */
5716 #define TC0_CCAINTLVL0_bm (1<<0) /* Compare or Capture A Interrupt Level bit 0 mask. */
5717 #define TC0_CCAINTLVL0_bp 0 /* Compare or Capture A Interrupt Level bit 0 position. */
5718 #define TC0_CCAINTLVL1_bm (1<<1) /* Compare or Capture A Interrupt Level bit 1 mask. */
5719 #define TC0_CCAINTLVL1_bp 1 /* Compare or Capture A Interrupt Level bit 1 position. */
5720 
5721 
5722 /* TC0.CTRLFCLR bit masks and bit positions */
5723 #define TC0_CMD_gm 0x0C /* Command group mask. */
5724 #define TC0_CMD_gp 2 /* Command group position. */
5725 #define TC0_CMD0_bm (1<<2) /* Command bit 0 mask. */
5726 #define TC0_CMD0_bp 2 /* Command bit 0 position. */
5727 #define TC0_CMD1_bm (1<<3) /* Command bit 1 mask. */
5728 #define TC0_CMD1_bp 3 /* Command bit 1 position. */
5729 
5730 #define TC0_LUPD_bm 0x02 /* Lock Update bit mask. */
5731 #define TC0_LUPD_bp 1 /* Lock Update bit position. */
5732 
5733 #define TC0_DIR_bm 0x01 /* Direction bit mask. */
5734 #define TC0_DIR_bp 0 /* Direction bit position. */
5735 
5736 
5737 /* TC0.CTRLFSET bit masks and bit positions */
5738 /* TC0_CMD_gm Predefined. */
5739 /* TC0_CMD_gp Predefined. */
5740 /* TC0_CMD0_bm Predefined. */
5741 /* TC0_CMD0_bp Predefined. */
5742 /* TC0_CMD1_bm Predefined. */
5743 /* TC0_CMD1_bp Predefined. */
5744 
5745 /* TC0_LUPD_bm Predefined. */
5746 /* TC0_LUPD_bp Predefined. */
5747 
5748 /* TC0_DIR_bm Predefined. */
5749 /* TC0_DIR_bp Predefined. */
5750 
5751 
5752 /* TC0.CTRLGCLR bit masks and bit positions */
5753 #define TC0_CCDBV_bm 0x10 /* Compare or Capture D Buffer Valid bit mask. */
5754 #define TC0_CCDBV_bp 4 /* Compare or Capture D Buffer Valid bit position. */
5755 
5756 #define TC0_CCCBV_bm 0x08 /* Compare or Capture C Buffer Valid bit mask. */
5757 #define TC0_CCCBV_bp 3 /* Compare or Capture C Buffer Valid bit position. */
5758 
5759 #define TC0_CCBBV_bm 0x04 /* Compare or Capture B Buffer Valid bit mask. */
5760 #define TC0_CCBBV_bp 2 /* Compare or Capture B Buffer Valid bit position. */
5761 
5762 #define TC0_CCABV_bm 0x02 /* Compare or Capture A Buffer Valid bit mask. */
5763 #define TC0_CCABV_bp 1 /* Compare or Capture A Buffer Valid bit position. */
5764 
5765 #define TC0_PERBV_bm 0x01 /* Period Buffer Valid bit mask. */
5766 #define TC0_PERBV_bp 0 /* Period Buffer Valid bit position. */
5767 
5768 
5769 /* TC0.CTRLGSET bit masks and bit positions */
5770 /* TC0_CCDBV_bm Predefined. */
5771 /* TC0_CCDBV_bp Predefined. */
5772 
5773 /* TC0_CCCBV_bm Predefined. */
5774 /* TC0_CCCBV_bp Predefined. */
5775 
5776 /* TC0_CCBBV_bm Predefined. */
5777 /* TC0_CCBBV_bp Predefined. */
5778 
5779 /* TC0_CCABV_bm Predefined. */
5780 /* TC0_CCABV_bp Predefined. */
5781 
5782 /* TC0_PERBV_bm Predefined. */
5783 /* TC0_PERBV_bp Predefined. */
5784 
5785 
5786 /* TC0.INTFLAGS bit masks and bit positions */
5787 #define TC0_CCDIF_bm 0x80 /* Compare or Capture D Interrupt Flag bit mask. */
5788 #define TC0_CCDIF_bp 7 /* Compare or Capture D Interrupt Flag bit position. */
5789 
5790 #define TC0_CCCIF_bm 0x40 /* Compare or Capture C Interrupt Flag bit mask. */
5791 #define TC0_CCCIF_bp 6 /* Compare or Capture C Interrupt Flag bit position. */
5792 
5793 #define TC0_CCBIF_bm 0x20 /* Compare or Capture B Interrupt Flag bit mask. */
5794 #define TC0_CCBIF_bp 5 /* Compare or Capture B Interrupt Flag bit position. */
5795 
5796 #define TC0_CCAIF_bm 0x10 /* Compare or Capture A Interrupt Flag bit mask. */
5797 #define TC0_CCAIF_bp 4 /* Compare or Capture A Interrupt Flag bit position. */
5798 
5799 #define TC0_ERRIF_bm 0x02 /* Error Interrupt Flag bit mask. */
5800 #define TC0_ERRIF_bp 1 /* Error Interrupt Flag bit position. */
5801 
5802 #define TC0_OVFIF_bm 0x01 /* Overflow Interrupt Flag bit mask. */
5803 #define TC0_OVFIF_bp 0 /* Overflow Interrupt Flag bit position. */
5804 
5805 
5806 /* TC1.CTRLA bit masks and bit positions */
5807 #define TC1_CLKSEL_gm 0x0F /* Clock Selection group mask. */
5808 #define TC1_CLKSEL_gp 0 /* Clock Selection group position. */
5809 #define TC1_CLKSEL0_bm (1<<0) /* Clock Selection bit 0 mask. */
5810 #define TC1_CLKSEL0_bp 0 /* Clock Selection bit 0 position. */
5811 #define TC1_CLKSEL1_bm (1<<1) /* Clock Selection bit 1 mask. */
5812 #define TC1_CLKSEL1_bp 1 /* Clock Selection bit 1 position. */
5813 #define TC1_CLKSEL2_bm (1<<2) /* Clock Selection bit 2 mask. */
5814 #define TC1_CLKSEL2_bp 2 /* Clock Selection bit 2 position. */
5815 #define TC1_CLKSEL3_bm (1<<3) /* Clock Selection bit 3 mask. */
5816 #define TC1_CLKSEL3_bp 3 /* Clock Selection bit 3 position. */
5817 
5818 
5819 /* TC1.CTRLB bit masks and bit positions */
5820 #define TC1_CCBEN_bm 0x20 /* Compare or Capture B Enable bit mask. */
5821 #define TC1_CCBEN_bp 5 /* Compare or Capture B Enable bit position. */
5822 
5823 #define TC1_CCAEN_bm 0x10 /* Compare or Capture A Enable bit mask. */
5824 #define TC1_CCAEN_bp 4 /* Compare or Capture A Enable bit position. */
5825 
5826 #define TC1_WGMODE_gm 0x07 /* Waveform generation mode group mask. */
5827 #define TC1_WGMODE_gp 0 /* Waveform generation mode group position. */
5828 #define TC1_WGMODE0_bm (1<<0) /* Waveform generation mode bit 0 mask. */
5829 #define TC1_WGMODE0_bp 0 /* Waveform generation mode bit 0 position. */
5830 #define TC1_WGMODE1_bm (1<<1) /* Waveform generation mode bit 1 mask. */
5831 #define TC1_WGMODE1_bp 1 /* Waveform generation mode bit 1 position. */
5832 #define TC1_WGMODE2_bm (1<<2) /* Waveform generation mode bit 2 mask. */
5833 #define TC1_WGMODE2_bp 2 /* Waveform generation mode bit 2 position. */
5834 
5835 
5836 /* TC1.CTRLC bit masks and bit positions */
5837 #define TC1_CMPB_bm 0x02 /* Compare B Output Value bit mask. */
5838 #define TC1_CMPB_bp 1 /* Compare B Output Value bit position. */
5839 
5840 #define TC1_CMPA_bm 0x01 /* Compare A Output Value bit mask. */
5841 #define TC1_CMPA_bp 0 /* Compare A Output Value bit position. */
5842 
5843 
5844 /* TC1.CTRLD bit masks and bit positions */
5845 #define TC1_EVACT_gm 0xE0 /* Event Action group mask. */
5846 #define TC1_EVACT_gp 5 /* Event Action group position. */
5847 #define TC1_EVACT0_bm (1<<5) /* Event Action bit 0 mask. */
5848 #define TC1_EVACT0_bp 5 /* Event Action bit 0 position. */
5849 #define TC1_EVACT1_bm (1<<6) /* Event Action bit 1 mask. */
5850 #define TC1_EVACT1_bp 6 /* Event Action bit 1 position. */
5851 #define TC1_EVACT2_bm (1<<7) /* Event Action bit 2 mask. */
5852 #define TC1_EVACT2_bp 7 /* Event Action bit 2 position. */
5853 
5854 #define TC1_EVDLY_bm 0x10 /* Event Delay bit mask. */
5855 #define TC1_EVDLY_bp 4 /* Event Delay bit position. */
5856 
5857 #define TC1_EVSEL_gm 0x0F /* Event Source Select group mask. */
5858 #define TC1_EVSEL_gp 0 /* Event Source Select group position. */
5859 #define TC1_EVSEL0_bm (1<<0) /* Event Source Select bit 0 mask. */
5860 #define TC1_EVSEL0_bp 0 /* Event Source Select bit 0 position. */
5861 #define TC1_EVSEL1_bm (1<<1) /* Event Source Select bit 1 mask. */
5862 #define TC1_EVSEL1_bp 1 /* Event Source Select bit 1 position. */
5863 #define TC1_EVSEL2_bm (1<<2) /* Event Source Select bit 2 mask. */
5864 #define TC1_EVSEL2_bp 2 /* Event Source Select bit 2 position. */
5865 #define TC1_EVSEL3_bm (1<<3) /* Event Source Select bit 3 mask. */
5866 #define TC1_EVSEL3_bp 3 /* Event Source Select bit 3 position. */
5867 
5868 
5869 /* TC1.CTRLE bit masks and bit positions */
5870 #define TC1_DTHM_bm 0x02 /* Dead Time Hold Mode bit mask. */
5871 #define TC1_DTHM_bp 1 /* Dead Time Hold Mode bit position. */
5872 
5873 #define TC1_BYTEM_bm 0x01 /* Byte Mode bit mask. */
5874 #define TC1_BYTEM_bp 0 /* Byte Mode bit position. */
5875 
5876 
5877 /* TC1.INTCTRLA bit masks and bit positions */
5878 #define TC1_ERRINTLVL_gm 0x0C /* Error Interrupt Level group mask. */
5879 #define TC1_ERRINTLVL_gp 2 /* Error Interrupt Level group position. */
5880 #define TC1_ERRINTLVL0_bm (1<<2) /* Error Interrupt Level bit 0 mask. */
5881 #define TC1_ERRINTLVL0_bp 2 /* Error Interrupt Level bit 0 position. */
5882 #define TC1_ERRINTLVL1_bm (1<<3) /* Error Interrupt Level bit 1 mask. */
5883 #define TC1_ERRINTLVL1_bp 3 /* Error Interrupt Level bit 1 position. */
5884 
5885 #define TC1_OVFINTLVL_gm 0x03 /* Overflow interrupt level group mask. */
5886 #define TC1_OVFINTLVL_gp 0 /* Overflow interrupt level group position. */
5887 #define TC1_OVFINTLVL0_bm (1<<0) /* Overflow interrupt level bit 0 mask. */
5888 #define TC1_OVFINTLVL0_bp 0 /* Overflow interrupt level bit 0 position. */
5889 #define TC1_OVFINTLVL1_bm (1<<1) /* Overflow interrupt level bit 1 mask. */
5890 #define TC1_OVFINTLVL1_bp 1 /* Overflow interrupt level bit 1 position. */
5891 
5892 
5893 /* TC1.INTCTRLB bit masks and bit positions */
5894 #define TC1_CCBINTLVL_gm 0x0C /* Compare or Capture B Interrupt Level group mask. */
5895 #define TC1_CCBINTLVL_gp 2 /* Compare or Capture B Interrupt Level group position. */
5896 #define TC1_CCBINTLVL0_bm (1<<2) /* Compare or Capture B Interrupt Level bit 0 mask. */
5897 #define TC1_CCBINTLVL0_bp 2 /* Compare or Capture B Interrupt Level bit 0 position. */
5898 #define TC1_CCBINTLVL1_bm (1<<3) /* Compare or Capture B Interrupt Level bit 1 mask. */
5899 #define TC1_CCBINTLVL1_bp 3 /* Compare or Capture B Interrupt Level bit 1 position. */
5900 
5901 #define TC1_CCAINTLVL_gm 0x03 /* Compare or Capture A Interrupt Level group mask. */
5902 #define TC1_CCAINTLVL_gp 0 /* Compare or Capture A Interrupt Level group position. */
5903 #define TC1_CCAINTLVL0_bm (1<<0) /* Compare or Capture A Interrupt Level bit 0 mask. */
5904 #define TC1_CCAINTLVL0_bp 0 /* Compare or Capture A Interrupt Level bit 0 position. */
5905 #define TC1_CCAINTLVL1_bm (1<<1) /* Compare or Capture A Interrupt Level bit 1 mask. */
5906 #define TC1_CCAINTLVL1_bp 1 /* Compare or Capture A Interrupt Level bit 1 position. */
5907 
5908 
5909 /* TC1.CTRLFCLR bit masks and bit positions */
5910 #define TC1_CMD_gm 0x0C /* Command group mask. */
5911 #define TC1_CMD_gp 2 /* Command group position. */
5912 #define TC1_CMD0_bm (1<<2) /* Command bit 0 mask. */
5913 #define TC1_CMD0_bp 2 /* Command bit 0 position. */
5914 #define TC1_CMD1_bm (1<<3) /* Command bit 1 mask. */
5915 #define TC1_CMD1_bp 3 /* Command bit 1 position. */
5916 
5917 #define TC1_LUPD_bm 0x02 /* Lock Update bit mask. */
5918 #define TC1_LUPD_bp 1 /* Lock Update bit position. */
5919 
5920 #define TC1_DIR_bm 0x01 /* Direction bit mask. */
5921 #define TC1_DIR_bp 0 /* Direction bit position. */
5922 
5923 
5924 /* TC1.CTRLFSET bit masks and bit positions */
5925 /* TC1_CMD_gm Predefined. */
5926 /* TC1_CMD_gp Predefined. */
5927 /* TC1_CMD0_bm Predefined. */
5928 /* TC1_CMD0_bp Predefined. */
5929 /* TC1_CMD1_bm Predefined. */
5930 /* TC1_CMD1_bp Predefined. */
5931 
5932 /* TC1_LUPD_bm Predefined. */
5933 /* TC1_LUPD_bp Predefined. */
5934 
5935 /* TC1_DIR_bm Predefined. */
5936 /* TC1_DIR_bp Predefined. */
5937 
5938 
5939 /* TC1.CTRLGCLR bit masks and bit positions */
5940 #define TC1_CCBBV_bm 0x04 /* Compare or Capture B Buffer Valid bit mask. */
5941 #define TC1_CCBBV_bp 2 /* Compare or Capture B Buffer Valid bit position. */
5942 
5943 #define TC1_CCABV_bm 0x02 /* Compare or Capture A Buffer Valid bit mask. */
5944 #define TC1_CCABV_bp 1 /* Compare or Capture A Buffer Valid bit position. */
5945 
5946 #define TC1_PERBV_bm 0x01 /* Period Buffer Valid bit mask. */
5947 #define TC1_PERBV_bp 0 /* Period Buffer Valid bit position. */
5948 
5949 
5950 /* TC1.CTRLGSET bit masks and bit positions */
5951 /* TC1_CCBBV_bm Predefined. */
5952 /* TC1_CCBBV_bp Predefined. */
5953 
5954 /* TC1_CCABV_bm Predefined. */
5955 /* TC1_CCABV_bp Predefined. */
5956 
5957 /* TC1_PERBV_bm Predefined. */
5958 /* TC1_PERBV_bp Predefined. */
5959 
5960 
5961 /* TC1.INTFLAGS bit masks and bit positions */
5962 #define TC1_CCBIF_bm 0x20 /* Compare or Capture B Interrupt Flag bit mask. */
5963 #define TC1_CCBIF_bp 5 /* Compare or Capture B Interrupt Flag bit position. */
5964 
5965 #define TC1_CCAIF_bm 0x10 /* Compare or Capture A Interrupt Flag bit mask. */
5966 #define TC1_CCAIF_bp 4 /* Compare or Capture A Interrupt Flag bit position. */
5967 
5968 #define TC1_ERRIF_bm 0x02 /* Error Interrupt Flag bit mask. */
5969 #define TC1_ERRIF_bp 1 /* Error Interrupt Flag bit position. */
5970 
5971 #define TC1_OVFIF_bm 0x01 /* Overflow Interrupt Flag bit mask. */
5972 #define TC1_OVFIF_bp 0 /* Overflow Interrupt Flag bit position. */
5973 
5974 
5975 /* AWEX.CTRL bit masks and bit positions */
5976 #define AWEX_PGM_bm 0x20 /* Pattern Generation Mode bit mask. */
5977 #define AWEX_PGM_bp 5 /* Pattern Generation Mode bit position. */
5978 
5979 #define AWEX_CWCM_bm 0x10 /* Common Waveform Channel Mode bit mask. */
5980 #define AWEX_CWCM_bp 4 /* Common Waveform Channel Mode bit position. */
5981 
5982 #define AWEX_DTICCDEN_bm 0x08 /* Dead Time Insertion Compare Channel D Enable bit mask. */
5983 #define AWEX_DTICCDEN_bp 3 /* Dead Time Insertion Compare Channel D Enable bit position. */
5984 
5985 #define AWEX_DTICCCEN_bm 0x04 /* Dead Time Insertion Compare Channel C Enable bit mask. */
5986 #define AWEX_DTICCCEN_bp 2 /* Dead Time Insertion Compare Channel C Enable bit position. */
5987 
5988 #define AWEX_DTICCBEN_bm 0x02 /* Dead Time Insertion Compare Channel B Enable bit mask. */
5989 #define AWEX_DTICCBEN_bp 1 /* Dead Time Insertion Compare Channel B Enable bit position. */
5990 
5991 #define AWEX_DTICCAEN_bm 0x01 /* Dead Time Insertion Compare Channel A Enable bit mask. */
5992 #define AWEX_DTICCAEN_bp 0 /* Dead Time Insertion Compare Channel A Enable bit position. */
5993 
5994 
5995 /* AWEX.FDCTRL bit masks and bit positions */
5996 #define AWEX_FDDBD_bm 0x10 /* Fault Detect on Disable Break Disable bit mask. */
5997 #define AWEX_FDDBD_bp 4 /* Fault Detect on Disable Break Disable bit position. */
5998 
5999 #define AWEX_FDMODE_bm 0x04 /* Fault Detect Mode bit mask. */
6000 #define AWEX_FDMODE_bp 2 /* Fault Detect Mode bit position. */
6001 
6002 #define AWEX_FDACT_gm 0x03 /* Fault Detect Action group mask. */
6003 #define AWEX_FDACT_gp 0 /* Fault Detect Action group position. */
6004 #define AWEX_FDACT0_bm (1<<0) /* Fault Detect Action bit 0 mask. */
6005 #define AWEX_FDACT0_bp 0 /* Fault Detect Action bit 0 position. */
6006 #define AWEX_FDACT1_bm (1<<1) /* Fault Detect Action bit 1 mask. */
6007 #define AWEX_FDACT1_bp 1 /* Fault Detect Action bit 1 position. */
6008 
6009 
6010 /* AWEX.STATUS bit masks and bit positions */
6011 #define AWEX_FDF_bm 0x04 /* Fault Detect Flag bit mask. */
6012 #define AWEX_FDF_bp 2 /* Fault Detect Flag bit position. */
6013 
6014 #define AWEX_DTHSBUFV_bm 0x02 /* Dead Time High Side Buffer Valid bit mask. */
6015 #define AWEX_DTHSBUFV_bp 1 /* Dead Time High Side Buffer Valid bit position. */
6016 
6017 #define AWEX_DTLSBUFV_bm 0x01 /* Dead Time Low Side Buffer Valid bit mask. */
6018 #define AWEX_DTLSBUFV_bp 0 /* Dead Time Low Side Buffer Valid bit position. */
6019 
6020 
6021 /* HIRES.CTRL bit masks and bit positions */
6022 #define HIRES_HREN_gm 0x03 /* High Resolution Enable group mask. */
6023 #define HIRES_HREN_gp 0 /* High Resolution Enable group position. */
6024 #define HIRES_HREN0_bm (1<<0) /* High Resolution Enable bit 0 mask. */
6025 #define HIRES_HREN0_bp 0 /* High Resolution Enable bit 0 position. */
6026 #define HIRES_HREN1_bm (1<<1) /* High Resolution Enable bit 1 mask. */
6027 #define HIRES_HREN1_bp 1 /* High Resolution Enable bit 1 position. */
6028 
6029 
6030 /* USART - Universal Asynchronous Receiver-Transmitter */
6031 /* USART.STATUS bit masks and bit positions */
6032 #define USART_RXCIF_bm 0x80 /* Receive Interrupt Flag bit mask. */
6033 #define USART_RXCIF_bp 7 /* Receive Interrupt Flag bit position. */
6034 
6035 #define USART_TXCIF_bm 0x40 /* Transmit Interrupt Flag bit mask. */
6036 #define USART_TXCIF_bp 6 /* Transmit Interrupt Flag bit position. */
6037 
6038 #define USART_DREIF_bm 0x20 /* Data Register Empty Flag bit mask. */
6039 #define USART_DREIF_bp 5 /* Data Register Empty Flag bit position. */
6040 
6041 #define USART_FERR_bm 0x10 /* Frame Error bit mask. */
6042 #define USART_FERR_bp 4 /* Frame Error bit position. */
6043 
6044 #define USART_BUFOVF_bm 0x08 /* Buffer Overflow bit mask. */
6045 #define USART_BUFOVF_bp 3 /* Buffer Overflow bit position. */
6046 
6047 #define USART_PERR_bm 0x04 /* Parity Error bit mask. */
6048 #define USART_PERR_bp 2 /* Parity Error bit position. */
6049 
6050 #define USART_RXB8_bm 0x01 /* Receive Bit 8 bit mask. */
6051 #define USART_RXB8_bp 0 /* Receive Bit 8 bit position. */
6052 
6053 
6054 /* USART.CTRLA bit masks and bit positions */
6055 #define USART_RXCINTLVL_gm 0x30 /* Receive Interrupt Level group mask. */
6056 #define USART_RXCINTLVL_gp 4 /* Receive Interrupt Level group position. */
6057 #define USART_RXCINTLVL0_bm (1<<4) /* Receive Interrupt Level bit 0 mask. */
6058 #define USART_RXCINTLVL0_bp 4 /* Receive Interrupt Level bit 0 position. */
6059 #define USART_RXCINTLVL1_bm (1<<5) /* Receive Interrupt Level bit 1 mask. */
6060 #define USART_RXCINTLVL1_bp 5 /* Receive Interrupt Level bit 1 position. */
6061 
6062 #define USART_TXCINTLVL_gm 0x0C /* Transmit Interrupt Level group mask. */
6063 #define USART_TXCINTLVL_gp 2 /* Transmit Interrupt Level group position. */
6064 #define USART_TXCINTLVL0_bm (1<<2) /* Transmit Interrupt Level bit 0 mask. */
6065 #define USART_TXCINTLVL0_bp 2 /* Transmit Interrupt Level bit 0 position. */
6066 #define USART_TXCINTLVL1_bm (1<<3) /* Transmit Interrupt Level bit 1 mask. */
6067 #define USART_TXCINTLVL1_bp 3 /* Transmit Interrupt Level bit 1 position. */
6068 
6069 #define USART_DREINTLVL_gm 0x03 /* Data Register Empty Interrupt Level group mask. */
6070 #define USART_DREINTLVL_gp 0 /* Data Register Empty Interrupt Level group position. */
6071 #define USART_DREINTLVL0_bm (1<<0) /* Data Register Empty Interrupt Level bit 0 mask. */
6072 #define USART_DREINTLVL0_bp 0 /* Data Register Empty Interrupt Level bit 0 position. */
6073 #define USART_DREINTLVL1_bm (1<<1) /* Data Register Empty Interrupt Level bit 1 mask. */
6074 #define USART_DREINTLVL1_bp 1 /* Data Register Empty Interrupt Level bit 1 position. */
6075 
6076 
6077 /* USART.CTRLB bit masks and bit positions */
6078 #define USART_RXEN_bm 0x10 /* Receiver Enable bit mask. */
6079 #define USART_RXEN_bp 4 /* Receiver Enable bit position. */
6080 
6081 #define USART_TXEN_bm 0x08 /* Transmitter Enable bit mask. */
6082 #define USART_TXEN_bp 3 /* Transmitter Enable bit position. */
6083 
6084 #define USART_CLK2X_bm 0x04 /* Double transmission speed bit mask. */
6085 #define USART_CLK2X_bp 2 /* Double transmission speed bit position. */
6086 
6087 #define USART_MPCM_bm 0x02 /* Multi-processor Communication Mode bit mask. */
6088 #define USART_MPCM_bp 1 /* Multi-processor Communication Mode bit position. */
6089 
6090 #define USART_TXB8_bm 0x01 /* Transmit bit 8 bit mask. */
6091 #define USART_TXB8_bp 0 /* Transmit bit 8 bit position. */
6092 
6093 
6094 /* USART.CTRLC bit masks and bit positions */
6095 #define USART_CMODE_gm 0xC0 /* Communication Mode group mask. */
6096 #define USART_CMODE_gp 6 /* Communication Mode group position. */
6097 #define USART_CMODE0_bm (1<<6) /* Communication Mode bit 0 mask. */
6098 #define USART_CMODE0_bp 6 /* Communication Mode bit 0 position. */
6099 #define USART_CMODE1_bm (1<<7) /* Communication Mode bit 1 mask. */
6100 #define USART_CMODE1_bp 7 /* Communication Mode bit 1 position. */
6101 
6102 #define USART_PMODE_gm 0x30 /* Parity Mode group mask. */
6103 #define USART_PMODE_gp 4 /* Parity Mode group position. */
6104 #define USART_PMODE0_bm (1<<4) /* Parity Mode bit 0 mask. */
6105 #define USART_PMODE0_bp 4 /* Parity Mode bit 0 position. */
6106 #define USART_PMODE1_bm (1<<5) /* Parity Mode bit 1 mask. */
6107 #define USART_PMODE1_bp 5 /* Parity Mode bit 1 position. */
6108 
6109 #define USART_SBMODE_bm 0x08 /* Stop Bit Mode bit mask. */
6110 #define USART_SBMODE_bp 3 /* Stop Bit Mode bit position. */
6111 
6112 #define USART_CHSIZE_gm 0x07 /* Character Size group mask. */
6113 #define USART_CHSIZE_gp 0 /* Character Size group position. */
6114 #define USART_CHSIZE0_bm (1<<0) /* Character Size bit 0 mask. */
6115 #define USART_CHSIZE0_bp 0 /* Character Size bit 0 position. */
6116 #define USART_CHSIZE1_bm (1<<1) /* Character Size bit 1 mask. */
6117 #define USART_CHSIZE1_bp 1 /* Character Size bit 1 position. */
6118 #define USART_CHSIZE2_bm (1<<2) /* Character Size bit 2 mask. */
6119 #define USART_CHSIZE2_bp 2 /* Character Size bit 2 position. */
6120 
6121 
6122 /* USART.BAUDCTRLA bit masks and bit positions */
6123 #define USART_BSEL_gm 0xFF /* Baud Rate Selection Bits [7:0] group mask. */
6124 #define USART_BSEL_gp 0 /* Baud Rate Selection Bits [7:0] group position. */
6125 #define USART_BSEL0_bm (1<<0) /* Baud Rate Selection Bits [7:0] bit 0 mask. */
6126 #define USART_BSEL0_bp 0 /* Baud Rate Selection Bits [7:0] bit 0 position. */
6127 #define USART_BSEL1_bm (1<<1) /* Baud Rate Selection Bits [7:0] bit 1 mask. */
6128 #define USART_BSEL1_bp 1 /* Baud Rate Selection Bits [7:0] bit 1 position. */
6129 #define USART_BSEL2_bm (1<<2) /* Baud Rate Selection Bits [7:0] bit 2 mask. */
6130 #define USART_BSEL2_bp 2 /* Baud Rate Selection Bits [7:0] bit 2 position. */
6131 #define USART_BSEL3_bm (1<<3) /* Baud Rate Selection Bits [7:0] bit 3 mask. */
6132 #define USART_BSEL3_bp 3 /* Baud Rate Selection Bits [7:0] bit 3 position. */
6133 #define USART_BSEL4_bm (1<<4) /* Baud Rate Selection Bits [7:0] bit 4 mask. */
6134 #define USART_BSEL4_bp 4 /* Baud Rate Selection Bits [7:0] bit 4 position. */
6135 #define USART_BSEL5_bm (1<<5) /* Baud Rate Selection Bits [7:0] bit 5 mask. */
6136 #define USART_BSEL5_bp 5 /* Baud Rate Selection Bits [7:0] bit 5 position. */
6137 #define USART_BSEL6_bm (1<<6) /* Baud Rate Selection Bits [7:0] bit 6 mask. */
6138 #define USART_BSEL6_bp 6 /* Baud Rate Selection Bits [7:0] bit 6 position. */
6139 #define USART_BSEL7_bm (1<<7) /* Baud Rate Selection Bits [7:0] bit 7 mask. */
6140 #define USART_BSEL7_bp 7 /* Baud Rate Selection Bits [7:0] bit 7 position. */
6141 
6142 
6143 /* USART.BAUDCTRLB bit masks and bit positions */
6144 #define USART_BSCALE_gm 0xF0 /* Baud Rate Scale group mask. */
6145 #define USART_BSCALE_gp 4 /* Baud Rate Scale group position. */
6146 #define USART_BSCALE0_bm (1<<4) /* Baud Rate Scale bit 0 mask. */
6147 #define USART_BSCALE0_bp 4 /* Baud Rate Scale bit 0 position. */
6148 #define USART_BSCALE1_bm (1<<5) /* Baud Rate Scale bit 1 mask. */
6149 #define USART_BSCALE1_bp 5 /* Baud Rate Scale bit 1 position. */
6150 #define USART_BSCALE2_bm (1<<6) /* Baud Rate Scale bit 2 mask. */
6151 #define USART_BSCALE2_bp 6 /* Baud Rate Scale bit 2 position. */
6152 #define USART_BSCALE3_bm (1<<7) /* Baud Rate Scale bit 3 mask. */
6153 #define USART_BSCALE3_bp 7 /* Baud Rate Scale bit 3 position. */
6154 
6155 /* USART_BSEL_gm Predefined. */
6156 /* USART_BSEL_gp Predefined. */
6157 /* USART_BSEL0_bm Predefined. */
6158 /* USART_BSEL0_bp Predefined. */
6159 /* USART_BSEL1_bm Predefined. */
6160 /* USART_BSEL1_bp Predefined. */
6161 /* USART_BSEL2_bm Predefined. */
6162 /* USART_BSEL2_bp Predefined. */
6163 /* USART_BSEL3_bm Predefined. */
6164 /* USART_BSEL3_bp Predefined. */
6165 
6166 
6167 /* SPI - Serial Peripheral Interface */
6168 /* SPI.CTRL bit masks and bit positions */
6169 #define SPI_CLK2X_bm 0x80 /* Enable Double Speed bit mask. */
6170 #define SPI_CLK2X_bp 7 /* Enable Double Speed bit position. */
6171 
6172 #define SPI_ENABLE_bm 0x40 /* Enable Module bit mask. */
6173 #define SPI_ENABLE_bp 6 /* Enable Module bit position. */
6174 
6175 #define SPI_DORD_bm 0x20 /* Data Order Setting bit mask. */
6176 #define SPI_DORD_bp 5 /* Data Order Setting bit position. */
6177 
6178 #define SPI_MASTER_bm 0x10 /* Master Operation Enable bit mask. */
6179 #define SPI_MASTER_bp 4 /* Master Operation Enable bit position. */
6180 
6181 #define SPI_MODE_gm 0x0C /* SPI Mode group mask. */
6182 #define SPI_MODE_gp 2 /* SPI Mode group position. */
6183 #define SPI_MODE0_bm (1<<2) /* SPI Mode bit 0 mask. */
6184 #define SPI_MODE0_bp 2 /* SPI Mode bit 0 position. */
6185 #define SPI_MODE1_bm (1<<3) /* SPI Mode bit 1 mask. */
6186 #define SPI_MODE1_bp 3 /* SPI Mode bit 1 position. */
6187 
6188 #define SPI_PRESCALER_gm 0x03 /* Prescaler group mask. */
6189 #define SPI_PRESCALER_gp 0 /* Prescaler group position. */
6190 #define SPI_PRESCALER0_bm (1<<0) /* Prescaler bit 0 mask. */
6191 #define SPI_PRESCALER0_bp 0 /* Prescaler bit 0 position. */
6192 #define SPI_PRESCALER1_bm (1<<1) /* Prescaler bit 1 mask. */
6193 #define SPI_PRESCALER1_bp 1 /* Prescaler bit 1 position. */
6194 
6195 
6196 /* SPI.INTCTRL bit masks and bit positions */
6197 #define SPI_INTLVL_gm 0x03 /* Interrupt level group mask. */
6198 #define SPI_INTLVL_gp 0 /* Interrupt level group position. */
6199 #define SPI_INTLVL0_bm (1<<0) /* Interrupt level bit 0 mask. */
6200 #define SPI_INTLVL0_bp 0 /* Interrupt level bit 0 position. */
6201 #define SPI_INTLVL1_bm (1<<1) /* Interrupt level bit 1 mask. */
6202 #define SPI_INTLVL1_bp 1 /* Interrupt level bit 1 position. */
6203 
6204 
6205 /* SPI.STATUS bit masks and bit positions */
6206 #define SPI_IF_bm 0x80 /* Interrupt Flag bit mask. */
6207 #define SPI_IF_bp 7 /* Interrupt Flag bit position. */
6208 
6209 #define SPI_WRCOL_bm 0x40 /* Write Collision bit mask. */
6210 #define SPI_WRCOL_bp 6 /* Write Collision bit position. */
6211 
6212 
6213 /* IRCOM - IR Communication Module */
6214 /* IRCOM.CTRL bit masks and bit positions */
6215 #define IRCOM_EVSEL_gm 0x0F /* Event Channel Select group mask. */
6216 #define IRCOM_EVSEL_gp 0 /* Event Channel Select group position. */
6217 #define IRCOM_EVSEL0_bm (1<<0) /* Event Channel Select bit 0 mask. */
6218 #define IRCOM_EVSEL0_bp 0 /* Event Channel Select bit 0 position. */
6219 #define IRCOM_EVSEL1_bm (1<<1) /* Event Channel Select bit 1 mask. */
6220 #define IRCOM_EVSEL1_bp 1 /* Event Channel Select bit 1 position. */
6221 #define IRCOM_EVSEL2_bm (1<<2) /* Event Channel Select bit 2 mask. */
6222 #define IRCOM_EVSEL2_bp 2 /* Event Channel Select bit 2 position. */
6223 #define IRCOM_EVSEL3_bm (1<<3) /* Event Channel Select bit 3 mask. */
6224 #define IRCOM_EVSEL3_bp 3 /* Event Channel Select bit 3 position. */
6225 
6226 
6227 /* AES - AES Module */
6228 /* AES.CTRL bit masks and bit positions */
6229 #define AES_START_bm 0x80 /* Start/Run bit mask. */
6230 #define AES_START_bp 7 /* Start/Run bit position. */
6231 
6232 #define AES_AUTO_bm 0x40 /* Auto Start Trigger bit mask. */
6233 #define AES_AUTO_bp 6 /* Auto Start Trigger bit position. */
6234 
6235 #define AES_RESET_bm 0x20 /* AES Software Reset bit mask. */
6236 #define AES_RESET_bp 5 /* AES Software Reset bit position. */
6237 
6238 #define AES_DECRYPT_bm 0x10 /* Decryption / Direction bit mask. */
6239 #define AES_DECRYPT_bp 4 /* Decryption / Direction bit position. */
6240 
6241 #define AES_XOR_bm 0x04 /* State XOR Load Enable bit mask. */
6242 #define AES_XOR_bp 2 /* State XOR Load Enable bit position. */
6243 
6244 
6245 /* AES.STATUS bit masks and bit positions */
6246 #define AES_ERROR_bm 0x80 /* AES Error bit mask. */
6247 #define AES_ERROR_bp 7 /* AES Error bit position. */
6248 
6249 #define AES_SRIF_bm 0x01 /* State Ready Interrupt Flag bit mask. */
6250 #define AES_SRIF_bp 0 /* State Ready Interrupt Flag bit position. */
6251 
6252 
6253 /* AES.INTCTRL bit masks and bit positions */
6254 #define AES_INTLVL_gm 0x03 /* Interrupt level group mask. */
6255 #define AES_INTLVL_gp 0 /* Interrupt level group position. */
6256 #define AES_INTLVL0_bm (1<<0) /* Interrupt level bit 0 mask. */
6257 #define AES_INTLVL0_bp 0 /* Interrupt level bit 0 position. */
6258 #define AES_INTLVL1_bm (1<<1) /* Interrupt level bit 1 mask. */
6259 #define AES_INTLVL1_bp 1 /* Interrupt level bit 1 position. */
6260 
6261 
6262 
6263 // Generic Port Pins
6264 
6265 #define PIN0_bm 0x01
6266 #define PIN0_bp 0
6267 #define PIN1_bm 0x02
6268 #define PIN1_bp 1
6269 #define PIN2_bm 0x04
6270 #define PIN2_bp 2
6271 #define PIN3_bm 0x08
6272 #define PIN3_bp 3
6273 #define PIN4_bm 0x10
6274 #define PIN4_bp 4
6275 #define PIN5_bm 0x20
6276 #define PIN5_bp 5
6277 #define PIN6_bm 0x40
6278 #define PIN6_bp 6
6279 #define PIN7_bm 0x80
6280 #define PIN7_bp 7
6281 
6282 
6283 /* ========== Interrupt Vector Definitions ========== */
6284 /* Vector 0 is the reset vector */
6285 
6286 /* OSC interrupt vectors */
6287 #define OSC_XOSCF_vect_num 1
6288 #define OSC_XOSCF_vect _VECTOR(1) /* External Oscillator Failure Interrupt (NMI) */
6289 
6290 /* PORTC interrupt vectors */
6291 #define PORTC_INT0_vect_num 2
6292 #define PORTC_INT0_vect _VECTOR(2) /* External Interrupt 0 */
6293 #define PORTC_INT1_vect_num 3
6294 #define PORTC_INT1_vect _VECTOR(3) /* External Interrupt 1 */
6295 
6296 /* PORTR interrupt vectors */
6297 #define PORTR_INT0_vect_num 4
6298 #define PORTR_INT0_vect _VECTOR(4) /* External Interrupt 0 */
6299 #define PORTR_INT1_vect_num 5
6300 #define PORTR_INT1_vect _VECTOR(5) /* External Interrupt 1 */
6301 
6302 /* DMA interrupt vectors */
6303 #define DMA_CH0_vect_num 6
6304 #define DMA_CH0_vect _VECTOR(6) /* Channel 0 Interrupt */
6305 #define DMA_CH1_vect_num 7
6306 #define DMA_CH1_vect _VECTOR(7) /* Channel 1 Interrupt */
6307 #define DMA_CH2_vect_num 8
6308 #define DMA_CH2_vect _VECTOR(8) /* Channel 2 Interrupt */
6309 #define DMA_CH3_vect_num 9
6310 #define DMA_CH3_vect _VECTOR(9) /* Channel 3 Interrupt */
6311 
6312 /* RTC interrupt vectors */
6313 #define RTC_OVF_vect_num 10
6314 #define RTC_OVF_vect _VECTOR(10) /* Overflow Interrupt */
6315 #define RTC_COMP_vect_num 11
6316 #define RTC_COMP_vect _VECTOR(11) /* Compare Interrupt */
6317 
6318 /* TWIC interrupt vectors */
6319 #define TWIC_TWIS_vect_num 12
6320 #define TWIC_TWIS_vect _VECTOR(12) /* TWI Slave Interrupt */
6321 #define TWIC_TWIM_vect_num 13
6322 #define TWIC_TWIM_vect _VECTOR(13) /* TWI Master Interrupt */
6323 
6324 /* TCC0 interrupt vectors */
6325 #define TCC0_OVF_vect_num 14
6326 #define TCC0_OVF_vect _VECTOR(14) /* Overflow Interrupt */
6327 #define TCC0_ERR_vect_num 15
6328 #define TCC0_ERR_vect _VECTOR(15) /* Error Interrupt */
6329 #define TCC0_CCA_vect_num 16
6330 #define TCC0_CCA_vect _VECTOR(16) /* Compare or Capture A Interrupt */
6331 #define TCC0_CCB_vect_num 17
6332 #define TCC0_CCB_vect _VECTOR(17) /* Compare or Capture B Interrupt */
6333 #define TCC0_CCC_vect_num 18
6334 #define TCC0_CCC_vect _VECTOR(18) /* Compare or Capture C Interrupt */
6335 #define TCC0_CCD_vect_num 19
6336 #define TCC0_CCD_vect _VECTOR(19) /* Compare or Capture D Interrupt */
6337 
6338 /* TCC1 interrupt vectors */
6339 #define TCC1_OVF_vect_num 20
6340 #define TCC1_OVF_vect _VECTOR(20) /* Overflow Interrupt */
6341 #define TCC1_ERR_vect_num 21
6342 #define TCC1_ERR_vect _VECTOR(21) /* Error Interrupt */
6343 #define TCC1_CCA_vect_num 22
6344 #define TCC1_CCA_vect _VECTOR(22) /* Compare or Capture A Interrupt */
6345 #define TCC1_CCB_vect_num 23
6346 #define TCC1_CCB_vect _VECTOR(23) /* Compare or Capture B Interrupt */
6347 
6348 /* SPIC interrupt vectors */
6349 #define SPIC_INT_vect_num 24
6350 #define SPIC_INT_vect _VECTOR(24) /* SPI Interrupt */
6351 
6352 /* USARTC0 interrupt vectors */
6353 #define USARTC0_RXC_vect_num 25
6354 #define USARTC0_RXC_vect _VECTOR(25) /* Reception Complete Interrupt */
6355 #define USARTC0_DRE_vect_num 26
6356 #define USARTC0_DRE_vect _VECTOR(26) /* Data Register Empty Interrupt */
6357 #define USARTC0_TXC_vect_num 27
6358 #define USARTC0_TXC_vect _VECTOR(27) /* Transmission Complete Interrupt */
6359 
6360 /* USARTC1 interrupt vectors */
6361 #define USARTC1_RXC_vect_num 28
6362 #define USARTC1_RXC_vect _VECTOR(28) /* Reception Complete Interrupt */
6363 #define USARTC1_DRE_vect_num 29
6364 #define USARTC1_DRE_vect _VECTOR(29) /* Data Register Empty Interrupt */
6365 #define USARTC1_TXC_vect_num 30
6366 #define USARTC1_TXC_vect _VECTOR(30) /* Transmission Complete Interrupt */
6367 
6368 /* AES interrupt vectors */
6369 #define AES_INT_vect_num 31
6370 #define AES_INT_vect _VECTOR(31) /* AES Interrupt */
6371 
6372 /* NVM interrupt vectors */
6373 #define NVM_EE_vect_num 32
6374 #define NVM_EE_vect _VECTOR(32) /* EE Interrupt */
6375 #define NVM_SPM_vect_num 33
6376 #define NVM_SPM_vect _VECTOR(33) /* SPM Interrupt */
6377 
6378 /* PORTB interrupt vectors */
6379 #define PORTB_INT0_vect_num 34
6380 #define PORTB_INT0_vect _VECTOR(34) /* External Interrupt 0 */
6381 #define PORTB_INT1_vect_num 35
6382 #define PORTB_INT1_vect _VECTOR(35) /* External Interrupt 1 */
6383 
6384 /* PORTE interrupt vectors */
6385 #define PORTE_INT0_vect_num 43
6386 #define PORTE_INT0_vect _VECTOR(43) /* External Interrupt 0 */
6387 #define PORTE_INT1_vect_num 44
6388 #define PORTE_INT1_vect _VECTOR(44) /* External Interrupt 1 */
6389 
6390 /* TWIE interrupt vectors */
6391 #define TWIE_TWIS_vect_num 45
6392 #define TWIE_TWIS_vect _VECTOR(45) /* TWI Slave Interrupt */
6393 #define TWIE_TWIM_vect_num 46
6394 #define TWIE_TWIM_vect _VECTOR(46) /* TWI Master Interrupt */
6395 
6396 /* TCE0 interrupt vectors */
6397 #define TCE0_OVF_vect_num 47
6398 #define TCE0_OVF_vect _VECTOR(47) /* Overflow Interrupt */
6399 #define TCE0_ERR_vect_num 48
6400 #define TCE0_ERR_vect _VECTOR(48) /* Error Interrupt */
6401 #define TCE0_CCA_vect_num 49
6402 #define TCE0_CCA_vect _VECTOR(49) /* Compare or Capture A Interrupt */
6403 #define TCE0_CCB_vect_num 50
6404 #define TCE0_CCB_vect _VECTOR(50) /* Compare or Capture B Interrupt */
6405 #define TCE0_CCC_vect_num 51
6406 #define TCE0_CCC_vect _VECTOR(51) /* Compare or Capture C Interrupt */
6407 #define TCE0_CCD_vect_num 52
6408 #define TCE0_CCD_vect _VECTOR(52) /* Compare or Capture D Interrupt */
6409 
6410 /* TCE1 interrupt vectors */
6411 #define TCE1_OVF_vect_num 53
6412 #define TCE1_OVF_vect _VECTOR(53) /* Overflow Interrupt */
6413 #define TCE1_ERR_vect_num 54
6414 #define TCE1_ERR_vect _VECTOR(54) /* Error Interrupt */
6415 #define TCE1_CCA_vect_num 55
6416 #define TCE1_CCA_vect _VECTOR(55) /* Compare or Capture A Interrupt */
6417 #define TCE1_CCB_vect_num 56
6418 #define TCE1_CCB_vect _VECTOR(56) /* Compare or Capture B Interrupt */
6419 
6420 /* USARTE0 interrupt vectors */
6421 #define USARTE0_RXC_vect_num 58
6422 #define USARTE0_RXC_vect _VECTOR(58) /* Reception Complete Interrupt */
6423 #define USARTE0_DRE_vect_num 59
6424 #define USARTE0_DRE_vect _VECTOR(59) /* Data Register Empty Interrupt */
6425 #define USARTE0_TXC_vect_num 60
6426 #define USARTE0_TXC_vect _VECTOR(60) /* Transmission Complete Interrupt */
6427 
6428 /* PORTD interrupt vectors */
6429 #define PORTD_INT0_vect_num 64
6430 #define PORTD_INT0_vect _VECTOR(64) /* External Interrupt 0 */
6431 #define PORTD_INT1_vect_num 65
6432 #define PORTD_INT1_vect _VECTOR(65) /* External Interrupt 1 */
6433 
6434 /* PORTA interrupt vectors */
6435 #define PORTA_INT0_vect_num 66
6436 #define PORTA_INT0_vect _VECTOR(66) /* External Interrupt 0 */
6437 #define PORTA_INT1_vect_num 67
6438 #define PORTA_INT1_vect _VECTOR(67) /* External Interrupt 1 */
6439 
6440 /* ACA interrupt vectors */
6441 #define ACA_AC0_vect_num 68
6442 #define ACA_AC0_vect _VECTOR(68) /* AC0 Interrupt */
6443 #define ACA_AC1_vect_num 69
6444 #define ACA_AC1_vect _VECTOR(69) /* AC1 Interrupt */
6445 #define ACA_ACW_vect_num 70
6446 #define ACA_ACW_vect _VECTOR(70) /* ACW Window Mode Interrupt */
6447 
6448 /* ADCA interrupt vectors */
6449 #define ADCA_CH0_vect_num 71
6450 #define ADCA_CH0_vect _VECTOR(71) /* Interrupt 0 */
6451 #define ADCA_CH1_vect_num 72
6452 #define ADCA_CH1_vect _VECTOR(72) /* Interrupt 1 */
6453 #define ADCA_CH2_vect_num 73
6454 #define ADCA_CH2_vect _VECTOR(73) /* Interrupt 2 */
6455 #define ADCA_CH3_vect_num 74
6456 #define ADCA_CH3_vect _VECTOR(74) /* Interrupt 3 */
6457 
6458 /* TCD0 interrupt vectors */
6459 #define TCD0_OVF_vect_num 77
6460 #define TCD0_OVF_vect _VECTOR(77) /* Overflow Interrupt */
6461 #define TCD0_ERR_vect_num 78
6462 #define TCD0_ERR_vect _VECTOR(78) /* Error Interrupt */
6463 #define TCD0_CCA_vect_num 79
6464 #define TCD0_CCA_vect _VECTOR(79) /* Compare or Capture A Interrupt */
6465 #define TCD0_CCB_vect_num 80
6466 #define TCD0_CCB_vect _VECTOR(80) /* Compare or Capture B Interrupt */
6467 #define TCD0_CCC_vect_num 81
6468 #define TCD0_CCC_vect _VECTOR(81) /* Compare or Capture C Interrupt */
6469 #define TCD0_CCD_vect_num 82
6470 #define TCD0_CCD_vect _VECTOR(82) /* Compare or Capture D Interrupt */
6471 
6472 /* TCD1 interrupt vectors */
6473 #define TCD1_OVF_vect_num 83
6474 #define TCD1_OVF_vect _VECTOR(83) /* Overflow Interrupt */
6475 #define TCD1_ERR_vect_num 84
6476 #define TCD1_ERR_vect _VECTOR(84) /* Error Interrupt */
6477 #define TCD1_CCA_vect_num 85
6478 #define TCD1_CCA_vect _VECTOR(85) /* Compare or Capture A Interrupt */
6479 #define TCD1_CCB_vect_num 86
6480 #define TCD1_CCB_vect _VECTOR(86) /* Compare or Capture B Interrupt */
6481 
6482 /* SPID interrupt vectors */
6483 #define SPID_INT_vect_num 87
6484 #define SPID_INT_vect _VECTOR(87) /* SPI Interrupt */
6485 
6486 /* USARTD0 interrupt vectors */
6487 #define USARTD0_RXC_vect_num 88
6488 #define USARTD0_RXC_vect _VECTOR(88) /* Reception Complete Interrupt */
6489 #define USARTD0_DRE_vect_num 89
6490 #define USARTD0_DRE_vect _VECTOR(89) /* Data Register Empty Interrupt */
6491 #define USARTD0_TXC_vect_num 90
6492 #define USARTD0_TXC_vect _VECTOR(90) /* Transmission Complete Interrupt */
6493 
6494 /* USARTD1 interrupt vectors */
6495 #define USARTD1_RXC_vect_num 91
6496 #define USARTD1_RXC_vect _VECTOR(91) /* Reception Complete Interrupt */
6497 #define USARTD1_DRE_vect_num 92
6498 #define USARTD1_DRE_vect _VECTOR(92) /* Data Register Empty Interrupt */
6499 #define USARTD1_TXC_vect_num 93
6500 #define USARTD1_TXC_vect _VECTOR(93) /* Transmission Complete Interrupt */
6501 
6502 
6503 #define _VECTOR_SIZE 4 /* Size of individual vector. */
6504 #define _VECTORS_SIZE (94 * _VECTOR_SIZE)
6505 
6506 
6507 /* ========== Constants ========== */
6508 
6509 #define PROGMEM_START (0x0000)
6510 #define PROGMEM_SIZE (36864)
6511 #define PROGMEM_PAGE_SIZE (256)
6512 #define PROGMEM_END (PROGMEM_START + PROGMEM_SIZE - 1)
6513 
6514 #define APP_SECTION_START (0x0000)
6515 #define APP_SECTION_SIZE (32768)
6516 #define APP_SECTION_PAGE_SIZE (256)
6517 #define APP_SECTION_END (APP_SECTION_START + APP_SECTION_SIZE - 1)
6518 
6519 #define APPTABLE_SECTION_START (0x07000)
6520 #define APPTABLE_SECTION_SIZE (4096)
6521 #define APPTABLE_SECTION_PAGE_SIZE (256)
6522 #define APPTABLE_SECTION_END (APPTABLE_SECTION_START + APPTABLE_SECTION_SIZE - 1)
6523 
6524 #define BOOT_SECTION_START (0x8000)
6525 #define BOOT_SECTION_SIZE (4096)
6526 #define BOOT_SECTION_PAGE_SIZE (256)
6527 #define BOOT_SECTION_END (BOOT_SECTION_START + BOOT_SECTION_SIZE - 1)
6528 
6529 #define DATAMEM_START (0x0000)
6530 #define DATAMEM_SIZE (12288)
6531 #define DATAMEM_PAGE_SIZE (0)
6532 #define DATAMEM_END (DATAMEM_START + DATAMEM_SIZE - 1)
6533 
6534 #define IO_START (0x0000)
6535 #define IO_SIZE (4096)
6536 #define IO_PAGE_SIZE (0)
6537 #define IO_END (IO_START + IO_SIZE - 1)
6538 
6539 #define MAPPED_EEPROM_START (0x1000)
6540 #define MAPPED_EEPROM_SIZE (1024)
6541 #define MAPPED_EEPROM_PAGE_SIZE (0)
6542 #define MAPPED_EEPROM_END (MAPPED_EEPROM_START + MAPPED_EEPROM_SIZE - 1)
6543 
6544 #define INTERNAL_SRAM_START (0x2000)
6545 #define INTERNAL_SRAM_SIZE (4096)
6546 #define INTERNAL_SRAM_PAGE_SIZE (0)
6547 #define INTERNAL_SRAM_END (INTERNAL_SRAM_START + INTERNAL_SRAM_SIZE - 1)
6548 
6549 #define EEPROM_START (0x0000)
6550 #define EEPROM_SIZE (1024)
6551 #define EEPROM_PAGE_SIZE (32)
6552 #define EEPROM_END (EEPROM_START + EEPROM_SIZE - 1)
6553 
6554 #define FUSE_START (0x0000)
6555 #define FUSE_SIZE (6)
6556 #define FUSE_PAGE_SIZE (0)
6557 #define FUSE_END (FUSE_START + FUSE_SIZE - 1)
6558 
6559 #define LOCKBIT_START (0x0000)
6560 #define LOCKBIT_SIZE (1)
6561 #define LOCKBIT_PAGE_SIZE (0)
6562 #define LOCKBIT_END (LOCKBIT_START + LOCKBIT_SIZE - 1)
6563 
6564 #define SIGNATURES_START (0x0000)
6565 #define SIGNATURES_SIZE (3)
6566 #define SIGNATURES_PAGE_SIZE (0)
6567 #define SIGNATURES_END (SIGNATURES_START + SIGNATURES_SIZE - 1)
6568 
6569 #define USER_SIGNATURES_START (0x0000)
6570 #define USER_SIGNATURES_SIZE (256)
6571 #define USER_SIGNATURES_PAGE_SIZE (0)
6572 #define USER_SIGNATURES_END (USER_SIGNATURES_START + USER_SIGNATURES_SIZE - 1)
6573 
6574 #define PROD_SIGNATURES_START (0x0000)
6575 #define PROD_SIGNATURES_SIZE (52)
6576 #define PROD_SIGNATURES_PAGE_SIZE (0)
6577 #define PROD_SIGNATURES_END (PROD_SIGNATURES_START + PROD_SIGNATURES_SIZE - 1)
6578 
6579 #define FLASHEND PROGMEM_END
6580 #define SPM_PAGESIZE PROGMEM_PAGE_SIZE
6581 #define RAMSTART INTERNAL_SRAM_START
6582 #define RAMSIZE INTERNAL_SRAM_SIZE
6583 #define RAMEND INTERNAL_SRAM_END
6584 #define XRAMSTART EXTERNAL_SRAM_START
6585 #define XRAMSIZE EXTERNAL_SRAM_SIZE
6586 #define XRAMEND INTERNAL_SRAM_END
6587 #define E2END EEPROM_END
6588 #define E2PAGESIZE EEPROM_PAGE_SIZE
6589 
6590 
6591 /* ========== Fuses ========== */
6592 #define FUSE_MEMORY_SIZE 6
6593 
6594 /* Fuse Byte 0 */
6595 #define FUSE_USERID0 (unsigned char)~_BV(0) /* User ID Bit 0 */
6596 #define FUSE_USERID1 (unsigned char)~_BV(1) /* User ID Bit 1 */
6597 #define FUSE_USERID2 (unsigned char)~_BV(2) /* User ID Bit 2 */
6598 #define FUSE_USERID3 (unsigned char)~_BV(3) /* User ID Bit 3 */
6599 #define FUSE_USERID4 (unsigned char)~_BV(4) /* User ID Bit 4 */
6600 #define FUSE_USERID5 (unsigned char)~_BV(5) /* User ID Bit 5 */
6601 #define FUSE_USERID6 (unsigned char)~_BV(6) /* User ID Bit 6 */
6602 #define FUSE_USERID7 (unsigned char)~_BV(7) /* User ID Bit 7 */
6603 #define FUSE0_DEFAULT (0xFF)
6604 
6605 /* Fuse Byte 1 */
6606 #define FUSE_WDP0 (unsigned char)~_BV(0) /* Watchdog Timeout Period Bit 0 */
6607 #define FUSE_WDP1 (unsigned char)~_BV(1) /* Watchdog Timeout Period Bit 1 */
6608 #define FUSE_WDP2 (unsigned char)~_BV(2) /* Watchdog Timeout Period Bit 2 */
6609 #define FUSE_WDP3 (unsigned char)~_BV(3) /* Watchdog Timeout Period Bit 3 */
6610 #define FUSE_WDWP0 (unsigned char)~_BV(4) /* Watchdog Window Timeout Period Bit 0 */
6611 #define FUSE_WDWP1 (unsigned char)~_BV(5) /* Watchdog Window Timeout Period Bit 1 */
6612 #define FUSE_WDWP2 (unsigned char)~_BV(6) /* Watchdog Window Timeout Period Bit 2 */
6613 #define FUSE_WDWP3 (unsigned char)~_BV(7) /* Watchdog Window Timeout Period Bit 3 */
6614 #define FUSE1_DEFAULT (0xFF)
6615 
6616 /* Fuse Byte 2 */
6617 #define FUSE_BODPD0 (unsigned char)~_BV(0) /* BOD Operation in Power-Down Mode Bit 0 */
6618 #define FUSE_BODPD1 (unsigned char)~_BV(1) /* BOD Operation in Power-Down Mode Bit 1 */
6619 #define FUSE_BOOTRST (unsigned char)~_BV(6) /* Boot Loader Section Reset Vector */
6620 #define FUSE_DVSDON (unsigned char)~_BV(7) /* Spike Detector Enable */
6621 #define FUSE2_DEFAULT (0xFF)
6622 
6623 /* Fuse Byte 3 Reserved */
6624 
6625 /* Fuse Byte 4 */
6626 #define FUSE_WDLOCK (unsigned char)~_BV(1) /* Watchdog Timer Lock */
6627 #define FUSE_SUT0 (unsigned char)~_BV(2) /* Start-up Time Bit 0 */
6628 #define FUSE_SUT1 (unsigned char)~_BV(3) /* Start-up Time Bit 1 */
6629 #define FUSE4_DEFAULT (0xFF)
6630 
6631 /* Fuse Byte 5 */
6632 #define FUSE_BODLVL0 (unsigned char)~_BV(0) /* Brown Out Detection Voltage Level Bit 0 */
6633 #define FUSE_BODLVL1 (unsigned char)~_BV(1) /* Brown Out Detection Voltage Level Bit 1 */
6634 #define FUSE_BODLVL2 (unsigned char)~_BV(2) /* Brown Out Detection Voltage Level Bit 2 */
6635 #define FUSE_EESAVE (unsigned char)~_BV(3) /* Preserve EEPROM Through Chip Erase */
6636 #define FUSE_BODACT0 (unsigned char)~_BV(4) /* BOD Operation in Active Mode Bit 0 */
6637 #define FUSE_BODACT1 (unsigned char)~_BV(5) /* BOD Operation in Active Mode Bit 1 */
6638 #define FUSE5_DEFAULT (0xFF)
6639 
6640 
6641 /* ========== Lock Bits ========== */
6642 #define __LOCK_BITS_EXIST
6643 #define __BOOT_LOCK_APPLICATION_TABLE_BITS_EXIST
6644 #define __BOOT_LOCK_APPLICATION_BITS_EXIST
6645 #define __BOOT_LOCK_BOOT_BITS_EXIST
6646 
6647 
6648 /* ========== Signature ========== */
6649 #define SIGNATURE_0 0x1E
6650 #define SIGNATURE_1 0x95
6651 #define SIGNATURE_2 0x41
6652 
6653 
6655 #endif /* _AVR_ATxmega32A4_H_ */
SLEEP_struct
Definition: iox128a1.h:237
NVM_struct
Definition: iox128a1.h:905
DAC_struct
Definition: iox128a1.h:1490
TWI_MASTER_struct
Definition: iox128a1.h:1853
DMA_CH_struct
Definition: iox128a1.h:428
OSC_struct
Definition: iox128a1.h:260
ADC_CH_struct
Definition: iox128a1.h:1276
EBI_CS_struct
Definition: iox128a1.h:1647
PORT_struct
Definition: iox128a1.h:1991
HIRES_struct
Definition: iox128a1.h:2326
PMIC_struct
Definition: iox128a1.h:413
PR_struct
Definition: iox128a1.h:171
DMA_struct
Definition: iox128a1.h:454
EVSYS_struct
Definition: iox128a1.h:697
PORTCFG_struct
Definition: iox128a1.h:1960
DFLL_struct
Definition: iox128a1.h:308
OCD_struct
Definition: iox128a1.h:134
EBI_struct
Definition: iox128a1.h:1661
RST_struct
Definition: iox128a1.h:328
RTC_struct
Definition: iox128a1.h:1593
NVM_PROD_SIGNATURES_struct
Definition: iox128a1.h:962
SPI_struct
Definition: iox128a1.h:2555
TC1_struct
Definition: iox128a1.h:2238
IRCOM_struct
Definition: iox128a1.h:2598
TC0_struct
Definition: iox128a1.h:2174
USART_struct
Definition: iox128a1.h:2481
TWI_SLAVE_struct
Definition: iox128a1.h:1871
CLK_struct
Definition: iox128a1.h:156
TWI_struct
Definition: iox128a1.h:1888
AC_struct
Definition: iox128a1.h:1179
ADC_struct
Definition: iox128a1.h:1294
AES_struct
Definition: iox128a1.h:2628
MCU_struct
Definition: iox128a1.h:389
WDT_struct
Definition: iox128a1.h:342
NVM_LOCKBITS_struct
Definition: iox128a1.h:933
AWEX_struct
Definition: iox128a1.h:2302
VPORT_struct
Definition: iox128a1.h:1976
NVM_FUSES_struct
Definition: iox128a1.h:945
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