RTEMS CPU Kit with SuperCore  4.11.3
iotn22.h
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1 /* Copyright (c) 2002, Marek Michalkiewicz
2  All rights reserved.
3 
4  Redistribution and use in source and binary forms, with or without
5  modification, are permitted provided that the following conditions are met:
6 
7  * Redistributions of source code must retain the above copyright
8  notice, this list of conditions and the following disclaimer.
9 
10  * Redistributions in binary form must reproduce the above copyright
11  notice, this list of conditions and the following disclaimer in
12  the documentation and/or other materials provided with the
13  distribution.
14 
15  * Neither the name of the copyright holders nor the names of
16  contributors may be used to endorse or promote products derived
17  from this software without specific prior written permission.
18 
19  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
20  AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
21  IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
22  ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
23  LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
24  CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
25  SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
26  INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
27  CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
28  ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
29  POSSIBILITY OF SUCH DAMAGE. */
30 
31 
32 /* avr/iotn22.h - definitions for ATtiny22 */
33 
34 #ifndef _AVR_IOTN22_H_
35 #define _AVR_IOTN22_H_ 1
36 
37 /* This file should only be included from <avr/io.h>, never directly. */
38 
39 #ifndef _AVR_IO_H_
40 # error "Include <avr/io.h> instead of this file."
41 #endif
42 
43 #ifndef _AVR_IOXXX_H_
44 # define _AVR_IOXXX_H_ "iotn22.h"
45 #else
46 # error "Attempt to include more than one <avr/ioXXX.h> file."
47 #endif
48 
49 /* I/O registers */
50 
51 /* Input Pins, Port B */
52 #define PINB _SFR_IO8(0x16)
53 
54 /* Data Direction Register, Port B */
55 #define DDRB _SFR_IO8(0x17)
56 
57 /* Data Register, Port B */
58 #define PORTB _SFR_IO8(0x18)
59 
60 /* EEPROM Control Register */
61 #define EECR _SFR_IO8(0x1C)
62 
63 /* EEPROM Data Register */
64 #define EEDR _SFR_IO8(0x1D)
65 
66 /* EEPROM Address Register */
67 #define EEAR _SFR_IO8(0x1E)
68 #define EEARL _SFR_IO8(0x1E)
69 
70 /* Watchdog Timer Control Register */
71 #define WDTCR _SFR_IO8(0x21)
72 
73 /* Timer/Counter 0 */
74 #define TCNT0 _SFR_IO8(0x32)
75 
76 /* Timer/Counter 0 Control Register */
77 #define TCCR0 _SFR_IO8(0x33)
78 
79 /* MCU Status Register */
80 #define MCUSR _SFR_IO8(0x34)
81 
82 /* MCU general Control Register */
83 #define MCUCR _SFR_IO8(0x35)
84 
85 /* Timer/Counter Interrupt Flag register */
86 #define TIFR _SFR_IO8(0x38)
87 
88 /* Timer/Counter Interrupt MaSK register */
89 #define TIMSK _SFR_IO8(0x39)
90 
91 /* General Interrupt Flag register */
92 #define GIFR _SFR_IO8(0x3A)
93 
94 /* General Interrupt MaSK register */
95 #define GIMSK _SFR_IO8(0x3B)
96 
97 /* 0x3D SP */
98 
99 /* 0x3F SREG */
100 
101 /* Interrupt vectors */
102 
103 /* External Interrupt 0 */
104 #define INT0_vect _VECTOR(1)
105 #define SIG_INTERRUPT0 _VECTOR(1)
106 
107 /* Timer/Counter0 Overflow */
108 #define TIMER0_OVF0_vect _VECTOR(2)
109 #define SIG_OVERFLOW0 _VECTOR(2)
110 
111 #define _VECTORS_SIZE 6
112 
113 /*
114  The Register Bit names are represented by their bit number (0-7).
115  */
116 
117 /* General Interrupt MaSK register */
118 #define INT0 6
119 #define INTF0 6
120 
121 /* General Interrupt Flag Register */
122 #define TOIE0 1
123 #define TOV0 1
124 
125 /* MCU general Control Register */
126 #define SE 5
127 #define SM 4
128 #define ISC01 1
129 #define ISC00 0
130 
131 /* Timer/Counter 0 Control Register */
132 #define CS02 2
133 #define CS01 1
134 #define CS00 0
135 
136 /* Watchdog Timer Control Register */
137 #define WDTOE 4
138 #define WDE 3
139 #define WDP2 2
140 #define WDP1 1
141 #define WDP0 0
142 
143 /*
144  PB2 = SCK/T0
145  PB1 = MISO/INT0
146  PB0 = MOSI
147  */
148 
149 /* Data Register, Port B */
150 #define PB4 4
151 #define PB3 3
152 #define PB2 2
153 #define PB1 1
154 #define PB0 0
155 
156 /* Data Direction Register, Port B */
157 #define DDB4 4
158 #define DDB3 3
159 #define DDB2 2
160 #define DDB1 1
161 #define DDB0 0
162 
163 /* Input Pins, Port B */
164 #define PINB4 4
165 #define PINB3 3
166 #define PINB2 2
167 #define PINB1 1
168 #define PINB0 0
169 
170 /* EEPROM Control Register */
171 #define EERIE 3
172 #define EEMWE 2
173 #define EEWE 1
174 #define EERE 0
175 
176 /* Constants */
177 #define RAMEND 0xDF
178 #define XRAMEND RAMEND
179 #define E2END 0x7F
180 #define E2PAGESIZE 0
181 #define FLASHEND 0x07FF
182 
183 
184 /* Fuses */
185 
186 #define FUSE_MEMORY_SIZE 1
187 
188 /* Fuse Byte */
189 #define FUSE_CKSEL (unsigned char)~_BV(0)
190 #define FUSE_SPIEN (unsigned char)~_BV(5)
191 #define FUSE_DEFAULT (FUSE_SPIEN)
192 
193 
194 /* Lock Bits */
195 #define __LOCK_BITS_EXIST
196 
197 
198 /* Signature */
199 #define SIGNATURE_0 0x1E
200 #define SIGNATURE_1 0x91
201 #define SIGNATURE_2 0x06
202 
203 
204 #endif /* _AVR_IOTN22_H_ */
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