RTEMS CPU Kit with SuperCore  4.11.3
iom645.h
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1 
9 /*
10  * Copyright (c) 2004,2005,2006 Eric B. Weddington
11  * All rights reserved.
12  *
13  * Redistribution and use in source and binary forms, with or without
14  * modification, are permitted provided that the following conditions are met:
15  *
16  * * Redistributions of source code must retain the above copyright
17  * notice, this list of conditions and the following disclaimer.
18  *
19  * * Redistributions in binary form must reproduce the above copyright
20  * notice, this list of conditions and the following disclaimer in
21  * the documentation and/or other materials provided with the
22  * distribution.
23  *
24  * * Neither the name of the copyright holders nor the names of
25  * contributors may be used to endorse or promote products derived
26  * from this software without specific prior written permission.
27  *
28  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
29  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
30  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
31  * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
32  * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
33  * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
34  * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
35  * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
36  * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
37  * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
38  * POSSIBILITY OF SUCH DAMAGE.
39  */
40 
41 #ifndef _AVR_IOM645_H_
42 #define _AVR_IOM645_H_ 1
43 
51 #ifndef _AVR_IO_H_
52 # error "Include <avr/io.h> instead of this file."
53 #endif
54 
55 #ifndef _AVR_IOXXX_H_
56 # define _AVR_IOXXX_H_ "iom645.h"
57 #else
58 # error "Attempt to include more than one <avr/ioXXX.h> file."
59 #endif
60 
61 /* Registers and associated bit numbers */
62 
63 #define PINA _SFR_IO8(0x00)
64 #define PINA7 7
65 #define PINA6 6
66 #define PINA5 5
67 #define PINA4 4
68 #define PINA3 3
69 #define PINA2 2
70 #define PINA1 1
71 #define PINA0 0
72 
73 #define DDRA _SFR_IO8(0x01)
74 #define DDA7 7
75 #define DDA6 6
76 #define DDA5 5
77 #define DDA4 4
78 #define DDA3 3
79 #define DDA2 2
80 #define DDA1 1
81 #define DDA0 0
82 
83 #define PORTA _SFR_IO8(0x02)
84 #define PA7 7
85 #define PA6 6
86 #define PA5 5
87 #define PA4 4
88 #define PA3 3
89 #define PA2 2
90 #define PA1 1
91 #define PA0 0
92 
93 #define PINB _SFR_IO8(0x03)
94 #define PINB7 7
95 #define PINB6 6
96 #define PINB5 5
97 #define PINB4 4
98 #define PINB3 3
99 #define PINB2 2
100 #define PINB1 1
101 #define PINB0 0
102 
103 #define DDRB _SFR_IO8(0x04)
104 #define DDB7 7
105 #define DDB6 6
106 #define DDB5 5
107 #define DDB4 4
108 #define DDB3 3
109 #define DDB2 2
110 #define DDB1 1
111 #define DDB0 0
112 
113 #define PORTB _SFR_IO8(0x05)
114 #define PB7 7
115 #define PB6 6
116 #define PB5 5
117 #define PB4 4
118 #define PB3 3
119 #define PB2 2
120 #define PB1 1
121 #define PB0 0
122 
123 #define PINC _SFR_IO8(0x06)
124 #define PINC7 7
125 #define PINC6 6
126 #define PINC5 5
127 #define PINC4 4
128 #define PINC3 3
129 #define PINC2 2
130 #define PINC1 1
131 #define PINC0 0
132 
133 #define DDRC _SFR_IO8(0x07)
134 #define DDC7 7
135 #define DDC6 6
136 #define DDC5 5
137 #define DDC4 4
138 #define DDC3 3
139 #define DDC2 2
140 #define DDC1 1
141 #define DDC0 0
142 
143 #define PORTC _SFR_IO8(0x08)
144 #define PC7 7
145 #define PC6 6
146 #define PC5 5
147 #define PC4 4
148 #define PC3 3
149 #define PC2 2
150 #define PC1 1
151 #define PC0 0
152 
153 #define PIND _SFR_IO8(0x09)
154 #define PIND7 7
155 #define PIND6 6
156 #define PIND5 5
157 #define PIND4 4
158 #define PIND3 3
159 #define PIND2 2
160 #define PIND1 1
161 #define PIND0 0
162 
163 #define DDRD _SFR_IO8(0x0A)
164 #define DDD7 7
165 #define DDD6 6
166 #define DDD5 5
167 #define DDD4 4
168 #define DDD3 3
169 #define DDD2 2
170 #define DDD1 1
171 #define DDD0 0
172 
173 #define PORTD _SFR_IO8(0x0B)
174 #define PD7 7
175 #define PD6 6
176 #define PD5 5
177 #define PD4 4
178 #define PD3 3
179 #define PD2 2
180 #define PD1 1
181 #define PD0 0
182 
183 #define PINE _SFR_IO8(0x0C)
184 #define PINE7 7
185 #define PINE6 6
186 #define PINE5 5
187 #define PINE4 4
188 #define PINE3 3
189 #define PINE2 2
190 #define PINE1 1
191 #define PINE0 0
192 
193 #define DDRE _SFR_IO8(0x0D)
194 #define DDE7 7
195 #define DDE6 6
196 #define DDE5 5
197 #define DDE4 4
198 #define DDE3 3
199 #define DDE2 2
200 #define DDE1 1
201 #define DDE0 0
202 
203 #define PORTE _SFR_IO8(0x0E)
204 #define PE7 7
205 #define PE6 6
206 #define PE5 5
207 #define PE4 4
208 #define PE3 3
209 #define PE2 2
210 #define PE1 1
211 #define PE0 0
212 
213 #define PINF _SFR_IO8(0x0F)
214 #define PINF7 7
215 #define PINF6 6
216 #define PINF5 5
217 #define PINF4 4
218 #define PINF3 3
219 #define PINF2 2
220 #define PINF1 1
221 #define PINF0 0
222 
223 #define DDRF _SFR_IO8(0x10)
224 #define DDF7 7
225 #define DDF6 6
226 #define DDF5 5
227 #define DDF4 4
228 #define DDF3 3
229 #define DDF2 2
230 #define DDF1 1
231 #define DDF0 0
232 
233 #define PORTF _SFR_IO8(0x11)
234 #define PF7 7
235 #define PF6 6
236 #define PF5 5
237 #define PF4 4
238 #define PF3 3
239 #define PF2 2
240 #define PF1 1
241 #define PF0 0
242 
243 #define PING _SFR_IO8(0x12)
244 #define PING5 5
245 #define PING4 4
246 #define PING3 3
247 #define PING2 2
248 #define PING1 1
249 #define PING0 0
250 
251 #define DDRG _SFR_IO8(0x13)
252 #define DDG4 4
253 #define DDG3 3
254 #define DDG2 2
255 #define DDG1 1
256 #define DDG0 0
257 
258 #define PORTG _SFR_IO8(0x14)
259 #define PG4 4
260 #define PG3 3
261 #define PG2 2
262 #define PG1 1
263 #define PG0 0
264 
265 #define TIFR0 _SFR_IO8(0x15)
266 #define TOV0 0
267 #define OCF0A 1
268 
269 #define TIFR1 _SFR_IO8(0x16)
270 #define TOV1 0
271 #define OCF1A 1
272 #define OCF1B 2
273 #define ICF1 5
274 
275 #define TIFR2 _SFR_IO8(0x17)
276 #define TOV2 0
277 #define OCF2A 1
278 
279 /* Reserved [0x18..0x1B] */
280 
281 #define EIFR _SFR_IO8(0x1C)
282 #define INTF0 0
283 #define PCIF0 4
284 #define PCIF1 5
285 
286 #define EIMSK _SFR_IO8(0x1D)
287 #define INT0 0
288 #define PCIE0 4
289 #define PCIE1 5
290 
291 #define GPIOR0 _SFR_IO8(0x1E)
292 
293 #define EECR _SFR_IO8(0x1F)
294 #define EERE 0
295 #define EEWE 1
296 #define EEMWE 2
297 #define EERIE 3
298 
299 #define EEDR _SFR_IO8(0X20)
300 
301 /* Combine EEARL and EEARH */
302 #define EEAR _SFR_IO16(0x21)
303 #define EEARL _SFR_IO8(0x21)
304 #define EEARH _SFR_IO8(0X22)
305 
306 /* 6-char sequence denoting where to find the EEPROM registers in memory space.
307  Adresses denoted in hex syntax with uppercase letters. Used by the EEPROM
308  subroutines.
309  First two letters: EECR address.
310  Second two letters: EEDR address.
311  Last two letters: EEAR address. */
312 #define __EEPROM_REG_LOCATIONS__ 1F2021
313 
314 #define GTCCR _SFR_IO8(0x23)
315 #define PSR10 0
316 #define PSR2 1
317 #define TSM 7
318 
319 #define TCCR0A _SFR_IO8(0x24)
320 #define CS00 0
321 #define CS01 1
322 #define CS02 2
323 #define WGM01 3
324 #define COM0A0 4
325 #define COM0A1 5
326 #define WGM00 6
327 #define FOC0A 7
328 
329 /* Reserved [0x25] */
330 
331 #define TCNT0 _SFR_IO8(0X26)
332 
333 #define OCR0A _SFR_IO8(0X27)
334 
335 /* Reserved [0x28..0x29] */
336 
337 #define GPIOR1 _SFR_IO8(0x2A)
338 
339 #define GPIOR2 _SFR_IO8(0x2B)
340 
341 #define SPCR _SFR_IO8(0x2C)
342 #define SPR0 0
343 #define SPR1 1
344 #define CPHA 2
345 #define CPOL 3
346 #define MSTR 4
347 #define DORD 5
348 #define SPE 6
349 #define SPIE 7
350 
351 #define SPSR _SFR_IO8(0x2D)
352 #define SPI2X 0
353 #define WCOL 6
354 #define SPIF 7
355 
356 #define SPDR _SFR_IO8(0X2E)
357 
358 /* Reserved [0x2F] */
359 
360 #define ACSR _SFR_IO8(0x30)
361 #define ACIS0 0
362 #define ACIS1 1
363 #define ACIC 2
364 #define ACIE 3
365 #define ACI 4
366 #define ACO 5
367 #define ACBG 6
368 #define ACD 7
369 
370 #define OCDR _SFR_IO8(0x31)
371 #define OCDR0 0
372 #define OCDR1 1
373 #define OCDR2 2
374 #define OCDR3 3
375 #define OCDR4 4
376 #define OCDR5 5
377 #define OCDR6 6
378 #define OCDR7 7
379 #define IDRD 7
380 
381 /* Reserved [0x32] */
382 
383 #define SMCR _SFR_IO8(0x33)
384 #define SE 0
385 #define SM0 1
386 #define SM1 2
387 #define SM2 3
388 
389 #define MCUSR _SFR_IO8(0x34)
390 #define PORF 0
391 #define EXTRF 1
392 #define BORF 2
393 #define WDRF 3
394 #define JTRF 4
395 
396 #define MCUCR _SFR_IO8(0X35)
397 #define IVCE 0
398 #define IVSEL 1
399 #define PUD 4
400 #define JTD 7
401 
402 /* Reserved [0x36] */
403 
404 #define SPMCSR _SFR_IO8(0x37)
405 #define SPMEN 0
406 #define PGERS 1
407 #define PGWRT 2
408 #define BLBSET 3
409 #define RWWSRE 4
410 #define RWWSB 6
411 #define SPMIE 7
412 
413 /* Reserved [0x38..0x3C] */
414 
415 /* SP [0x3D..0x3E] */
416 /* SREG [0x3F] */
417 
418 #define WDTCR _SFR_MEM8(0x60)
419 #define WDP0 0
420 #define WDP1 1
421 #define WDP2 2
422 #define WDE 3
423 #define WDCE 4
424 
425 #define CLKPR _SFR_MEM8(0x61)
426 #define CLKPS0 0
427 #define CLKPS1 1
428 #define CLKPS2 2
429 #define CLKPS3 3
430 #define CLKPCE 7
431 
432 /* Reserved [0x62..0x63] */
433 
434 #define PRR _SFR_MEM8(0x64)
435 #define PRADC 0
436 #define PRUSART0 1
437 #define PRSPI 2
438 #define PRTIM1 3
439 
440 /* Reserved [0x65] */
441 
442 #define OSCCAL _SFR_MEM8(0x66)
443 
444 /* Reserved [0x67..0x68] */
445 
446 #define EICRA _SFR_MEM8(0x69)
447 #define ISC00 0
448 #define ISC01 1
449 
450 /* Reserved [0x6A] */
451 
452 #define PCMSK0 _SFR_MEM8(0x6B)
453 #define PCINT0 0
454 #define PCINT1 1
455 #define PCINT2 2
456 #define PCINT3 3
457 #define PCINT4 4
458 #define PCINT5 5
459 #define PCINT6 6
460 #define PCINT7 7
461 
462 #define PCMSK1 _SFR_MEM8(0x6C)
463 #define PCINT8 0
464 #define PCINT9 1
465 #define PCINT10 2
466 #define PCINT11 3
467 #define PCINT12 4
468 #define PCINT13 5
469 #define PCINT14 6
470 #define PCINT15 7
471 
472 /* Reserved [0x6D] */
473 
474 #define TIMSK0 _SFR_MEM8(0x6E)
475 #define TOIE0 0
476 #define OCIE0A 1
477 
478 #define TIMSK1 _SFR_MEM8(0x6F)
479 #define TOIE1 0
480 #define OCIE1A 1
481 #define OCIE1B 2
482 #define ICIE1 5
483 
484 #define TIMSK2 _SFR_MEM8(0x70)
485 #define TOIE2 0
486 #define OCIE2A 1
487 
488 /* Reserved [0x71..0x77] */
489 
490 /* Combine ADCL and ADCH */
491 #ifndef __ASSEMBLER__
492 #define ADC _SFR_MEM16(0x78)
493 #endif
494 #define ADCW _SFR_MEM16(0x78)
495 #define ADCL _SFR_MEM8(0x78)
496 #define ADCH _SFR_MEM8(0x79)
497 
498 #define ADCSRA _SFR_MEM8(0x7A)
499 #define ADPS0 0
500 #define ADPS1 1
501 #define ADPS2 2
502 #define ADIE 3
503 #define ADIF 4
504 #define ADATE 5
505 #define ADSC 6
506 #define ADEN 7
507 
508 #define ADCSRB _SFR_MEM8(0x7B)
509 #define ADTS0 0
510 #define ADTS1 1
511 #define ADTS2 2
512 #define ACME 6
513 
514 #define ADMUX _SFR_MEM8(0x7C)
515 #define MUX0 0
516 #define MUX1 1
517 #define MUX2 2
518 #define MUX3 3
519 #define MUX4 4
520 #define ADLAR 5
521 #define REFS0 6
522 #define REFS1 7
523 
524 /* Reserved [0x7D] */
525 
526 #define DIDR0 _SFR_MEM8(0x7E)
527 #define ADC0D 0
528 #define ADC1D 1
529 #define ADC2D 2
530 #define ADC3D 3
531 #define ADC4D 4
532 #define ADC5D 5
533 #define ADC6D 6
534 #define ADC7D 7
535 
536 #define DIDR1 _SFR_MEM8(0x7F)
537 #define AIN0D 0
538 #define AIN1D 1
539 
540 #define TCCR1A _SFR_MEM8(0X80)
541 #define WGM10 0
542 #define WGM11 1
543 #define COM1B0 4
544 #define COM1B1 5
545 #define COM1A0 6
546 #define COM1A1 7
547 
548 #define TCCR1B _SFR_MEM8(0X81)
549 #define CS10 0
550 #define CS11 1
551 #define CS12 2
552 #define WGM12 3
553 #define WGM13 4
554 #define ICES1 6
555 #define ICNC1 7
556 
557 #define TCCR1C _SFR_MEM8(0x82)
558 #define FOC1B 6
559 #define FOC1A 7
560 
561 /* Reserved [0x83] */
562 
563 /* Combine TCNT1L and TCNT1H */
564 #define TCNT1 _SFR_MEM16(0x84)
565 
566 #define TCNT1L _SFR_MEM8(0x84)
567 #define TCNT1H _SFR_MEM8(0x85)
568 
569 /* Combine ICR1L and ICR1H */
570 #define ICR1 _SFR_MEM16(0x86)
571 
572 #define ICR1L _SFR_MEM8(0x86)
573 #define ICR1H _SFR_MEM8(0x87)
574 
575 /* Combine OCR1AL and OCR1AH */
576 #define OCR1A _SFR_MEM16(0x88)
577 
578 #define OCR1AL _SFR_MEM8(0x88)
579 #define OCR1AH _SFR_MEM8(0x89)
580 
581 /* Combine OCR1BL and OCR1BH */
582 #define OCR1B _SFR_MEM16(0x8A)
583 
584 #define OCR1BL _SFR_MEM8(0x8A)
585 #define OCR1BH _SFR_MEM8(0x8B)
586 
587 /* Reserved [0x8C..0xAF] */
588 
589 #define TCCR2A _SFR_MEM8(0xB0)
590 #define CS20 0
591 #define CS21 1
592 #define CS22 2
593 #define WGM21 3
594 #define COM2A0 4
595 #define COM2A1 5
596 #define WGM20 6
597 #define FOC2A 7
598 
599 /* Reserved [0xB1] */
600 
601 #define TCNT2 _SFR_MEM8(0xB2)
602 
603 #define OCR2A _SFR_MEM8(0xB3)
604 
605 /* Reserved [0xB4..0xB5] */
606 
607 #define ASSR _SFR_MEM8(0xB6)
608 #define TCR2UB 0
609 #define OCR2UB 1
610 #define TCN2UB 2
611 #define AS2 3
612 #define EXCLK 4
613 
614 /* Reserved [0xB7] */
615 
616 #define USICR _SFR_MEM8(0xB8)
617 #define USITC 0
618 #define USICLK 1
619 #define USICS0 2
620 #define USICS1 3
621 #define USIWM0 4
622 #define USIWM1 5
623 #define USIOIE 6
624 #define USISIE 7
625 
626 #define USISR _SFR_MEM8(0xB9)
627 #define USICNT0 0
628 #define USICNT1 1
629 #define USICNT2 2
630 #define USICNT3 3
631 #define USIDC 4
632 #define USIPF 5
633 #define USIOIF 6
634 #define USISIF 7
635 
636 #define USIDR _SFR_MEM8(0xBA)
637 
638 /* Reserved [0xBB..0xBF] */
639 
640 #define UCSR0A _SFR_MEM8(0xC0)
641 #define MPCM0 0
642 #define U2X0 1
643 #define UPE0 2
644 #define DOR0 3
645 #define FE0 4
646 #define UDRE0 5
647 #define TXC0 6
648 #define RXC0 7
649 
650 #define UCSR0B _SFR_MEM8(0XC1)
651 #define TXB80 0
652 #define RXB80 1
653 #define UCSZ02 2
654 #define TXEN0 3
655 #define RXEN0 4
656 #define UDRIE0 5
657 #define TXCIE0 6
658 #define RXCIE0 7
659 
660 #define UCSR0C _SFR_MEM8(0xC2)
661 #define UCPOL0 0
662 #define UCSZ00 1
663 #define UCSZ01 2
664 #define USBS0 3
665 #define UPM00 4
666 #define UPM01 5
667 #define UMSEL0 6
668 
669 /* Reserved [0xC3] */
670 
671 /* Combine UBRR0L and UBRR0H */
672 #define UBRR0 _SFR_MEM16(0xC4)
673 
674 #define UBRR0L _SFR_MEM8(0xC4)
675 #define UBRR0H _SFR_MEM8(0xC5)
676 
677 #define UDR0 _SFR_MEM8(0XC6)
678 
679 /* Reserved [0xC7..0xFF] */
680 
681 
682 /* Interrupt vectors */
683 /* Vector 0 is the reset vector */
684 /* External Interrupt Request 0 */
685 #define INT0_vect _VECTOR(1)
686 #define SIG_INTERRUPT0 _VECTOR(1)
687 
688 /* Pin Change Interrupt Request 0 */
689 #define PCINT0_vect _VECTOR(2)
690 #define SIG_PIN_CHANGE0 _VECTOR(2)
691 
692 /* Pin Change Interrupt Request 1 */
693 #define PCINT1_vect _VECTOR(3)
694 #define SIG_PIN_CHANGE1 _VECTOR(3)
695 
696 /* Timer/Counter2 Compare Match */
697 #define TIMER2_COMP_vect _VECTOR(4)
698 #define SIG_OUTPUT_COMPARE2 _VECTOR(4)
699 
700 /* Timer/Counter2 Overflow */
701 #define TIMER2_OVF_vect _VECTOR(5)
702 #define SIG_OVERFLOW2 _VECTOR(5)
703 
704 /* Timer/Counter1 Capture Event */
705 #define TIMER1_CAPT_vect _VECTOR(6)
706 #define SIG_INPUT_CAPTURE1 _VECTOR(6)
707 
708 /* Timer/Counter1 Compare Match A */
709 #define TIMER1_COMPA_vect _VECTOR(7)
710 #define SIG_OUTPUT_COMPARE1A _VECTOR(7)
711 
712 /* Timer/Counter Compare Match B */
713 #define TIMER1_COMPB_vect _VECTOR(8)
714 #define SIG_OUTPUT_COMPARE1B _VECTOR(8)
715 
716 /* Timer/Counter1 Overflow */
717 #define TIMER1_OVF_vect _VECTOR(9)
718 #define SIG_OVERFLOW1 _VECTOR(9)
719 
720 /* Timer/Counter0 Compare Match */
721 #define TIMER0_COMP_vect _VECTOR(10)
722 #define SIG_OUTPUT_COMPARE0 _VECTOR(10)
723 
724 /* Timer/Counter0 Overflow */
725 #define TIMER0_OVF_vect _VECTOR(11)
726 #define SIG_OVERFLOW0 _VECTOR(11)
727 
728 /* SPI Serial Transfer Complete */
729 #define SPI_STC_vect _VECTOR(12)
730 #define SIG_SPI _VECTOR(12)
731 
732 /* USART0, Rx Complete */
733 #define USART0_RX_vect _VECTOR(13)
734 #define SIG_UART_RECV _VECTOR(13)
735 
736 /* USART0 Data register Empty */
737 #define USART0_UDRE_vect _VECTOR(14)
738 #define SIG_UART_DATA _VECTOR(14)
739 
740 /* USART0, Tx Complete */
741 #define USART0_TX_vect _VECTOR(15)
742 #define SIG_UART_TRANS _VECTOR(15)
743 
744 /* USI Start Condition */
745 #define USI_START_vect _VECTOR(16)
746 #define SIG_USI_START _VECTOR(16)
747 
748 /* USI Overflow */
749 #define USI_OVERFLOW_vect _VECTOR(17)
750 #define SIG_USI_OVERFLOW _VECTOR(17)
751 
752 /* Analog Comparator */
753 #define ANALOG_COMP_vect _VECTOR(18)
754 #define SIG_COMPARATOR _VECTOR(18)
755 
756 /* ADC Conversion Complete */
757 #define ADC_vect _VECTOR(19)
758 #define SIG_ADC _VECTOR(19)
759 
760 /* EEPROM Ready */
761 #define EE_READY_vect _VECTOR(20)
762 #define SIG_EEPROM_READY _VECTOR(20)
763 
764 /* Store Program Memory Read */
765 #define SPM_READY_vect _VECTOR(21)
766 #define SIG_SPM_READY _VECTOR(21)
767 
768 /* Vector 22 is Reserved */
769 
770 #define _VECTORS_SIZE 92
771 
772 
773 /* Constants */
774 #define SPM_PAGESIZE 256
775 #define RAMEND 0x10FF
776 #define XRAMEND RAMEND
777 #define E2END 0x7FF
778 #define E2PAGESIZE 8
779 #define FLASHEND 0xFFFF
780 
781 
782 /* Fuses */
783 
784 #define FUSE_MEMORY_SIZE 3
785 
786 /* Low Fuse Byte */
787 #define FUSE_CKSEL0 (unsigned char)~_BV(0)
788 #define FUSE_CKSEL1 (unsigned char)~_BV(1)
789 #define FUSE_CKSEL2 (unsigned char)~_BV(2)
790 #define FUSE_CKSEL3 (unsigned char)~_BV(3)
791 #define FUSE_SUT0 (unsigned char)~_BV(4)
792 #define FUSE_SUT1 (unsigned char)~_BV(5)
793 #define FUSE_CKOUT (unsigned char)~_BV(6)
794 #define FUSE_CKDIV8 (unsigned char)~_BV(7)
795 #define LFUSE_DEFAULT (FUSE_CKSEL0 & FUSE_CKSEL2 & FUSE_CKSEL3 & FUSE_SUT0 & FUSE_CKDIV8)
796 
797 /* High Fuse Byte */
798 #define FUSE_BOOTRST (unsigned char)~_BV(0)
799 #define FUSE_BOOTSZ0 (unsigned char)~_BV(1)
800 #define FUSE_BOOTSZ1 (unsigned char)~_BV(2)
801 #define FUSE_EESAVE (unsigned char)~_BV(3)
802 #define FUSE_WDTON (unsigned char)~_BV(4)
803 #define FUSE_SPIEN (unsigned char)~_BV(5)
804 #define FUSE_JTAGEN (unsigned char)~_BV(6)
805 #define FUSE_OCDEN (unsigned char)~_BV(7)
806 #define HFUSE_DEFAULT (FUSE_BOOTSZ0 & FUSE_BOOTSZ1 & FUSE_SPIEN & FUSE_JTAGEN)
807 
808 /* Extended Fuse Byte */
809 #define FUSE_RSTDISBL (unsigned char)~_BV(0)
810 #define FUSE_BODLEVEL0 (unsigned char)~_BV(1)
811 #define FUSE_BODLEVEL1 (unsigned char)~_BV(2)
812 #define EFUSE_DEFAULT (0xFF)
813 
814 
815 /* Lock Bits */
816 #define __LOCK_BITS_EXIST
817 #define __BOOT_LOCK_BITS_0_EXIST
818 #define __BOOT_LOCK_BITS_1_EXIST
819 
820 
821 /* Signature */
822 #define SIGNATURE_0 0x1E
823 #define SIGNATURE_1 0x96
824 #define SIGNATURE_2 0x05
825 
827 #endif /* _AVR_IOM645_H_ */