RTEMS CPU Kit with SuperCore  4.11.3
iom16.h
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1 
9 /*
10  * Copyright (c) 2004 Eric B. Weddington
11  * All rights reserved.
12  *
13  * Redistribution and use in source and binary forms, with or without
14  * modification, are permitted provided that the following conditions are met:
15  *
16  * * Redistributions of source code must retain the above copyright
17  * notice, this list of conditions and the following disclaimer.
18  *
19  * * Redistributions in binary form must reproduce the above copyright
20  * notice, this list of conditions and the following disclaimer in
21  * the documentation and/or other materials provided with the
22  * distribution.
23  *
24  * * Neither the name of the copyright holders nor the names of
25  * contributors may be used to endorse or promote products derived
26  * from this software without specific prior written permission.
27  *
28  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
29  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
30  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
31  * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
32  * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
33  * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
34  * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
35  * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
36  * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
37  * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
38  * POSSIBILITY OF SUCH DAMAGE.
39  */
40 
41 #ifndef _AVR_IOM16_H_
42 #define _AVR_IOM16_H_ 1
43 
51 #ifndef _AVR_IO_H_
52 # error "Include <avr/io.h> instead of this file."
53 #endif
54 
55 #ifndef _AVR_IOXXX_H_
56 # define _AVR_IOXXX_H_ "iom16.h"
57 #else
58 # error "Attempt to include more than one <avr/ioXXX.h> file."
59 #endif
60 
61 /* Registers and associated bit numbers */
62 
63 #define TWBR _SFR_IO8(0x00)
64 
65 #define TWSR _SFR_IO8(0x01)
66 #define TWPS0 0
67 #define TWPS1 1
68 #define TWS3 3
69 #define TWS4 4
70 #define TWS5 5
71 #define TWS6 6
72 #define TWS7 7
73 
74 #define TWAR _SFR_IO8(0x02)
75 #define TWGCE 0
76 #define TWA0 1
77 #define TWA1 2
78 #define TWA2 3
79 #define TWA3 4
80 #define TWA4 5
81 #define TWA5 6
82 #define TWA6 7
83 
84 #define TWDR _SFR_IO8(0x03)
85 
86 /* Combine ADCL and ADCH */
87 #ifndef __ASSEMBLER__
88 #define ADC _SFR_IO16(0x04)
89 #endif
90 #define ADCW _SFR_IO16(0x04)
91 #define ADCL _SFR_IO8(0x04)
92 #define ADCH _SFR_IO8(0x05)
93 
94 #define ADCSRA _SFR_IO8(0x06)
95 #define ADPS0 0
96 #define ADPS1 1
97 #define ADPS2 2
98 #define ADIE 3
99 #define ADIF 4
100 #define ADATE 5
101 #define ADSC 6
102 #define ADEN 7
103 
104 #define ADMUX _SFR_IO8(0x07)
105 #define MUX0 0
106 #define MUX1 1
107 #define MUX2 2
108 #define MUX3 3
109 #define MUX4 4
110 #define ADLAR 5
111 #define REFS0 6
112 #define REFS1 7
113 
114 #define ACSR _SFR_IO8(0x08)
115 #define ACIS0 0
116 #define ACIS1 1
117 #define ACIC 2
118 #define ACIE 3
119 #define ACI 4
120 #define ACO 5
121 #define ACBG 6
122 #define ACD 7
123 
124 #define UBRRL _SFR_IO8(0x09)
125 
126 #define UCSRB _SFR_IO8(0x0A)
127 #define TXB8 0
128 #define RXB8 1
129 #define UCSZ2 2
130 #define TXEN 3
131 #define RXEN 4
132 #define UDRIE 5
133 #define TXCIE 6
134 #define RXCIE 7
135 
136 #define UCSRA _SFR_IO8(0x0B)
137 #define MPCM 0
138 #define U2X 1
139 #define PE 2
140 #define DOR 3
141 #define FE 4
142 #define UDRE 5
143 #define TXC 6
144 #define RXC 7
145 
146 #define UDR _SFR_IO8(0x0C)
147 
148 #define SPCR _SFR_IO8(0x0D)
149 #define SPR0 0
150 #define SPR1 1
151 #define CPHA 2
152 #define CPOL 3
153 #define MSTR 4
154 #define DORD 5
155 #define SPE 6
156 #define SPIE 7
157 
158 #define SPSR _SFR_IO8(0x0E)
159 #define SPI2X 0
160 #define WCOL 6
161 #define SPIF 7
162 
163 #define SPDR _SFR_IO8(0x0F)
164 
165 #define PIND _SFR_IO8(0x10)
166 #define PIND0 0
167 #define PIND1 1
168 #define PIND2 2
169 #define PIND3 3
170 #define PIND4 4
171 #define PIND5 5
172 #define PIND6 6
173 #define PIND7 7
174 
175 #define DDRD _SFR_IO8(0x11)
176 #define DDD0 0
177 #define DDD1 1
178 #define DDD2 2
179 #define DDD3 3
180 #define DDD4 4
181 #define DDD5 5
182 #define DDD6 6
183 #define DDD7 7
184 
185 #define PORTD _SFR_IO8(0x12)
186 #define PD0 0
187 #define PD1 1
188 #define PD2 2
189 #define PD3 3
190 #define PD4 4
191 #define PD5 5
192 #define PD6 6
193 #define PD7 7
194 
195 #define PINC _SFR_IO8(0x13)
196 #define PINC0 0
197 #define PINC1 1
198 #define PINC2 2
199 #define PINC3 3
200 #define PINC4 4
201 #define PINC5 5
202 #define PINC6 6
203 #define PINC7 7
204 
205 #define DDRC _SFR_IO8(0x14)
206 #define DDC0 0
207 #define DDC1 1
208 #define DDC2 2
209 #define DDC3 3
210 #define DDC4 4
211 #define DDC5 5
212 #define DDC6 6
213 #define DDC7 7
214 
215 #define PORTC _SFR_IO8(0x15)
216 #define PC0 0
217 #define PC1 1
218 #define PC2 2
219 #define PC3 3
220 #define PC4 4
221 #define PC5 5
222 #define PC6 6
223 #define PC7 7
224 
225 #define PINB _SFR_IO8(0x16)
226 #define PINB0 0
227 #define PINB1 1
228 #define PINB2 2
229 #define PINB3 3
230 #define PINB4 4
231 #define PINB5 5
232 #define PINB6 6
233 #define PINB7 7
234 
235 #define DDRB _SFR_IO8(0x17)
236 #define DDB0 0
237 #define DDB1 1
238 #define DDB2 2
239 #define DDB3 3
240 #define DDB4 4
241 #define DDB5 5
242 #define DDB6 6
243 #define DDB7 7
244 
245 #define PORTB _SFR_IO8(0x18)
246 #define PB0 0
247 #define PB1 1
248 #define PB2 2
249 #define PB3 3
250 #define PB4 4
251 #define PB5 5
252 #define PB6 6
253 #define PB7 7
254 
255 #define PINA _SFR_IO8(0x19)
256 #define PINA0 0
257 #define PINA1 1
258 #define PINA2 2
259 #define PINA3 3
260 #define PINA4 4
261 #define PINA5 5
262 #define PINA6 6
263 #define PINA7 7
264 
265 #define DDRA _SFR_IO8(0x1A)
266 #define DDA0 0
267 #define DDA1 1
268 #define DDA2 2
269 #define DDA3 3
270 #define DDA4 4
271 #define DDA5 5
272 #define DDA6 6
273 #define DDA7 7
274 
275 #define PORTA _SFR_IO8(0x1B)
276 #define PA0 0
277 #define PA1 1
278 #define PA2 2
279 #define PA3 3
280 #define PA4 4
281 #define PA5 5
282 #define PA6 6
283 #define PA7 7
284 
285 /* EEPROM Control Register */
286 #define EECR _SFR_IO8(0x1C)
287 #define EERE 0
288 #define EEWE 1
289 #define EEMWE 2
290 #define EERIE 3
291 
292 /* EEPROM Data Register */
293 #define EEDR _SFR_IO8(0x1D)
294 
295 /* EEPROM Address Register */
296 #define EEAR _SFR_IO16(0x1E)
297 #define EEARL _SFR_IO8(0x1E)
298 #define EEARH _SFR_IO8(0x1F)
299 
300 #define UCSRC _SFR_IO8(0x20)
301 #define UCPOL 0
302 #define UCSZ0 1
303 #define UCSZ1 2
304 #define USBS 3
305 #define UPM0 4
306 #define UPM1 5
307 #define UMSEL 6
308 #define URSEL 7
309 
310 #define UBRRH _SFR_IO8(0x20)
311 #define URSEL 7
312 
313 #define WDTCR _SFR_IO8(0x21)
314 #define WDP0 0
315 #define WDP1 1
316 #define WDP2 2
317 #define WDE 3
318 #define WDTOE 4
319 
320 #define ASSR _SFR_IO8(0x22)
321 #define TCR2UB 0
322 #define OCR2UB 1
323 #define TCN2UB 2
324 #define AS2 3
325 
326 #define OCR2 _SFR_IO8(0x23)
327 
328 #define TCNT2 _SFR_IO8(0x24)
329 
330 #define TCCR2 _SFR_IO8(0x25)
331 #define CS20 0
332 #define CS21 1
333 #define CS22 2
334 #define WGM21 3
335 #define COM20 4
336 #define COM21 5
337 #define WGM20 6
338 #define FOC2 7
339 
340 /* Combine ICR1L and ICR1H */
341 #define ICR1 _SFR_IO16(0x26)
342 
343 #define ICR1L _SFR_IO8(0x26)
344 #define ICR1H _SFR_IO8(0x27)
345 
346 /* Combine OCR1BL and OCR1BH */
347 #define OCR1B _SFR_IO16(0x28)
348 
349 #define OCR1BL _SFR_IO8(0x28)
350 #define OCR1BH _SFR_IO8(0x29)
351 
352 /* Combine OCR1AL and OCR1AH */
353 #define OCR1A _SFR_IO16(0x2A)
354 
355 #define OCR1AL _SFR_IO8(0x2A)
356 #define OCR1AH _SFR_IO8(0x2B)
357 
358 /* Combine TCNT1L and TCNT1H */
359 #define TCNT1 _SFR_IO16(0x2C)
360 
361 #define TCNT1L _SFR_IO8(0x2C)
362 #define TCNT1H _SFR_IO8(0x2D)
363 
364 #define TCCR1B _SFR_IO8(0x2E)
365 #define CS10 0
366 #define CS11 1
367 #define CS12 2
368 #define WGM12 3
369 #define WGM13 4
370 #define ICES1 6
371 #define ICNC1 7
372 
373 #define TCCR1A _SFR_IO8(0x2F)
374 #define WGM10 0
375 #define WGM11 1
376 #define FOC1B 2
377 #define FOC1A 3
378 #define COM1B0 4
379 #define COM1B1 5
380 #define COM1A0 6
381 #define COM1A1 7
382 
383 /*
384  The ADHSM bit has been removed from all documentation,
385  as being not needed at all since the comparator has proven
386  to be fast enough even without feeding it more power.
387 */
388 
389 #define SFIOR _SFR_IO8(0x30)
390 #define PSR10 0
391 #define PSR2 1
392 #define PUD 2
393 #define ACME 3
394 #define ADTS0 5
395 #define ADTS1 6
396 #define ADTS2 7
397 
398 #define OSCCAL _SFR_IO8(0x31)
399 
400 #define OCDR _SFR_IO8(0x31)
401 
402 #define TCNT0 _SFR_IO8(0x32)
403 
404 #define TCCR0 _SFR_IO8(0x33)
405 #define CS00 0
406 #define CS01 1
407 #define CS02 2
408 #define WGM01 3
409 #define COM00 4
410 #define COM01 5
411 #define WGM00 6
412 #define FOC0 7
413 
414 #define MCUCSR _SFR_IO8(0x34)
415 #define PORF 0
416 #define EXTRF 1
417 #define BORF 2
418 #define WDRF 3
419 #define JTRF 4
420 #define ISC2 6
421 #define JTD 7
422 
423 #define MCUCR _SFR_IO8(0x35)
424 #define ISC00 0
425 #define ISC01 1
426 #define ISC10 2
427 #define ISC11 3
428 #define SM0 4
429 #define SM1 5
430 #define SE 6
431 #define SM2 7
432 
433 #define TWCR _SFR_IO8(0x36)
434 #define TWIE 0
435 #define TWEN 2
436 #define TWWC 3
437 #define TWSTO 4
438 #define TWSTA 5
439 #define TWEA 6
440 #define TWINT 7
441 
442 #define SPMCR _SFR_IO8(0x37)
443 #define SPMEN 0
444 #define PGERS 1
445 #define PGWRT 2
446 #define BLBSET 3
447 #define RWWSRE 4
448 #define RWWSB 6
449 #define SPMIE 7
450 
451 #define TIFR _SFR_IO8(0x38)
452 #define TOV0 0
453 #define OCF0 1
454 #define TOV1 2
455 #define OCF1B 3
456 #define OCF1A 4
457 #define ICF1 5
458 #define TOV2 6
459 #define OCF2 7
460 
461 #define TIMSK _SFR_IO8(0x39)
462 #define TOIE0 0
463 #define OCIE0 1
464 #define TOIE1 2
465 #define OCIE1B 3
466 #define OCIE1A 4
467 #define TICIE1 5
468 #define TOIE2 6
469 #define OCIE2 7
470 
471 #define GIFR _SFR_IO8(0x3A)
472 #define INTF2 5
473 #define INTF0 6
474 #define INTF1 7
475 
476 #define GICR _SFR_IO8(0x3B)
477 #define IVCE 0
478 #define IVSEL 1
479 #define INT2 5
480 #define INT0 6
481 #define INT1 7
482 
483 #define OCR0 _SFR_IO8(0x3C)
484 
485 /* SP [0x3D..0x3E] */
486 /* SREG [0x3F] */
487 
488 
489 /* Interrupt vectors */
490 /* Vector 0 is the reset vector. */
491 /* External Interrupt Request 0 */
492 #define INT0_vect _VECTOR(1)
493 #define SIG_INTERRUPT0 _VECTOR(1)
494 
495 /* External Interrupt Request 1 */
496 #define INT1_vect _VECTOR(2)
497 #define SIG_INTERRUPT1 _VECTOR(2)
498 
499 /* Timer/Counter2 Compare Match */
500 #define TIMER2_COMP_vect _VECTOR(3)
501 #define SIG_OUTPUT_COMPARE2 _VECTOR(3)
502 
503 /* Timer/Counter2 Overflow */
504 #define TIMER2_OVF_vect _VECTOR(4)
505 #define SIG_OVERFLOW2 _VECTOR(4)
506 
507 /* Timer/Counter1 Capture Event */
508 #define TIMER1_CAPT_vect _VECTOR(5)
509 #define SIG_INPUT_CAPTURE1 _VECTOR(5)
510 
511 /* Timer/Counter1 Compare Match A */
512 #define TIMER1_COMPA_vect _VECTOR(6)
513 #define SIG_OUTPUT_COMPARE1A _VECTOR(6)
514 
515 /* Timer/Counter1 Compare Match B */
516 #define TIMER1_COMPB_vect _VECTOR(7)
517 #define SIG_OUTPUT_COMPARE1B _VECTOR(7)
518 
519 /* Timer/Counter1 Overflow */
520 #define TIMER1_OVF_vect _VECTOR(8)
521 #define SIG_OVERFLOW1 _VECTOR(8)
522 
523 /* Timer/Counter0 Overflow */
524 #define TIMER0_OVF_vect _VECTOR(9)
525 #define SIG_OVERFLOW0 _VECTOR(9)
526 
527 /* Serial Transfer Complete */
528 #define SPI_STC_vect _VECTOR(10)
529 #define SIG_SPI _VECTOR(10)
530 
531 /* USART, Rx Complete */
532 #define USART_RXC_vect _VECTOR(11)
533 #define SIG_USART_RECV _VECTOR(11)
534 #define SIG_UART_RECV _VECTOR(11)
535 
536 /* USART Data Register Empty */
537 #define USART_UDRE_vect _VECTOR(12)
538 #define SIG_USART_DATA _VECTOR(12)
539 #define SIG_UART_DATA _VECTOR(12)
540 
541 /* USART, Tx Complete */
542 #define USART_TXC_vect _VECTOR(13)
543 #define SIG_USART_TRANS _VECTOR(13)
544 #define SIG_UART_TRANS _VECTOR(13)
545 
546 /* ADC Conversion Complete */
547 #define ADC_vect _VECTOR(14)
548 #define SIG_ADC _VECTOR(14)
549 
550 /* EEPROM Ready */
551 #define EE_RDY_vect _VECTOR(15)
552 #define SIG_EEPROM_READY _VECTOR(15)
553 
554 /* Analog Comparator */
555 #define ANA_COMP_vect _VECTOR(16)
556 #define SIG_COMPARATOR _VECTOR(16)
557 
558 /* 2-wire Serial Interface */
559 #define TWI_vect _VECTOR(17)
560 #define SIG_2WIRE_SERIAL _VECTOR(17)
561 
562 /* External Interrupt Request 2 */
563 #define INT2_vect _VECTOR(18)
564 #define SIG_INTERRUPT2 _VECTOR(18)
565 
566 /* Timer/Counter0 Compare Match */
567 #define TIMER0_COMP_vect _VECTOR(19)
568 #define SIG_OUTPUT_COMPARE0 _VECTOR(19)
569 
570 /* Store Program Memory Ready */
571 #define SPM_RDY_vect _VECTOR(20)
572 #define SIG_SPM_READY _VECTOR(20)
573 
574 #define _VECTORS_SIZE 84
575 
576 
577 /* Constants */
578 #define SPM_PAGESIZE 128
579 #define RAMEND 0x45F
580 #define XRAMEND RAMEND
581 #define E2END 0x1FF
582 #define E2PAGESIZE 4
583 #define FLASHEND 0x3FFF
584 
585 
586 /* Fuses */
587 
588 #define FUSE_MEMORY_SIZE 2
589 
590 /* Low Fuse Byte */
591 #define FUSE_CKSEL0 (unsigned char)~_BV(0)
592 #define FUSE_CKSEL1 (unsigned char)~_BV(1)
593 #define FUSE_CKSEL2 (unsigned char)~_BV(2)
594 #define FUSE_CKSEL3 (unsigned char)~_BV(3)
595 #define FUSE_SUT0 (unsigned char)~_BV(4)
596 #define FUSE_SUT1 (unsigned char)~_BV(5)
597 #define FUSE_BODEN (unsigned char)~_BV(6)
598 #define FUSE_BODLEVEL (unsigned char)~_BV(7)
599 #define LFUSE_DEFAULT (FUSE_CKSEL1 & FUSE_CKSEL2 & FUSE_CKSEL3 & FUSE_SUT0)
600 
601 /* High Fuse Byte */
602 #define FUSE_BOOTRST (unsigned char)~_BV(0)
603 #define FUSE_BOOTSZ0 (unsigned char)~_BV(1)
604 #define FUSE_BOOTSZ1 (unsigned char)~_BV(2)
605 #define FUSE_EESAVE (unsigned char)~_BV(3)
606 #define FUSE_CKOPT (unsigned char)~_BV(4)
607 #define FUSE_SPIEN (unsigned char)~_BV(5)
608 #define FUSE_JTAGEN (unsigned char)~_BV(6)
609 #define FUSE_OCDEN (unsigned char)~_BV(7)
610 #define HFUSE_DEFAULT (FUSE_BOOTSZ0 & FUSE_BOOTSZ1 & FUSE_SPIEN & FUSE_JTAGEN)
611 
612 
613 /* Lock Bits */
614 #define __LOCK_BITS_EXIST
615 #define __BOOT_LOCK_BITS_0_EXIST
616 #define __BOOT_LOCK_BITS_1_EXIST
617 
618 
619 /* Signature */
620 #define SIGNATURE_0 0x1E
621 #define SIGNATURE_1 0x94
622 #define SIGNATURE_2 0x03
623 
625 #endif /* _AVR_IOM16_H_ */