RTEMS CPU Kit with SuperCore
4.11.3
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Definitions for ATmega128. More...
Go to the source code of this file.
Macros | |
#define | _AVR_IOXXX_H_ "iom128.h" |
#define | PINF _SFR_IO8(0x00) |
#define | PINE _SFR_IO8(0x01) |
#define | DDRE _SFR_IO8(0x02) |
#define | PORTE _SFR_IO8(0x03) |
#define | ADCW _SFR_IO16(0x04) /* for backwards compatibility */ |
#define | ADC _SFR_IO16(0x04) |
#define | ADCL _SFR_IO8(0x04) |
#define | ADCH _SFR_IO8(0x05) |
#define | ADCSR _SFR_IO8(0x06) |
#define | ADCSRA _SFR_IO8(0x06) /* new name in datasheet (2467E-AVR-05/02) */ |
#define | ADMUX _SFR_IO8(0x07) |
#define | ACSR _SFR_IO8(0x08) |
#define | UBRR0L _SFR_IO8(0x09) |
#define | UCSR0B _SFR_IO8(0x0A) |
#define | UCSR0A _SFR_IO8(0x0B) |
#define | UDR0 _SFR_IO8(0x0C) |
#define | SPCR _SFR_IO8(0x0D) |
#define | SPSR _SFR_IO8(0x0E) |
#define | SPDR _SFR_IO8(0x0F) |
#define | PIND _SFR_IO8(0x10) |
#define | DDRD _SFR_IO8(0x11) |
#define | PORTD _SFR_IO8(0x12) |
#define | PINC _SFR_IO8(0x13) |
#define | DDRC _SFR_IO8(0x14) |
#define | PORTC _SFR_IO8(0x15) |
#define | PINB _SFR_IO8(0x16) |
#define | DDRB _SFR_IO8(0x17) |
#define | PORTB _SFR_IO8(0x18) |
#define | PINA _SFR_IO8(0x19) |
#define | DDRA _SFR_IO8(0x1A) |
#define | PORTA _SFR_IO8(0x1B) |
#define | EECR _SFR_IO8(0x1C) |
#define | EEDR _SFR_IO8(0x1D) |
#define | EEAR _SFR_IO16(0x1E) |
#define | EEARL _SFR_IO8(0x1E) |
#define | EEARH _SFR_IO8(0x1F) |
#define | SFIOR _SFR_IO8(0x20) |
#define | WDTCR _SFR_IO8(0x21) |
#define | OCDR _SFR_IO8(0x22) |
#define | OCR2 _SFR_IO8(0x23) |
#define | TCNT2 _SFR_IO8(0x24) |
#define | TCCR2 _SFR_IO8(0x25) |
#define | ICR1 _SFR_IO16(0x26) |
#define | ICR1L _SFR_IO8(0x26) |
#define | ICR1H _SFR_IO8(0x27) |
#define | OCR1B _SFR_IO16(0x28) |
#define | OCR1BL _SFR_IO8(0x28) |
#define | OCR1BH _SFR_IO8(0x29) |
#define | OCR1A _SFR_IO16(0x2A) |
#define | OCR1AL _SFR_IO8(0x2A) |
#define | OCR1AH _SFR_IO8(0x2B) |
#define | TCNT1 _SFR_IO16(0x2C) |
#define | TCNT1L _SFR_IO8(0x2C) |
#define | TCNT1H _SFR_IO8(0x2D) |
#define | TCCR1B _SFR_IO8(0x2E) |
#define | TCCR1A _SFR_IO8(0x2F) |
#define | ASSR _SFR_IO8(0x30) |
#define | OCR0 _SFR_IO8(0x31) |
#define | TCNT0 _SFR_IO8(0x32) |
#define | TCCR0 _SFR_IO8(0x33) |
#define | MCUSR _SFR_IO8(0x34) |
#define | MCUCSR _SFR_IO8(0x34) /* new name in datasheet (2467E-AVR-05/02) */ |
#define | MCUCR _SFR_IO8(0x35) |
#define | TIFR _SFR_IO8(0x36) |
#define | TIMSK _SFR_IO8(0x37) |
#define | EIFR _SFR_IO8(0x38) |
#define | EIMSK _SFR_IO8(0x39) |
#define | EICRB _SFR_IO8(0x3A) |
#define | RAMPZ _SFR_IO8(0x3B) |
#define | XDIV _SFR_IO8(0x3C) |
#define | DDRF _SFR_MEM8(0x61) |
#define | PORTF _SFR_MEM8(0x62) |
#define | PING _SFR_MEM8(0x63) |
#define | DDRG _SFR_MEM8(0x64) |
#define | PORTG _SFR_MEM8(0x65) |
#define | SPMCR _SFR_MEM8(0x68) |
#define | SPMCSR _SFR_MEM8(0x68) /* new name in datasheet (2467E-AVR-05/02) */ |
#define | EICRA _SFR_MEM8(0x6A) |
#define | XMCRB _SFR_MEM8(0x6C) |
#define | XMCRA _SFR_MEM8(0x6D) |
#define | OSCCAL _SFR_MEM8(0x6F) |
#define | TWBR _SFR_MEM8(0x70) |
#define | TWSR _SFR_MEM8(0x71) |
#define | TWAR _SFR_MEM8(0x72) |
#define | TWDR _SFR_MEM8(0x73) |
#define | TWCR _SFR_MEM8(0x74) |
#define | OCR1C _SFR_MEM16(0x78) |
#define | OCR1CL _SFR_MEM8(0x78) |
#define | OCR1CH _SFR_MEM8(0x79) |
#define | TCCR1C _SFR_MEM8(0x7A) |
#define | ETIFR _SFR_MEM8(0x7C) |
#define | ETIMSK _SFR_MEM8(0x7D) |
#define | ICR3 _SFR_MEM16(0x80) |
#define | ICR3L _SFR_MEM8(0x80) |
#define | ICR3H _SFR_MEM8(0x81) |
#define | OCR3C _SFR_MEM16(0x82) |
#define | OCR3CL _SFR_MEM8(0x82) |
#define | OCR3CH _SFR_MEM8(0x83) |
#define | OCR3B _SFR_MEM16(0x84) |
#define | OCR3BL _SFR_MEM8(0x84) |
#define | OCR3BH _SFR_MEM8(0x85) |
#define | OCR3A _SFR_MEM16(0x86) |
#define | OCR3AL _SFR_MEM8(0x86) |
#define | OCR3AH _SFR_MEM8(0x87) |
#define | TCNT3 _SFR_MEM16(0x88) |
#define | TCNT3L _SFR_MEM8(0x88) |
#define | TCNT3H _SFR_MEM8(0x89) |
#define | TCCR3B _SFR_MEM8(0x8A) |
#define | TCCR3A _SFR_MEM8(0x8B) |
#define | TCCR3C _SFR_MEM8(0x8C) |
#define | UBRR0H _SFR_MEM8(0x90) |
#define | UCSR0C _SFR_MEM8(0x95) |
#define | UBRR1H _SFR_MEM8(0x98) |
#define | UBRR1L _SFR_MEM8(0x99) |
#define | UCSR1B _SFR_MEM8(0x9A) |
#define | UCSR1A _SFR_MEM8(0x9B) |
#define | UDR1 _SFR_MEM8(0x9C) |
#define | UCSR1C _SFR_MEM8(0x9D) |
#define | INT0_vect _VECTOR(1) |
#define | SIG_INTERRUPT0 _VECTOR(1) |
#define | INT1_vect _VECTOR(2) |
#define | SIG_INTERRUPT1 _VECTOR(2) |
#define | INT2_vect _VECTOR(3) |
#define | SIG_INTERRUPT2 _VECTOR(3) |
#define | INT3_vect _VECTOR(4) |
#define | SIG_INTERRUPT3 _VECTOR(4) |
#define | INT4_vect _VECTOR(5) |
#define | SIG_INTERRUPT4 _VECTOR(5) |
#define | INT5_vect _VECTOR(6) |
#define | SIG_INTERRUPT5 _VECTOR(6) |
#define | INT6_vect _VECTOR(7) |
#define | SIG_INTERRUPT6 _VECTOR(7) |
#define | INT7_vect _VECTOR(8) |
#define | SIG_INTERRUPT7 _VECTOR(8) |
#define | TIMER2_COMP_vect _VECTOR(9) |
#define | SIG_OUTPUT_COMPARE2 _VECTOR(9) |
#define | TIMER2_OVF_vect _VECTOR(10) |
#define | SIG_OVERFLOW2 _VECTOR(10) |
#define | TIMER1_CAPT_vect _VECTOR(11) |
#define | SIG_INPUT_CAPTURE1 _VECTOR(11) |
#define | TIMER1_COMPA_vect _VECTOR(12) |
#define | SIG_OUTPUT_COMPARE1A _VECTOR(12) |
#define | TIMER1_COMPB_vect _VECTOR(13) |
#define | SIG_OUTPUT_COMPARE1B _VECTOR(13) |
#define | TIMER1_OVF_vect _VECTOR(14) |
#define | SIG_OVERFLOW1 _VECTOR(14) |
#define | TIMER0_COMP_vect _VECTOR(15) |
#define | SIG_OUTPUT_COMPARE0 _VECTOR(15) |
#define | TIMER0_OVF_vect _VECTOR(16) |
#define | SIG_OVERFLOW0 _VECTOR(16) |
#define | SPI_STC_vect _VECTOR(17) |
#define | SIG_SPI _VECTOR(17) |
#define | USART0_RX_vect _VECTOR(18) |
#define | SIG_USART0_RECV _VECTOR(18) |
#define | SIG_UART0_RECV _VECTOR(18) |
#define | USART0_UDRE_vect _VECTOR(19) |
#define | SIG_USART0_DATA _VECTOR(19) |
#define | SIG_UART0_DATA _VECTOR(19) |
#define | USART0_TX_vect _VECTOR(20) |
#define | SIG_USART0_TRANS _VECTOR(20) |
#define | SIG_UART0_TRANS _VECTOR(20) |
#define | ADC_vect _VECTOR(21) |
#define | SIG_ADC _VECTOR(21) |
#define | EE_READY_vect _VECTOR(22) |
#define | SIG_EEPROM_READY _VECTOR(22) |
#define | ANALOG_COMP_vect _VECTOR(23) |
#define | SIG_COMPARATOR _VECTOR(23) |
#define | TIMER1_COMPC_vect _VECTOR(24) |
#define | SIG_OUTPUT_COMPARE1C _VECTOR(24) |
#define | TIMER3_CAPT_vect _VECTOR(25) |
#define | SIG_INPUT_CAPTURE3 _VECTOR(25) |
#define | TIMER3_COMPA_vect _VECTOR(26) |
#define | SIG_OUTPUT_COMPARE3A _VECTOR(26) |
#define | TIMER3_COMPB_vect _VECTOR(27) |
#define | SIG_OUTPUT_COMPARE3B _VECTOR(27) |
#define | TIMER3_COMPC_vect _VECTOR(28) |
#define | SIG_OUTPUT_COMPARE3C _VECTOR(28) |
#define | TIMER3_OVF_vect _VECTOR(29) |
#define | SIG_OVERFLOW3 _VECTOR(29) |
#define | USART1_RX_vect _VECTOR(30) |
#define | SIG_USART1_RECV _VECTOR(30) |
#define | SIG_UART1_RECV _VECTOR(30) |
#define | USART1_UDRE_vect _VECTOR(31) |
#define | SIG_USART1_DATA _VECTOR(31) |
#define | SIG_UART1_DATA _VECTOR(31) |
#define | USART1_TX_vect _VECTOR(32) |
#define | SIG_USART1_TRANS _VECTOR(32) |
#define | SIG_UART1_TRANS _VECTOR(32) |
#define | TWI_vect _VECTOR(33) |
#define | SIG_2WIRE_SERIAL _VECTOR(33) |
#define | SPM_READY_vect _VECTOR(34) |
#define | SIG_SPM_READY _VECTOR(34) |
#define | _VECTORS_SIZE 140 |
#define | TWINT 7 |
#define | TWEA 6 |
#define | TWSTA 5 |
#define | TWSTO 4 |
#define | TWWC 3 |
#define | TWEN 2 |
#define | TWIE 0 |
#define | TWA6 7 |
#define | TWA5 6 |
#define | TWA4 5 |
#define | TWA3 4 |
#define | TWA2 3 |
#define | TWA1 2 |
#define | TWA0 1 |
#define | TWGCE 0 |
#define | TWS7 7 |
#define | TWS6 6 |
#define | TWS5 5 |
#define | TWS4 4 |
#define | TWS3 3 |
#define | TWPS1 1 |
#define | TWPS0 0 |
#define | SRL2 6 |
#define | SRL1 5 |
#define | SRL0 4 |
#define | SRW01 3 |
#define | SRW00 2 |
#define | SRW11 1 |
#define | XMBK 7 |
#define | XMM2 2 |
#define | XMM1 1 |
#define | XMM0 0 |
#define | XDIVEN 7 |
#define | XDIV6 6 |
#define | XDIV5 5 |
#define | XDIV4 4 |
#define | XDIV3 3 |
#define | XDIV2 2 |
#define | XDIV1 1 |
#define | XDIV0 0 |
#define | RAMPZ0 0 |
#define | ISC31 7 |
#define | ISC30 6 |
#define | ISC21 5 |
#define | ISC20 4 |
#define | ISC11 3 |
#define | ISC10 2 |
#define | ISC01 1 |
#define | ISC00 0 |
#define | ISC71 7 |
#define | ISC70 6 |
#define | ISC61 5 |
#define | ISC60 4 |
#define | ISC51 3 |
#define | ISC50 2 |
#define | ISC41 1 |
#define | ISC40 0 |
#define | SPMIE 7 |
#define | RWWSB 6 |
#define | RWWSRE 4 |
#define | BLBSET 3 |
#define | PGWRT 2 |
#define | PGERS 1 |
#define | SPMEN 0 |
#define | INT7 7 |
#define | INT6 6 |
#define | INT5 5 |
#define | INT4 4 |
#define | INT3 3 |
#define | INT2 2 |
#define | INT1 1 |
#define | INT0 0 |
#define | INTF7 7 |
#define | INTF6 6 |
#define | INTF5 5 |
#define | INTF4 4 |
#define | INTF3 3 |
#define | INTF2 2 |
#define | INTF1 1 |
#define | INTF0 0 |
#define | OCIE2 7 |
#define | TOIE2 6 |
#define | TICIE1 5 |
#define | OCIE1A 4 |
#define | OCIE1B 3 |
#define | TOIE1 2 |
#define | OCIE0 1 |
#define | TOIE0 0 |
#define | OCF2 7 |
#define | TOV2 6 |
#define | ICF1 5 |
#define | OCF1A 4 |
#define | OCF1B 3 |
#define | TOV1 2 |
#define | OCF0 1 |
#define | TOV0 0 |
#define | TICIE3 5 |
#define | OCIE3A 4 |
#define | OCIE3B 3 |
#define | TOIE3 2 |
#define | OCIE3C 1 |
#define | OCIE1C 0 |
#define | ICF3 5 |
#define | OCF3A 4 |
#define | OCF3B 3 |
#define | TOV3 2 |
#define | OCF3C 1 |
#define | OCF1C 0 |
#define | SRE 7 |
#define | SRW 6 |
#define | SRW10 6 /* new name in datasheet (2467E-AVR-05/02) */ |
#define | SE 5 |
#define | SM1 4 |
#define | SM0 3 |
#define | SM2 2 |
#define | IVSEL 1 |
#define | IVCE 0 |
#define | JTD 7 |
#define | JTRF 4 |
#define | WDRF 3 |
#define | BORF 2 |
#define | EXTRF 1 |
#define | PORF 0 |
#define | FOC 7 |
#define | WGM0 6 |
#define | COM1 5 |
#define | COM0 4 |
#define | WGM1 3 |
#define | CS2 2 |
#define | CS1 1 |
#define | CS0 0 |
#define | FOC0 7 |
#define | WGM00 6 |
#define | COM01 5 |
#define | COM00 4 |
#define | WGM01 3 |
#define | CS02 2 |
#define | CS01 1 |
#define | CS00 0 |
#define | FOC2 7 |
#define | WGM20 6 |
#define | COM21 5 |
#define | COM20 4 |
#define | WGM21 3 |
#define | CS22 2 |
#define | CS21 1 |
#define | CS20 0 |
#define | AS0 3 |
#define | TCN0UB 2 |
#define | OCR0UB 1 |
#define | TCR0UB 0 |
#define | COMA1 7 |
#define | COMA0 6 |
#define | COMB1 5 |
#define | COMB0 4 |
#define | COMC1 3 |
#define | COMC0 2 |
#define | WGMA1 1 |
#define | WGMA0 0 |
#define | COM1A1 7 |
#define | COM1A0 6 |
#define | COM1B1 5 |
#define | COM1B0 4 |
#define | COM1C1 3 |
#define | COM1C0 2 |
#define | WGM11 1 |
#define | WGM10 0 |
#define | COM3A1 7 |
#define | COM3A0 6 |
#define | COM3B1 5 |
#define | COM3B0 4 |
#define | COM3C1 3 |
#define | COM3C0 2 |
#define | WGM31 1 |
#define | WGM30 0 |
#define | ICNC 7 |
#define | ICES 6 |
#define | WGMB3 4 |
#define | WGMB2 3 |
#define | CSB2 2 |
#define | CSB1 1 |
#define | CSB0 0 |
#define | ICNC1 7 |
#define | ICES1 6 |
#define | WGM13 4 |
#define | WGM12 3 |
#define | CS12 2 |
#define | CS11 1 |
#define | CS10 0 |
#define | ICNC3 7 |
#define | ICES3 6 |
#define | WGM33 4 |
#define | WGM32 3 |
#define | CS32 2 |
#define | CS31 1 |
#define | CS30 0 |
#define | FOCA 7 |
#define | FOCB 6 |
#define | FOCC 5 |
#define | FOC3A 7 |
#define | FOC3B 6 |
#define | FOC3C 5 |
#define | FOC1A 7 |
#define | FOC1B 6 |
#define | FOC1C 5 |
#define | IDRD 7 |
#define | OCDR7 7 |
#define | OCDR6 6 |
#define | OCDR5 5 |
#define | OCDR4 4 |
#define | OCDR3 3 |
#define | OCDR2 2 |
#define | OCDR1 1 |
#define | OCDR0 0 |
#define | WDCE 4 |
#define | WDE 3 |
#define | WDP2 2 |
#define | WDP1 1 |
#define | WDP0 0 |
#define | TSM 7 |
#define | ACME 3 |
#define | PUD 2 |
#define | PSR0 1 |
#define | PSR321 0 |
#define | SPIF 7 |
#define | WCOL 6 |
#define | SPI2X 0 |
#define | SPIE 7 |
#define | SPE 6 |
#define | DORD 5 |
#define | MSTR 4 |
#define | CPOL 3 |
#define | CPHA 2 |
#define | SPR1 1 |
#define | SPR0 0 |
#define | UMSEL 6 |
#define | UPM1 5 |
#define | UPM0 4 |
#define | USBS 3 |
#define | UCSZ1 2 |
#define | UCSZ0 1 |
#define | UCPOL 0 |
#define | UMSEL1 6 |
#define | UPM11 5 |
#define | UPM10 4 |
#define | USBS1 3 |
#define | UCSZ11 2 |
#define | UCSZ10 1 |
#define | UCPOL1 0 |
#define | UMSEL0 6 |
#define | UPM01 5 |
#define | UPM00 4 |
#define | USBS0 3 |
#define | UCSZ01 2 |
#define | UCSZ00 1 |
#define | UCPOL0 0 |
#define | RXC 7 |
#define | TXC 6 |
#define | UDRE 5 |
#define | FE 4 |
#define | DOR 3 |
#define | UPE 2 |
#define | U2X 1 |
#define | MPCM 0 |
#define | RXC1 7 |
#define | TXC1 6 |
#define | UDRE1 5 |
#define | FE1 4 |
#define | DOR1 3 |
#define | UPE1 2 |
#define | U2X1 1 |
#define | MPCM1 0 |
#define | RXC0 7 |
#define | TXC0 6 |
#define | UDRE0 5 |
#define | FE0 4 |
#define | DOR0 3 |
#define | UPE0 2 |
#define | U2X0 1 |
#define | MPCM0 0 |
#define | RXCIE 7 |
#define | TXCIE 6 |
#define | UDRIE 5 |
#define | RXEN 4 |
#define | TXEN 3 |
#define | UCSZ 2 |
#define | UCSZ2 2 /* new name in datasheet (2467E-AVR-05/02) */ |
#define | RXB8 1 |
#define | TXB8 0 |
#define | RXCIE1 7 |
#define | TXCIE1 6 |
#define | UDRIE1 5 |
#define | RXEN1 4 |
#define | TXEN1 3 |
#define | UCSZ12 2 |
#define | RXB81 1 |
#define | TXB81 0 |
#define | RXCIE0 7 |
#define | TXCIE0 6 |
#define | UDRIE0 5 |
#define | RXEN0 4 |
#define | TXEN0 3 |
#define | UCSZ02 2 |
#define | RXB80 1 |
#define | TXB80 0 |
#define | ACD 7 |
#define | ACBG 6 |
#define | ACO 5 |
#define | ACI 4 |
#define | ACIE 3 |
#define | ACIC 2 |
#define | ACIS1 1 |
#define | ACIS0 0 |
#define | ADEN 7 |
#define | ADSC 6 |
#define | ADFR 5 |
#define | ADIF 4 |
#define | ADIE 3 |
#define | ADPS2 2 |
#define | ADPS1 1 |
#define | ADPS0 0 |
#define | REFS1 7 |
#define | REFS0 6 |
#define | ADLAR 5 |
#define | MUX4 4 |
#define | MUX3 3 |
#define | MUX2 2 |
#define | MUX1 1 |
#define | MUX0 0 |
#define | PA7 7 |
#define | PA6 6 |
#define | PA5 5 |
#define | PA4 4 |
#define | PA3 3 |
#define | PA2 2 |
#define | PA1 1 |
#define | PA0 0 |
#define | DDA7 7 |
#define | DDA6 6 |
#define | DDA5 5 |
#define | DDA4 4 |
#define | DDA3 3 |
#define | DDA2 2 |
#define | DDA1 1 |
#define | DDA0 0 |
#define | PINA7 7 |
#define | PINA6 6 |
#define | PINA5 5 |
#define | PINA4 4 |
#define | PINA3 3 |
#define | PINA2 2 |
#define | PINA1 1 |
#define | PINA0 0 |
#define | PB7 7 |
#define | PB6 6 |
#define | PB5 5 |
#define | PB4 4 |
#define | PB3 3 |
#define | PB2 2 |
#define | PB1 1 |
#define | PB0 0 |
#define | DDB7 7 |
#define | DDB6 6 |
#define | DDB5 5 |
#define | DDB4 4 |
#define | DDB3 3 |
#define | DDB2 2 |
#define | DDB1 1 |
#define | DDB0 0 |
#define | PINB7 7 |
#define | PINB6 6 |
#define | PINB5 5 |
#define | PINB4 4 |
#define | PINB3 3 |
#define | PINB2 2 |
#define | PINB1 1 |
#define | PINB0 0 |
#define | PC7 7 |
#define | PC6 6 |
#define | PC5 5 |
#define | PC4 4 |
#define | PC3 3 |
#define | PC2 2 |
#define | PC1 1 |
#define | PC0 0 |
#define | DDC7 7 |
#define | DDC6 6 |
#define | DDC5 5 |
#define | DDC4 4 |
#define | DDC3 3 |
#define | DDC2 2 |
#define | DDC1 1 |
#define | DDC0 0 |
#define | PINC7 7 |
#define | PINC6 6 |
#define | PINC5 5 |
#define | PINC4 4 |
#define | PINC3 3 |
#define | PINC2 2 |
#define | PINC1 1 |
#define | PINC0 0 |
#define | PD7 7 |
#define | PD6 6 |
#define | PD5 5 |
#define | PD4 4 |
#define | PD3 3 |
#define | PD2 2 |
#define | PD1 1 |
#define | PD0 0 |
#define | DDD7 7 |
#define | DDD6 6 |
#define | DDD5 5 |
#define | DDD4 4 |
#define | DDD3 3 |
#define | DDD2 2 |
#define | DDD1 1 |
#define | DDD0 0 |
#define | PIND7 7 |
#define | PIND6 6 |
#define | PIND5 5 |
#define | PIND4 4 |
#define | PIND3 3 |
#define | PIND2 2 |
#define | PIND1 1 |
#define | PIND0 0 |
#define | PE7 7 |
#define | PE6 6 |
#define | PE5 5 |
#define | PE4 4 |
#define | PE3 3 |
#define | PE2 2 |
#define | PE1 1 |
#define | PE0 0 |
#define | DDE7 7 |
#define | DDE6 6 |
#define | DDE5 5 |
#define | DDE4 4 |
#define | DDE3 3 |
#define | DDE2 2 |
#define | DDE1 1 |
#define | DDE0 0 |
#define | PINE7 7 |
#define | PINE6 6 |
#define | PINE5 5 |
#define | PINE4 4 |
#define | PINE3 3 |
#define | PINE2 2 |
#define | PINE1 1 |
#define | PINE0 0 |
#define | PF7 7 |
#define | PF6 6 |
#define | PF5 5 |
#define | PF4 4 |
#define | PF3 3 |
#define | PF2 2 |
#define | PF1 1 |
#define | PF0 0 |
#define | DDF7 7 |
#define | DDF6 6 |
#define | DDF5 5 |
#define | DDF4 4 |
#define | DDF3 3 |
#define | DDF2 2 |
#define | DDF1 1 |
#define | DDF0 0 |
#define | PINF7 7 |
#define | PINF6 6 |
#define | PINF5 5 |
#define | PINF4 4 |
#define | PINF3 3 |
#define | PINF2 2 |
#define | PINF1 1 |
#define | PINF0 0 |
#define | PG4 4 |
#define | PG3 3 |
#define | PG2 2 |
#define | PG1 1 |
#define | PG0 0 |
#define | DDG4 4 |
#define | DDG3 3 |
#define | DDG2 2 |
#define | DDG1 1 |
#define | DDG0 0 |
#define | PING4 4 |
#define | PING3 3 |
#define | PING2 2 |
#define | PING1 1 |
#define | PING0 0 |
#define | EERIE 3 |
#define | EEMWE 2 |
#define | EEWE 1 |
#define | EERE 0 |
#define | SPM_PAGESIZE 256 |
#define | RAMEND 0x10FF /* Last On-Chip SRAM Location */ |
#define | XRAMEND 0xFFFF |
#define | E2END 0x0FFF |
#define | E2PAGESIZE 8 |
#define | FLASHEND 0x1FFFF |
#define | FUSE_MEMORY_SIZE 3 |
#define | FUSE_CKSEL0 (unsigned char)~_BV(0) |
#define | FUSE_CKSEL1 (unsigned char)~_BV(1) |
#define | FUSE_CKSEL2 (unsigned char)~_BV(2) |
#define | FUSE_CKSEL3 (unsigned char)~_BV(3) |
#define | FUSE_SUT0 (unsigned char)~_BV(4) |
#define | FUSE_SUT1 (unsigned char)~_BV(5) |
#define | FUSE_BODEN (unsigned char)~_BV(6) |
#define | FUSE_BODLEVEL (unsigned char)~_BV(7) |
#define | LFUSE_DEFAULT (FUSE_CKSEL1 & FUSE_CKSEL2 & FUSE_CKSEL3 & FUSE_SUT0) |
#define | FUSE_BOOTRST (unsigned char)~_BV(0) |
#define | FUSE_BOOTSZ0 (unsigned char)~_BV(1) |
#define | FUSE_BOOTSZ1 (unsigned char)~_BV(2) |
#define | FUSE_EESAVE (unsigned char)~_BV(3) |
#define | FUSE_CKOPT (unsigned char)~_BV(4) |
#define | FUSE_SPIEN (unsigned char)~_BV(5) |
#define | FUSE_JTAGEN (unsigned char)~_BV(6) |
#define | FUSE_OCDEN (unsigned char)~_BV(7) |
#define | HFUSE_DEFAULT (FUSE_BOOTSZ0 & FUSE_BOOTSZ1 & FUSE_SPIEN & FUSE_JTAGEN) |
#define | FUSE_WDTON (unsigned char)~_BV(0) |
#define | FUSE_M103C (unsigned char)~_BV(1) |
#define | EFUSE_DEFAULT (FUSE_M103C) |
#define | __LOCK_BITS_EXIST |
#define | __BOOT_LOCK_BITS_0_EXIST |
#define | __BOOT_LOCK_BITS_1_EXIST |
#define | SIGNATURE_0 0x1E |
#define | SIGNATURE_1 0x97 |
#define | SIGNATURE_2 0x02 |
Definitions for ATmega128.
This file should only be included from <avr/io.h>, never directly.
As of 2002-08-27: