RTEMS CPU Kit with SuperCore
4.11.3
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rtems
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rtems-release.git
4.11.3
ws-rtems
rtems-4.11.3
cpukit
score
cpu
avr
avr
iocanxx.h
Go to the documentation of this file.
1
17
/*
18
* Copyright (c) 2004,2005,2006 Colin O'Flynn <coflynn@newae.com>
19
* All rights reserved.
20
*
21
* Redistribution and use in source and binary forms, with or without
22
* modification, are permitted provided that the following conditions are met:
23
*
24
* * Redistributions of source code must retain the above copyright
25
* notice, this list of conditions and the following disclaimer.
26
*
27
* * Redistributions in binary form must reproduce the above copyright
28
* notice, this list of conditions and the following disclaimer in
29
* the documentation and/or other materials provided with the
30
* distribution.
31
*
32
* * Neither the name of the copyright holders nor the names of
33
* contributors may be used to endorse or promote products derived
34
* from this software without specific prior written permission.
35
*
36
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
37
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
38
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
39
* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
40
* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
41
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
42
* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
43
* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
44
* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
45
* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
46
* POSSIBILITY OF SUCH DAMAGE.
47
*/
48
49
#ifndef _AVR_IOCANXX_H_
50
#define _AVR_IOCANXX_H_ 1
51
59
#ifndef _AVR_IO_H_
60
# error "Include <avr/io.h> instead of this file."
61
#endif
62
63
#ifndef _AVR_IOXXX_H_
64
# define _AVR_IOXXX_H_ "iocanxx.h"
65
#else
66
# error "Attempt to include more than one <avr/ioXXX.h> file."
67
#endif
68
69
/* I/O registers and bit definitions. */
70
71
/* RegDef: Port A */
72
#define PINA _SFR_IO8(0x00)
73
#define DDRA _SFR_IO8(0x01)
74
#define PORTA _SFR_IO8(0x02)
75
76
/* RegDef: Port B */
77
#define PINB _SFR_IO8(0x03)
78
#define DDRB _SFR_IO8(0x04)
79
#define PORTB _SFR_IO8(0x05)
80
81
/* RegDef: Port C */
82
#define PINC _SFR_IO8(0x06)
83
#define DDRC _SFR_IO8(0x07)
84
#define PORTC _SFR_IO8(0x08)
85
86
/* RegDef: Port D */
87
#define PIND _SFR_IO8(0x09)
88
#define DDRD _SFR_IO8(0x0A)
89
#define PORTD _SFR_IO8(0x0B)
90
91
/* RegDef: Port E */
92
#define PINE _SFR_IO8(0x0C)
93
#define DDRE _SFR_IO8(0x0D)
94
#define PORTE _SFR_IO8(0x0E)
95
96
/* RegDef: Port F */
97
#define PINF _SFR_IO8(0x0F)
98
#define DDRF _SFR_IO8(0x10)
99
#define PORTF _SFR_IO8(0x11)
100
101
/* RegDef: Port G */
102
#define PING _SFR_IO8(0x12)
103
#define DDRG _SFR_IO8(0x13)
104
#define PORTG _SFR_IO8(0x14)
105
106
/* RegDef: Timer/Counter 0 interrupt Flag Register */
107
#define TIFR0 _SFR_IO8(0x15)
108
109
/* RegDef: Timer/Counter 1 interrupt Flag Register */
110
#define TIFR1 _SFR_IO8(0x16)
111
112
/* RegDef: Timer/Counter 2 interrupt Flag Register */
113
#define TIFR2 _SFR_IO8(0x17)
114
115
/* RegDef: Timer/Counter 3 interrupt Flag Register */
116
#define TIFR3 _SFR_IO8(0x18)
117
118
/* RegDef: External Interrupt Flag Register */
119
#define EIFR _SFR_IO8(0x1C)
120
121
/* RegDef: External Interrupt Mask Register */
122
#define EIMSK _SFR_IO8(0x1D)
123
124
/* RegDef: General Purpose I/O Register 0 */
125
#define GPIOR0 _SFR_IO8(0x1E)
126
127
/* RegDef: EEPROM Control Register */
128
#define EECR _SFR_IO8(0x1F)
129
130
/* RegDef: EEPROM Data Register */
131
#define EEDR _SFR_IO8(0x20)
132
133
/* RegDef: EEPROM Address Register */
134
#define EEAR _SFR_IO16(0x21)
135
#define EEARL _SFR_IO8(0x21)
136
#define EEARH _SFR_IO8(0x22)
137
138
/* 6-char sequence denoting where to find the EEPROM registers in memory space.
139
Adresses denoted in hex syntax with uppercase letters. Used by the EEPROM
140
subroutines.
141
First two letters: EECR address.
142
Second two letters: EEDR address.
143
Last two letters: EEAR address. */
144
#define __EEPROM_REG_LOCATIONS__ 1F2021
145
146
/* RegDef: General Timer/Counter Control Register */
147
#define GTCCR _SFR_IO8(0x23)
148
149
/* RegDef: Timer/Counter Control Register A */
150
#define TCCR0A _SFR_IO8(0x24)
151
152
/* RegDef: Timer/Counter Register */
153
#define TCNT0 _SFR_IO8(0x26)
154
155
/* RegDef: Output Compare Register A */
156
#define OCR0A _SFR_IO8(0x27)
157
158
/* RegDef: General Purpose I/O Register 1 */
159
#define GPIOR1 _SFR_IO8(0x2A)
160
161
/* RegDef: General Purpose I/O Register 2 */
162
#define GPIOR2 _SFR_IO8(0x2B)
163
164
/* RegDef: SPI Control Register */
165
#define SPCR _SFR_IO8(0x2C)
166
167
/* RegDef: SPI Status Register */
168
#define SPSR _SFR_IO8(0x2D)
169
170
/* RegDef: SPI Data Register */
171
#define SPDR _SFR_IO8(0x2E)
172
173
/* RegDef: Analog Comperator Control and Status Register */
174
#define ACSR _SFR_IO8(0x30)
175
176
/* RegDef: On-chip Debug Register */
177
#define OCDR _SFR_IO8(0x31)
178
179
/* RegDef: Sleep Mode Control Register */
180
#define SMCR _SFR_IO8(0x33)
181
182
/* RegDef: MCU Status Register */
183
#define MCUSR _SFR_IO8(0x34)
184
185
/* RegDef: MCU Control Rgeister */
186
#define MCUCR _SFR_IO8(0x35)
187
188
/* RegDef: Store Program Memory Control and Status Register */
189
#define SPMCSR _SFR_IO8(0x37)
190
191
/* RegDef: RAMPZ register. */
192
#define RAMPZ _SFR_IO8(0x3B)
193
194
/* RegDef: Watchdog Timer Control Register */
195
#define WDTCR _SFR_MEM8(0x60)
196
197
/* RegDef: Clock Prescale Register */
198
#define CLKPR _SFR_MEM8(0x61)
199
200
/* RegDef: Oscillator Calibration Register */
201
#define OSCCAL _SFR_MEM8(0x66)
202
203
/* RegDef: External Interrupt Control Register A */
204
#define EICRA _SFR_MEM8(0x69)
205
206
/* RegDef: External Interrupt Control Register B */
207
#define EICRB _SFR_MEM8(0x6A)
208
209
/* RegDef: Timer/Counter 0 Interrupt Mask Register */
210
#define TIMSK0 _SFR_MEM8(0x6E)
211
212
/* RegDef: Timer/Counter 1 Interrupt Mask Register */
213
#define TIMSK1 _SFR_MEM8(0x6F)
214
215
/* RegDef: Timer/Counter 2 Interrupt Mask Register */
216
#define TIMSK2 _SFR_MEM8(0x70)
217
218
/* RegDef: Timer/Counter 3 Interrupt Mask Register */
219
#define TIMSK3 _SFR_MEM8(0x71)
220
221
/* RegDef: External Memory Control Register A */
222
#define XMCRA _SFR_MEM8(0x74)
223
224
/* RegDef: External Memory Control Register A */
225
#define XMCRB _SFR_MEM8(0x75)
226
227
/* RegDef: ADC Data Register */
228
#ifndef __ASSEMBLER__
229
#define ADC _SFR_MEM16(0x78)
230
#endif
231
#define ADCW _SFR_MEM16(0x78)
232
#define ADCL _SFR_MEM8(0x78)
233
#define ADCH _SFR_MEM8(0x79)
234
235
/* RegDef: ADC Control and Status Register A */
236
#define ADCSRA _SFR_MEM8(0x7A)
237
238
/* RegDef: ADC Control and Status Register B */
239
#define ADCSRB _SFR_MEM8(0x7B)
240
241
/* RegDef: ADC Multiplex Selection Register */
242
#define ADMUX _SFR_MEM8(0x7C)
243
244
/* RegDef: Digital Input Disable Register 0 */
245
#define DIDR0 _SFR_MEM8(0x7E)
246
247
/* RegDef: Digital Input Disable Register 1 */
248
#define DIDR1 _SFR_MEM8(0x7F)
249
250
/* RegDef: Timer/Counter1 Control Register A */
251
#define TCCR1A _SFR_MEM8(0x80)
252
253
/* RegDef: Timer/Counter1 Control Register B */
254
#define TCCR1B _SFR_MEM8(0x81)
255
256
/* RegDef: Timer/Counter1 Control Register C */
257
#define TCCR1C _SFR_MEM8(0x82)
258
259
/* RegDef: Timer/Counter1 Register */
260
#define TCNT1 _SFR_MEM16(0x84)
261
#define TCNT1L _SFR_MEM8(0x84)
262
#define TCNT1H _SFR_MEM8(0x85)
263
264
/* RegDef: Timer/Counter1 Input Capture Register */
265
#define ICR1 _SFR_MEM16(0x86)
266
#define ICR1L _SFR_MEM8(0x86)
267
#define ICR1H _SFR_MEM8(0x87)
268
269
/* RegDef: Timer/Counter1 Output Compare Register A */
270
#define OCR1A _SFR_MEM16(0x88)
271
#define OCR1AL _SFR_MEM8(0x88)
272
#define OCR1AH _SFR_MEM8(0x89)
273
274
/* RegDef: Timer/Counter1 Output Compare Register B */
275
#define OCR1B _SFR_MEM16(0x8A)
276
#define OCR1BL _SFR_MEM8(0x8A)
277
#define OCR1BH _SFR_MEM8(0x8B)
278
279
/* RegDef: Timer/Counter1 Output Compare Register C */
280
#define OCR1C _SFR_MEM16(0x8C)
281
#define OCR1CL _SFR_MEM8(0x8C)
282
#define OCR1CH _SFR_MEM8(0x8D)
283
284
/* RegDef: Timer/Counter3 Control Register A */
285
#define TCCR3A _SFR_MEM8(0x90)
286
287
/* RegDef: Timer/Counter3 Control Register B */
288
#define TCCR3B _SFR_MEM8(0x91)
289
290
/* RegDef: Timer/Counter3 Control Register C */
291
#define TCCR3C _SFR_MEM8(0x92)
292
293
/* RegDef: Timer/Counter3 Register */
294
#define TCNT3 _SFR_MEM16(0x94)
295
#define TCNT3L _SFR_MEM8(0x94)
296
#define TCNT3H _SFR_MEM8(0x95)
297
298
/* RegDef: Timer/Counter3 Input Capture Register */
299
#define ICR3 _SFR_MEM16(0x96)
300
#define ICR3L _SFR_MEM8(0x96)
301
#define ICR3H _SFR_MEM8(0x97)
302
303
/* RegDef: Timer/Counter3 Output Compare Register A */
304
#define OCR3A _SFR_MEM16(0x98)
305
#define OCR3AL _SFR_MEM8(0x98)
306
#define OCR3AH _SFR_MEM8(0x99)
307
308
/* RegDef: Timer/Counter3 Output Compare Register B */
309
#define OCR3B _SFR_MEM16(0x9A)
310
#define OCR3BL _SFR_MEM8(0x9A)
311
#define OCR3BH _SFR_MEM8(0x9B)
312
313
/* RegDef: Timer/Counter3 Output Compare Register C */
314
#define OCR3C _SFR_MEM16(0x9C)
315
#define OCR3CL _SFR_MEM8(0x9C)
316
#define OCR3CH _SFR_MEM8(0x9D)
317
318
/* RegDef: Timer/Counter2 Control Register A */
319
#define TCCR2A _SFR_MEM8(0xB0)
320
321
/* RegDef: Timer/Counter2 Register */
322
#define TCNT2 _SFR_MEM8(0xB2)
323
324
/* RegDef: Timer/Counter2 Output Compare Register */
325
#define OCR2A _SFR_MEM8(0xB3)
326
327
/* RegDef: Asynchronous Status Register */
328
#define ASSR _SFR_MEM8(0xB6)
329
330
/* RegDef: TWI Bit Rate Register */
331
#define TWBR _SFR_MEM8(0xB8)
332
333
/* RegDef: TWI Status Register */
334
#define TWSR _SFR_MEM8(0xB9)
335
336
/* RegDef: TWI (Slave) Address Register */
337
#define TWAR _SFR_MEM8(0xBA)
338
339
/* RegDef: TWI Data Register */
340
#define TWDR _SFR_MEM8(0xBB)
341
342
/* RegDef: TWI Control Register */
343
#define TWCR _SFR_MEM8(0xBC)
344
345
/* RegDef: USART0 Control and Status Register A */
346
#define UCSR0A _SFR_MEM8(0xC0)
347
348
/* RegDef: USART0 Control and Status Register B */
349
#define UCSR0B _SFR_MEM8(0xC1)
350
351
/* RegDef: USART0 Control and Status Register C */
352
#define UCSR0C _SFR_MEM8(0xC2)
353
354
/* RegDef: USART0 Baud Rate Register */
355
#define UBRR0 _SFR_MEM16(0xC4)
356
#define UBRR0L _SFR_MEM8(0xC4)
357
#define UBRR0H _SFR_MEM8(0xC5)
358
359
/* RegDef: USART0 I/O Data Register */
360
#define UDR0 _SFR_MEM8(0xC6)
361
362
/* RegDef: USART1 Control and Status Register A */
363
#define UCSR1A _SFR_MEM8(0xC8)
364
365
/* RegDef: USART1 Control and Status Register B */
366
#define UCSR1B _SFR_MEM8(0xC9)
367
368
/* RegDef: USART1 Control and Status Register C */
369
#define UCSR1C _SFR_MEM8(0xCA)
370
371
/* RegDef: USART1 Baud Rate Register */
372
#define UBRR1 _SFR_MEM16(0xCC)
373
#define UBRR1L _SFR_MEM8(0xCC)
374
#define UBRR1H _SFR_MEM8(0xCD)
375
376
/* RegDef: USART1 I/O Data Register */
377
#define UDR1 _SFR_MEM8(0xCE)
378
379
/* RegDef: CAN General Control Register*/
380
#define CANGCON _SFR_MEM8(0xD8)
381
382
/* RegDef: CAN General Status Register*/
383
#define CANGSTA _SFR_MEM8(0xD9)
384
385
/* RegDef: CAN General Interrupt Register*/
386
#define CANGIT _SFR_MEM8(0xDA)
387
388
/* RegDef: CAN General Interrupt Enable Register*/
389
#define CANGIE _SFR_MEM8(0xDB)
390
391
/* RegDef: CAN Enable MOb Register*/
392
#define CANEN2 _SFR_MEM8(0xDC)
393
394
/* RegDef: CAN Enable MOb Register*/
395
#define CANEN1 _SFR_MEM8(0xDD)
396
397
/* RegDef: CAN Enable Interrupt MOb Register*/
398
#define CANIE2 _SFR_MEM8(0xDE)
399
400
/* RegDef: CAN Enable Interrupt MOb Register*/
401
#define CANIE1 _SFR_MEM8(0xDF)
402
403
/* RegDef: CAN Status Interrupt MOb Register*/
404
/*
405
* WARNING: Do not apply the SIT8...SIT14 constants to bits in the CANSIT
406
* register.
407
*/
408
#define CANSIT _SFR_MEM16(0xE0)
409
#define CANSIT2 _SFR_MEM8(0xE0)
410
#define CANSIT1 _SFR_MEM8(0xE1)
411
412
/* RegDef: CAN Bit Timing Register 1*/
413
#define CANBT1 _SFR_MEM8(0xE2)
414
415
/* RegDef: CAN Bit Timing Register 2*/
416
#define CANBT2 _SFR_MEM8(0xE3)
417
418
/* RegDef: CAN Bit Timing Register 3*/
419
#define CANBT3 _SFR_MEM8(0xE4)
420
421
/* RegDef: CAN Timer Control Register*/
422
#define CANTCON _SFR_MEM8(0xE5)
423
424
/* RegDef: CAN Timer Register*/
425
#define CANTIM _SFR_MEM16(0xE6)
426
#define CANTIML _SFR_MEM8(0xE6)
427
#define CANTIMH _SFR_MEM8(0xE7)
428
429
/* RegDef: CAN TTC Timer Register*/
430
#define CANTTC _SFR_MEM16(0xE8)
431
#define CANTTCL _SFR_MEM8(0xE8)
432
#define CANTTCH _SFR_MEM8(0xE9)
433
434
/* RegDef: CAN Transmitt Error Counter Register*/
435
#define CANTEC _SFR_MEM8(0xEA)
436
437
/* RegDef: CAN Receive Error Counter Register*/
438
#define CANREC _SFR_MEM8(0xEB)
439
440
/* RegDef: CAN Highest Priority MOb Register*/
441
#define CANHPMOB _SFR_MEM8(0xEC)
442
443
/* RegDef: CAN Page MOb Register*/
444
#define CANPAGE _SFR_MEM8(0xED)
445
446
/* RegDef: CAN MOb Status Register*/
447
#define CANSTMOB _SFR_MEM8(0xEE)
448
449
/* RegDef: CAN MOb Control and DLC Register*/
450
#define CANCDMOB _SFR_MEM8(0xEF)
451
452
/* RegDef: CAN Identifier Tag Registers*/
453
#define CANIDT _SFR_MEM32(0xF0)
454
455
#define CANIDT4 _SFR_MEM8(0xF0)
456
#define CANIDT3 _SFR_MEM8(0xF1)
457
#define CANIDT2 _SFR_MEM8(0xF2)
458
#define CANIDT1 _SFR_MEM8(0xF3)
459
460
/* RegDef: CAN Identifier Mask Registers */
461
#define CANIDM _SFR_MEM32(0xF4)
462
463
#define CANIDM4 _SFR_MEM8(0xF4)
464
#define CANIDM3 _SFR_MEM8(0xF5)
465
#define CANIDM2 _SFR_MEM8(0xF6)
466
#define CANIDM1 _SFR_MEM8(0xF7)
467
468
/* RegDef: CAN TTC Timer Register*/
469
#define CANSTM _SFR_MEM16(0xF8)
470
#define CANSTML _SFR_MEM8(0xF8)
471
#define CANSTMH _SFR_MEM8(0xF9)
472
473
/* RegDef: CAN Message Register*/
474
#define CANMSG _SFR_MEM8(0xFA)
475
476
/* Interrupt vectors */
477
478
/* External Interrupt Request 0 */
479
#define INT0_vect _VECTOR(1)
480
#define SIG_INTERRUPT0 _VECTOR(1)
481
482
/* External Interrupt Request 1 */
483
#define INT1_vect _VECTOR(2)
484
#define SIG_INTERRUPT1 _VECTOR(2)
485
486
/* External Interrupt Request 2 */
487
#define INT2_vect _VECTOR(3)
488
#define SIG_INTERRUPT2 _VECTOR(3)
489
490
/* External Interrupt Request 3 */
491
#define INT3_vect _VECTOR(4)
492
#define SIG_INTERRUPT3 _VECTOR(4)
493
494
/* External Interrupt Request 4 */
495
#define INT4_vect _VECTOR(5)
496
#define SIG_INTERRUPT4 _VECTOR(5)
497
498
/* External Interrupt Request 5 */
499
#define INT5_vect _VECTOR(6)
500
#define SIG_INTERRUPT5 _VECTOR(6)
501
502
/* External Interrupt Request 6 */
503
#define INT6_vect _VECTOR(7)
504
#define SIG_INTERRUPT6 _VECTOR(7)
505
506
/* External Interrupt Request 7 */
507
#define INT7_vect _VECTOR(8)
508
#define SIG_INTERRUPT7 _VECTOR(8)
509
510
/* Timer/Counter2 Compare Match */
511
#define TIMER2_COMP_vect _VECTOR(9)
512
#define SIG_OUTPUT_COMPARE2 _VECTOR(9)
513
514
/* Timer/Counter2 Overflow */
515
#define TIMER2_OVF_vect _VECTOR(10)
516
#define SIG_OVERFLOW2 _VECTOR(10)
517
518
/* Timer/Counter1 Capture Event */
519
#define TIMER1_CAPT_vect _VECTOR(11)
520
#define SIG_INPUT_CAPTURE1 _VECTOR(11)
521
522
/* Timer/Counter1 Compare Match A */
523
#define TIMER1_COMPA_vect _VECTOR(12)
524
#define SIG_OUTPUT_COMPARE1A _VECTOR(12)
525
526
/* Timer/Counter Compare Match B */
527
#define TIMER1_COMPB_vect _VECTOR(13)
528
#define SIG_OUTPUT_COMPARE1B _VECTOR(13)
529
530
/* Timer/Counter1 Compare Match C */
531
#define TIMER1_COMPC_vect _VECTOR(14)
532
#define SIG_OUTPUT_COMPARE1C _VECTOR(14)
533
534
/* Timer/Counter1 Overflow */
535
#define TIMER1_OVF_vect _VECTOR(15)
536
#define SIG_OVERFLOW1 _VECTOR(15)
537
538
/* Timer/Counter0 Compare Match */
539
#define TIMER0_COMP_vect _VECTOR(16)
540
#define SIG_OUTPUT_COMPARE0 _VECTOR(16)
541
542
/* Timer/Counter0 Overflow */
543
#define TIMER0_OVF_vect _VECTOR(17)
544
#define SIG_OVERFLOW0 _VECTOR(17)
545
546
/* CAN Transfer Complete or Error */
547
#define CANIT_vect _VECTOR(18)
548
#define SIG_CAN_INTERRUPT1 _VECTOR(18)
549
550
/* CAN Timer Overrun */
551
#define OVRIT_vect _VECTOR(19)
552
#define SIG_CAN_OVERFLOW1 _VECTOR(19)
553
554
/* SPI Serial Transfer Complete */
555
#define SPI_STC_vect _VECTOR(20)
556
#define SIG_SPI _VECTOR(20)
557
558
/* USART0, Rx Complete */
559
#define USART0_RX_vect _VECTOR(21)
560
#define SIG_UART0_RECV _VECTOR(21)
561
#define SIG_USART0_RECV _VECTOR(21)
562
563
/* USART0 Data Register Empty */
564
#define USART0_UDRE_vect _VECTOR(22)
565
#define SIG_UART0_DATA _VECTOR(22)
566
#define SIG_USART0_DATA _VECTOR(22)
567
568
/* USART0, Tx Complete */
569
#define USART0_TX_vect _VECTOR(23)
570
#define SIG_UART0_TRANS _VECTOR(23)
571
#define SIG_USART0_TRANS _VECTOR(23)
572
573
/* Analog Comparator */
574
#define ANALOG_COMP_vect _VECTOR(24)
575
#define SIG_COMPARATOR _VECTOR(24)
576
577
/* ADC Conversion Complete */
578
#define ADC_vect _VECTOR(25)
579
#define SIG_ADC _VECTOR(25)
580
581
/* EEPROM Ready */
582
#define EE_READY_vect _VECTOR(26)
583
#define SIG_EEPROM_READY _VECTOR(26)
584
585
/* Timer/Counter3 Capture Event */
586
#define TIMER3_CAPT_vect _VECTOR(27)
587
#define SIG_INPUT_CAPTURE3 _VECTOR(27)
588
589
/* Timer/Counter3 Compare Match A */
590
#define TIMER3_COMPA_vect _VECTOR(28)
591
#define SIG_OUTPUT_COMPARE3A _VECTOR(28)
592
593
/* Timer/Counter3 Compare Match B */
594
#define TIMER3_COMPB_vect _VECTOR(29)
595
#define SIG_OUTPUT_COMPARE3B _VECTOR(29)
596
597
/* Timer/Counter3 Compare Match C */
598
#define TIMER3_COMPC_vect _VECTOR(30)
599
#define SIG_OUTPUT_COMPARE3C _VECTOR(30)
600
601
/* Timer/Counter3 Overflow */
602
#define TIMER3_OVF_vect _VECTOR(31)
603
#define SIG_OVERFLOW3 _VECTOR(31)
604
605
/* USART1, Rx Complete */
606
#define USART1_RX_vect _VECTOR(32)
607
#define SIG_UART1_RECV _VECTOR(32)
608
#define SIG_USART1_RECV _VECTOR(32)
609
610
/* USART1, Data Register Empty */
611
#define USART1_UDRE_vect _VECTOR(33)
612
#define SIG_UART1_DATA _VECTOR(33)
613
#define SIG_USART1_DATA _VECTOR(33)
614
615
/* USART1, Tx Complete */
616
#define USART1_TX_vect _VECTOR(34)
617
#define SIG_UART1_TRANS _VECTOR(34)
618
#define SIG_USART1_TRANS _VECTOR(34)
619
620
/* 2-wire Serial Interface */
621
#define TWI_vect _VECTOR(35)
622
#define SIG_2WIRE_SERIAL _VECTOR(35)
623
624
/* Store Program Memory Read */
625
#define SPM_READY_vect _VECTOR(36)
626
#define SIG_SPM_READY _VECTOR(36)
627
628
#define _VECTORS_SIZE 148
629
630
/* The Register Bit names are represented by their bit number (0-7). */
631
632
/* Register Bits [ASSR] */
633
/* Asynchronous Status Register */
634
#define EXCLK 4
635
#define AS2 3
636
#define TCN2UB 2
637
#define OCR2UB 1
638
#define TCR2UB 0
639
/* End Register Bits */
640
641
/* Register Bits [TWCR] */
642
/* 2-wire Control Register - TWCR */
643
#define TWINT 7
644
#define TWEA 6
645
#define TWSTA 5
646
#define TWSTO 4
647
#define TWWC 3
648
#define TWEN 2
649
#define TWIE 0
650
/* End Register Bits */
651
652
/* Register Bits [TWAR] */
653
/* 2-wire Address Register - TWAR */
654
#define TWA6 7
655
#define TWA5 6
656
#define TWA4 5
657
#define TWA3 4
658
#define TWA2 3
659
#define TWA1 2
660
#define TWA0 1
661
#define TWGCE 0
662
/* End Register Bits */
663
664
/* Register Bits [TWSR] */
665
/* 2-wire Status Register - TWSR */
666
#define TWS7 7
667
#define TWS6 6
668
#define TWS5 5
669
#define TWS4 4
670
#define TWS3 3
671
#define TWPS1 1
672
#define TWPS0 0
673
/* End Register Bits */
674
675
/* Register Bits [XMCRB] */
676
/* External Memory Control Register B - XMCRB */
677
#define XMBK 7
678
#define XMM2 2
679
#define XMM1 1
680
#define XMM0 0
681
/* End Register Bits */
682
683
/* Register Bits [XMCRA] */
684
/* External Memory Control Register A - XMCRA */
685
#define SRE 7
686
#define SRL2 6
687
#define SRL1 5
688
#define SRL0 4
689
#define SRW11 3
690
#define SRW10 2
691
#define SRW01 1
692
#define SRW00 0
693
/* End Register Bits */
694
695
/* Register Bits [RAMPZ] */
696
/* RAM Page Z select register - RAMPZ */
697
#define RAMPZ0 0
698
/* End Register Bits */
699
700
/* Register Bits [EICRA] */
701
/* External Interrupt Control Register A - EICRA */
702
#define ISC31 7
703
#define ISC30 6
704
#define ISC21 5
705
#define ISC20 4
706
#define ISC11 3
707
#define ISC10 2
708
#define ISC01 1
709
#define ISC00 0
710
/* End Register Bits */
711
712
/* Register Bits [EICRB] */
713
/* External Interrupt Control Register B - EICRB */
714
#define ISC71 7
715
#define ISC70 6
716
#define ISC61 5
717
#define ISC60 4
718
#define ISC51 3
719
#define ISC50 2
720
#define ISC41 1
721
#define ISC40 0
722
/* End Register Bits */
723
724
/* Register Bits [SPMCSR] */
725
/* Store Program Memory Control Register - SPMCSR, SPMCR */
726
#define SPMIE 7
727
#define RWWSB 6
728
#define RWWSRE 4
729
#define BLBSET 3
730
#define PGWRT 2
731
#define PGERS 1
732
#define SPMEN 0
733
/* End Register Bits */
734
735
/* Register Bits [EIMSK] */
736
/* External Interrupt MaSK register - EIMSK */
737
#define INT7 7
738
#define INT6 6
739
#define INT5 5
740
#define INT4 4
741
#define INT3 3
742
#define INT2 2
743
#define INT1 1
744
#define INT0 0
745
/* End Register Bits */
746
747
/* Register Bits [EIFR] */
748
/* External Interrupt Flag Register - EIFR */
749
#define INTF7 7
750
#define INTF6 6
751
#define INTF5 5
752
#define INTF4 4
753
#define INTF3 3
754
#define INTF2 2
755
#define INTF1 1
756
#define INTF0 0
757
/* End Register Bits */
758
759
/* Register Bits [TCCR2] */
760
/* Timer/Counter 2 Control Register - TCCR2 */
761
#define FOC2A 7
762
#define WGM20 6
763
#define COM2A1 5
764
#define COM2A0 4
765
#define WGM21 3
766
#define CS22 2
767
#define CS21 1
768
#define CS20 0
769
/* End Register Bits */
770
771
/* Register Bits [TCCR1A] */
772
/* Timer/Counter 1 Control and Status Register A - TCCR1A */
773
#define COM1A1 7
774
#define COM1A0 6
775
#define COM1B1 5
776
#define COM1B0 4
777
#define COM1C1 3
778
#define COM1C0 2
779
#define WGM11 1
780
#define WGM10 0
781
/* End Register Bits */
782
783
/* Register Bits [TCCR3A] */
784
/* Timer/Counter 3 Control and Status Register A - TCCR3A */
785
#define COM3A1 7
786
#define COM3A0 6
787
#define COM3B1 5
788
#define COM3B0 4
789
#define COM3C1 3
790
#define COM3C0 2
791
#define WGM31 1
792
#define WGM30 0
793
/* End Register Bits */
794
795
/* Register Bits [TCCR1B] */
796
/* Timer/Counter 1 Control and Status Register B - TCCR1B */
797
#define ICNC1 7
798
#define ICES1 6
799
#define WGM13 4
800
#define WGM12 3
801
#define CS12 2
802
#define CS11 1
803
#define CS10 0
804
/* End Register Bits */
805
806
/* Register Bits [TCCR3B] */
807
/* Timer/Counter 3 Control and Status Register B - TCCR3B */
808
#define ICNC3 7
809
#define ICES3 6
810
#define WGM33 4
811
#define WGM32 3
812
#define CS32 2
813
#define CS31 1
814
#define CS30 0
815
/* End Register Bits */
816
817
/* Register Bits [TCCR3C] */
818
/* Timer/Counter 3 Control Register C - TCCR3C */
819
#define FOC3A 7
820
#define FOC3B 6
821
#define FOC3C 5
822
/* End Register Bits */
823
824
/* Register Bits [TCCR1C] */
825
/* Timer/Counter 1 Control Register C - TCCR1C */
826
#define FOC1A 7
827
#define FOC1B 6
828
#define FOC1C 5
829
/* End Register Bits */
830
831
/* Register Bits [OCDR] */
832
/* On-chip Debug Register - OCDR */
833
#define IDRD 7
834
#define OCDR7 7
835
#define OCDR6 6
836
#define OCDR5 5
837
#define OCDR4 4
838
#define OCDR3 3
839
#define OCDR2 2
840
#define OCDR1 1
841
#define OCDR0 0
842
/* End Register Bits */
843
844
/* Register Bits [WDTCR] */
845
/* Watchdog Timer Control Register - WDTCR */
846
#define WDCE 4
847
#define WDE 3
848
#define WDP2 2
849
#define WDP1 1
850
#define WDP0 0
851
/* End Register Bits */
852
853
/* Register Bits [SPSR] */
854
/* SPI Status Register - SPSR */
855
#define SPIF 7
856
#define WCOL 6
857
#define SPI2X 0
858
/* End Register Bits */
859
860
/* Register Bits [SPCR] */
861
/* SPI Control Register - SPCR */
862
#define SPIE 7
863
#define SPE 6
864
#define DORD 5
865
#define MSTR 4
866
#define CPOL 3
867
#define CPHA 2
868
#define SPR1 1
869
#define SPR0 0
870
/* End Register Bits */
871
872
/* Register Bits [UCSR1C] */
873
/* USART1 Register C - UCSR1C */
874
#define UMSEL1 6
875
#define UPM11 5
876
#define UPM10 4
877
#define USBS1 3
878
#define UCSZ11 2
879
#define UCSZ10 1
880
#define UCPOL1 0
881
/* End Register Bits */
882
883
/* Register Bits [UCSR0C] */
884
/* USART0 Register C - UCSR0C */
885
#define UMSEL0 6
886
#define UPM01 5
887
#define UPM00 4
888
#define USBS0 3
889
#define UCSZ01 2
890
#define UCSZ00 1
891
#define UCPOL0 0
892
/* End Register Bits */
893
894
/* Register Bits [UCSR1A] */
895
/* USART1 Status Register A - UCSR1A */
896
#define RXC1 7
897
#define TXC1 6
898
#define UDRE1 5
899
#define FE1 4
900
#define DOR1 3
901
#define UPE1 2
902
#define U2X1 1
903
#define MPCM1 0
904
/* End Register Bits */
905
906
/* Register Bits [UCSR0A] */
907
/* USART0 Status Register A - UCSR0A */
908
#define RXC0 7
909
#define TXC0 6
910
#define UDRE0 5
911
#define FE0 4
912
#define DOR0 3
913
#define UPE0 2
914
#define U2X0 1
915
#define MPCM0 0
916
/* End Register Bits */
917
918
/* Register Bits [UCSR1B] */
919
/* USART1 Control Register B - UCSR1B */
920
#define RXCIE1 7
921
#define TXCIE1 6
922
#define UDRIE1 5
923
#define RXEN1 4
924
#define TXEN1 3
925
#define UCSZ12 2
926
#define RXB81 1
927
#define TXB81 0
928
/* End Register Bits */
929
930
/* Register Bits [UCSR0B] */
931
/* USART0 Control Register B - UCSR0B */
932
#define RXCIE0 7
933
#define TXCIE0 6
934
#define UDRIE0 5
935
#define RXEN0 4
936
#define TXEN0 3
937
#define UCSZ02 2
938
#define RXB80 1
939
#define TXB80 0
940
/* End Register Bits */
941
942
/* Register Bits [ACSR] */
943
/* Analog Comparator Control and Status Register - ACSR */
944
#define ACD 7
945
#define ACBG 6
946
#define ACO 5
947
#define ACI 4
948
#define ACIE 3
949
#define ACIC 2
950
#define ACIS1 1
951
#define ACIS0 0
952
/* End Register Bits */
953
954
/* Register Bits [ADCSRA] */
955
/* ADC Control and status register - ADCSRA */
956
#define ADEN 7
957
#define ADSC 6
958
#define ADATE 5
959
#define ADIF 4
960
#define ADIE 3
961
#define ADPS2 2
962
#define ADPS1 1
963
#define ADPS0 0
964
/* End Register Bits */
965
966
/*
967
The ADHSM bit has been removed from all documentation,
968
as being not needed at all since the comparator has proven
969
to be fast enough even without feeding it more power.
970
*/
971
972
/* Register Bits [ADCSRB] */
973
/* ADC Control and status register - ADCSRB */
974
#define ACME 6
975
#define ADTS2 2
976
#define ADTS1 1
977
#define ADTS0 0
978
/* End Register Bits */
979
980
/* Register Bits [ADMUX] */
981
/* ADC Multiplexer select - ADMUX */
982
#define REFS1 7
983
#define REFS0 6
984
#define ADLAR 5
985
#define MUX4 4
986
#define MUX3 3
987
#define MUX2 2
988
#define MUX1 1
989
#define MUX0 0
990
/* End Register Bits */
991
992
/* Register Bits [DIDR0] */
993
/* Digital Input Disable Register 0 */
994
#define ADC7D 7
995
#define ADC6D 6
996
#define ADC5D 5
997
#define ADC4D 4
998
#define ADC3D 3
999
#define ADC2D 2
1000
#define ADC1D 1
1001
#define ADC0D 0
1002
/* End Register Bits */
1003
1004
/* Register Bits [DIDR1] */
1005
/* Digital Input Disable Register 1 */
1006
#define AIN1D 1
1007
#define AIN0D 0
1008
/* End Register Bits */
1009
1010
/* Register Bits [PORTA] */
1011
/* Port A Data Register - PORTA */
1012
#define PA7 7
1013
#define PA6 6
1014
#define PA5 5
1015
#define PA4 4
1016
#define PA3 3
1017
#define PA2 2
1018
#define PA1 1
1019
#define PA0 0
1020
/* End Register Bits */
1021
1022
/* Register Bits [DDRA] */
1023
/* Port A Data Direction Register - DDRA */
1024
#define DDA7 7
1025
#define DDA6 6
1026
#define DDA5 5
1027
#define DDA4 4
1028
#define DDA3 3
1029
#define DDA2 2
1030
#define DDA1 1
1031
#define DDA0 0
1032
/* End Register Bits */
1033
1034
/* Register Bits [PINA] */
1035
/* Port A Input Pins - PINA */
1036
#define PINA7 7
1037
#define PINA6 6
1038
#define PINA5 5
1039
#define PINA4 4
1040
#define PINA3 3
1041
#define PINA2 2
1042
#define PINA1 1
1043
#define PINA0 0
1044
/* End Register Bits */
1045
1046
/* Register Bits [PORTB] */
1047
/* Port B Data Register - PORTB */
1048
#define PB7 7
1049
#define PB6 6
1050
#define PB5 5
1051
#define PB4 4
1052
#define PB3 3
1053
#define PB2 2
1054
#define PB1 1
1055
#define PB0 0
1056
/* End Register Bits */
1057
1058
/* Register Bits [DDRB] */
1059
/* Port B Data Direction Register - DDRB */
1060
#define DDB7 7
1061
#define DDB6 6
1062
#define DDB5 5
1063
#define DDB4 4
1064
#define DDB3 3
1065
#define DDB2 2
1066
#define DDB1 1
1067
#define DDB0 0
1068
/* End Register Bits */
1069
1070
/* Register Bits [PINB] */
1071
/* Port B Input Pins - PINB */
1072
#define PINB7 7
1073
#define PINB6 6
1074
#define PINB5 5
1075
#define PINB4 4
1076
#define PINB3 3
1077
#define PINB2 2
1078
#define PINB1 1
1079
#define PINB0 0
1080
/* End Register Bits */
1081
1082
/* Register Bits [PORTC] */
1083
/* Port C Data Register - PORTC */
1084
#define PC7 7
1085
#define PC6 6
1086
#define PC5 5
1087
#define PC4 4
1088
#define PC3 3
1089
#define PC2 2
1090
#define PC1 1
1091
#define PC0 0
1092
/* End Register Bits */
1093
1094
/* Register Bits [DDRC] */
1095
/* Port C Data Direction Register - DDRC */
1096
#define DDC7 7
1097
#define DDC6 6
1098
#define DDC5 5
1099
#define DDC4 4
1100
#define DDC3 3
1101
#define DDC2 2
1102
#define DDC1 1
1103
#define DDC0 0
1104
/* End Register Bits */
1105
1106
/* Register Bits [PINC] */
1107
/* Port C Input Pins - PINC */
1108
#define PINC7 7
1109
#define PINC6 6
1110
#define PINC5 5
1111
#define PINC4 4
1112
#define PINC3 3
1113
#define PINC2 2
1114
#define PINC1 1
1115
#define PINC0 0
1116
/* End Register Bits */
1117
1118
/* Register Bits [PORTD] */
1119
/* Port D Data Register - PORTD */
1120
#define PD7 7
1121
#define PD6 6
1122
#define PD5 5
1123
#define PD4 4
1124
#define PD3 3
1125
#define PD2 2
1126
#define PD1 1
1127
#define PD0 0
1128
/* End Register Bits */
1129
1130
/* Register Bits [DDRD] */
1131
/* Port D Data Direction Register - DDRD */
1132
#define DDD7 7
1133
#define DDD6 6
1134
#define DDD5 5
1135
#define DDD4 4
1136
#define DDD3 3
1137
#define DDD2 2
1138
#define DDD1 1
1139
#define DDD0 0
1140
/* End Register Bits */
1141
1142
/* Register Bits [PIND] */
1143
/* Port D Input Pins - PIND */
1144
#define PIND7 7
1145
#define PIND6 6
1146
#define PIND5 5
1147
#define PIND4 4
1148
#define PIND3 3
1149
#define PIND2 2
1150
#define PIND1 1
1151
#define PIND0 0
1152
/* End Register Bits */
1153
1154
/* Register Bits [PORTE] */
1155
/* Port E Data Register - PORTE */
1156
#define PE7 7
1157
#define PE6 6
1158
#define PE5 5
1159
#define PE4 4
1160
#define PE3 3
1161
#define PE2 2
1162
#define PE1 1
1163
#define PE0 0
1164
/* End Register Bits */
1165
1166
/* Register Bits [DDRE] */
1167
/* Port E Data Direction Register - DDRE */
1168
#define DDE7 7
1169
#define DDE6 6
1170
#define DDE5 5
1171
#define DDE4 4
1172
#define DDE3 3
1173
#define DDE2 2
1174
#define DDE1 1
1175
#define DDE0 0
1176
/* End Register Bits */
1177
1178
/* Register Bits [PINE] */
1179
/* Port E Input Pins - PINE */
1180
#define PINE7 7
1181
#define PINE6 6
1182
#define PINE5 5
1183
#define PINE4 4
1184
#define PINE3 3
1185
#define PINE2 2
1186
#define PINE1 1
1187
#define PINE0 0
1188
/* End Register Bits */
1189
1190
/* Register Bits [PORTF] */
1191
/* Port F Data Register - PORTF */
1192
#define PF7 7
1193
#define PF6 6
1194
#define PF5 5
1195
#define PF4 4
1196
#define PF3 3
1197
#define PF2 2
1198
#define PF1 1
1199
#define PF0 0
1200
/* End Register Bits */
1201
1202
/* Register Bits [DDRF] */
1203
/* Port F Data Direction Register - DDRF */
1204
#define DDF7 7
1205
#define DDF6 6
1206
#define DDF5 5
1207
#define DDF4 4
1208
#define DDF3 3
1209
#define DDF2 2
1210
#define DDF1 1
1211
#define DDF0 0
1212
/* End Register Bits */
1213
1214
/* Register Bits [PINF] */
1215
/* Port F Input Pins - PINF */
1216
#define PINF7 7
1217
#define PINF6 6
1218
#define PINF5 5
1219
#define PINF4 4
1220
#define PINF3 3
1221
#define PINF2 2
1222
#define PINF1 1
1223
#define PINF0 0
1224
/* End Register Bits */
1225
1226
/* Register Bits [PORTG] */
1227
/* Port G Data Register - PORTG */
1228
#define PG4 4
1229
#define PG3 3
1230
#define PG2 2
1231
#define PG1 1
1232
#define PG0 0
1233
/* End Register Bits */
1234
1235
/* Register Bits [DDRG] */
1236
/* Port G Data Direction Register - DDRG */
1237
#define DDG4 4
1238
#define DDG3 3
1239
#define DDG2 2
1240
#define DDG1 1
1241
#define DDG0 0
1242
/* End Register Bits */
1243
1244
/* Register Bits [PING] */
1245
/* Port G Input Pins - PING */
1246
#define PING4 4
1247
#define PING3 3
1248
#define PING2 2
1249
#define PING1 1
1250
#define PING0 0
1251
/* End Register Bits */
1252
1253
1254
/* Register Bits [TIFR0] */
1255
/* Timer/Counter 0 interrupt Flag Register */
1256
#define OCF0A 1
1257
#define TOV0 0
1258
/* End Register Bits */
1259
1260
/* Register Bits [TIFR1] */
1261
/* Timer/Counter 1 interrupt Flag Register */
1262
#define ICF1 5
1263
#define OCF1C 3
1264
#define OCF1B 2
1265
#define OCF1A 1
1266
#define TOV1 0
1267
/* End Register Bits */
1268
1269
/* Register Bits [TIFR2] */
1270
/* Timer/Counter 2 interrupt Flag Register */
1271
#define OCF2A 1
1272
#define TOV2 0
1273
/* End Register Bits */
1274
1275
/* Register Bits [TIFR3] */
1276
/* Timer/Counter 3 interrupt Flag Register */
1277
#define ICF3 5
1278
#define OCF3C 3
1279
#define OCF3B 2
1280
#define OCF3A 1
1281
#define TOV3 0
1282
/* End Register Bits */
1283
1284
/* Register Bits [GPIOR0] */
1285
/* General Purpose I/O Register 0 */
1286
#define GPIOR07 7
1287
#define GPIOR06 6
1288
#define GPIOR05 5
1289
#define GPIOR04 4
1290
#define GPIOR03 3
1291
#define GPIOR02 2
1292
#define GPIOR01 1
1293
#define GPIOR00 0
1294
/* End Register Bits */
1295
1296
/* Register Bits [GPIOR1] */
1297
/* General Purpose I/O Register 1 */
1298
#define GPIOR17 7
1299
#define GPIOR16 6
1300
#define GPIOR15 5
1301
#define GPIOR14 4
1302
#define GPIOR13 3
1303
#define GPIOR12 2
1304
#define GPIOR11 1
1305
#define GPIOR10 0
1306
/* End Register Bits */
1307
1308
/* Register Bits [GPIOR2] */
1309
/* General Purpose I/O Register 2 */
1310
#define GPIOR27 7
1311
#define GPIOR26 6
1312
#define GPIOR25 5
1313
#define GPIOR24 4
1314
#define GPIOR23 3
1315
#define GPIOR22 2
1316
#define GPIOR21 1
1317
#define GPIOR20 0
1318
/* End Register Bits */
1319
1320
/* Register Bits [EECR] */
1321
/* EEPROM Control Register */
1322
#define EERIE 3
1323
#define EEMWE 2
1324
#define EEWE 1
1325
#define EERE 0
1326
/* End Register Bits */
1327
1328
/* Register Bits [EEDR] */
1329
/* EEPROM Data Register */
1330
#define EEDR7 7
1331
#define EEDR6 6
1332
#define EEDR5 5
1333
#define EEDR4 4
1334
#define EEDR3 3
1335
#define EEDR2 2
1336
#define EEDR1 1
1337
#define EEDR0 0
1338
/* End Register Bits */
1339
1340
/* Register Bits [EEARL] */
1341
/* EEPROM Address Register */
1342
#define EEAR7 7
1343
#define EEAR6 6
1344
#define EEAR5 5
1345
#define EEAR4 4
1346
#define EEAR3 3
1347
#define EEAR2 2
1348
#define EEAR1 1
1349
#define EEAR0 0
1350
/* End Register Bits */
1351
1352
/* Register Bits [EEARH] */
1353
/* EEPROM Address Register */
1354
#define EEAR11 3
1355
#define EEAR10 2
1356
#define EEAR9 1
1357
#define EEAR8 0
1358
/* End Register Bits */
1359
1360
/* Register Bits [GTCCR] */
1361
/* General Timer/Counter Control Register */
1362
#define TSM 7
1363
#define PSR2 1
1364
#define PSR310 0
1365
/* End Register Bits */
1366
1367
/* Register Bits [TCCR0A] */
1368
/* Timer/Counter Control Register A */
1369
/* ALSO COVERED IN GENERIC SECTION */
1370
#define FOC0A 7
1371
#define WGM00 6
1372
#define COM0A1 5
1373
#define COM0A0 4
1374
#define WGM01 3
1375
#define CS02 2
1376
#define CS01 1
1377
#define CS00 0
1378
/* End Register Bits */
1379
1380
/* Register Bits [OCR0A] */
1381
/* Output Compare Register A */
1382
#define OCR0A7 7
1383
#define OCR0A6 6
1384
#define OCR0A5 5
1385
#define OCR0A4 4
1386
#define OCR0A3 3
1387
#define OCR0A2 2
1388
#define OCR0A1 1
1389
#define OCR0A0 0
1390
/* End Register Bits */
1391
1392
1393
/* Register Bits [SPIDR] */
1394
/* SPI Data Register */
1395
#define SPD7 7
1396
#define SPD6 6
1397
#define SPD5 5
1398
#define SPD4 4
1399
#define SPD3 3
1400
#define SPD2 2
1401
#define SPD1 1
1402
#define SPD0 0
1403
/* End Register Bits */
1404
1405
/* Register Bits [SMCR] */
1406
/* Sleep Mode Control Register */
1407
#define SM2 3
1408
#define SM1 2
1409
#define SM0 1
1410
#define SE 0
1411
/* End Register Bits */
1412
1413
/* Register Bits [MCUSR] */
1414
/* MCU Status Register */
1415
#define JTRF 4
1416
#define WDRF 3
1417
#define BORF 2
1418
#define EXTRF 1
1419
#define PORF 0
1420
/* End Register Bits */
1421
1422
/* Register Bits [MCUCR] */
1423
/* MCU Control Register */
1424
#define JTD 7
1425
#define PUD 4
1426
#define IVSEL 1
1427
#define IVCE 0
1428
/* End Register Bits */
1429
1430
/* Register Bits [CLKPR] */
1431
/* Clock Prescale Register */
1432
#define CLKPCE 7
1433
#define CLKPS3 3
1434
#define CLKPS2 2
1435
#define CLKPS1 1
1436
#define CLKPS0 0
1437
/* End Register Bits */
1438
1439
/* Register Bits [OSCCAL] */
1440
/* Oscillator Calibration Register */
1441
#define CAL6 6
1442
#define CAL5 5
1443
#define CAL4 4
1444
#define CAL3 3
1445
#define CAL2 2
1446
#define CAL1 1
1447
#define CAL0 0
1448
/* End Register Bits */
1449
1450
/* Register Bits [TIMSK0] */
1451
/* Timer/Counter 0 interrupt mask Register */
1452
#define OCIE0A 1
1453
#define TOIE0 0
1454
/* End Register Bits */
1455
1456
/* Register Bits [TIMSK1] */
1457
/* Timer/Counter 1 interrupt mask Register */
1458
#define ICIE1 5
1459
#define OCIE1C 3
1460
#define OCIE1B 2
1461
#define OCIE1A 1
1462
#define TOIE1 0
1463
/* End Register Bits */
1464
1465
/* Register Bits [TIMSK2] */
1466
/* Timer/Counter 2 interrupt mask Register */
1467
#define OCIE2A 1
1468
#define TOIE2 0
1469
/* End Register Bits */
1470
1471
/* Register Bits [TIMSK3] */
1472
/* Timer/Counter 3 interrupt mask Register */
1473
#define ICIE3 5
1474
#define OCIE3C 3
1475
#define OCIE3B 2
1476
#define OCIE3A 1
1477
#define TOIE3 0
1478
/* End Register Bits */
1479
1480
//Begin CAN specific parts
1481
1482
/* Register Bits [CANGCON] */
1483
/* CAN General Control Register */
1484
#define ABRQ 7
1485
#define OVRQ 6
1486
#define TTC 5
1487
#define SYNTTC 4
1488
#define LISTEN 3
1489
#define TEST 2
1490
#define ENASTB 1
1491
#define SWRES 0
1492
/* End Register Bits */
1493
1494
/* Register Bits [CANGSTA] */
1495
/* CAN General Status Register */
1496
#define OVFG 6
1497
#define OVRG 6
1498
#define TXBSY 4
1499
#define RXBSY 3
1500
#define ENFG 2
1501
#define BOFF 1
1502
#define ERRP 0
1503
/* End Register Bits */
1504
1505
/* Register Bits [CANGIT] */
1506
/* CAN General Interrupt Register */
1507
#define CANIT 7
1508
#define BOFFIT 6
1509
#define OVRTIM 5
1510
#define BXOK 4
1511
#define SERG 3
1512
#define CERG 2
1513
#define FERG 1
1514
#define AERG 0
1515
/* End Register Bits */
1516
1517
/* Register Bits [CANGIE] */
1518
/* CAN General Interrupt Enable */
1519
#define ENIT 7
1520
#define ENBOFF 6
1521
#define ENRX 5
1522
#define ENTX 4
1523
#define ENERR 3
1524
#define ENBX 2
1525
#define ENERG 1
1526
#define ENOVRT 0
1527
/* End Register Bits */
1528
1529
/* Register Bits [CANEN2] */
1530
/* CAN Enable MOb Register */
1531
#define ENMOB7 7
1532
#define ENMOB6 6
1533
#define ENMOB5 5
1534
#define ENMOB4 4
1535
#define ENMOB3 3
1536
#define ENMOB2 2
1537
#define ENMOB1 1
1538
#define ENMOB0 0
1539
/* End Register Bits */
1540
1541
/* Register Bits [CANEN1] */
1542
/* CAN Enable MOb Register */
1543
#define ENMOB14 6
1544
#define ENMOB13 5
1545
#define ENMOB12 4
1546
#define ENMOB11 3
1547
#define ENMOB10 2
1548
#define ENMOB9 1
1549
#define ENMOB8 0
1550
/* End Register Bits */
1551
1552
/* Register Bits [CANIE2] */
1553
/* CAN Interrupt Enable MOb Register */
1554
#define IEMOB7 7
1555
#define IEMOB6 6
1556
#define IEMOB5 5
1557
#define IEMOB4 4
1558
#define IEMOB3 3
1559
#define IEMOB2 2
1560
#define IEMOB1 1
1561
#define IEMOB0 0
1562
/* End Register Bits */
1563
1564
/* Register Bits [CANIE1] */
1565
/* CAN Interrupt Enable MOb Register */
1566
#define IEMOB14 6
1567
#define IEMOB13 5
1568
#define IEMOB12 4
1569
#define IEMOB11 3
1570
#define IEMOB10 2
1571
#define IEMOB9 1
1572
#define IEMOB8 0
1573
/* End Register Bits */
1574
1575
/* Register Bits [CANSIT2] */
1576
/* CAN Status Interrupt MOb Register */
1577
#define SIT7 7
1578
#define SIT6 6
1579
#define SIT5 5
1580
#define SIT4 4
1581
#define SIT3 3
1582
#define SIT2 2
1583
#define SIT1 1
1584
#define SIT0 0
1585
/* End Register Bits */
1586
1587
/* Register Bits [CANSIT1] */
1588
/* CAN Status Interrupt MOb Register */
1589
#define SIT14 6
1590
#define SIT13 5
1591
#define SIT12 4
1592
#define SIT11 3
1593
#define SIT10 2
1594
#define SIT9 1
1595
#define SIT8 0
1596
/* End Register Bits */
1597
1598
/* Register Bits [CANBT1] */
1599
/* Bit Timing Register 1 */
1600
#define BRP5 6
1601
#define BRP4 5
1602
#define BRP3 4
1603
#define BRP2 3
1604
#define BRP1 2
1605
#define BRP0 1
1606
/* End Register Bits */
1607
1608
/* Register Bits [CANBT2] */
1609
/* Bit Timing Register 2 */
1610
#define SJW1 6
1611
#define SJW0 5
1612
#define PRS2 3
1613
#define PRS1 2
1614
#define PRS0 1
1615
/* End Register Bits */
1616
1617
/* Register Bits [CANBT3] */
1618
/* Bit Timing Register 3 */
1619
#define PHS22 6
1620
#define PHS21 5
1621
#define PHS20 4
1622
#define PHS12 3
1623
#define PHS11 2
1624
#define PHS10 1
1625
#define SMP 0
1626
/* End Register Bits */
1627
1628
/* Register Bits [CANTCON] */
1629
/* CAN Timer Control Register */
1630
#define TPRSC7 7
1631
#define TPRSC6 6
1632
#define TPRSC5 5
1633
#define TPRSC4 4
1634
#define TPRSC3 3
1635
#define TPRSC2 2
1636
#define TPRSC1 1
1637
#define TPRSC0 0
1638
/* End Register Bits */
1639
1640
/* Register Bits [CANTIML] */
1641
/* CAN Timer Register Low */
1642
#define CANTIM7 7
1643
#define CANTIM6 6
1644
#define CANTIM5 5
1645
#define CANTIM4 4
1646
#define CANTIM3 3
1647
#define CANTIM2 2
1648
#define CANTIM1 1
1649
#define CANTIM0 0
1650
/* End Register Bits */
1651
1652
/* Register Bits [CANTIMH] */
1653
/* CAN Timer Register High */
1654
#define CANTIM15 7
1655
#define CANTIM14 6
1656
#define CANTIM13 5
1657
#define CANTIM12 4
1658
#define CANTIM11 3
1659
#define CANTIM10 2
1660
#define CANTIM9 1
1661
#define CANTIM8 0
1662
/* End Register Bits */
1663
1664
/* Register Bits [CANTTCL] */
1665
/* CAN TTC Timer Register Low */
1666
#define TIMTTC7 7
1667
#define TIMTTC6 6
1668
#define TIMTTC5 5
1669
#define TIMTTC4 4
1670
#define TIMTTC3 3
1671
#define TIMTTC2 2
1672
#define TIMTTC1 1
1673
#define TIMTTC0 0
1674
/* End Register Bits */
1675
1676
/* Register Bits [CANTTCH] */
1677
/* CAN TTC Timer Register High */
1678
#define TIMTTC15 7
1679
#define TIMTTC14 6
1680
#define TIMTTC13 5
1681
#define TIMTTC12 4
1682
#define TIMTTC11 3
1683
#define TIMTTC10 2
1684
#define TIMTTC9 1
1685
#define TIMTTC8 0
1686
/* End Register Bits */
1687
1688
/* Register Bits [CANTEC] */
1689
/* CAN Transmitt Error Counter */
1690
#define TEC7 7
1691
#define TEC6 6
1692
#define TEC5 5
1693
#define TEC4 4
1694
#define TEC3 3
1695
#define TEC2 2
1696
#define TEC1 1
1697
#define TEC0 0
1698
/* End Register Bits */
1699
1700
/* Register Bits [CANREC] */
1701
/* CAN Receive Error Counter */
1702
#define REC7 7
1703
#define REC6 6
1704
#define REC5 5
1705
#define REC4 4
1706
#define REC3 3
1707
#define REC2 2
1708
#define REC1 1
1709
#define REC0 0
1710
/* End Register Bits */
1711
1712
/* Register Bits [CANHPMOB] */
1713
/* Highest Priority MOb */
1714
#define HPMOB3 7
1715
#define HPMOB2 6
1716
#define HPMOB1 5
1717
#define HPMOB0 4
1718
#define CGP3 3
1719
#define CGP2 2
1720
#define CGP1 1
1721
#define CGP0 0
1722
/* End Register Bits */
1723
1724
/* Register Bits [CANPAGE] */
1725
/* CAN Page MOb Register */
1726
#define MOBNB3 7
1727
#define MOBNB2 6
1728
#define MOBNB1 5
1729
#define MOBNB0 4
1730
#define AINC 3
1731
#define INDX2 2
1732
#define INDX1 1
1733
#define INDX0 0
1734
/* End Register Bits */
1735
1736
/* Register Bits [CANSTMOB] */
1737
/* CAN MOb Status Register */
1738
#define DLCW 7
1739
#define TXOK 6
1740
#define RXOK 5
1741
#define BERR 4
1742
#define SERR 3
1743
#define CERR 2
1744
#define FERR 1
1745
#define AERR 0
1746
/* End Register Bits */
1747
1748
/* Register Bits [CANCDMOB] */
1749
/* CAN MOb Control and DLC Register */
1750
#define CONMOB1 7
1751
#define CONMOB0 6
1752
#define RPLV 5
1753
#define IDE 4
1754
#define DLC3 3
1755
#define DLC2 2
1756
#define DLC1 1
1757
#define DLC0 0
1758
/* End Register Bits */
1759
1760
/* Register Bits [CANIDT4] */
1761
/* CAN Identifier Tag Register 4 */
1762
#define IDT4 7
1763
#define IDT3 6
1764
#define IDT2 5
1765
#define IDT1 4
1766
#define IDT0 3
1767
#define RTRTAG 2
1768
#define RB1TAG 1
1769
#define RB0TAG 0
1770
/* End Register Bits */
1771
1772
/* Register Bits [CANIDT3] */
1773
/* CAN Identifier Tag Register 3 */
1774
#define IDT12 7
1775
#define IDT11 6
1776
#define IDT10 5
1777
#define IDT9 4
1778
#define IDT8 3
1779
#define IDT7 2
1780
#define IDT6 1
1781
#define IDT5 0
1782
/* End Register Bits */
1783
1784
/* Register Bits [CANIDT2] */
1785
/* CAN Identifier Tag Register 2 */
1786
#define IDT20 7
1787
#define IDT19 6
1788
#define IDT18 5
1789
#define IDT17 4
1790
#define IDT16 3
1791
#define IDT15 2
1792
#define IDT14 1
1793
#define IDT13 0
1794
/* End Register Bits */
1795
1796
/* Register Bits [CANIDT1] */
1797
/* CAN Identifier Tag Register 1 */
1798
#define IDT28 7
1799
#define IDT27 6
1800
#define IDT26 5
1801
#define IDT25 4
1802
#define IDT24 3
1803
#define IDT23 2
1804
#define IDT22 1
1805
#define IDT21 0
1806
/* End Register Bits */
1807
1808
/* Register Bits [CANIDM4] */
1809
/* CAN Identifier Mask Register 4 */
1810
#define IDMSK4 7
1811
#define IDMSK3 6
1812
#define IDMSK2 5
1813
#define IDMSK1 4
1814
#define IDMSK0 3
1815
#define RTRMSK 2
1816
#define IDEMSK 0
1817
/* End Register Bits */
1818
1819
/* Register Bits [CANIDM3] */
1820
/* CAN Identifier Mask Register 3 */
1821
#define IDMSK12 7
1822
#define IDMSK11 6
1823
#define IDMSK10 5
1824
#define IDMSK9 4
1825
#define IDMSK8 3
1826
#define IDMSK7 2
1827
#define IDMSK6 1
1828
#define IDMSK5 0
1829
/* End Register Bits */
1830
1831
/* Register Bits [CANIDM2] */
1832
/* CAN Identifier Mask Register 2 */
1833
#define IDMSK20 7
1834
#define IDMSK19 6
1835
#define IDMSK18 5
1836
#define IDMSK17 4
1837
#define IDMSK16 3
1838
#define IDMSK15 2
1839
#define IDMSK14 1
1840
#define IDMSK13 0
1841
/* End Register Bits */
1842
1843
/* Register Bits [CANIDM1] */
1844
/* CAN Identifier Mask Register 1 */
1845
#define IDMSK28 7
1846
#define IDMSK27 6
1847
#define IDMSK26 5
1848
#define IDMSK25 4
1849
#define IDMSK24 3
1850
#define IDMSK23 2
1851
#define IDMSK22 1
1852
#define IDMSK21 0
1853
/* End Register Bits */
1854
1855
/* Register Bits [CANSTML] */
1856
/* CAN Timer Register of some sort, low*/
1857
#define TIMSTM7 7
1858
#define TIMSTM6 6
1859
#define TIMSTM5 5
1860
#define TIMSTM4 4
1861
#define TIMSTM3 3
1862
#define TIMSTM2 2
1863
#define TIMSTM1 1
1864
#define TIMSTM0 0
1865
/* End Register Bits */
1866
1867
/* Register Bits [CANSTMH] */
1868
/* CAN Timer Register of some sort, high */
1869
#define TIMSTM15 7
1870
#define TIMSTM14 6
1871
#define TIMSTM13 5
1872
#define TIMSTM12 4
1873
#define TIMSTM11 3
1874
#define TIMSTM10 2
1875
#define TIMSTM9 1
1876
#define TIMSTM8 0
1877
/* End Register Bits */
1878
1879
/* Register Bits [CANMSG] */
1880
/* CAN Message Register */
1881
#define MSG7 7
1882
#define MSG6 6
1883
#define MSG5 5
1884
#define MSG4 4
1885
#define MSG3 3
1886
#define MSG2 2
1887
#define MSG1 1
1888
#define MSG0 0
1889
/* End Register Bits */
1890
1891
/* Begin Verbatim */
1892
1893
/* Timer/Counter Control Register (generic) */
1894
#define FOC 7
1895
#define WGM0 6
1896
#define COM1 5
1897
#define COM0 4
1898
#define WGM1 3
1899
#define CS2 2
1900
#define CS1 1
1901
#define CS0 0
1902
1903
/* Timer/Counter Control Register A (generic) */
1904
#define COMA1 7
1905
#define COMA0 6
1906
#define COMB1 5
1907
#define COMB0 4
1908
#define COMC1 3
1909
#define COMC0 2
1910
#define WGMA1 1
1911
#define WGMA0 0
1912
1913
/* Timer/Counter Control and Status Register B (generic) */
1914
#define ICNC 7
1915
#define ICES 6
1916
#define WGMB3 4
1917
#define WGMB2 3
1918
#define CSB2 2
1919
#define CSB1 1
1920
#define CSB0 0
1921
1922
/* Timer/Counter Control Register C (generic) */
1923
#define FOCA 7
1924
#define FOCB 6
1925
#define FOCC 5
1926
1927
/* Port Data Register (generic) */
1928
#define PORT7 7
1929
#define PORT6 6
1930
#define PORT5 5
1931
#define PORT4 4
1932
#define PORT3 3
1933
#define PORT2 2
1934
#define PORT1 1
1935
#define PORT0 0
1936
1937
/* Port Data Direction Register (generic) */
1938
#define DD7 7
1939
#define DD6 6
1940
#define DD5 5
1941
#define DD4 4
1942
#define DD3 3
1943
#define DD2 2
1944
#define DD1 1
1945
#define DD0 0
1946
1947
/* Port Input Pins (generic) */
1948
#define PIN7 7
1949
#define PIN6 6
1950
#define PIN5 5
1951
#define PIN4 4
1952
#define PIN3 3
1953
#define PIN2 2
1954
#define PIN1 1
1955
#define PIN0 0
1956
1957
/* USART Status Register A (generic) */
1958
#define RXC 7
1959
#define TXC 6
1960
#define UDRE 5
1961
#define FE 4
1962
#define DOR 3
1963
#define UPE 2
1964
#define U2X 1
1965
#define MPCM 0
1966
1967
/* USART Control Register B (generic) */
1968
#define RXCIE 7
1969
#define TXCIE 6
1970
#define UDRIE 5
1971
#define RXEN 4
1972
#define TXEN 3
1973
#define UCSZ 2
1974
#define UCSZ2 2
/* new name in datasheet (2467E-AVR-05/02) */
1975
#define RXB8 1
1976
#define TXB8 0
1977
1978
/* USART Register C (generic) */
1979
#define UMSEL 6
1980
#define UPM1 5
1981
#define UPM0 4
1982
#define USBS 3
1983
#define UCSZ1 2
1984
#define UCSZ0 1
1985
#define UCPOL 0
1986
1987
/* End Verbatim */
1988
1990
#endif
/* _AVR_IOCANXX_H_ */
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