RTEMS CPU Kit with SuperCore  4.11.3
io8534.h
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1 
9 /* Copyright (c) 2002, Marek Michalkiewicz
10  All rights reserved.
11 
12  Redistribution and use in source and binary forms, with or without
13  modification, are permitted provided that the following conditions are met:
14 
15  * Redistributions of source code must retain the above copyright
16  notice, this list of conditions and the following disclaimer.
17 
18  * Redistributions in binary form must reproduce the above copyright
19  notice, this list of conditions and the following disclaimer in
20  the documentation and/or other materials provided with the
21  distribution.
22 
23  * Neither the name of the copyright holders nor the names of
24  contributors may be used to endorse or promote products derived
25  from this software without specific prior written permission.
26 
27  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
28  AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
29  IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
30  ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
31  LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
32  CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
33  SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
34  INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
35  CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
36  ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
37  POSSIBILITY OF SUCH DAMAGE. */
38 
39 
40 /* avr/io8534.h - definitions for AT90C8534 */
41 
42 #ifndef _AVR_IO8534_
43 #define _AVR_IO8534_ 1
44 
45 /* This file should only be included from <avr/io.h>, never directly. */
46 
47 #ifndef _AVR_IO_H_
48 # error "Include <avr/io.h> instead of this file."
49 #endif
50 
51 #ifndef _AVR_IOXXX_H_
52 # define _AVR_IOXXX_H_ "io8534.h"
53 #else
54 # error "Attempt to include more than one <avr/ioXXX.h> file."
55 #endif
56 
65 /* I/O registers */
66 
67 /* 0x00..0x03 reserved */
68 
69 /* ADC Data Register */
70 #ifndef __ASSEMBLER__
71 #define ADC _SFR_IO16(0x04)
72 #endif
73 #define ADCW _SFR_IO16(0x04)
74 #define ADCL _SFR_IO8(0x04)
75 #define ADCH _SFR_IO8(0x05)
76 
77 /* ADC Control and Status Register */
78 #define ADCSR _SFR_IO8(0x06)
79 
80 /* ADC Multiplexer Select Register */
81 #define ADMUX _SFR_IO8(0x07)
82 
83 /* 0x08..0x0F reserved */
84 
85 /* General Interrupt Pin Register */
86 #define GIPR _SFR_IO8(0x10)
87 
88 /* 0x11..0x19 reserved */
89 
90 /* Data Direction Register, Port A */
91 #define DDRA _SFR_IO8(0x1A)
92 
93 /* Data Register, Port A */
94 #define PORTA _SFR_IO8(0x1B)
95 
96 /* EEPROM Control Register */
97 #define EECR _SFR_IO8(0x1C)
98 
99 /* EEPROM Data Register */
100 #define EEDR _SFR_IO8(0x1D)
101 
102 /* EEPROM Address Register */
103 #define EEAR _SFR_IO16(0x1E)
104 #define EEARL _SFR_IO8(0x1E)
105 #define EEARH _SFR_IO8(0x1F)
106 
107 /* 0x20..0x2B reserved */
108 
109 /* Timer/Counter1 */
110 #define TCNT1 _SFR_IO16(0x2C)
111 #define TCNT1L _SFR_IO8(0x2C)
112 #define TCNT1H _SFR_IO8(0x2D)
113 
114 /* Timer/Counter1 Control Register */
115 #define TCCR1 _SFR_IO8(0x2E)
116 
117 /* 0x2F..0x31 reserved */
118 
119 /* Timer/Counter0 (8-bit) */
120 #define TCNT0 _SFR_IO8(0x32)
121 
122 /* Timer/Counter0 Control Register */
123 #define TCCR0 _SFR_IO8(0x33)
124 
125 /* 0x34 reserved */
126 
127 /* MCU general Control Register */
128 #define MCUCR _SFR_IO8(0x35)
129 
130 /* 0x36..0x37 reserved */
131 
132 /* Timer/Counter Interrupt Flag Register */
133 #define TIFR _SFR_IO8(0x38)
134 
135 /* Timer/Counter Interrupt MaSK Register */
136 #define TIMSK _SFR_IO8(0x39)
137 
138 /* General Interrupt Flag Register */
139 #define GIFR _SFR_IO8(0x3A)
140 
141 /* General Interrupt MaSK register */
142 #define GIMSK _SFR_IO8(0x3B)
143 
144 /* 0x3C reserved */
145 
146 /* 0x3D..0x3E SP */
147 
148 /* 0x3F SREG */
149 
150 /* Interrupt vectors */
151 
152 #define SIG_INTERRUPT0 _VECTOR(1)
153 #define SIG_INTERRUPT1 _VECTOR(2)
154 #define SIG_OVERFLOW1 _VECTOR(3)
155 #define SIG_OVERFLOW0 _VECTOR(4)
156 #define SIG_ADC _VECTOR(5)
157 #define SIG_EEPROM_READY _VECTOR(6)
158 
159 #define _VECTORS_SIZE 14
160 
161 /* Bit numbers */
162 
163 /* GIMSK */
164 #define INT1 7
165 #define INT0 6
166 
167 /* GIFR */
168 #define INTF1 7
169 #define INTF0 6
170 
171 /* GIPR */
172 #define IPIN1 3
173 #define IPIN0 2
174 
175 /* TIMSK */
176 #define TOIE1 2
177 #define TOIE0 0
178 
179 /* TIFR */
180 #define TOV1 2
181 #define TOV0 0
182 
183 /* MCUCR */
184 #define SE 6
185 #define SM 5
186 #define ISC1 2
187 #define ISC0 0
188 
189 /* TCCR0 */
190 #define CS02 2
191 #define CS01 1
192 #define CS00 0
193 
194 /* TCCR1 */
195 #define CS12 2
196 #define CS11 1
197 #define CS10 0
198 
199 /* PORTA */
200 #define PA7 7
201 #define PA6 6
202 #define PA5 5
203 #define PA4 4
204 #define PA3 3
205 #define PA2 2
206 #define PA1 1
207 #define PA0 0
208 
209 /* DDRA */
210 #define DDA7 7
211 #define DDA6 6
212 #define DDA5 5
213 #define DDA4 4
214 #define DDA3 3
215 #define DDA2 2
216 #define DDA1 1
217 #define DDA0 0
218 
219 /* EEPROM Control Register */
220 #define EERIE 3
221 #define EEMWE 2
222 #define EEWE 1
223 #define EERE 0
224 
225 /* Last memory addresses */
226 #define RAMEND 0x15F
227 #define XRAMEND RAMEND
228 #define E2END 0x1FF
229 #define FLASHEND 0x1FFF
230 
233 #endif /* _AVR_IO8534_H_ */
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