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#define | _AVR_IOXXX_H_ "io43u35x.h" |
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#define | TICIE1 3 |
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#define | OCIE1A 6 |
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#define | OCIE1B 5 |
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#define | TOIE1 7 |
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#define | TOIE0 1 |
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#define | ICF1 3 |
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#define | OCF1A 6 |
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#define | OCF1B 5 |
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#define | TOV1 7 |
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#define | TOV0 1 |
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#define | SE 5 |
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#define | SM 4 |
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#define | ISC11 3 |
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#define | ISC10 2 |
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#define | ISC01 1 |
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#define | ISC00 0 |
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#define | CS02 2 |
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#define | CS01 1 |
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#define | CS00 0 |
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#define | COM1A1 7 |
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#define | COM1A0 6 |
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#define | COM1B1 5 |
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#define | COM1B0 4 |
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#define | PWM11 1 |
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#define | PWM10 0 |
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#define | ICNC1 7 |
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#define | ICES1 6 |
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#define | CTC1 3 |
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#define | CS12 2 |
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#define | CS11 1 |
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#define | CS10 0 |
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#define | WDTOE 4 |
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#define | WDE 3 |
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#define | WDP2 2 |
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#define | WDP1 1 |
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#define | WDP0 0 |
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#define | PA7 7 |
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#define | PA6 6 |
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#define | PA5 5 |
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#define | PA4 4 |
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#define | PA3 3 |
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#define | PA2 2 |
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#define | PA1 1 |
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#define | PA0 0 |
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#define | DDA7 7 |
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#define | DDA6 6 |
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#define | DDA5 5 |
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#define | DDA4 4 |
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#define | DDA3 3 |
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#define | DDA2 2 |
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#define | DDA1 1 |
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#define | DDA0 0 |
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#define | PINA7 7 |
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#define | PINA6 6 |
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#define | PINA5 5 |
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#define | PINA4 4 |
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#define | PINA3 3 |
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#define | PINA2 2 |
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#define | PINA1 1 |
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#define | PINA0 0 |
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#define | PB7 7 |
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#define | PB6 6 |
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#define | PB5 5 |
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#define | PB4 4 |
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#define | PB3 3 |
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#define | PB2 2 |
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#define | PB1 1 |
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#define | PB0 0 |
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#define | DDB7 7 |
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#define | DDB6 6 |
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#define | DDB5 5 |
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#define | DDB4 4 |
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#define | DDB3 3 |
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#define | DDB2 2 |
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#define | DDB1 1 |
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#define | DDB0 0 |
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#define | PINB7 7 |
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#define | PINB6 6 |
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#define | PINB5 5 |
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#define | PINB4 4 |
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#define | PINB3 3 |
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#define | PINB2 2 |
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#define | PINB1 1 |
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#define | PINB0 0 |
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#define | DDC7 7 |
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#define | DDC6 6 |
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#define | DDC5 5 |
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#define | DDC4 4 |
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#define | DDC3 3 |
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#define | DDC2 2 |
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#define | DDC1 1 |
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#define | DDC0 0 |
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#define | PINC7 7 |
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#define | PINC6 6 |
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#define | PINC5 5 |
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#define | PINC4 4 |
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#define | PINC3 3 |
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#define | PINC2 2 |
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#define | PINC1 1 |
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#define | PINC0 0 |
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#define | PC7 7 |
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#define | PC6 6 |
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#define | PC5 5 |
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#define | PC4 4 |
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#define | PC3 3 |
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#define | PC2 2 |
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#define | PC1 1 |
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#define | PC0 0 |
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#define | PD7 7 |
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#define | PD6 6 |
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#define | PD5 5 |
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#define | PD4 4 |
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#define | PD3 3 |
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#define | PD2 2 |
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#define | PD1 1 |
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#define | PD0 0 |
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#define | DDD7 7 |
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#define | DDD6 6 |
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#define | DDD5 5 |
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#define | DDD4 4 |
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#define | DDD3 3 |
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#define | DDD2 2 |
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#define | DDD1 1 |
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#define | DDD0 0 |
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#define | PIND7 7 |
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#define | PIND6 6 |
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#define | PIND5 5 |
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#define | PIND4 4 |
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#define | PIND3 3 |
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#define | PIND2 2 |
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#define | PIND1 1 |
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#define | PIND0 0 |
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#define | PF3 3 |
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#define | PF2 2 |
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#define | PF1 1 |
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#define | PF0 0 |
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#define | DDF3 3 |
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#define | DDF2 2 |
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#define | DDF1 1 |
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#define | PINF3 3 |
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#define | PINF2 2 |
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#define | PINF1 1 |
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#define | PINF0 0 |
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#define | SPIF 7 |
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#define | WCOL 6 |
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#define | SPIE 7 |
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#define | SPE 6 |
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#define | DORD 5 |
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#define | MSTR 4 |
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#define | CPOL 3 |
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#define | CPHA 2 |
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#define | SPR1 1 |
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#define | SPR0 0 |
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#define | MUX2 2 |
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#define | MUX1 1 |
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#define | MUX0 0 |
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#define | ADEN 7 |
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#define | ADSC 6 |
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#define | ADFR 5 |
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#define | ADIF 4 |
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#define | ADIE 3 |
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#define | ADPS2 2 |
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#define | ADPS1 1 |
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#define | ADPS0 0 |
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#define | ADC _SFR_IO16(0x02) |
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#define | ADCW _SFR_IO16(0x02) |
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#define | ADCL _SFR_IO8(0x02) |
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#define | ADCH _SFR_IO8(0x03) |
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#define | ADCSR _SFR_IO8(0x07) |
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#define | ADMUX _SFR_IO8(0x08) |
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#define | ACSR _SFR_IO8(0x08) |
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#define | PINF _SFR_IO8(0x04) |
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#define | DDRF _SFR_IO8(0x05) |
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#define | PORTF _SFR_IO8(0x06) |
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#define | PINE _SFR_IO8(0x01) |
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#define | DDRE _SFR_IO8(0x02) |
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#define | PORTE _SFR_IO8(0x03) |
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#define | SPCR _SFR_IO8(0x0D) |
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#define | SPSR _SFR_IO8(0x0E) |
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#define | SPDR _SFR_IO8(0x0F) |
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#define | PIND _SFR_IO8(0x10) |
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#define | DDRD _SFR_IO8(0x11) |
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#define | PORTD _SFR_IO8(0x12) |
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#define | PINC _SFR_IO8(0x13) |
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#define | DDRC _SFR_IO8(0x14) |
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#define | PORTC _SFR_IO8(0x15) |
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#define | PINB _SFR_IO8(0x16) |
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#define | DDRB _SFR_IO8(0x17) |
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#define | PORTB _SFR_IO8(0x18) |
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#define | PINA _SFR_IO8(0x19) |
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#define | DDRA _SFR_IO8(0x1A) |
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#define | PORTA _SFR_IO8(0x1B) |
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#define | WDTCR _SFR_IO8(0x21) |
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#define | ICR1 _SFR_IO16(0x24) |
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#define | ICR1L _SFR_IO8(0x24) |
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#define | ICR1H _SFR_IO8(0x25) |
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#define | OCR1B _SFR_IO16(0x28) |
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#define | OCR1BL _SFR_IO8(0x28) |
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#define | OCR1BH _SFR_IO8(0x29) |
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#define | OCR1A _SFR_IO16(0x2A) |
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#define | OCR1AL _SFR_IO8(0x2A) |
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#define | OCR1AH _SFR_IO8(0x2B) |
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#define | TCNT1 _SFR_IO16(0x2C) |
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#define | TCNT1L _SFR_IO8(0x2C) |
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#define | TCNT1H _SFR_IO8(0x2D) |
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#define | TCCR1B _SFR_IO8(0x2E) |
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#define | TCCR1A _SFR_IO8(0x2F) |
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#define | TCNT0 _SFR_IO8(0x32) |
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#define | TCCR0 _SFR_IO8(0x33) |
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#define | MCUCR _SFR_IO8(0x35) |
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#define | TIFR _SFR_IO8(0x38) |
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#define | TIMSK _SFR_IO8(0x39) |
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#define | GIFR _SFR_IO8(0x3A) |
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#define | GIMSK _SFR_IO8(0x3B) |
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#define | SIG_INTERRUPT0 _VECTOR(1) /* suspend/resume */ |
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#define | SIG_INTERRUPT1 _VECTOR(2) |
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#define | SIG_TIMER1_CAPT1 _VECTOR(3) |
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#define | SIG_INPUT_CAPTURE1 _VECTOR(3) |
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#define | SIG_OUTPUT_COMPARE1A _VECTOR(4) |
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#define | SIG_OUTPUT_COMPARE1B _VECTOR(5) |
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#define | SIG_OVERFLOW1 _VECTOR(6) |
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#define | SIG_OVERFLOW0 _VECTOR(7) |
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#define | SIG_SPI _VECTOR(8) |
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#define | SIG_ADC _VECTOR(11) |
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#define | SIG_USB_INT _VECTOR(12) |
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#define | _VECTORS_SIZE 52 |
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#define | RAMEND 0x045F /*Last On-Chip SRAM Location*/ |
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#define | XRAMEND RAMEND |
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#define | E2END 0x0000 |
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#define | FLASHEND 0x5FFF |
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