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#define | PRR _SFR_IO8(0x00) |
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#define | PRADC 0 |
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#define | PRUSI 1 |
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#define | PRTIM0 2 |
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#define | PRTIM1 3 |
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#define | DIDR0 _SFR_IO8(0x01) |
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#define | ADC0D 0 |
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#define | ADC1D 1 |
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#define | ADC2D 2 |
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#define | ADC3D 3 |
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#define | ADC4D 4 |
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#define | ADC5D 5 |
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#define | ADC6D 6 |
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#define | ADC7D 7 |
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#define | ADCSRB _SFR_IO8(0x03) |
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#define | ADTS0 0 |
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#define | ADTS1 1 |
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#define | ADTS2 2 |
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#define | ADLAR 4 |
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#define | ACME 6 |
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#define | BIN 7 |
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#define | ADC _SFR_IO16(0x04) |
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#define | ADCW _SFR_IO16(0x04) |
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#define | ADCL _SFR_IO8(0x04) |
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#define | ADCL0 0 |
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#define | ADCL1 1 |
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#define | ADCL2 2 |
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#define | ADCL3 3 |
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#define | ADCL4 4 |
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#define | ADCL5 5 |
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#define | ADCL6 6 |
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#define | ADCL7 7 |
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#define | ADCH _SFR_IO8(0x05) |
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#define | ADCH0 0 |
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#define | ADCH1 1 |
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#define | ADCH2 2 |
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#define | ADCH3 3 |
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#define | ADCH4 4 |
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#define | ADCH5 5 |
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#define | ADCH6 6 |
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#define | ADCH7 7 |
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#define | ADCSRA _SFR_IO8(0x06) |
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#define | ADPS0 0 |
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#define | ADPS1 1 |
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#define | ADPS2 2 |
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#define | ADIE 3 |
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#define | ADIF 4 |
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#define | ADATE 5 |
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#define | ADSC 6 |
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#define | ADEN 7 |
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#define | ADMUX _SFR_IO8(0x07) |
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#define | MUX0 0 |
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#define | MUX1 1 |
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#define | MUX2 2 |
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#define | MUX3 3 |
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#define | MUX4 4 |
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#define | MUX5 5 |
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#define | REFS0 6 |
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#define | REFS1 7 |
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#define | ACSR _SFR_IO8(0x08) |
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#define | ACIS0 0 |
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#define | ACIS1 1 |
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#define | ACIC 2 |
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#define | ACIE 3 |
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#define | ACI 4 |
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#define | ACO 5 |
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#define | ACBG 6 |
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#define | ACD 7 |
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#define | TIFR1 _SFR_IO8(0x0B) |
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#define | TOV1 0 |
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#define | OCF1A 1 |
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#define | OCF1B 2 |
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#define | ICF1 5 |
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#define | TIMSK1 _SFR_IO8(0x0C) |
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#define | TOIE1 0 |
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#define | OCIE1A 1 |
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#define | OCIE1B 2 |
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#define | ICIE1 5 |
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#define | USICR _SFR_IO8(0x0D) |
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#define | USITC 0 |
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#define | USICLK 1 |
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#define | USICS0 2 |
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#define | USICS1 3 |
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#define | USIWM0 4 |
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#define | USIWM1 5 |
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#define | USIOIE 6 |
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#define | USISIE 7 |
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#define | USISR _SFR_IO8(0x0E) |
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#define | USICNT0 0 |
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#define | USICNT1 1 |
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#define | USICNT2 2 |
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#define | USICNT3 3 |
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#define | USIDC 4 |
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#define | USIPF 5 |
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#define | USIOIF 6 |
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#define | USISIF 7 |
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#define | USIDR _SFR_IO8(0x0F) |
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#define | USIDR0 0 |
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#define | USIDR1 1 |
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#define | USIDR2 2 |
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#define | USIDR3 3 |
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#define | USIDR4 4 |
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#define | USIDR5 5 |
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#define | USIDR6 6 |
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#define | USIDR7 7 |
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#define | USIBR _SFR_IO8(0x10) |
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#define | USIBR0 0 |
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#define | USIBR1 1 |
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#define | USIBR2 2 |
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#define | USIBR3 3 |
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#define | USIBR4 4 |
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#define | USIBR5 5 |
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#define | USIBR6 6 |
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#define | USIBR7 7 |
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#define | PCMSK0 _SFR_IO8(0x12) |
| |
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#define | PCINT0 0 |
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#define | PCINT1 1 |
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#define | PCINT2 2 |
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#define | PCINT3 3 |
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#define | PCINT4 4 |
| |
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#define | PCINT5 5 |
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#define | PCINT6 6 |
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#define | PCINT7 7 |
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#define | GPIOR0 _SFR_IO8(0x13) |
| |
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#define | GPIOR00 0 |
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#define | GPIOR01 1 |
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#define | GPIOR02 2 |
| |
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#define | GPIOR03 3 |
| |
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#define | GPIOR04 4 |
| |
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#define | GPIOR05 5 |
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#define | GPIOR06 6 |
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#define | GPIOR07 7 |
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#define | GPIOR1 _SFR_IO8(0x14) |
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#define | GPIOR10 0 |
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#define | GPIOR11 1 |
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#define | GPIOR12 2 |
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#define | GPIOR13 3 |
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#define | GPIOR14 4 |
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#define | GPIOR15 5 |
| |
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#define | GPIOR16 6 |
| |
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#define | GPIOR17 7 |
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#define | GPIOR2 _SFR_IO8(0x15) |
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#define | GPIOR20 0 |
| |
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#define | GPIOR21 1 |
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#define | GPIOR22 2 |
| |
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#define | GPIOR23 3 |
| |
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#define | GPIOR24 4 |
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#define | GPIOR25 5 |
| |
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#define | GPIOR26 6 |
| |
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#define | GPIOR27 7 |
| |
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#define | PINB _SFR_IO8(0x16) |
| |
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#define | PINB0 0 |
| |
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#define | PINB1 1 |
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#define | PINB2 2 |
| |
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#define | PINB3 3 |
| |
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#define | DDRB _SFR_IO8(0x17) |
| |
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#define | DDB0 0 |
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#define | DDB1 1 |
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#define | DDB2 2 |
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#define | DDB3 3 |
| |
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#define | PORTB _SFR_IO8(0x18) |
| |
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#define | PORTB0 0 |
| |
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#define | PORTB1 1 |
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#define | PORTB2 2 |
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#define | PORTB3 3 |
| |
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#define | PINA _SFR_IO8(0x19) |
| |
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#define | PINA0 0 |
| |
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#define | PINA1 1 |
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#define | PINA2 2 |
| |
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#define | PINA3 3 |
| |
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#define | PINA4 4 |
| |
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#define | PINA5 5 |
| |
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#define | PINA6 6 |
| |
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#define | PINA7 7 |
| |
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#define | DDRA _SFR_IO8(0x1A) |
| |
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#define | DDA0 0 |
| |
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#define | DDA1 1 |
| |
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#define | DDA2 2 |
| |
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#define | DDA3 3 |
| |
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#define | DDA4 4 |
| |
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#define | DDA5 5 |
| |
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#define | DDA6 6 |
| |
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#define | DDA7 7 |
| |
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#define | PORTA _SFR_IO8(0x1B) |
| |
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#define | PORTA0 0 |
| |
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#define | PORTA1 1 |
| |
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#define | PORTA2 2 |
| |
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#define | PORTA3 3 |
| |
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#define | PORTA4 4 |
| |
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#define | PORTA5 5 |
| |
|
#define | PORTA6 6 |
| |
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#define | PORTA7 7 |
| |
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#define | EECR _SFR_IO8(0x1C) |
| |
|
#define | EERE 0 |
| |
|
#define | EEPE 1 |
| |
|
#define | EEMPE 2 |
| |
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#define | EERIE 3 |
| |
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#define | EEPM0 4 |
| |
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#define | EEPM1 5 |
| |
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#define | EEDR _SFR_IO8(0x1D) |
| |
|
#define | EEDR0 0 |
| |
|
#define | EEDR1 1 |
| |
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#define | EEDR2 2 |
| |
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#define | EEDR3 3 |
| |
|
#define | EEDR4 4 |
| |
|
#define | EEDR5 5 |
| |
|
#define | EEDR6 6 |
| |
|
#define | EEDR7 7 |
| |
|
#define | EEAR _SFR_IO16(0x1E) |
| |
|
#define | EEARL _SFR_IO8(0x1E) |
| |
|
#define | EEAR0 0 |
| |
|
#define | EEAR1 1 |
| |
|
#define | EEAR2 2 |
| |
|
#define | EEAR3 3 |
| |
|
#define | EEAR4 4 |
| |
|
#define | EEAR5 5 |
| |
|
#define | EEAR6 6 |
| |
|
#define | EEAR7 7 |
| |
|
#define | EEARH _SFR_IO8(0x1F) |
| |
|
#define | EEAR8 0 |
| |
|
#define | PCMSK1 _SFR_IO8(0x20) |
| |
|
#define | PCINT8 0 |
| |
|
#define | PCINT9 1 |
| |
|
#define | PCINT10 2 |
| |
|
#define | PCINT11 3 |
| |
|
#define | WDTCSR _SFR_IO8(0x21) |
| |
|
#define | WDP0 0 |
| |
|
#define | WDP1 1 |
| |
|
#define | WDP2 2 |
| |
|
#define | WDE 3 |
| |
|
#define | WDCE 4 |
| |
|
#define | WDP3 5 |
| |
|
#define | WDIE 6 |
| |
|
#define | WDIF 7 |
| |
|
#define | TCCR1C _SFR_IO8(0x22) |
| |
|
#define | FOC1B 6 |
| |
|
#define | FOC1A 7 |
| |
|
#define | GTCCR _SFR_IO8(0x23) |
| |
|
#define | PSR10 0 |
| |
|
#define | TSM 7 |
| |
|
#define | ICR1 _SFR_IO16(0x24) |
| |
|
#define | ICR1L _SFR_IO8(0x24) |
| |
|
#define | ICR1L0 0 |
| |
|
#define | ICR1L1 1 |
| |
|
#define | ICR1L2 2 |
| |
|
#define | ICR1L3 3 |
| |
|
#define | ICR1L4 4 |
| |
|
#define | ICR1L5 5 |
| |
|
#define | ICR1L6 6 |
| |
|
#define | ICR1L7 7 |
| |
|
#define | ICR1H _SFR_IO8(0x25) |
| |
|
#define | ICR1H0 0 |
| |
|
#define | ICR1H1 1 |
| |
|
#define | ICR1H2 2 |
| |
|
#define | ICR1H3 3 |
| |
|
#define | ICR1H4 4 |
| |
|
#define | ICR1H5 5 |
| |
|
#define | ICR1H6 6 |
| |
|
#define | ICR1H7 7 |
| |
|
#define | CLKPR _SFR_IO8(0x26) |
| |
|
#define | CLKPS0 0 |
| |
|
#define | CLKPS1 1 |
| |
|
#define | CLKPS2 2 |
| |
|
#define | CLKPS3 3 |
| |
|
#define | CLKPCE 7 |
| |
|
#define | DWDR _SFR_IO8(0x27) |
| |
|
#define | OCR1B _SFR_IO16(0x28) |
| |
|
#define | OCR1BL _SFR_IO8(0x28) |
| |
|
#define | OCR1BL0 0 |
| |
|
#define | OCR1BL1 1 |
| |
|
#define | OCR1BL2 2 |
| |
|
#define | OCR1BL3 3 |
| |
|
#define | OCR1BL4 4 |
| |
|
#define | OCR1BL5 5 |
| |
|
#define | OCR1BL6 6 |
| |
|
#define | OCR1BL7 7 |
| |
|
#define | OCR1BH _SFR_IO8(0x29) |
| |
|
#define | OCR1BH0 0 |
| |
|
#define | OCR1BH1 1 |
| |
|
#define | OCR1BH2 2 |
| |
|
#define | OCR1BH3 3 |
| |
|
#define | OCR1BH4 4 |
| |
|
#define | OCR1BH5 5 |
| |
|
#define | OCR1BH6 6 |
| |
|
#define | OCR1BH7 7 |
| |
|
#define | OCR1A _SFR_IO16(0x2A) |
| |
|
#define | OCR1AL _SFR_IO8(0x2A) |
| |
|
#define | OCR1AL0 0 |
| |
|
#define | OCR1AL1 1 |
| |
|
#define | OCR1AL2 2 |
| |
|
#define | OCR1AL3 3 |
| |
|
#define | OCR1AL4 4 |
| |
|
#define | OCR1AL5 5 |
| |
|
#define | OCR1AL6 6 |
| |
|
#define | OCR1AL7 7 |
| |
|
#define | OCR1AH _SFR_IO8(0x2B) |
| |
|
#define | OCR1AH0 0 |
| |
|
#define | OCR1AH1 1 |
| |
|
#define | OCR1AH2 2 |
| |
|
#define | OCR1AH3 3 |
| |
|
#define | OCR1AH4 4 |
| |
|
#define | OCR1AH5 5 |
| |
|
#define | OCR1AH6 6 |
| |
|
#define | OCR1AH7 7 |
| |
|
#define | TCNT1 _SFR_IO16(0x2C) |
| |
|
#define | TCNT1L _SFR_IO8(0x2C) |
| |
|
#define | TCNT1L0 0 |
| |
|
#define | TCNT1L1 1 |
| |
|
#define | TCNT1L2 2 |
| |
|
#define | TCNT1L3 3 |
| |
|
#define | TCNT1L4 4 |
| |
|
#define | TCNT1L5 5 |
| |
|
#define | TCNT1L6 6 |
| |
|
#define | TCNT1L7 7 |
| |
|
#define | TCNT1H _SFR_IO8(0x2D) |
| |
|
#define | TCNT1H0 0 |
| |
|
#define | TCNT1H1 1 |
| |
|
#define | TCNT1H2 2 |
| |
|
#define | TCNT1H3 3 |
| |
|
#define | TCNT1H4 4 |
| |
|
#define | TCNT1H5 5 |
| |
|
#define | TCNT1H6 6 |
| |
|
#define | TCNT1H7 7 |
| |
|
#define | TCCR1B _SFR_IO8(0x2E) |
| |
|
#define | CS10 0 |
| |
|
#define | CS11 1 |
| |
|
#define | CS12 2 |
| |
|
#define | WGM12 3 |
| |
|
#define | WGM13 4 |
| |
|
#define | ICES1 6 |
| |
|
#define | ICNC1 7 |
| |
|
#define | TCCR1A _SFR_IO8(0x2F) |
| |
|
#define | WGM10 0 |
| |
|
#define | WGM11 1 |
| |
|
#define | COM1B0 4 |
| |
|
#define | COM1B1 5 |
| |
|
#define | COM1A0 6 |
| |
|
#define | COM1A1 7 |
| |
|
#define | TCCR0A _SFR_IO8(0x30) |
| |
|
#define | WGM00 0 |
| |
|
#define | WGM01 1 |
| |
|
#define | COM0B0 4 |
| |
|
#define | COM0B1 5 |
| |
|
#define | COM0A0 6 |
| |
|
#define | COM0A1 7 |
| |
|
#define | OSCCAL _SFR_IO8(0x31) |
| |
|
#define | CAL0 0 |
| |
|
#define | CAL1 1 |
| |
|
#define | CAL2 2 |
| |
|
#define | CAL3 3 |
| |
|
#define | CAL4 4 |
| |
|
#define | CAL5 5 |
| |
|
#define | CAL6 6 |
| |
|
#define | CAL7 7 |
| |
|
#define | TCNT0 _SFR_IO8(0x32) |
| |
|
#define | TCNT0_0 0 |
| |
|
#define | TCNT0_1 1 |
| |
|
#define | TCNT0_2 2 |
| |
|
#define | TCNT0_3 3 |
| |
|
#define | TCNT0_4 4 |
| |
|
#define | TCNT0_5 5 |
| |
|
#define | TCNT0_6 6 |
| |
|
#define | TCNT0_7 7 |
| |
|
#define | TCCR0B _SFR_IO8(0x33) |
| |
|
#define | CS00 0 |
| |
|
#define | CS01 1 |
| |
|
#define | CS02 2 |
| |
|
#define | WGM02 3 |
| |
|
#define | FOC0B 6 |
| |
|
#define | FOC0A 7 |
| |
|
#define | MCUSR _SFR_IO8(0x34) |
| |
|
#define | PORF 0 |
| |
|
#define | EXTRF 1 |
| |
|
#define | BORF 2 |
| |
|
#define | WDRF 3 |
| |
|
#define | MCUCR _SFR_IO8(0x35) |
| |
|
#define | ISC00 0 |
| |
|
#define | ISC01 1 |
| |
|
#define | SM0 3 |
| |
|
#define | SM1 4 |
| |
|
#define | SE 5 |
| |
|
#define | PUD 6 |
| |
|
#define | OCR0A _SFR_IO8(0x36) |
| |
|
#define | OCR0A_0 0 |
| |
|
#define | OCR0A_1 1 |
| |
|
#define | OCR0A_2 2 |
| |
|
#define | OCR0A_3 3 |
| |
|
#define | OCR0A_4 4 |
| |
|
#define | OCR0A_5 5 |
| |
|
#define | OCR0A_6 6 |
| |
|
#define | OCR0A_7 7 |
| |
|
#define | SPMCSR _SFR_IO8(0x37) |
| |
|
#define | SPMEN 0 |
| |
|
#define | PGERS 1 |
| |
|
#define | PGWRT 2 |
| |
|
#define | RFLB 3 |
| |
|
#define | CTPB 4 |
| |
|
#define | TIFR0 _SFR_IO8(0x38) |
| |
|
#define | TOV0 0 |
| |
|
#define | OCF0A 1 |
| |
|
#define | OCF0B 2 |
| |
|
#define | TIMSK0 _SFR_IO8(0x39) |
| |
|
#define | TOIE0 0 |
| |
|
#define | OCIE0A 1 |
| |
|
#define | OCIE0B 2 |
| |
|
#define | GIFR _SFR_IO8(0x3A) |
| |
|
#define | PCIF0 4 |
| |
|
#define | PCIF1 5 |
| |
|
#define | INTF0 6 |
| |
|
#define | GIMSK _SFR_IO8(0x3B) |
| |
|
#define | PCIE0 4 |
| |
|
#define | PCIE1 5 |
| |
|
#define | INT0 6 |
| |
|
#define | OCR0B _SFR_IO8(0x3C) |
| |
|
#define | OCR0_0 0 |
| |
|
#define | OCR0_1 1 |
| |
|
#define | OCR0_2 2 |
| |
|
#define | OCR0_3 3 |
| |
|
#define | OCR0_4 4 |
| |
|
#define | OCR0_5 5 |
| |
|
#define | OCR0_6 6 |
| |
|
#define | OCR0_7 7 |
| |
|
#define | EXT_INT0_vect_num 1 |
| |
|
#define | EXT_INT0_vect _VECTOR(1) /* External Interrupt Request 0 */ |
| |
|
#define | PCINT0_vect_num 2 |
| |
|
#define | PCINT0_vect _VECTOR(2) /* Pin Change Interrupt Request 0 */ |
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#define | PCINT1_vect_num 3 |
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#define | PCINT1_vect _VECTOR(3) /* Pin Change Interrupt Request 1 */ |
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#define | WATCHDOG_vect_num 4 |
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#define | WATCHDOG_vect _VECTOR(4) /* Watchdog Time-out */ |
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#define | TIM1_CAPT_vect_num 5 |
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#define | TIM1_CAPT_vect _VECTOR(5) /* Timer/Counter1 Capture Event */ |
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#define | TIM1_COMPA_vect_num 6 |
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#define | TIM1_COMPA_vect _VECTOR(6) /* Timer/Counter1 Compare Match A */ |
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#define | TIM1_COMPB_vect_num 7 |
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#define | TIM1_COMPB_vect _VECTOR(7) /* Timer/Counter1 Compare Match B */ |
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#define | TIM1_OVF_vect_num 8 |
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#define | TIM1_OVF_vect _VECTOR(8) /* Timer/Counter1 Overflow */ |
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#define | TIM0_COMPA_vect_num 9 |
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#define | TIM0_COMPA_vect _VECTOR(9) /* Timer/Counter0 Compare Match A */ |
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#define | TIM0_COMPB_vect_num 10 |
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#define | TIM0_COMPB_vect _VECTOR(10) /* Timer/Counter0 Compare Match B */ |
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#define | TIM0_OVF_vect_num 11 |
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#define | TIM0_OVF_vect _VECTOR(11) /* Timer/Counter0 Overflow */ |
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#define | ANA_COMP_vect_num 12 |
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#define | ANA_COMP_vect _VECTOR(12) /* Analog Comparator */ |
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#define | ADC_vect_num 13 |
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#define | ADC_vect _VECTOR(13) /* ADC Conversion Complete */ |
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#define | EE_RDY_vect_num 14 |
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#define | EE_RDY_vect _VECTOR(14) /* EEPROM Ready */ |
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#define | USI_STR_vect_num 15 |
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#define | USI_STR_vect _VECTOR(15) /* USI START */ |
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#define | USI_OVF_vect_num 16 |
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#define | USI_OVF_vect _VECTOR(16) /* USI Overflow */ |
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#define | _VECTOR_SIZE 2 /* Size of individual vector. */ |
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#define | _VECTORS_SIZE (17 * _VECTOR_SIZE) |
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#define | SPM_PAGESIZE (32) |
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#define | RAMSTART (0x60) |
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#define | RAMSIZE (128) |
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#define | RAMEND (RAMSTART + RAMSIZE - 1) |
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#define | XRAMSTART (NA) |
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#define | XRAMSIZE (0) |
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#define | XRAMEND (RAMEND) |
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#define | E2END (0x7F) |
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#define | E2PAGESIZE (4) |
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#define | FLASHEND (0x7FF) |
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#define | FUSE_MEMORY_SIZE 3 |
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#define | FUSE_CKSEL0 (unsigned char)~_BV(0) /* Select Clock source */ |
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#define | FUSE_CKSEL1 (unsigned char)~_BV(1) /* Select Clock source */ |
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#define | FUSE_CKSEL2 (unsigned char)~_BV(2) /* Select Clock source */ |
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#define | FUSE_CKSEL3 (unsigned char)~_BV(3) /* Select Clock source */ |
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#define | FUSE_SUT0 (unsigned char)~_BV(4) /* Select start-up time */ |
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#define | FUSE_SUT1 (unsigned char)~_BV(5) /* Select start-up time */ |
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#define | FUSE_CKOUT (unsigned char)~_BV(6) /* Clock Output Enable */ |
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#define | FUSE_CKDIV8 (unsigned char)~_BV(7) /* Divide clock by 8 */ |
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#define | LFUSE_DEFAULT (FUSE_CKSEL0 & FUSE_CKSEL2 & FUSE_SUT0 & FUSE_CKDIV8) |
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#define | FUSE_BODLEVEL0 (unsigned char)~_BV(0) /* Brown-out Detector trigger level */ |
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#define | FUSE_BODLEVEL1 (unsigned char)~_BV(1) /* Brown-out Detector trigger level */ |
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#define | FUSE_BODLEVEL2 (unsigned char)~_BV(2) /* Brown-out Detector trigger level */ |
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#define | FUSE_EESAVE (unsigned char)~_BV(3) /* EEPROM memory is preserved through the Chip Erase */ |
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#define | FUSE_WDTON (unsigned char)~_BV(4) /* Watchdog Timer always on */ |
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#define | FUSE_SPIEN (unsigned char)~_BV(5) /* Enable Serial Program and Data Downloading */ |
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#define | FUSE_DWEN (unsigned char)~_BV(6) /* DebugWIRE Enable */ |
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#define | FUSE_RSTDISBL (unsigned char)~_BV(7) /* External Reset disable */ |
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#define | HFUSE_DEFAULT (FUSE_SPIEN) |
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#define | FUSE_SELFPRGEN (unsigned char)~_BV(0) /* Self-Programming Enable */ |
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#define | EFUSE_DEFAULT (0xFF) |
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#define | __LOCK_BITS_EXIST |
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#define | SIGNATURE_0 0x1E |
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#define | SIGNATURE_1 0x91 |
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#define | SIGNATURE_2 0x0B |
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#define | ADC4_DDR DDRA |
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#define | ADC4_PORT PORTA |
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#define | ADC4_PIN PINA |
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#define | ADC4_BIT 4 |
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#define | USCK_DDR DDRA |
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#define | USCK_PORT PORTA |
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#define | USCK_PIN PINA |
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#define | USCK_BIT 4 |
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#define | SCL_DDR DDRA |
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#define | SCL_PORT PORTA |
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#define | SCL_PIN PINA |
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#define | SCL_BIT 4 |
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#define | T1_DDR DDRA |
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#define | T1_PORT PORTA |
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#define | T1_PIN PINA |
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#define | T1_BIT 4 |
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#define | PCINT4_DDR DDRA |
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#define | PCINT4_PORT PORTA |
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#define | PCINT4_PIN PINA |
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#define | PCINT4_BIT 4 |
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#define | ADC3_DDR DDRA |
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#define | ADC3_PORT PORTA |
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#define | ADC3_PIN PINA |
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#define | ADC3_BIT 3 |
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#define | T0_DDR DDRA |
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#define | T0_PORT PORTA |
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#define | T0_PIN PINA |
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#define | T0_BIT 3 |
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#define | PCINT3_DDR DDRA |
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#define | PCINT3_PORT PORTA |
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#define | PCINT3_PIN PINA |
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#define | PCINT3_BIT 3 |
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#define | ADC2_DDR DDRA |
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#define | ADC2_PORT PORTA |
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#define | ADC2_PIN PINA |
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#define | ADC2_BIT 2 |
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#define | AIN1_DDR DDRA |
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#define | AIN1_PORT PORTA |
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#define | AIN1_PIN PINA |
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#define | AIN1_BIT 2 |
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#define | PCINT2_DDR DDRA |
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#define | PCINT2_PORT PORTA |
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#define | PCINT2_PIN PINA |
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#define | PCINT2_BIT 2 |
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#define | ADC1_DDR DDRA |
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#define | ADC1_PORT PORTA |
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#define | ADC1_PIN PINA |
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#define | ADC1_BIT 1 |
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#define | AIN0_DDR DDRA |
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#define | AIN0_PORT PORTA |
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#define | AIN0_PIN PINA |
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#define | AIN0_BIT 1 |
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#define | PCINT1_DDR DDRA |
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#define | PCINT1_PORT PORTA |
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#define | PCINT1_PIN PINA |
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#define | PCINT1_BIT 1 |
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#define | ADC0_DDR DDRA |
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#define | ADC0_PORT PORTA |
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#define | ADC0_PIN PINA |
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#define | ADC0_BIT 0 |
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#define | PCINT0_DDR DDRA |
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#define | PCINT0_PORT PORTA |
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#define | PCINT0_PIN PINA |
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#define | PCINT0_BIT 0 |
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#define | PCINT8_DDR DDRB |
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#define | PCINT8_PORT PORTB |
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#define | PCINT8_PIN PINB |
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#define | PCINT8_BIT 0 |
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#define | PCINT9_DDR DDRB |
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#define | PCINT9_PORT PORTB |
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#define | PCINT9_PIN PINB |
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#define | PCINT9_BIT 1 |
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#define | PCINT11_DDR DDRB |
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#define | PCINT11_PORT PORTB |
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#define | PCINT11_PIN PINB |
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#define | PCINT11_BIT 3 |
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#define | dW_DDR DDRB |
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#define | dW_PORT PORTB |
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#define | dW_PIN PINB |
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#define | dW_BIT 3 |
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#define | PCINT10_DDR DDRB |
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#define | PCINT10_PORT PORTB |
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#define | PCINT10_PIN PINB |
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#define | PCINT10_BIT 2 |
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#define | INT0_DDR DDRB |
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#define | INT0_PORT PORTB |
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#define | INT0_PIN PINB |
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#define | INT0_BIT 2 |
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#define | OC0A_DDR DDRB |
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#define | OC0A_PORT PORTB |
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#define | OC0A_PIN PINB |
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#define | OC0A_BIT 2 |
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#define | CKOUT_DDR DDRB |
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#define | CKOUT_PORT PORTB |
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#define | CKOUT_PIN PINB |
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#define | CKOUT_BIT 2 |
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#define | PCINT7_DDR DDRA |
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#define | PCINT7_PORT PORTA |
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#define | PCINT7_PIN PINA |
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#define | PCINT7_BIT 7 |
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#define | ICP1_DDR DDRA |
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#define | ICP1_PORT PORTA |
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#define | ICP1_PIN PINA |
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#define | ICP1_BIT 7 |
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#define | OC0B_DDR DDRA |
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#define | OC0B_PORT PORTA |
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#define | OC0B_PIN PINA |
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#define | OC0B_BIT 7 |
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#define | ADC7_DDR DDRA |
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#define | ADC7_PORT PORTA |
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#define | ADC7_PIN PINA |
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#define | ADC7_BIT 7 |
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#define | PCINT6_DDR DDRA |
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#define | PCINT6_PORT PORTA |
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#define | PCINT6_PIN PINA |
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#define | PCINT6_BIT 6 |
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#define | OC1A_DDR DDRA |
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#define | OC1A_PORT PORTA |
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#define | OC1A_PIN PINA |
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#define | OC1A_BIT 6 |
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#define | DI_DDR DDRA |
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#define | DI_PORT PORTA |
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#define | DI_PIN PINA |
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#define | DI_BIT 6 |
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#define | SDA_DDR DDRA |
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#define | SDA_PORT PORTA |
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#define | SDA_PIN PINA |
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#define | SDA_BIT 6 |
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#define | MOSI_DDR DDRA |
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#define | MOSI_PORT PORTA |
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#define | MOSI_PIN PINA |
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#define | MOSI_BIT 6 |
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#define | ADC6_DDR DDRA |
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#define | ADC6_PORT PORTA |
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#define | ADC6_PIN PINA |
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#define | ADC6_BIT 6 |
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#define | ADC5_DDR DDRA |
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#define | ADC5_PORT PORTA |
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#define | ADC5_PIN PINA |
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#define | ADC5_BIT 5 |
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#define | DO_DDR DDRA |
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#define | DO_PORT PORTA |
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#define | DO_PIN PINA |
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#define | DO_BIT 5 |
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#define | MISO_DDR DDRA |
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#define | MISO_PORT PORTA |
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#define | MISO_PIN PINA |
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#define | MISO_BIT 5 |
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#define | OC1B_DDR DDRA |
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#define | OC1B_PORT PORTA |
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#define | OC1B_PIN PINA |
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#define | OC1B_BIT 5 |
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#define | PCINT5_DDR DDRA |
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#define | PCINT5_PORT PORTA |
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#define | PCINT5_PIN PINA |
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#define | PCINT5_BIT 5 |
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