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#define | _AVR_IOXXX_H_ "iom8515.h" |
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#define | OSCCAL _SFR_IO8(0x04) |
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#define | PINE _SFR_IO8(0x05) |
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#define | DDRE _SFR_IO8(0x06) |
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#define | PORTE _SFR_IO8(0x07) |
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#define | ACSR _SFR_IO8(0x08) |
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#define | UBRRL _SFR_IO8(0x09) |
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#define | UCSRB _SFR_IO8(0x0A) |
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#define | UCSRA _SFR_IO8(0x0B) |
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#define | UDR _SFR_IO8(0x0C) |
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#define | SPCR _SFR_IO8(0x0D) |
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#define | SPSR _SFR_IO8(0x0E) |
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#define | SPDR _SFR_IO8(0x0F) |
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#define | PIND _SFR_IO8(0x10) |
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#define | DDRD _SFR_IO8(0x11) |
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#define | PORTD _SFR_IO8(0x12) |
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#define | PINC _SFR_IO8(0x13) |
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#define | DDRC _SFR_IO8(0x14) |
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#define | PORTC _SFR_IO8(0x15) |
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#define | PINB _SFR_IO8(0x16) |
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#define | DDRB _SFR_IO8(0x17) |
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#define | PORTB _SFR_IO8(0x18) |
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#define | PINA _SFR_IO8(0x19) |
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#define | DDRA _SFR_IO8(0x1A) |
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#define | PORTA _SFR_IO8(0x1B) |
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#define | EECR _SFR_IO8(0x1C) |
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#define | EEDR _SFR_IO8(0x1D) |
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#define | EEAR _SFR_IO16(0x1E) |
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#define | EEARL _SFR_IO8(0x1E) |
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#define | EEARH _SFR_IO8(0x1F) |
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#define | UBRRH _SFR_IO8(0x20) |
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#define | UCSRC UBRRH |
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#define | WDTCR _SFR_IO8(0x21) |
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#define | ICR1 _SFR_IO16(0x24) |
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#define | ICR1L _SFR_IO8(0x24) |
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#define | ICR1H _SFR_IO8(0x25) |
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#define | OCR1B _SFR_IO16(0x28) |
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#define | OCR1BL _SFR_IO8(0x28) |
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#define | OCR1BH _SFR_IO8(0x29) |
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#define | OCR1A _SFR_IO16(0x2A) |
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#define | OCR1AL _SFR_IO8(0x2A) |
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#define | OCR1AH _SFR_IO8(0x2B) |
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#define | TCNT1 _SFR_IO16(0x2C) |
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#define | TCNT1L _SFR_IO8(0x2C) |
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#define | TCNT1H _SFR_IO8(0x2D) |
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#define | TCCR1B _SFR_IO8(0x2E) |
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#define | TCCR1A _SFR_IO8(0x2F) |
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#define | SFIOR _SFR_IO8(0x30) |
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#define | OCR0 _SFR_IO8(0x31) |
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#define | TCNT0 _SFR_IO8(0x32) |
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#define | TCCR0 _SFR_IO8(0x33) |
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#define | MCUCSR _SFR_IO8(0x34) |
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#define | MCUCR _SFR_IO8(0x35) |
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#define | EMCUCR _SFR_IO8(0x36) |
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#define | SPMCR _SFR_IO8(0x37) |
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#define | TIFR _SFR_IO8(0x38) |
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#define | TIMSK _SFR_IO8(0x39) |
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#define | GIFR _SFR_IO8(0x3A) |
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#define | GICR _SFR_IO8(0x3B) |
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#define | INT0_vect _VECTOR(1) |
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#define | SIG_INTERRUPT0 _VECTOR(1) |
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#define | INT1_vect _VECTOR(2) |
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#define | SIG_INTERRUPT1 _VECTOR(2) |
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#define | TIMER1_CAPT_vect _VECTOR(3) |
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#define | SIG_INPUT_CAPTURE1 _VECTOR(3) |
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#define | TIMER1_COMPA_vect _VECTOR(4) |
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#define | SIG_OUTPUT_COMPARE1A _VECTOR(4) |
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#define | TIMER1_COMPB_vect _VECTOR(5) |
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#define | SIG_OUTPUT_COMPARE1B _VECTOR(5) |
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#define | TIMER1_OVF_vect _VECTOR(6) |
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#define | SIG_OVERFLOW1 _VECTOR(6) |
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#define | TIMER0_OVF_vect _VECTOR(7) |
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#define | SIG_OVERFLOW0 _VECTOR(7) |
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#define | SPI_STC_vect _VECTOR(8) |
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#define | SIG_SPI _VECTOR(8) |
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#define | USART_RX_vect _VECTOR(9) |
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#define | UART_RX_vect _VECTOR(9) /* For compatability only */ |
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#define | SIG_UART_RECV _VECTOR(9) /* For compatability only */ |
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#define | USART_UDRE_vect _VECTOR(10) |
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#define | UART_UDRE_vect _VECTOR(10) /* For compatability only */ |
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#define | SIG_UART_DATA _VECTOR(10) /* For compatability only */ |
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#define | USART_TX_vect _VECTOR(11) |
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#define | UART_TX_vect _VECTOR(11) /* For compatability only */ |
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#define | SIG_UART_TRANS _VECTOR(11) /* For compatability only */ |
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#define | ANA_COMP_vect _VECTOR(12) |
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#define | SIG_COMPARATOR _VECTOR(12) |
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#define | INT2_vect _VECTOR(13) |
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#define | SIG_INTERRUPT2 _VECTOR(13) |
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#define | TIMER0_COMP_vect _VECTOR(14) |
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#define | SIG_OUTPUT_COMPARE0 _VECTOR(14) |
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#define | EE_RDY_vect _VECTOR(15) |
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#define | SIG_EEPROM_READY _VECTOR(15) |
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#define | SPM_RDY_vect _VECTOR(16) |
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#define | SIG_SPM_READY _VECTOR(16) |
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#define | _VECTORS_SIZE 34 |
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#define | INT1 7 |
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#define | INT0 6 |
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#define | INT2 5 |
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#define | IVSEL 1 |
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#define | IVCE 0 |
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#define | INTF1 7 |
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#define | INTF0 6 |
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#define | INTF2 5 |
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#define | TOIE1 7 |
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#define | OCIE1A 6 |
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#define | OCIE1B 5 |
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#define | TICIE1 3 |
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#define | TOIE0 1 |
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#define | OCIE0 0 |
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#define | TOV1 7 |
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#define | OCF1A 6 |
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#define | OCF1B 5 |
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#define | ICF1 3 |
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#define | TOV0 1 |
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#define | OCF0 0 |
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#define | SPMIE 7 |
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#define | RWWSB 6 |
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#define | RWWSRE 4 |
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#define | BLBSET 3 |
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#define | PGWRT 2 |
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#define | PGERS 1 |
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#define | SPMEN 0 |
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#define | SM0 7 |
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#define | SRL2 6 |
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#define | SRL1 5 |
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#define | SRL0 4 |
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#define | SRW01 3 |
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#define | SRW00 2 |
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#define | SRW11 1 |
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#define | ISC2 0 |
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#define | SRE 7 |
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#define | SRW10 6 |
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#define | SE 5 |
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#define | SM1 4 |
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#define | ISC11 3 |
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#define | ISC10 2 |
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#define | ISC01 1 |
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#define | ISC00 0 |
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#define | SM2 5 |
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#define | WDRF 3 |
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#define | BORF 2 |
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#define | EXTRF 1 |
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#define | PORF 0 |
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#define | FOC0 7 |
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#define | WGM00 6 |
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#define | COM01 5 |
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#define | COM00 4 |
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#define | WGM01 3 |
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#define | CS02 2 |
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#define | CS01 1 |
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#define | CS00 0 |
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#define | XMBK 6 |
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#define | XMM2 5 |
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#define | XMM1 4 |
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#define | XMM0 3 |
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#define | PUD 2 |
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#define | PSR10 0 |
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#define | COM1A1 7 |
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#define | COM1A0 6 |
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#define | COM1B1 5 |
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#define | COM1B0 4 |
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#define | FOC1A 3 |
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#define | FOC1B 2 |
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#define | WGM11 1 |
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#define | WGM10 0 |
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#define | ICNC1 7 |
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#define | ICES1 6 |
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#define | WGM13 4 |
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#define | WGM12 3 |
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#define | CS12 2 |
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#define | CS11 1 |
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#define | CS10 0 |
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#define | WDCE 4 |
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#define | WDE 3 |
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#define | WDP2 2 |
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#define | WDP1 1 |
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#define | WDP0 0 |
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#define | URSEL 7 |
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#define | UMSEL 6 |
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#define | UPM1 5 |
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#define | UPM0 4 |
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#define | USBS 3 |
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#define | UCSZ1 2 |
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#define | UCSZ0 1 |
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#define | UCPOL 0 |
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#define | PA7 7 |
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#define | PA6 6 |
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#define | PA5 5 |
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#define | PA4 4 |
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#define | PA3 3 |
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#define | PA2 2 |
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#define | PA1 1 |
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#define | PA0 0 |
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#define | DDA7 7 |
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#define | DDA6 6 |
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#define | DDA5 5 |
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#define | DDA4 4 |
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#define | DDA3 3 |
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#define | DDA2 2 |
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#define | DDA1 1 |
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#define | DDA0 0 |
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#define | PINA7 7 |
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#define | PINA6 6 |
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#define | PINA5 5 |
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#define | PINA4 4 |
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#define | PINA3 3 |
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#define | PINA2 2 |
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#define | PINA1 1 |
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#define | PINA0 0 |
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#define | PB7 7 |
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#define | PB6 6 |
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#define | PB5 5 |
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#define | PB4 4 |
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#define | PB3 3 |
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#define | PB2 2 |
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#define | PB1 1 |
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#define | PB0 0 |
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#define | DDB7 7 |
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#define | DDB6 6 |
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#define | DDB5 5 |
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#define | DDB4 4 |
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#define | DDB3 3 |
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#define | DDB2 2 |
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#define | DDB1 1 |
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#define | DDB0 0 |
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#define | PINB7 7 |
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#define | PINB6 6 |
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#define | PINB5 5 |
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#define | PINB4 4 |
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#define | PINB3 3 |
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#define | PINB2 2 |
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#define | PINB1 1 |
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#define | PINB0 0 |
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#define | PC7 7 |
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#define | PC6 6 |
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#define | PC5 5 |
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#define | PC4 4 |
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#define | PC3 3 |
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#define | PC2 2 |
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#define | PC1 1 |
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#define | PC0 0 |
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#define | DDC7 7 |
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#define | DDC6 6 |
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#define | DDC5 5 |
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#define | DDC4 4 |
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#define | DDC3 3 |
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#define | DDC2 2 |
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#define | DDC1 1 |
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#define | DDC0 0 |
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#define | PINC7 7 |
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#define | PINC6 6 |
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#define | PINC5 5 |
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#define | PINC4 4 |
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#define | PINC3 3 |
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#define | PINC2 2 |
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#define | PINC1 1 |
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#define | PINC0 0 |
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#define | PD7 7 |
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#define | PD6 6 |
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#define | PD5 5 |
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#define | PD4 4 |
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#define | PD3 3 |
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#define | PD2 2 |
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#define | PD1 1 |
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#define | PD0 0 |
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#define | DDD7 7 |
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#define | DDD6 6 |
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#define | DDD5 5 |
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#define | DDD4 4 |
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#define | DDD3 3 |
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#define | DDD2 2 |
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#define | DDD1 1 |
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#define | DDD0 0 |
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#define | PIND7 7 |
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#define | PIND6 6 |
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#define | PIND5 5 |
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#define | PIND4 4 |
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#define | PIND3 3 |
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#define | PIND2 2 |
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#define | PIND1 1 |
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#define | PIND0 0 |
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#define | SPIF 7 |
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#define | WCOL 6 |
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#define | SPI2X 0 |
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#define | SPIE 7 |
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#define | SPE 6 |
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#define | DORD 5 |
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#define | MSTR 4 |
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#define | CPOL 3 |
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#define | CPHA 2 |
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#define | SPR1 1 |
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#define | SPR0 0 |
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#define | RXC 7 |
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#define | TXC 6 |
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#define | UDRE 5 |
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#define | FE 4 |
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#define | DOR 3 |
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#define | PE 2 |
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#define | U2X 1 |
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#define | MPCM 0 |
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#define | RXCIE 7 |
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#define | TXCIE 6 |
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#define | UDRIE 5 |
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#define | RXEN 4 |
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#define | TXEN 3 |
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#define | UCSZ2 2 |
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#define | RXB8 1 |
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#define | TXB8 0 |
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#define | ACD 7 |
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#define | ACBG 6 |
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#define | ACO 5 |
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#define | ACI 4 |
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#define | ACIE 3 |
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#define | ACIC 2 |
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#define | ACIS1 1 |
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#define | ACIS0 0 |
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#define | PE2 2 |
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#define | PE1 1 |
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#define | PE0 0 |
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#define | DDE2 2 |
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#define | DDE1 1 |
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#define | DDE0 0 |
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#define | PINE2 2 |
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#define | PINE1 1 |
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#define | PINE0 0 |
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#define | EERIE 3 |
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#define | EEMWE 2 |
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#define | EEWE 1 |
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#define | EERE 0 |
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#define | SPM_PAGESIZE 64 |
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#define | RAMEND 0x25F /* Last On-Chip SRAM Location */ |
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#define | XRAMEND 0xFFFF |
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#define | E2END 0x1FF |
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#define | E2PAGESIZE 4 |
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#define | FLASHEND 0x1FFF |
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#define | FUSE_MEMORY_SIZE 2 |
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#define | FUSE_CKSEL0 (unsigned char)~_BV(0) |
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#define | FUSE_CKSEL1 (unsigned char)~_BV(1) |
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#define | FUSE_CKSEL2 (unsigned char)~_BV(2) |
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#define | FUSE_CKSEL3 (unsigned char)~_BV(3) |
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#define | FUSE_SUT0 (unsigned char)~_BV(4) |
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#define | FUSE_SUT1 (unsigned char)~_BV(5) |
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#define | FUSE_BODEN (unsigned char)~_BV(6) |
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#define | FUSE_BODLEVEL (unsigned char)~_BV(7) |
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#define | LFUSE_DEFAULT (FUSE_CKSEL1 & FUSE_CKSEL2 & FUSE_CKSEL3 & FUSE_SUT0) |
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#define | FUSE_BOOTRST (unsigned char)~_BV(0) |
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#define | FUSE_BOOTSZ0 (unsigned char)~_BV(1) |
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#define | FUSE_BOOTSZ1 (unsigned char)~_BV(2) |
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#define | FUSE_EESAVE (unsigned char)~_BV(3) |
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#define | FUSE_CKOPT (unsigned char)~_BV(4) |
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#define | FUSE_SPIEN (unsigned char)~_BV(5) |
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#define | FUSE_WDTON (unsigned char)~_BV(6) |
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#define | FUSE_S8515C (unsigned char)~_BV(7) |
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#define | HFUSE_DEFAULT (FUSE_BOOTSZ0 & FUSE_BOOTSZ1 & FUSE_SPIEN) |
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#define | __LOCK_BITS_EXIST |
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#define | __BOOT_LOCK_BITS_0_EXIST |
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#define | __BOOT_LOCK_BITS_1_EXIST |
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#define | SIGNATURE_0 0x1E |
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#define | SIGNATURE_1 0x93 |
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#define | SIGNATURE_2 0x06 |
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