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#define | _AVR_IOXXX_H_ "iom406.h" |
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#define | PINA _SFR_IO8(0x00) |
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#define | PINA7 7 |
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#define | PINA6 6 |
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#define | PINA5 5 |
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#define | PINA4 4 |
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#define | PINA3 3 |
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#define | PINA2 2 |
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#define | PINA1 1 |
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#define | PINA0 0 |
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#define | DDRA _SFR_IO8(0x01) |
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#define | DDA7 7 |
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#define | DDA6 6 |
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#define | DDA5 5 |
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#define | DDA4 4 |
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#define | DDA3 3 |
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#define | DDA2 2 |
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#define | DDA1 1 |
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#define | DDA0 0 |
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#define | PORTA _SFR_IO8(0x02) |
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#define | PA7 7 |
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#define | PA6 6 |
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#define | PA5 5 |
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#define | PA4 4 |
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#define | PA3 3 |
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#define | PA2 2 |
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#define | PA1 1 |
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#define | PA0 0 |
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#define | PINB _SFR_IO8(0x03) |
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#define | PINB7 7 |
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#define | PINB6 6 |
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#define | PINB5 5 |
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#define | PINB4 4 |
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#define | PINB3 3 |
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#define | PINB2 2 |
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#define | PINB1 1 |
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#define | PINB0 0 |
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#define | DDRB _SFR_IO8(0x04) |
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#define | DDB7 7 |
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#define | DDB6 6 |
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#define | DDB5 5 |
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#define | DDB4 4 |
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#define | DDB3 3 |
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#define | DDB2 2 |
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#define | DDB1 1 |
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#define | DDB0 0 |
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#define | PORTB _SFR_IO8(0x05) |
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#define | PB7 7 |
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#define | PB6 6 |
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#define | PB5 5 |
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#define | PB4 4 |
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#define | PB3 3 |
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#define | PB2 2 |
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#define | PB1 1 |
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#define | PB0 0 |
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#define | PORTC _SFR_IO8(0x08) |
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#define | PC0 0 |
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#define | PIND _SFR_IO8(0x09) |
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#define | PIND1 1 |
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#define | PIND0 0 |
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#define | DDRD _SFR_IO8(0x0A) |
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#define | DDD1 1 |
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#define | DDD0 0 |
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#define | PORTD _SFR_IO8(0x0B) |
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#define | PD1 1 |
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#define | PD0 0 |
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#define | TIFR0 _SFR_IO8(0x15) |
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#define | OCF0B 2 |
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#define | OCF0A 1 |
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#define | TOV0 0 |
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#define | TIFR1 _SFR_IO8(0x16) |
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#define | OCF1A 1 |
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#define | TOV1 0 |
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#define | PCIFR _SFR_IO8(0x1B) |
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#define | PCIF1 1 |
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#define | PCIF0 0 |
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#define | EIFR _SFR_IO8(0x1C) |
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#define | INTF3 3 |
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#define | INTF2 2 |
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#define | INTF1 1 |
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#define | INTF0 0 |
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#define | EIMSK _SFR_IO8(0x1D) |
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#define | INT3 3 |
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#define | INT2 2 |
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#define | INT1 1 |
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#define | INT0 0 |
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#define | GPIOR0 _SFR_IO8(0x1E) |
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#define | EECR _SFR_IO8(0x1F) |
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#define | EEPM1 5 |
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#define | EEPM0 4 |
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#define | EERIE 3 |
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#define | EEMPE 2 |
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#define | EEPE 1 |
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#define | EERE 0 |
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#define | EEDR _SFR_IO8(0x20) |
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#define | EEAR _SFR_IO16(0x21) |
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#define | EEARL _SFR_IO8(0x21) |
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#define | EEARH _SFR_IO8(0x22) |
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#define | __EEPROM_REG_LOCATIONS__ 1F2021 |
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#define | GTCCR _SFR_IO8(0x23) |
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#define | TSM 7 |
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#define | PSRSYNC 0 |
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#define | TCCR0A _SFR_IO8(0x24) |
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#define | COM0A1 7 |
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#define | COM0A0 6 |
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#define | COM0B1 5 |
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#define | COM0B0 4 |
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#define | WGM01 1 |
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#define | WGM00 0 |
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#define | TCCR0B _SFR_IO8(0x25) |
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#define | FOC0A 7 |
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#define | FOC0B 6 |
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#define | WGM02 3 |
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#define | CS02 2 |
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#define | CS01 1 |
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#define | CS00 0 |
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#define | TCNT0 _SFR_IO8(0x26) |
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#define | OCR0A _SFR_IO8(0x27) |
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#define | OCR0B _SFR_IO8(0x28) |
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#define | GPIOR1 _SFR_IO8(0x2A) |
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#define | GPIOR2 _SFR_IO8(0x2B) |
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#define | OCDR _SFR_IO8(0x31) |
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#define | SMCR _SFR_IO8(0x33) |
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#define | SM2 3 |
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#define | SM1 2 |
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#define | SM0 1 |
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#define | SE 0 |
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#define | MCUSR _SFR_IO8(0x34) |
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#define | JTRF 4 |
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#define | WDRF 3 |
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#define | BODRF 2 |
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#define | EXTRF 1 |
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#define | PORF 0 |
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#define | MCUCR _SFR_IO8(0x35) |
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#define | JTD 7 |
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#define | PUD 4 |
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#define | IVSEL 1 |
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#define | IVCE 0 |
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#define | SPMCSR _SFR_IO8(0x37) |
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#define | SPMIE 7 |
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#define | RWWSB 6 |
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#define | SIGRD 5 |
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#define | RWWSRE 4 |
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#define | BLBSET 3 |
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#define | PGWRT 2 |
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#define | PGERS 1 |
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#define | SPMEN 0 |
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#define | WDTCSR _SFR_MEM8(0x60) |
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#define | WDIF 7 |
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#define | WDIE 6 |
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#define | WDP3 5 |
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#define | WDCE 4 |
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#define | WDE 3 |
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#define | WDP2 2 |
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#define | WDP1 1 |
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#define | WDP0 0 |
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#define | WUTCSR _SFR_MEM8(0x62) |
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#define | WUTIF 7 |
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#define | WUTIE 6 |
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#define | WUTCF 5 |
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#define | WUTR 4 |
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#define | WUTE 3 |
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#define | WUTP2 2 |
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#define | WUTP1 1 |
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#define | WUTP0 0 |
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#define | PRR0 _SFR_MEM8(0x64) |
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#define | PRTWI 3 |
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#define | PRTIM1 2 |
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#define | PRTIM0 1 |
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#define | PRVADC 0 |
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#define | FOSCCAL _SFR_MEM8(0x66) |
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#define | PCICR _SFR_MEM8(0x68) |
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#define | PCIE1 1 |
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#define | PCIE0 0 |
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#define | EICRA _SFR_MEM8(0x69) |
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#define | ISC31 7 |
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#define | ISC30 6 |
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#define | ISC21 5 |
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#define | ISC20 4 |
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#define | ISC11 3 |
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#define | ISC10 2 |
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#define | ISC01 1 |
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#define | ISC00 0 |
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#define | PCMSK0 _SFR_MEM8(0x6B) |
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#define | PCINT7 7 |
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#define | PCINT6 6 |
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#define | PCINT5 5 |
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#define | PCINT4 4 |
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#define | PCINT3 3 |
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#define | PCINT2 2 |
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#define | PCINT1 1 |
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#define | PCINT0 0 |
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#define | PCMSK1 _SFR_MEM8(0x6C) |
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#define | PCINT15 7 |
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#define | PCINT14 6 |
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#define | PCINT13 5 |
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#define | PCINT12 4 |
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#define | PCINT11 3 |
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#define | PCINT10 2 |
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#define | PCINT9 1 |
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#define | PCINT8 0 |
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#define | TIMSK0 _SFR_MEM8(0x6E) |
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#define | OCIE0B 2 |
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#define | OCIE0A 1 |
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#define | TOIE0 0 |
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#define | TIMSK1 _SFR_MEM8(0x6F) |
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#define | OCIE1A 1 |
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#define | TOIE1 0 |
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#define | VADC _SFR_MEM16(0x78) |
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#define | VADCL _SFR_MEM8(0x78) |
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#define | VADCH _SFR_MEM8(0x79) |
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#define | VADCSR _SFR_MEM8(0x7A) |
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#define | VADEN 3 |
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#define | VADSC 2 |
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#define | VADCCIF 1 |
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#define | VADCCIE 0 |
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#define | VADMUX _SFR_MEM8(0x7C) |
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#define | VADMUX3 3 |
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#define | VADMUX2 2 |
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#define | VADMUX1 1 |
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#define | VADMUX0 0 |
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#define | DIDR0 _SFR_MEM8(0x7E) |
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#define | VADC3D 3 |
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#define | VADC2D 2 |
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#define | VADC1D 1 |
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#define | VADC0D 0 |
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#define | TCCR1B _SFR_MEM8(0x81) |
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#define | CTC1 3 |
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#define | CS12 2 |
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#define | CS11 1 |
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#define | CS10 0 |
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#define | TCNT1 _SFR_MEM16(0x84) |
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#define | TCNT1L _SFR_MEM8(0x84) |
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#define | TCNT1H _SFR_MEM8(0x85) |
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#define | OCR1A _SFR_MEM16(0x88) |
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#define | OCR1AL _SFR_MEM8(0x88) |
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#define | OCR1AH _SFR_MEM8(0x89) |
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#define | TWBR _SFR_MEM8(0xB8) |
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#define | TWSR _SFR_MEM8(0xB9) |
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#define | TWS7 7 |
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#define | TWS6 6 |
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#define | TWS5 5 |
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#define | TWS4 4 |
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#define | TWS3 3 |
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#define | TWPS1 1 |
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#define | TWPS0 0 |
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#define | TWAR _SFR_MEM8(0xBA) |
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#define | TWA6 7 |
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#define | TWA5 6 |
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#define | TWA4 5 |
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#define | TWA3 4 |
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#define | TWA2 3 |
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#define | TWA1 2 |
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#define | TWA0 1 |
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#define | TWGCE 0 |
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#define | TWDR _SFR_MEM8(0xBB) |
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#define | TWCR _SFR_MEM8(0xBC) |
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#define | TWINT 7 |
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#define | TWEA 6 |
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#define | TWSTA 5 |
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#define | TWSTO 4 |
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#define | TWWC 3 |
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#define | TWEN 2 |
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#define | TWIE 0 |
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#define | TWAMR _SFR_MEM8(0xBD) |
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#define | TWAM6 7 |
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#define | TWAM5 6 |
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#define | TWAM4 5 |
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#define | TWAM3 4 |
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#define | TWAM2 3 |
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#define | TWAM1 2 |
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#define | TWAM0 1 |
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#define | TWBCSR _SFR_MEM8(0xBE) |
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#define | TWBCIF 7 |
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#define | TWBCIE 6 |
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#define | TWBDT1 2 |
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#define | TWBDT0 1 |
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#define | TWBCIP 0 |
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#define | CCSR _SFR_MEM8(0xC0) |
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#define | XOE 1 |
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#define | ACS 0 |
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#define | BGCCR _SFR_MEM8(0xD0) |
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#define | BGEN 7 |
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#define | BGCC5 5 |
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#define | BGCC4 4 |
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#define | BGCC3 3 |
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#define | BGCC2 2 |
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#define | BGCC1 1 |
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#define | BGCC0 0 |
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#define | BGCRR _SFR_MEM8(0xD1) |
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#define | BGCR7 7 |
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#define | BGCR6 6 |
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#define | BGCR5 5 |
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#define | BGCR4 4 |
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#define | BGCR3 3 |
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#define | BGCR2 2 |
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#define | BGCR1 1 |
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#define | BGCR0 0 |
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#define | CADAC0 _SFR_MEM8(0xE0) |
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#define | CADAC1 _SFR_MEM8(0xE1) |
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#define | CADAC2 _SFR_MEM8(0xE2) |
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#define | CADAC3 _SFR_MEM8(0xE3) |
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#define | CADCSRA _SFR_MEM8(0xE4) |
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#define | CADEN 7 |
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#define | CADUB 5 |
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#define | CADAS1 4 |
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#define | CADAS0 3 |
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#define | CADSI1 2 |
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#define | CADSI0 1 |
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#define | CADSE 0 |
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#define | CADCSRB _SFR_MEM8(0xE5) |
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#define | CADACIE 6 |
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#define | CADRCIE 5 |
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#define | CADICIE 4 |
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#define | CADACIF 2 |
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#define | CADRCIF 1 |
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#define | CADICIF 0 |
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#define | CADRCC _SFR_MEM8(0xE6) |
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#define | CADRDC _SFR_MEM8(0xE7) |
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#define | CADIC _SFR_MEM16(0xE8) |
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#define | CADICL _SFR_MEM8(0xE8) |
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#define | CADICH _SFR_MEM8(0xE9) |
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#define | FCSR _SFR_MEM8(0xF0) |
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#define | PWMOC 5 |
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#define | PWMOPC 4 |
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#define | CPS 3 |
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#define | DFE 2 |
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#define | CFE 1 |
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#define | PFD 0 |
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#define | CBCR _SFR_MEM8(0xF1) |
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#define | CBE4 3 |
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#define | CBE3 2 |
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#define | CBE2 1 |
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#define | CBE1 0 |
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#define | BPIR _SFR_MEM8(0xF2) |
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#define | DUVIF 7 |
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#define | COCIF 6 |
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#define | DOCIF 5 |
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#define | SCIF 4 |
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#define | DUVIE 3 |
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#define | COCIE 2 |
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#define | DOCIE 1 |
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#define | SCIE 0 |
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#define | BPDUV _SFR_MEM8(0xF3) |
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#define | DUVT1 5 |
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#define | DUVT0 4 |
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#define | DUDL3 3 |
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#define | DUDL2 2 |
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#define | DUDL1 1 |
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#define | DUDL0 0 |
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#define | BPSCD _SFR_MEM8(0xF4) |
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#define | SCDL3 3 |
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#define | SCDL2 2 |
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#define | SCDL1 1 |
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#define | SCDL0 0 |
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#define | BPOCD _SFR_MEM8(0xF5) |
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#define | DCDL3 7 |
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#define | DCDL2 6 |
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#define | DCDL1 5 |
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#define | DCDL0 4 |
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#define | CCDL3 3 |
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#define | CCDL2 2 |
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#define | CCDL1 1 |
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#define | CCDL0 0 |
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#define | CBPTR _SFR_MEM8(0xF6) |
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#define | SCPT3 7 |
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#define | SCPT2 6 |
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#define | SCPT1 5 |
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#define | SCPT0 4 |
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#define | OCPT3 3 |
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#define | OCPT2 2 |
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#define | OCPT1 1 |
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#define | OCPT0 0 |
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#define | BPCR _SFR_MEM8(0xF7) |
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#define | DUVD 3 |
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#define | SCD 2 |
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#define | DCD 1 |
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#define | CCD 0 |
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#define | BPPLR _SFR_MEM8(0xF8) |
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#define | BPPLE 1 |
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#define | BPPL 0 |
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#define | BPINT_vect _VECTOR(1) |
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#define | INT0_vect _VECTOR(2) |
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#define | INT1_vect _VECTOR(3) |
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#define | INT2_vect _VECTOR(4) |
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#define | INT3_vect _VECTOR(5) |
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#define | PCINT0_vect _VECTOR(6) |
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#define | PCINT1_vect _VECTOR(7) |
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#define | WDT_vect _VECTOR(8) |
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#define | WAKE_UP_vect _VECTOR(9) |
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#define | TIM1_COMP_vect _VECTOR(10) |
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#define | TIM1_OVF_vect _VECTOR(11) |
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#define | TIM0_COMPA_vect _VECTOR(12) |
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#define | TIM0_COMPB_vect _VECTOR(13) |
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#define | TIM0_OVF_vect _VECTOR(14) |
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#define | TWI_BUS_CD_vect _VECTOR(15) |
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#define | TWI_vect _VECTOR(16) |
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#define | VADC_vect _VECTOR(17) |
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#define | CCADC_CONV_vect _VECTOR(18) |
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#define | CCADC_REG_CUR_vect _VECTOR(19) |
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#define | CCADC_ACC_vect _VECTOR(20) |
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#define | EE_READY_vect _VECTOR(21) |
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#define | SPM_READY_vect _VECTOR(22) |
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#define | _VECTORS_SIZE 92 |
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#define | SPM_PAGESIZE 128 |
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#define | RAMEND 0x8FF |
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#define | XRAMEND RAMEND |
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#define | E2END 0x1FF |
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#define | E2PAGESIZE 4 |
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#define | FLASHEND 0x9FFF |
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#define | FUSE_MEMORY_SIZE 2 |
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#define | FUSE_CKSEL (unsigned char)~_BV(0) |
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#define | FUSE_SUT0 (unsigned char)~_BV(1) |
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#define | FUSE_SUT1 (unsigned char)~_BV(2) |
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#define | FUSE_BOOTRST (unsigned char)~_BV(3) |
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#define | FUSE_BOOTSZ0 (unsigned char)~_BV(4) |
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#define | FUSE_BOOTSZ1 (unsigned char)~_BV(5) |
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#define | FUSE_EESAVE (unsigned char)~_BV(6) |
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#define | FUSE_WDTON (unsigned char)~_BV(7) |
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#define | LFUSE_DEFAULT (FUSE_SUT0 & FUSE_BOOTSZ0 & FUSE_BOOTSZ1) |
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#define | FUSE_JTAGEN (unsigned char)~_BV(0) |
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#define | FUSE_OCDEN (unsigned char)~_BV(1) |
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#define | HFUSE_DEFAULT (FUSE_JTAGEN) |
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#define | __LOCK_BITS_EXIST |
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#define | __BOOT_LOCK_BITS_0_EXIST |
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#define | __BOOT_LOCK_BITS_1_EXIST |
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#define | SIGNATURE_0 0x1E |
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#define | SIGNATURE_1 0x95 |
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#define | SIGNATURE_2 0x07 |
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