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#define | UBRR1 _SFR_IO8(0x00) |
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#define | UCSR1B _SFR_IO8(0x01) |
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#define | UCSR1A _SFR_IO8(0x02) |
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#define | UDR1 _SFR_IO8(0x03) |
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#define | PINE _SFR_IO8(0x05) |
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#define | DDRE _SFR_IO8(0x06) |
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#define | PORTE _SFR_IO8(0x07) |
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#define | OCDR _SFR_IO8(0x08) |
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#define | UBRR0 _SFR_IO8(0x09) |
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#define | UCSR0B _SFR_IO8(0x0A) |
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#define | UCSR0A _SFR_IO8(0x0B) |
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#define | UDR0 _SFR_IO8(0x0C) |
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#define | PIND _SFR_IO8(0x10) |
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#define | DDRD _SFR_IO8(0x11) |
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#define | PORTD _SFR_IO8(0x12) |
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#define | FISCR _SFR_IO8(0x13) |
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#define | FISUA _SFR_IO8(0x14) |
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#define | FISUB _SFR_IO8(0x15) |
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#define | FISUC _SFR_IO8(0x16) |
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#define | FISUD _SFR_IO8(0x17) |
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#define | FPGAX _SFR_IO8(0x18) |
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#define | FPGAY _SFR_IO8(0x19) |
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#define | FPGAZ _SFR_IO8(0x1A) |
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#define | FPGAD _SFR_IO8(0x1B) |
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#define | TWBR _SFR_IO8(0x1C) |
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#define | TWSR _SFR_IO8(0x1D) |
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#define | TWAR _SFR_IO8(0x1E) |
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#define | TWDR _SFR_IO8(0x1F) |
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#define | UBRRH _SFR_IO8(0x20) |
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#define | UBRRHI UBRRH /* New name in datasheet (1138F-FPSLI-06/02) */ |
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#define | WDTCR _SFR_IO8(0x21) |
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#define | OCR2 _SFR_IO8(0x22) |
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#define | TCNT2 _SFR_IO8(0x23) |
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#define | ICR1 _SFR_IO16(0x24) |
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#define | ICR1L _SFR_IO8(0x24) |
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#define | ICR1H _SFR_IO8(0x25) |
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#define | ASSR _SFR_IO8(0x26) |
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#define | TCCR2 _SFR_IO8(0x27) |
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#define | OCR1B _SFR_IO16(0x28) |
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#define | OCR1BL _SFR_IO8(0x28) |
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#define | OCR1BH _SFR_IO8(0x29) |
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#define | OCR1A _SFR_IO16(0x2A) |
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#define | OCR1AL _SFR_IO8(0x2A) |
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#define | OCR1AH _SFR_IO8(0x2B) |
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#define | TCNT1 _SFR_IO16(0x2C) |
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#define | TCNT1L _SFR_IO8(0x2C) |
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#define | TCNT1H _SFR_IO8(0x2D) |
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#define | TCCR1B _SFR_IO8(0x2E) |
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#define | TCCR1A _SFR_IO8(0x2F) |
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#define | SFIOR _SFR_IO8(0x30) |
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#define | OCR0 _SFR_IO8(0x31) |
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#define | TCNT0 _SFR_IO8(0x32) |
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#define | TCCR0 _SFR_IO8(0x33) |
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#define | MCUR _SFR_IO8(0x35) |
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#define | TWCR _SFR_IO8(0x36) |
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#define | TIFR _SFR_IO8(0x38) |
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#define | TIMSK _SFR_IO8(0x39) |
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#define | SFTCR _SFR_IO8(0x3A) |
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#define | EIMF _SFR_IO8(0x3B) |
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#define | SIG_FPGA_INTERRUPT0 _VECTOR(1) /* FPGA_INT0 */ |
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#define | SIG_INTERRUPT0 _VECTOR(2) /* EXT_INT0 */ |
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#define | SIG_FPGA_INTERRUPT1 _VECTOR(3) /* FPGA_INT1 */ |
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#define | SIG_INTERRUPT1 _VECTOR(4) /* EXT_INT1 */ |
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#define | SIG_FPGA_INTERRUPT2 _VECTOR(5) /* FPGA_INT2 */ |
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#define | SIG_INTERRUPT2 _VECTOR(6) /* EXT_INT2 */ |
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#define | SIG_FPGA_INTERRUPT3 _VECTOR(7) /* FPGA_INT3 */ |
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#define | SIG_INTERRUPT3 _VECTOR(8) /* EXT_INT3 */ |
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#define | SIG_OUTPUT_COMPARE2 _VECTOR(9) /* TIM2_COMP */ |
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#define | SIG_OVERFLOW2 _VECTOR(10) /* TIM2_OVF */ |
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#define | SIG_INPUT_CAPTURE1 _VECTOR(11) /* TIM1_CAPT */ |
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#define | SIG_OUTPUT_COMPARE1A _VECTOR(12) /* TIM1_COMPA */ |
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#define | SIG_OUTPUT_COMPARE1B _VECTOR(13) /* TIM1_COMPB */ |
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#define | SIG_OVERFLOW1 _VECTOR(14) /* TIM1_OVF */ |
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#define | SIG_OUTPUT_COMPARE0 _VECTOR(15) /* TIM0_COMP */ |
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#define | SIG_OVERFLOW0 _VECTOR(16) /* TIM0_OVF */ |
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#define | SIG_FPGA_INTERRUPT4 _VECTOR(17) /* FPGA_INT4 */ |
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#define | SIG_FPGA_INTERRUPT5 _VECTOR(18) /* FPGA_INT5 */ |
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#define | SIG_FPGA_INTERRUPT6 _VECTOR(19) /* FPGA_INT6 */ |
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#define | SIG_FPGA_INTERRUPT7 _VECTOR(20) /* FPGA_INT7 */ |
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#define | SIG_UART0_RECV _VECTOR(21) /* UART0_RXC */ |
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#define | SIG_UART0_DATA _VECTOR(22) /* UART0_DRE */ |
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#define | SIG_UART0_TRANS _VECTOR(23) /* UART0_TXC */ |
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#define | SIG_FPGA_INTERRUPT8 _VECTOR(24) /* FPGA_INT8 */ |
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#define | SIG_FPGA_INTERRUPT9 _VECTOR(25) /* FPGA_INT9 */ |
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#define | SIG_FPGA_INTERRUPT10 _VECTOR(26) /* FPGA_INT10 */ |
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#define | SIG_FPGA_INTERRUPT11 _VECTOR(27) /* FPGA_INT11 */ |
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#define | SIG_UART1_RECV _VECTOR(28) /* UART1_RXC */ |
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#define | SIG_UART1_DATA _VECTOR(29) /* UART1_DRE */ |
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#define | SIG_UART1_TRANS _VECTOR(30) /* UART1_TXC */ |
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#define | SIG_FPGA_INTERRUPT12 _VECTOR(31) /* FPGA_INT12 */ |
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#define | SIG_FPGA_INTERRUPT13 _VECTOR(32) /* FPGA_INT13 */ |
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#define | SIG_FPGA_INTERRUPT14 _VECTOR(33) /* FPGA_INT14 */ |
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#define | SIG_FPGA_INTERRUPT15 _VECTOR(34) /* FPGA_INT15 */ |
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#define | SIG_2WIRE_SERIAL _VECTOR(35) /* TWS_INT */ |
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#define | _VECTORS_SIZE 144 |
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#define | AS2 3 |
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#define | TCN2UB 2 |
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#define | OCR2UB 1 |
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#define | TCR2UB 0 |
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#define | DDD7 7 |
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#define | DDD6 6 |
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#define | DDD5 5 |
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#define | DDD4 4 |
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#define | DDD3 3 |
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#define | DDD2 2 |
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#define | DDD1 1 |
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#define | DDD0 0 |
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#define | DDE7 7 |
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#define | DDE6 6 |
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#define | DDE5 5 |
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#define | DDE4 4 |
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#define | DDE3 3 |
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#define | DDE2 2 |
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#define | DDE1 1 |
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#define | DDE0 0 |
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#define | INTF3 7 |
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#define | INTF2 6 |
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#define | INTF1 5 |
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#define | INTF0 4 |
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#define | INT3 3 |
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#define | INT2 2 |
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#define | INT1 1 |
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#define | INT0 0 |
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#define | FIADR 7 |
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#define | XFIS1 1 |
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#define | XFIS0 0 |
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#define | FIF3 7 |
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#define | FIF2 6 |
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#define | FIF1 5 |
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#define | FIF0 4 |
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#define | FINT3 3 |
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#define | FINT2 2 |
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#define | FINT1 1 |
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#define | FINT0 0 |
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#define | FIF7 7 |
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#define | FIF6 6 |
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#define | FIF5 5 |
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#define | FIF4 4 |
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#define | FINT7 3 |
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#define | FINT6 2 |
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#define | FINT5 1 |
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#define | FINT4 0 |
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#define | FIF11 7 |
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#define | FIF10 6 |
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#define | FIF9 5 |
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#define | FIF8 4 |
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#define | FINT11 3 |
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#define | FINT10 2 |
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#define | FINT9 1 |
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#define | FINT8 0 |
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#define | FIF15 7 |
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#define | FIF14 6 |
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#define | FIF13 5 |
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#define | FIF12 4 |
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#define | FINT15 3 |
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#define | FINT14 2 |
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#define | FINT13 1 |
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#define | FINT12 0 |
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#define | JTRF 7 |
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#define | JTD 6 |
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#define | SE 5 |
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#define | SM1 4 |
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#define | SM0 3 |
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#define | PORF 2 |
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#define | WDRF 1 |
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#define | EXTRF 0 |
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#define | IDRD 7 |
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#define | PIND7 7 |
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#define | PIND6 6 |
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#define | PIND5 5 |
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#define | PIND4 4 |
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#define | PIND3 3 |
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#define | PIND2 2 |
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#define | PIND1 1 |
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#define | PIND0 0 |
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#define | PINE7 7 |
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#define | PINE6 6 |
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#define | PINE5 5 |
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#define | PINE4 4 |
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#define | PINE3 3 |
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#define | PINE2 2 |
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#define | PINE1 1 |
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#define | PINE0 0 |
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#define | PD7 7 |
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#define | PD6 6 |
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#define | PD5 5 |
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#define | PD4 4 |
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#define | PD3 3 |
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#define | PD2 2 |
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#define | PD1 1 |
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#define | PD0 0 |
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#define | PE7 7 |
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#define | PE6 6 |
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#define | PE5 5 |
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#define | PE4 4 |
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#define | PE3 3 |
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#define | PE2 2 |
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#define | PE1 1 |
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#define | PE0 0 |
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#define | PSR2 1 |
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#define | PSR10 0 |
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#define | FMXOR 3 |
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#define | WDTS 2 |
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#define | DBG 1 |
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#define | SRST 0 |
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#define | FOC0 7 |
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#define | PWM0 6 |
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#define | COM01 5 |
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#define | COM00 4 |
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#define | CTC0 3 |
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#define | CS02 2 |
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#define | CS01 1 |
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#define | CS00 0 |
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#define | COM1A1 7 |
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#define | COM1A0 6 |
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#define | COM1B1 5 |
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#define | COM1B0 4 |
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#define | FOC1A 3 |
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#define | FOC1B 2 |
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#define | PWM11 1 |
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#define | PWM10 0 |
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#define | ICNC1 7 |
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#define | ICES1 6 |
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#define | ICPE 5 |
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#define | CTC1 3 |
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#define | CS12 2 |
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#define | CS11 1 |
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#define | CS10 0 |
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#define | FOC2 7 |
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#define | PWM2 6 |
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#define | COM21 5 |
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#define | COM20 4 |
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#define | CTC2 3 |
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#define | CS22 2 |
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#define | CS21 1 |
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#define | CS20 0 |
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#define | TOV1 7 |
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#define | OCF1A 6 |
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#define | OCF1B 5 |
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#define | TOV2 4 |
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#define | ICF1 3 |
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#define | OCF2 2 |
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#define | TOV0 1 |
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#define | OCF0 0 |
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#define | TOIE1 7 |
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#define | OCIE1A 6 |
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#define | OCIE1B 5 |
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#define | TOIE2 4 |
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#define | TICIE1 3 |
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#define | OCIE2 2 |
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#define | TOIE0 1 |
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#define | OCIE0 0 |
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#define | TWGCE 0 |
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#define | TWINT 7 |
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#define | TWEA 6 |
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#define | TWSTA 5 |
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#define | TWSTO 4 |
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#define | TWWC 3 |
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#define | TWEN 2 |
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#define | TWIE 0 |
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#define | TWS7 7 |
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#define | TWS6 6 |
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#define | TWS5 5 |
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#define | TWS4 4 |
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#define | TWS3 3 |
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#define | RXC0 7 |
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#define | TXC0 6 |
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#define | UDRE0 5 |
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#define | FE0 4 |
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#define | OR0 3 |
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#define | U2X0 1 |
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#define | MPCM0 0 |
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#define | RXCIE0 7 |
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#define | TXCIE0 6 |
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#define | UDRIE0 5 |
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#define | RXEN0 4 |
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#define | TXEN0 3 |
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#define | CHR90 2 |
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#define | RXB80 1 |
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#define | TXB80 0 |
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#define | RXC1 7 |
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#define | TXC1 6 |
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#define | UDRE1 5 |
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#define | FE1 4 |
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#define | OR1 3 |
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#define | U2X1 1 |
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#define | MPCM1 0 |
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#define | RXCIE1 7 |
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#define | TXCIE1 6 |
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#define | UDRIE1 5 |
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#define | RXEN1 4 |
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#define | TXEN1 3 |
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#define | CHR91 2 |
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#define | RXB81 1 |
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#define | TXB81 0 |
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#define | WDTOE 4 |
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#define | WDE 3 |
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#define | WDP2 2 |
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#define | WDP1 1 |
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#define | WDP0 0 |
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#define | RAMEND 0x0FFF |
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#define | XRAMEND RAMEND |
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#define | E2END 0 |
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#define | FLASHEND 0x7FFF |
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