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#define | _AVR_IOXXX_H_ "iousbxx2.h" |
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#define | PINB _SFR_IO8(0X03) |
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#define | PINB7 7 |
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#define | PINB6 6 |
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#define | PINB5 5 |
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#define | PINB4 4 |
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#define | PINB3 3 |
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#define | PINB2 2 |
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#define | PINB1 1 |
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#define | PINB0 0 |
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#define | DDRB _SFR_IO8(0x04) |
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#define | DDB7 7 |
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#define | DDB6 6 |
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#define | DDB5 5 |
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#define | DDB4 4 |
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#define | DDB3 3 |
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#define | DDB2 2 |
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#define | DDB1 1 |
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#define | DDB0 0 |
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#define | PORTB _SFR_IO8(0x05) |
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#define | PB7 7 |
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#define | PB6 6 |
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#define | PB5 5 |
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#define | PB4 4 |
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#define | PB3 3 |
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#define | PB2 2 |
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#define | PB1 1 |
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#define | PB0 0 |
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#define | PINC _SFR_IO8(0x06) |
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#define | PINC7 7 |
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#define | PINC6 6 |
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#define | PINC5 5 |
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#define | PINC4 4 |
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#define | PINC2 2 |
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#define | PINC1 1 |
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#define | PINC0 0 |
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#define | DDRC _SFR_IO8(0x07) |
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#define | DDC7 7 |
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#define | DDC6 6 |
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#define | DDC5 5 |
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#define | DDC4 4 |
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#define | DDC2 2 |
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#define | DDC1 1 |
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#define | DDC0 0 |
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#define | PORTC _SFR_IO8(0x08) |
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#define | PC7 7 |
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#define | PC6 6 |
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#define | PC5 5 |
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#define | PC4 4 |
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#define | PC2 2 |
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#define | PC1 1 |
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#define | PC0 0 |
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#define | PIND _SFR_IO8(0x09) |
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#define | PIND7 7 |
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#define | PIND6 6 |
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#define | PIND5 5 |
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#define | PIND4 4 |
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#define | PIND3 3 |
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#define | PIND2 2 |
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#define | PIND1 1 |
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#define | PIND0 0 |
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#define | DDRD _SFR_IO8(0x0A) |
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#define | DDD7 7 |
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#define | DDD6 6 |
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#define | DDD5 5 |
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#define | DDD4 4 |
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#define | DDD3 3 |
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#define | DDD2 2 |
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#define | DDD1 1 |
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#define | DDD0 0 |
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#define | PORTD _SFR_IO8(0x0B) |
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#define | PD7 7 |
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#define | PD6 6 |
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#define | PD5 5 |
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#define | PD4 4 |
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#define | PD3 3 |
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#define | PD2 2 |
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#define | PD1 1 |
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#define | PD0 0 |
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#define | TIFR0 _SFR_IO8(0x15) |
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#define | OCF0B 2 |
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#define | OCF0A 1 |
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#define | TOV0 0 |
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#define | TIFR1 _SFR_IO8(0x16) |
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#define | ICF1 5 |
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#define | OCF1C 3 |
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#define | OCF1B 2 |
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#define | OCF1A 1 |
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#define | TOV1 0 |
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#define | PCIFR _SFR_IO8(0x1B) |
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#define | PCIF1 1 |
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#define | PCIF0 0 |
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#define | EIFR _SFR_IO8(0x1C) |
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#define | INTF7 7 |
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#define | INTF6 6 |
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#define | INTF5 5 |
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#define | INTF4 4 |
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#define | INTF3 3 |
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#define | INTF2 2 |
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#define | INTF1 1 |
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#define | INTF0 0 |
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#define | EIMSK _SFR_IO8(0x1D) |
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#define | INT7 7 |
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#define | INT6 6 |
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#define | INT5 5 |
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#define | INT4 4 |
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#define | INT3 3 |
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#define | INT2 2 |
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#define | INT1 1 |
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#define | INT0 0 |
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#define | GPIOR0 _SFR_IO8(0x1E) |
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#define | EECR _SFR_IO8(0x1F) |
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#define | EEPM1 5 |
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#define | EEPM0 4 |
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#define | EERIE 3 |
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#define | EEMPE 2 |
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#define | EEPE 1 |
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#define | EERE 0 |
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#define | EEDR _SFR_IO8(0x20) |
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#define | EEAR _SFR_IO16(0x21) |
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#define | EEARL _SFR_IO8(0x21) |
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#define | EEARH _SFR_IO8(0x22) |
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#define | __EEPROM_REG_LOCATIONS__ 1F2021 |
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#define | GTCCR _SFR_IO8(0x23) |
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#define | TSM 7 |
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#define | PSRASY 1 |
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#define | PSRSYNC 0 |
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#define | TCCR0A _SFR_IO8(0x24) |
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#define | COM0A1 7 |
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#define | COM0A0 6 |
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#define | COM0B1 5 |
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#define | COM0B0 4 |
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#define | WGM01 1 |
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#define | WGM00 0 |
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#define | TCCR0B _SFR_IO8(0x25) |
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#define | FOC0A 7 |
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#define | FOC0B 6 |
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#define | WGM02 3 |
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#define | CS02 2 |
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#define | CS01 1 |
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#define | CS00 0 |
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#define | TCNT0 _SFR_IO8(0X26) |
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#define | OCR0A _SFR_IO8(0x27) |
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#define | OCR0B _SFR_IO8(0X28) |
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#define | PLLCSR _SFR_IO8(0x29) |
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#define | PLLP2 4 |
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#define | PLLP1 3 |
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#define | PLLP0 2 |
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#define | PLLE 1 |
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#define | PLOCK 0 |
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#define | GPIOR1 _SFR_IO8(0x2A) |
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#define | GPIOR2 _SFR_IO8(0x2B) |
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#define | SPCR _SFR_IO8(0x2C) |
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#define | SPIE 7 |
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#define | SPE 6 |
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#define | DORD 5 |
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#define | MSTR 4 |
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#define | CPOL 3 |
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#define | CPHA 2 |
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#define | SPR1 1 |
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#define | SPR0 0 |
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#define | SPSR _SFR_IO8(0x2D) |
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#define | SPIF 7 |
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#define | WCOL 6 |
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#define | SPI2X 0 |
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#define | SPDR _SFR_IO8(0x2E) |
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#define | ACSR _SFR_IO8(0x30) |
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#define | ACD 7 |
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#define | ACBG 6 |
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#define | ACO 5 |
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#define | ACI 4 |
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#define | ACIE 3 |
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#define | ACIC 2 |
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#define | ACIS1 1 |
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#define | ACIS0 0 |
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#define | DWDR _SFR_IO8(0x31) |
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#define | IDRD 7 |
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#define | SMCR _SFR_IO8(0x33) |
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#define | SM2 3 |
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#define | SM1 2 |
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#define | SM0 1 |
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#define | SE 0 |
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#define | MCUSR _SFR_IO8(0x34) |
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#define | USBRF 5 |
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#define | WDRF 3 |
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#define | BORF 2 |
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#define | EXTRF 1 |
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#define | PORF 0 |
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#define | MCUCR _SFR_IO8(0x35) |
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#define | IVSEL 1 |
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#define | IVCE 0 |
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#define | SPMCSR _SFR_IO8(0x37) |
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#define | SPMIE 7 |
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#define | RWWSB 6 |
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#define | SIGRD 5 |
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#define | RWWSRE 4 |
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#define | BLBSET 3 |
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#define | PGWRT 2 |
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#define | PGERS 1 |
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#define | SPMEN 0 |
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#define | WDTCSR _SFR_MEM8(0x60) |
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#define | WDIF 7 |
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#define | WDIE 6 |
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#define | WDP3 5 |
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#define | WDCE 4 |
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#define | WDE 3 |
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#define | WDP2 2 |
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#define | WDP1 1 |
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#define | WDP0 0 |
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#define | CLKPR _SFR_MEM8(0x61) |
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#define | CLKPCE 7 |
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#define | CLKPS3 3 |
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#define | CLKPS2 2 |
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#define | CLKPS1 1 |
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#define | CLKPS0 0 |
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#define | WDTCKD _SFR_MEM8(0x62) |
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#define | WDEWIF 3 |
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#define | WDEWIE 2 |
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#define | WCLKD1 1 |
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#define | WCLKD0 0 |
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#define | REGCR _SFR_MEM8(0x63) |
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#define | REGDIS 0 |
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#define | PRR0 _SFR_MEM8(0x64) |
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#define | PRTIM0 5 |
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#define | PRTIM1 3 |
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#define | PRSPI 2 |
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#define | PRR1 _SFR_MEM8(0x65) |
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#define | PRUSB 7 |
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#define | PRUSART1 0 |
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#define | OSCCAL _SFR_MEM8(0x66) |
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#define | PCICR _SFR_MEM8(0x68) |
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#define | PCIE1 1 |
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#define | PCIE0 0 |
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#define | EICRA _SFR_MEM8(0x69) |
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#define | ISC31 7 |
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#define | ISC30 6 |
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#define | ISC21 5 |
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#define | ISC20 4 |
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#define | ISC11 3 |
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#define | ISC10 2 |
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#define | ISC01 1 |
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#define | ISC00 0 |
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#define | EICRB _SFR_MEM8(0x6A) |
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#define | ISC71 7 |
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#define | ISC70 6 |
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#define | ISC61 5 |
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#define | ISC60 4 |
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#define | ISC51 3 |
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#define | ISC50 2 |
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#define | ISC41 1 |
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#define | ISC40 0 |
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#define | PCMSK0 _SFR_MEM8(0x6B) |
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#define | PCINT7 7 |
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#define | PCINT6 6 |
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#define | PCINT5 5 |
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#define | PCINT4 4 |
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#define | PCINT3 3 |
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#define | PCINT2 2 |
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#define | PCINT1 1 |
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#define | PCINT0 0 |
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#define | PCMSK1 _SFR_MEM8(0x6C) |
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#define | PCINT12 4 |
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#define | PCINT11 3 |
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#define | PCINT10 2 |
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#define | PCINT9 1 |
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#define | PCINT8 0 |
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#define | TIMSK0 _SFR_MEM8(0x6E) |
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#define | OCIE0B 2 |
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#define | OCIE0A 1 |
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#define | TOIE0 0 |
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#define | TIMSK1 _SFR_MEM8(0x6F) |
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#define | ICIE1 5 |
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#define | OCIE1C 3 |
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#define | OCIE1B 2 |
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#define | OCIE1A 1 |
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#define | TOIE1 0 |
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#define | TCCR1A _SFR_MEM8(0x80) |
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#define | COM1A1 7 |
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#define | COM1A0 6 |
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#define | COM1B1 5 |
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#define | COM1B0 4 |
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#define | COM1C1 3 |
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#define | COM1C0 2 |
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#define | WGM11 1 |
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#define | WGM10 0 |
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#define | TCCR1B _SFR_MEM8(0x81) |
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#define | ICNC1 7 |
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#define | ICES1 6 |
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#define | WGM13 4 |
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#define | WGM12 3 |
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#define | CS12 2 |
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#define | CS11 1 |
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#define | CS10 0 |
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#define | TCCR1C _SFR_MEM8(0x82) |
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#define | FOC1A 7 |
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#define | FOC1B 6 |
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#define | FOC1C 5 |
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#define | TCNT1 _SFR_MEM16(0x84) |
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#define | TCNT1L _SFR_MEM8(0x84) |
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#define | TCNT1H _SFR_MEM8(0x85) |
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#define | ICR1 _SFR_MEM16(0x86) |
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#define | ICR1L _SFR_MEM8(0x86) |
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#define | ICR1H _SFR_MEM8(0x87) |
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#define | OCR1A _SFR_MEM16(0x88) |
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#define | OCR1AL _SFR_MEM8(0x88) |
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#define | OCR1AH _SFR_MEM8(0x89) |
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#define | OCR1B _SFR_MEM16(0x8A) |
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#define | OCR1BL _SFR_MEM8(0x8A) |
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#define | OCR1BH _SFR_MEM8(0x8B) |
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#define | OCR1C _SFR_MEM16(0x8C) |
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#define | OCR1CL _SFR_MEM8(0x8C) |
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#define | OCR1CH _SFR_MEM8(0x8D) |
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#define | UCSR1A _SFR_MEM8(0xC8) |
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#define | RXC1 7 |
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#define | TXC1 6 |
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#define | UDRE1 5 |
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#define | FE1 4 |
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#define | DOR1 3 |
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#define | UPE1 2 |
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#define | U2X1 1 |
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#define | MPCM1 0 |
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#define | UCSR1B _SFR_MEM8(0XC9) |
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#define | RXCIE1 7 |
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#define | TXCIE1 6 |
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#define | UDRIE1 5 |
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#define | RXEN1 4 |
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#define | TXEN1 3 |
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#define | UCSZ12 2 |
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#define | RXB81 1 |
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#define | TXB81 0 |
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#define | UCSR1C _SFR_MEM8(0xCA) |
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#define | UMSEL11 7 |
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#define | UMSEL10 6 |
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#define | UPM11 5 |
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#define | UPM10 4 |
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#define | USBS1 3 |
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#define | UCSZ11 2 |
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#define | UCSZ10 1 |
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#define | UCPOL1 0 |
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#define | UCSR1D _SFR_MEM8(0xCB) |
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#define | CTSEN 1 |
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#define | RTSEN 0 |
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#define | UBRR1 _SFR_MEM16(0xCC) |
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#define | UBRR1L _SFR_MEM8(0xCC) |
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#define | UBRR1H _SFR_MEM8(0xCD) |
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#define | UDR1 _SFR_MEM8(0XCE) |
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#define | CKSEL0 _SFR_MEM8(0XD0) |
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#define | RCSUT1 7 |
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#define | RCSUT0 6 |
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#define | EXSUT1 5 |
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#define | EXSUT0 4 |
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#define | RCE 3 |
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#define | EXTE 2 |
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#define | CLKS 0 |
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#define | CKSEL1 _SFR_MEM8(0XD1) |
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#define | RCCKSEL3 7 |
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#define | RCCKSEL2 6 |
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#define | RCCKSEL1 5 |
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#define | RCCKSEL0 4 |
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#define | EXCKSEL3 3 |
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#define | EXCKSEL2 2 |
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#define | EXCKSEL1 1 |
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#define | EXCKSEL0 0 |
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#define | CKSTA _SFR_MEM8(0XD2) |
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#define | RCON 1 |
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#define | EXTON 0 |
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#define | USBCON _SFR_MEM8(0XD8) |
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#define | USBE 7 |
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#define | FRZCLK 5 |
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#define | UDPADD _SFR_MEM16(0xDB) |
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#define | UDPADDL _SFR_MEM8(0xDB) |
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#define | UDPADDH _SFR_MEM8(0xDC) |
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#define | DPACC 7 |
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#define | UDCON _SFR_MEM8(0XE0) |
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#define | RSTCPU 2 |
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#define | RMWKUP 1 |
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#define | DETACH 0 |
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#define | UDINT _SFR_MEM8(0XE1) |
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#define | UPRSMI 6 |
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#define | EORSMI 5 |
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#define | WAKEUPI 4 |
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#define | EORSTI 3 |
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#define | SOFI 2 |
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#define | SUSPI 0 |
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#define | UDIEN _SFR_MEM8(0XE2) |
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#define | UPRSME 6 |
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#define | EORSME 5 |
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#define | WAKEUPE 4 |
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#define | EORSTE 3 |
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#define | SOFE 2 |
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#define | SUSPE 0 |
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#define | UDADDR _SFR_MEM8(0XE3) |
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#define | ADDEN 7 |
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#define | UDFNUM _SFR_MEM16(0xE4) |
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#define | UDFNUML _SFR_MEM8(0xE4) |
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#define | UDFNUMH _SFR_MEM8(0xE5) |
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#define | UDMFN _SFR_MEM8(0XE6) |
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#define | FNCERR 4 |
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#define | UEINTX _SFR_MEM8(0XE8) |
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#define | FIFOCON 7 |
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#define | NAKINI 6 |
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#define | RWAL 5 |
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#define | NAKOUTI 4 |
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#define | RXSTPI 3 |
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#define | RXOUTI 2 |
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#define | STALLEDI 1 |
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#define | TXINI 0 |
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#define | UENUM _SFR_MEM8(0XE9) |
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#define | EPNUM2 2 |
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#define | EPNUM1 1 |
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#define | EPNUM0 0 |
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#define | UERST _SFR_MEM8(0XEA) |
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#define | EPRST4 4 |
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#define | EPRST3 3 |
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#define | EPRST2 2 |
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#define | EPRST1 1 |
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#define | EPRST0 0 |
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#define | UECONX _SFR_MEM8(0XEB) |
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#define | STALLRQ 5 |
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#define | STALLRQC 4 |
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#define | RSTDT 3 |
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#define | EPEN 0 |
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#define | UECFG0X _SFR_MEM8(0XEC) |
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#define | EPTYPE1 7 |
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#define | EPTYPE0 6 |
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#define | EPDIR 0 |
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#define | UECFG1X _SFR_MEM8(0XED) |
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#define | EPSIZE2 6 |
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#define | EPSIZE1 5 |
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#define | EPSIZE0 4 |
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#define | EPBK1 3 |
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#define | EPBK0 2 |
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#define | ALLOC 1 |
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#define | UESTA0X _SFR_MEM8(0XEE) |
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#define | CFGOK 7 |
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#define | OVERFI 6 |
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#define | UNDERFI 5 |
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#define | DTSEQ1 3 |
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#define | DTSEQ0 2 |
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#define | NBUSYBK1 1 |
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#define | NBUSYBK0 0 |
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#define | UESTA1X _SFR_MEM8(0XEF) |
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#define | CTRLDIR 2 |
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#define | CURRBK1 1 |
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#define | CURRBK0 0 |
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#define | UEIENX _SFR_MEM8(0XF0) |
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#define | FLERRE 7 |
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#define | NAKINE 6 |
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#define | NAKOUTE 4 |
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#define | RXSTPE 3 |
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#define | RXOUTE 2 |
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#define | STALLEDE 1 |
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#define | TXINE 0 |
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#define | UEDATX _SFR_MEM8(0XF1) |
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#define | UEBCLX _SFR_MEM8(0xF2) |
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#define | UEINT _SFR_MEM8(0XF4) |
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#define | EPINT4 4 |
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#define | EPINT3 3 |
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#define | EPINT2 2 |
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#define | EPINT1 1 |
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#define | EPINT0 0 |
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#define | PS2CON _SFR_MEM8(0XFA) |
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#define | PS2EN 0 |
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#define | UPOE _SFR_MEM8(0XFB) |
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#define | UPWE1 7 |
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#define | UPWE0 6 |
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#define | UPDRV1 5 |
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#define | UPDRV0 4 |
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#define | SCKI 3 |
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#define | DATAI 2 |
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#define | DPI 1 |
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#define | DMI 0 |
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#define | INT0_vect _VECTOR(1) |
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#define | INT1_vect _VECTOR(2) |
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#define | INT2_vect _VECTOR(3) |
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#define | INT3_vect _VECTOR(4) |
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#define | INT4_vect _VECTOR(5) |
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#define | INT5_vect _VECTOR(6) |
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#define | INT6_vect _VECTOR(7) |
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#define | INT7_vect _VECTOR(8) |
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#define | PCINT0_vect _VECTOR(9) |
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#define | PCINT1_vect _VECTOR(10) |
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#define | USB_GEN_vect _VECTOR(11) |
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#define | USB_COM_vect _VECTOR(12) |
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#define | WDT_vect _VECTOR(13) |
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#define | TIMER1_CAPT_vect _VECTOR(14) |
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#define | TIMER1_COMPA_vect _VECTOR(15) |
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#define | TIMER1_COMPB_vect _VECTOR(16) |
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#define | TIMER1_COMPC_vect _VECTOR(17) |
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#define | TIMER1_OVF_vect _VECTOR(18) |
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#define | TIMER0_COMPA_vect _VECTOR(19) |
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#define | TIMER0_COMPB_vect _VECTOR(20) |
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#define | TIMER0_OVF_vect _VECTOR(21) |
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#define | SPI_STC_vect _VECTOR(22) |
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#define | USART1_RX_vect _VECTOR(23) |
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#define | USART1_UDRE_vect _VECTOR(24) |
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#define | USART1_TX_vect _VECTOR(25) |
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#define | ANALOG_COMP_vect _VECTOR(26) |
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#define | EE_READY_vect _VECTOR(27) |
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#define | SPM_READY_vect _VECTOR(28) |
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#define | _VECTORS_SIZE 116 |
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