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#define | ADCW _SFR_IO16(0x04) |
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#define | ADC _SFR_IO16(0x04) |
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#define | ADCL _SFR_IO8(0x04) |
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#define | ADCH _SFR_IO8(0x05) |
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#define | ADCSR _SFR_IO8(0x06) |
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#define | ADPS0 0 |
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#define | ADPS1 1 |
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#define | ADPS2 2 |
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#define | ADIE 3 |
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#define | ADIF 4 |
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#define | ADFR 5 |
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#define | ADSC 6 |
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#define | ADEN 7 |
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#define | ADMUX _SFR_IO8(0x07) |
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#define | MUX0 0 |
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#define | MUX1 1 |
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#define | MUX2 2 |
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#define | MUX3 3 |
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#define | MUX4 4 |
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#define | ADLAR 5 |
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#define | REFS0 6 |
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#define | REFS1 7 |
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#define | ACSR _SFR_IO8(0x08) |
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#define | ACIS0 0 |
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#define | ACIS1 1 |
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#define | ACME 2 |
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#define | ACIE 3 |
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#define | ACI 4 |
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#define | ACO 5 |
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#define | ACBG 6 |
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#define | ACD 7 |
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#define | USICR _SFR_IO8(0x0D) |
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#define | USITC 0 |
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#define | USICLK 1 |
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#define | USICS0 2 |
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#define | USICS1 3 |
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#define | USIWM0 4 |
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#define | USIWM1 5 |
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#define | USIOIE 6 |
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#define | USISIE 7 |
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#define | USISR _SFR_IO8(0x0E) |
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#define | USICNT0 0 |
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#define | USICNT1 1 |
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#define | USICNT2 2 |
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#define | USICNT3 3 |
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#define | USIDC 4 |
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#define | USIPF 5 |
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#define | USIOIF 6 |
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#define | USISIF 7 |
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#define | USIDR _SFR_IO8(0x0F) |
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#define | PINB _SFR_IO8(0x16) |
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#define | PINB0 0 |
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#define | PINB1 1 |
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#define | PINB2 2 |
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#define | PINB3 3 |
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#define | PINB4 4 |
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#define | PINB5 5 |
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#define | PINB6 6 |
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#define | PINB7 7 |
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#define | DDRB _SFR_IO8(0x17) |
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#define | DDB0 0 |
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#define | DDB1 1 |
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#define | DDB2 2 |
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#define | DDB3 3 |
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#define | DDB4 4 |
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#define | DDB5 5 |
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#define | DDB6 6 |
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#define | DDB7 7 |
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#define | PORTB _SFR_IO8(0x18) |
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#define | PB0 0 |
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#define | PB1 1 |
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#define | PB2 2 |
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#define | PB3 3 |
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#define | PB4 4 |
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#define | PB5 5 |
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#define | PB6 6 |
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#define | PB7 7 |
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#define | PINA _SFR_IO8(0x19) |
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#define | PINA0 0 |
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#define | PINA1 1 |
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#define | PINA2 2 |
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#define | PINA3 3 |
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#define | PINA4 4 |
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#define | PINA5 5 |
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#define | PINA6 6 |
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#define | PINA7 7 |
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#define | DDRA _SFR_IO8(0x1A) |
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#define | DDA0 0 |
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#define | DDA1 1 |
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#define | DDA2 2 |
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#define | DDA3 3 |
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#define | DDA4 4 |
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#define | DDA5 5 |
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#define | DDA6 6 |
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#define | DDA7 7 |
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#define | PORTA _SFR_IO8(0x1B) |
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#define | PA0 0 |
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#define | PA1 1 |
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#define | PA2 2 |
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#define | PA3 3 |
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#define | PA4 4 |
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#define | PA5 5 |
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#define | PA6 6 |
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#define | PA7 7 |
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#define | EECR _SFR_IO8(0x1C) |
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#define | EERE 0 |
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#define | EEWE 1 |
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#define | EEMWE 2 |
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#define | EERIE 3 |
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#define | EEDR _SFR_IO8(0x1D) |
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#define | EEAR _SFR_IO8(0x1E) |
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#define | EEARL _SFR_IO8(0x1E) |
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#define | WDTCR _SFR_IO8(0x21) |
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#define | WDP0 0 |
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#define | WDP1 1 |
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#define | WDP2 2 |
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#define | WDE 3 |
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#define | WDCE 4 |
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#define | PLLCSR _SFR_IO8(0x29) |
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#define | PLOCK 0 |
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#define | PLLE 1 |
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#define | PCKE 2 |
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#define | OCR1C _SFR_IO8(0x2B) |
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#define | OCR1B _SFR_IO8(0x2C) |
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#define | OCR1A _SFR_IO8(0x2D) |
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#define | TCNT1 _SFR_IO8(0x2E) |
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#define | TCCR1B _SFR_IO8(0x2F) |
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#define | CS10 0 |
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#define | CS11 1 |
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#define | CS12 2 |
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#define | CS13 3 |
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#define | PSR1 6 |
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#define | CTC1 7 |
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#define | TCCR1A _SFR_IO8(0x30) |
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#define | PWM1B 0 |
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#define | PWM1A 1 |
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#define | FOC1B 2 |
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#define | FOC1A 3 |
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#define | COM1B0 4 |
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#define | COM1B1 5 |
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#define | COM1A0 6 |
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#define | COM1A1 7 |
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#define | OSCCAL _SFR_IO8(0x31) |
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#define | TCNT0 _SFR_IO8(0x32) |
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#define | TCCR0 _SFR_IO8(0x33) |
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#define | CS00 0 |
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#define | CS01 1 |
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#define | CS02 2 |
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#define | PSR0 3 |
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#define | MCUSR _SFR_IO8(0x34) |
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#define | PORF 0 |
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#define | EXTRF 1 |
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#define | BORF 2 |
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#define | WDRF 3 |
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#define | MCUCR _SFR_IO8(0x35) |
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#define | ISC00 0 |
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#define | ISC01 1 |
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#define | SM0 3 |
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#define | SM1 4 |
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#define | SE 5 |
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#define | PUD 6 |
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#define | TIFR _SFR_IO8(0x38) |
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#define | TOV0 1 |
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#define | TOV1 2 |
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#define | OCF1B 5 |
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#define | OCF1A 6 |
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#define | TIMSK _SFR_IO8(0x39) |
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#define | TOIE0 1 |
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#define | TOIE1 2 |
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#define | OCIE1B 5 |
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#define | OCIE1A 6 |
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#define | GIFR _SFR_IO8(0x3A) |
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#define | PCIF 5 |
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#define | INTF0 6 |
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#define | GIMSK _SFR_IO8(0x3B) |
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#define | PCIE0 4 |
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#define | PCIE1 5 |
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#define | INT0 6 |
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#define | INT0_vect _VECTOR(1) |
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#define | SIG_INTERRUPT0 _VECTOR(1) |
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#define | IO_PINS_vect _VECTOR(2) |
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#define | SIG_PIN_CHANGE _VECTOR(2) |
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#define | TIMER1_CMPA_vect _VECTOR(3) |
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#define | SIG_OUTPUT_COMPARE1A _VECTOR(3) |
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#define | TIMER1_CMPB_vect _VECTOR(4) |
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#define | SIG_OUTPUT_COMPARE1B _VECTOR(4) |
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#define | TIMER1_OVF1_vect _VECTOR(5) |
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#define | SIG_OVERFLOW1 _VECTOR(5) |
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#define | TIMER0_OVF0_vect _VECTOR(6) |
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#define | SIG_OVERFLOW0 _VECTOR(6) |
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#define | USI_STRT_vect _VECTOR(7) |
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#define | SIG_USI_START _VECTOR(7) |
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#define | USI_OVF_vect _VECTOR(8) |
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#define | SIG_USI_OVERFLOW _VECTOR(8) |
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#define | EE_RDY_vect _VECTOR(9) |
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#define | SIG_EEPROM_READY _VECTOR(9) |
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#define | ANA_COMP_vect _VECTOR(10) |
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#define | SIG_ANA_COMP _VECTOR(10) |
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#define | SIG_COMPARATOR _VECTOR(10) |
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#define | ADC_vect _VECTOR(11) |
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#define | SIG_ADC _VECTOR(11) |
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#define | _VECTORS_SIZE 24 |
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#define | RAMEND 0xDF |
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#define | XRAMEND RAMEND |
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#define | E2END 0x7F |
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#define | E2PAGESIZE 4 |
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#define | FLASHEND 0x07FF |
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#define | FUSE_MEMORY_SIZE 2 |
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#define | FUSE_CKSEL0 (unsigned char)~_BV(0) |
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#define | FUSE_CKSEL1 (unsigned char)~_BV(1) |
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#define | FUSE_CKSEL2 (unsigned char)~_BV(2) |
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#define | FUSE_CKSEL3 (unsigned char)~_BV(3) |
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#define | FUSE_SUT0 (unsigned char)~_BV(4) |
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#define | FUSE_SUT1 (unsigned char)~_BV(5) |
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#define | FUSE_CKOPT (unsigned char)~_BV(6) |
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#define | FUSE_PLLCK (unsigned char)~_BV(7) |
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#define | LFUSE_DEFAULT (FUSE_CKSEL1 & FUSE_CKSEL2 & FUSE_CKSEL3 & FUSE_SUT0) |
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#define | FUSE_BODEN (unsigned char)~_BV(0) |
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#define | FUSE_BODLEVEL (unsigned char)~_BV(1) |
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#define | FUSE_EESAVE (unsigned char)~_BV(2) |
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#define | FUSE_SPIEN (unsigned char)~_BV(3) |
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#define | FUSE_RSTDISBL (unsigned char)~_BV(4) |
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#define | HFUSE_DEFAULT (FUSE_SPIEN) |
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#define | __LOCK_BITS_EXIST |
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#define | SIGNATURE_0 0x1E |
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#define | SIGNATURE_1 0x91 |
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#define | SIGNATURE_2 0x09 |
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