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#define | DIDR _SFR_IO8(0x01) |
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#define | AIN1D 1 |
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#define | AIN0D 0 |
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#define | UBRRH _SFR_IO8(0x02) |
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#define | UCSRC _SFR_IO8(0x03) |
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#define | UMSEL 6 |
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#define | UPM1 5 |
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#define | UPM0 4 |
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#define | USBS 3 |
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#define | UCSZ1 2 |
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#define | UCSZ0 1 |
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#define | UCPOL 0 |
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#define | ACSR _SFR_IO8(0x08) |
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#define | ACD 7 |
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#define | ACBG 6 |
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#define | ACO 5 |
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#define | ACI 4 |
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#define | ACIE 3 |
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#define | ACIC 2 |
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#define | ACIS1 1 |
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#define | ACIS0 0 |
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#define | UBRRL _SFR_IO8(0x09) |
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#define | UCSRB _SFR_IO8(0x0A) |
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#define | RXCIE 7 |
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#define | TXCIE 6 |
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#define | UDRIE 5 |
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#define | RXEN 4 |
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#define | TXEN 3 |
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#define | UCSZ2 2 |
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#define | RXB8 1 |
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#define | TXB8 0 |
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#define | UCSRA _SFR_IO8(0x0B) |
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#define | RXC 7 |
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#define | TXC 6 |
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#define | UDRE 5 |
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#define | FE 4 |
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#define | DOR 3 |
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#define | UPE 2 |
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#define | U2X 1 |
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#define | MPCM 0 |
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#define | UDR _SFR_IO8(0x0C) |
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#define | RXB _SFR_IO8(0x0C) |
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#define | TXB _SFR_IO8(0x0C) |
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#define | USICR _SFR_IO8(0x0D) |
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#define | USISIE 7 |
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#define | USIOIE 6 |
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#define | USIWM1 5 |
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#define | USIWM0 4 |
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#define | USICS1 3 |
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#define | USICS0 2 |
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#define | USICLK 1 |
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#define | USITC 0 |
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#define | USISR _SFR_IO8(0x0E) |
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#define | USISIF 7 |
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#define | USIOIF 6 |
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#define | USIPF 5 |
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#define | USIDC 4 |
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#define | USICNT3 3 |
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#define | USICNT2 2 |
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#define | USICNT1 1 |
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#define | USICNT0 0 |
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#define | USIDR _SFR_IO8(0x0F) |
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#define | PIND _SFR_IO8(0x10) |
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#define | PIND6 6 |
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#define | PIND5 5 |
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#define | PIND4 4 |
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#define | PIND3 3 |
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#define | PIND2 2 |
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#define | PIND1 1 |
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#define | PIND0 0 |
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#define | DDRD _SFR_IO8(0x11) |
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#define | DDD6 6 |
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#define | DDD5 5 |
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#define | DDD4 4 |
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#define | DDD3 3 |
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#define | DDD2 2 |
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#define | DDD1 1 |
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#define | DDD0 0 |
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#define | PORTD _SFR_IO8(0x12) |
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#define | PD6 6 |
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#define | PD5 5 |
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#define | PD4 4 |
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#define | PD3 3 |
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#define | PD2 2 |
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#define | PD1 1 |
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#define | PD0 0 |
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#define | GPIOR0 _SFR_IO8(0x13) |
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#define | GPIOR1 _SFR_IO8(0x14) |
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#define | GPIOR2 _SFR_IO8(0x15) |
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#define | PINB _SFR_IO8(0x16) |
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#define | PINB7 7 |
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#define | PINB6 6 |
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#define | PINB5 5 |
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#define | PINB4 4 |
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#define | PINB3 3 |
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#define | PINB2 2 |
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#define | PINB1 1 |
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#define | PINB0 0 |
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#define | DDRB _SFR_IO8(0x17) |
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#define | DDB7 7 |
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#define | DDB6 6 |
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#define | DDB5 5 |
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#define | DDB4 4 |
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#define | DDB3 3 |
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#define | DDB2 2 |
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#define | DDB1 1 |
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#define | DDB0 0 |
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#define | PORTB _SFR_IO8(0x18) |
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#define | PB7 7 |
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#define | PB6 6 |
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#define | PB5 5 |
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#define | PB4 4 |
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#define | PB3 3 |
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#define | PB2 2 |
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#define | PB1 1 |
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#define | PB0 0 |
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#define | PINA _SFR_IO8(0x19) |
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#define | PINA2 2 |
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#define | PINA1 1 |
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#define | PINA0 0 |
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#define | DDRA _SFR_IO8(0x1A) |
| |
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#define | DDRA2 2 |
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#define | DDRA1 1 |
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#define | DDRA0 0 |
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#define | PORTA _SFR_IO8(0x1B) |
| |
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#define | PA2 2 |
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#define | PA1 1 |
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#define | PA0 0 |
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#define | EECR _SFR_IO8(0x1C) |
| |
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#define | EEPM1 5 |
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#define | EEPM0 4 |
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#define | EERIE 3 |
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#define | EEMPE 2 |
| |
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#define | EEPE 1 |
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#define | EERE 0 |
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#define | EEDR _SFR_IO8(0x1D) |
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#define | EEAR _SFR_IO8(0x1E) |
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#define | EEARL _SFR_IO8(0x1E) |
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#define | EEAR6 6 |
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#define | EEAR5 5 |
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#define | EEAR4 4 |
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#define | EEAR3 3 |
| |
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#define | EEAR2 2 |
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#define | EEAR1 1 |
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#define | EEAR0 0 |
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#define | PCMSK _SFR_IO8(0x20) |
| |
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#define | PCINT7 7 |
| |
|
#define | PCINT6 6 |
| |
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#define | PCINT5 5 |
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#define | PCINT4 4 |
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#define | PCINT3 3 |
| |
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#define | PCINT2 2 |
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#define | PCINT1 1 |
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#define | PCINT0 0 |
| |
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#define | WDTCSR _SFR_IO8(0x21) |
| |
|
#define | WDIF 7 |
| |
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#define | WDIE 6 |
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#define | WDP3 5 |
| |
|
#define | WDCE 4 |
| |
|
#define | WDE 3 |
| |
|
#define | WDP2 2 |
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|
#define | WDP1 1 |
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#define | WDP0 0 |
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#define | TCCR1C _SFR_IO8(0x22) |
| |
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#define | FOC1A 7 |
| |
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#define | FOC1B 6 |
| |
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#define | GTCCR _SFR_IO8(0x23) |
| |
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#define | PSR10 0 |
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#define | ICR1 _SFR_IO16(0x24) |
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#define | ICR1L _SFR_IO8(0x24) |
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#define | ICR1H _SFR_IO8(0x25) |
| |
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#define | CLKPR _SFR_IO8(0x26) |
| |
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#define | CLKPCE 7 |
| |
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#define | CLKPS3 3 |
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#define | CLKPS2 2 |
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#define | CLKPS1 1 |
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#define | CLKPS0 0 |
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#define | OCR1B _SFR_IO16(0x28) |
| |
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#define | OCR1BL _SFR_IO8(0x28) |
| |
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#define | OCR1BH _SFR_IO8(0x29) |
| |
|
#define | OCR1 _SFR_IO16(0x2A) |
| |
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#define | OCR1L _SFR_IO8(0x2A) |
| |
|
#define | OCR1H _SFR_IO8(0x2B) |
| |
|
#define | OCR1A _SFR_IO16(0x2A) |
| |
|
#define | OCR1AL _SFR_IO8(0x2A) |
| |
|
#define | OCR1AH _SFR_IO8(0x2B) |
| |
|
#define | TCNT1 _SFR_IO16(0x2C) |
| |
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#define | TCNT1L _SFR_IO8(0x2C) |
| |
|
#define | TCNT1H _SFR_IO8(0x2D) |
| |
|
#define | TCCR1B _SFR_IO8(0x2E) |
| |
|
#define | ICNC1 7 |
| |
|
#define | ICES1 6 |
| |
|
#define | WGM13 4 |
| |
|
#define | WGM12 3 /* Was CTC1 in AT90S2313 */ |
| |
|
#define | CS12 2 |
| |
|
#define | CS11 1 |
| |
|
#define | CS10 0 |
| |
|
#define | TCCR1A _SFR_IO8(0x2F) |
| |
|
#define | COM1A1 7 |
| |
|
#define | COM1A0 6 |
| |
|
#define | COM1B1 5 |
| |
|
#define | COM1B0 4 |
| |
|
#define | WGM11 1 /* Was PWM11 in AT90S2313 */ |
| |
|
#define | WGM10 0 /* Was PWM10 in AT90S2313 */ |
| |
|
#define | TCCR0A _SFR_IO8(0x30) |
| |
|
#define | COM0A1 7 |
| |
|
#define | COM0A0 6 |
| |
|
#define | COM0B1 5 |
| |
|
#define | COM0B0 4 |
| |
|
#define | WGM01 1 |
| |
|
#define | WGM00 0 |
| |
|
#define | OSCCAL _SFR_IO8(0x31) |
| |
|
#define | CAL6 6 |
| |
|
#define | CAL5 5 |
| |
|
#define | CAL4 4 |
| |
|
#define | CAL3 3 |
| |
|
#define | CAL2 2 |
| |
|
#define | CAL1 1 |
| |
|
#define | CAL0 0 |
| |
|
#define | TCNT0 _SFR_IO8(0x32) |
| |
|
#define | TCCR0B _SFR_IO8(0x33) |
| |
|
#define | FOC0A 7 |
| |
|
#define | FOC0B 6 |
| |
|
#define | WGM02 3 |
| |
|
#define | CS02 2 |
| |
|
#define | CS01 1 |
| |
|
#define | CS00 0 |
| |
|
#define | MCUSR _SFR_IO8(0x34) |
| |
|
#define | WDRF 3 |
| |
|
#define | BORF 2 |
| |
|
#define | EXTRF 1 |
| |
|
#define | PORF 0 |
| |
|
#define | MCUCR _SFR_IO8(0x35) |
| |
|
#define | PUD 7 |
| |
|
#define | SM1 6 |
| |
|
#define | SE 5 |
| |
| #define | SM0 |
| |
|
#define | ISC11 3 |
| |
|
#define | ISC10 2 |
| |
|
#define | ISC01 1 |
| |
|
#define | ISC00 0 |
| |
|
#define | OCR0A _SFR_IO8(0x36) |
| |
|
#define | SPMCSR _SFR_IO8(0x37) |
| |
|
#define | CTPB 4 |
| |
|
#define | RFLB 3 |
| |
|
#define | PGWRT 2 |
| |
|
#define | PGERS 1 |
| |
|
#define | SPMEN 0 /* The name is used in ATtiny2313.xml file. */ |
| |
|
#define | SELFPRGEN 0 /* The name is used in datasheet. */ |
| |
|
#define | SELFPRGE 0 /* The name is left for compatibility. */ |
| |
|
#define | TIFR _SFR_IO8(0x38) |
| |
|
#define | TOV1 7 |
| |
|
#define | OCF1A 6 |
| |
|
#define | OCF1B 5 |
| |
|
#define | ICF1 3 |
| |
|
#define | OCF0B 2 |
| |
|
#define | TOV0 1 |
| |
|
#define | OCF0A 0 |
| |
|
#define | TIMSK _SFR_IO8(0x39) |
| |
|
#define | TOIE1 7 |
| |
|
#define | OCIE1A 6 |
| |
|
#define | OCIE1B 5 |
| |
|
#define | ICIE1 3 |
| |
|
#define | OCIE0B 2 |
| |
|
#define | TOIE0 1 |
| |
|
#define | OCIE0A 0 |
| |
|
#define | EIFR _SFR_IO8(0x3A) |
| |
|
#define | INTF1 7 |
| |
|
#define | INTF0 6 |
| |
|
#define | PCIF 5 |
| |
|
#define | GIMSK _SFR_IO8(0x3B) |
| |
|
#define | INT1 7 |
| |
|
#define | INT0 6 |
| |
|
#define | PCIE 5 |
| |
|
#define | OCR0B _SFR_IO8(0x3C) |
| |
|
#define | INT0_vect _VECTOR(1) |
| |
|
#define | SIG_INTERRUPT0 _VECTOR(1) |
| |
|
#define | SIG_INT0 _VECTOR(1) |
| |
|
#define | INT1_vect _VECTOR(2) |
| |
|
#define | SIG_INTERRUPT1 _VECTOR(2) |
| |
|
#define | SIG_INT1 _VECTOR(2) |
| |
|
#define | TIMER1_CAPT_vect _VECTOR(3) |
| |
|
#define | SIG_INPUT_CAPTURE1 _VECTOR(3) |
| |
|
#define | SIG_TIMER1_CAPT _VECTOR(3) |
| |
|
#define | TIMER1_COMPA_vect _VECTOR(4) |
| |
|
#define | SIG_OUTPUT_COMPARE1A _VECTOR(4) |
| |
|
#define | SIG_TIMER1_COMPA _VECTOR(4) |
| |
|
#define | TIMER1_OVF_vect _VECTOR(5) |
| |
|
#define | SIG_OVERFLOW1 _VECTOR(5) |
| |
|
#define | SIG_TIMER1_OVF _VECTOR(5) |
| |
|
#define | TIMER0_OVF_vect _VECTOR(6) |
| |
|
#define | SIG_OVERFLOW0 _VECTOR(6) |
| |
|
#define | SIG_TIMER0_OVF _VECTOR(6) |
| |
|
#define | USART_RX_vect _VECTOR(7) |
| |
|
#define | SIG_USART0_RECV _VECTOR(7) |
| |
|
#define | SIG_USART0_RX _VECTOR(7) |
| |
|
#define | USART_UDRE_vect _VECTOR(8) |
| |
|
#define | SIG_USART0_DATA _VECTOR(8) |
| |
|
#define | SIG_USART0_UDRE _VECTOR(8) |
| |
|
#define | USART_TX_vect _VECTOR(9) |
| |
|
#define | SIG_USART0_TRANS _VECTOR(9) |
| |
|
#define | SIG_USART0_TX _VECTOR(9) |
| |
|
#define | ANA_COMP_vect _VECTOR(10) |
| |
|
#define | SIG_COMPARATOR _VECTOR(10) |
| |
|
#define | SIG_ANALOG_COMP _VECTOR(10) |
| |
|
#define | PCINT_vect _VECTOR(11) |
| |
|
#define | SIG_PIN_CHANGE _VECTOR(11) |
| |
|
#define | SIG_PCINT _VECTOR(11) |
| |
|
#define | TIMER1_COMPB_vect _VECTOR(12) |
| |
|
#define | SIG_OUTPUT_COMPARE1B _VECTOR(12) |
| |
|
#define | SIG_TIMER1_COMPB _VECTOR(12) |
| |
|
#define | TIMER0_COMPA_vect _VECTOR(13) |
| |
|
#define | SIG_OUTPUT_COMPARE0A _VECTOR(13) |
| |
|
#define | SIG_TIMER0_COMPA _VECTOR(13) |
| |
|
#define | TIMER0_COMPB_vect _VECTOR(14) |
| |
|
#define | SIG_OUTPUT_COMPARE0B _VECTOR(14) |
| |
|
#define | SIG_TIMER0_COMPB _VECTOR(14) |
| |
|
#define | USI_START_vect _VECTOR(15) |
| |
|
#define | SIG_USI_START _VECTOR(15) |
| |
|
#define | SIG_USI_START _VECTOR(15) |
| |
|
#define | USI_OVERFLOW_vect _VECTOR(16) |
| |
|
#define | SIG_USI_OVERFLOW _VECTOR(16) |
| |
|
#define | SIG_USI_OVERFLOW _VECTOR(16) |
| |
|
#define | EEPROM_READY_vect _VECTOR(17) |
| |
|
#define | SIG_EEPROM_READY _VECTOR(17) |
| |
|
#define | SIG_EE_READY _VECTOR(17) |
| |
|
#define | WDT_OVERFLOW_vect _VECTOR(18) |
| |
|
#define | SIG_WATCHDOG_TIMEOUT _VECTOR(18) |
| |
|
#define | SIG_WDT_OVERFLOW _VECTOR(18) |
| |
|
#define | _VECTORS_SIZE 38 |
| |
|
#define | SPM_PAGESIZE 32 |
| |
|
#define | RAMEND 0xDF |
| |
|
#define | XRAMEND RAMEND |
| |
|
#define | E2END 0x7F |
| |
|
#define | E2PAGESIZE 4 |
| |
|
#define | FLASHEND 0x07FF |
| |
|
#define | FUSE_MEMORY_SIZE 3 |
| |
|
#define | FUSE_CKSEL0 (unsigned char)~_BV(0) |
| |
|
#define | FUSE_CKSEL1 (unsigned char)~_BV(1) |
| |
|
#define | FUSE_CKSEL2 (unsigned char)~_BV(2) |
| |
|
#define | FUSE_CKSEL3 (unsigned char)~_BV(3) |
| |
|
#define | FUSE_SUT0 (unsigned char)~_BV(4) |
| |
|
#define | FUSE_SUT1 (unsigned char)~_BV(5) |
| |
|
#define | FUSE_CKOUT (unsigned char)~_BV(6) |
| |
|
#define | FUSE_CKDIV8 (unsigned char)~_BV(7) |
| |
|
#define | LFUSE_DEFAULT (FUSE_CKSEL0 & FUSE_CKSEL1 & FUSE_CKSEL3 & FUSE_SUT0 & FUSE_CKDIV8) |
| |
|
#define | FUSE_RSTDISBL (unsigned char)~_BV(0) |
| |
|
#define | FUSE_BODLEVEL0 (unsigned char)~_BV(1) |
| |
|
#define | FUSE_BODLEVEL1 (unsigned char)~_BV(2) |
| |
|
#define | FUSE_BODLEVEL2 (unsigned char)~_BV(3) |
| |
|
#define | FUSE_WDTON (unsigned char)~_BV(4) |
| |
|
#define | FUSE_SPIEN (unsigned char)~_BV(5) |
| |
|
#define | FUSE_EESAVE (unsigned char)~_BV(6) |
| |
|
#define | FUSE_DWEN (unsigned char)~_BV(7) |
| |
|
#define | HFUSE_DEFAULT (FUSE_SPIEN) |
| |
|
#define | FUSE_SELFPRGEN (unsigned char)~_BV(0) |
| |
|
#define | EFUSE_DEFAULT (0xFF) |
| |
|
#define | __LOCK_BITS_EXIST |
| |
|
#define | SIGNATURE_0 0x1E |
| |
|
#define | SIGNATURE_1 0x91 |
| |
|
#define | SIGNATURE_2 0x0A |
| |
