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#define | _AVR_IOXXX_H_ "iotn15.h" |
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#define | ADC _SFR_IO16 (0x04) |
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#define | ADCW _SFR_IO16(0x04) |
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#define | ADCL _SFR_IO8(0x04) |
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#define | ADCH _SFR_IO8(0x05) |
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#define | ADCSR _SFR_IO8(0x06) |
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#define | ADMUX _SFR_IO8(0x07) |
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#define | ACSR _SFR_IO8(0x08) |
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#define | PINB _SFR_IO8(0x16) |
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#define | DDRB _SFR_IO8(0x17) |
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#define | PORTB _SFR_IO8(0x18) |
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#define | EECR _SFR_IO8(0x1C) |
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#define | EEDR _SFR_IO8(0x1D) |
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#define | EEAR _SFR_IO8(0x1E) |
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#define | EEARL _SFR_IO8(0x1E) |
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#define | WDTCR _SFR_IO8(0x21) |
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#define | SFIOR _SFR_IO8(0x2C) |
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#define | OCR1B _SFR_IO8(0x2D) |
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#define | OCR1A _SFR_IO8(0x2E) |
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#define | TCNT1 _SFR_IO8(0x2F) |
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#define | TCCR1 _SFR_IO8(0x30) |
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#define | OSCCAL _SFR_IO8(0x31) |
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#define | TCNT0 _SFR_IO8(0x32) |
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#define | TCCR0 _SFR_IO8(0x33) |
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#define | MCUSR _SFR_IO8(0x34) |
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#define | MCUCR _SFR_IO8(0x35) |
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#define | TIFR _SFR_IO8(0x38) |
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#define | TIMSK _SFR_IO8(0x39) |
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#define | GIFR _SFR_IO8(0x3A) |
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#define | GIMSK _SFR_IO8(0x3B) |
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#define | INT0_vect _VECTOR(1) |
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#define | SIG_INTERRUPT0 _VECTOR(1) |
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#define | IO_PINS_vect _VECTOR(2) |
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#define | SIG_PIN _VECTOR(2) |
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#define | SIG_PIN_CHANGE _VECTOR(2) |
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#define | TIMER1_COMP_vect _VECTOR(3) |
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#define | SIG_OUTPUT_COMPARE1A _VECTOR(3) |
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#define | TIMER1_OVF_vect _VECTOR(4) |
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#define | SIG_OVERFLOW1 _VECTOR(4) |
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#define | TIMER0_OVF_vect _VECTOR(5) |
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#define | SIG_OVERFLOW0 _VECTOR(5) |
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#define | EE_RDY_vect _VECTOR(6) |
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#define | SIG_EEPROM_READY _VECTOR(6) |
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#define | ANA_COMP_vect _VECTOR(7) |
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#define | SIG_COMPARATOR _VECTOR(7) |
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#define | ADC_vect _VECTOR(8) |
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#define | SIG_ADC _VECTOR(8) |
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#define | _VECTORS_SIZE 18 |
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#define | INT0 6 |
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#define | PCIE 5 |
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#define | INTF0 6 |
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#define | PCIF 5 |
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#define | OCIE1 6 |
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#define | TOIE1 2 |
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#define | TOIE0 1 |
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#define | OCF1 6 |
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#define | TOV1 2 |
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#define | TOV0 1 |
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#define | PUD 6 |
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#define | SE 5 |
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#define | SM1 4 |
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#define | SM0 3 |
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#define | ISC01 1 |
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#define | ISC00 0 |
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#define | WDRF 3 |
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#define | BORF 2 |
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#define | EXTRF 1 |
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#define | PORF 0 |
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#define | CS02 2 |
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#define | CS01 1 |
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#define | CS00 0 |
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#define | CTC1 7 |
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#define | PWM1 6 |
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#define | COM1A1 5 |
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#define | COM1A0 4 |
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#define | CS13 3 |
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#define | CS12 2 |
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#define | CS11 1 |
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#define | CS10 0 |
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#define | FOC1A 2 |
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#define | PSR1 1 |
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#define | PSR0 0 |
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#define | WDTOE 4 |
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#define | WDE 3 |
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#define | WDP2 2 |
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#define | WDP1 1 |
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#define | WDP0 0 |
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#define | PB4 4 |
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#define | PB3 3 |
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#define | PB2 2 |
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#define | PB1 1 |
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#define | PB0 0 |
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#define | DDB4 4 |
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#define | DDB3 3 |
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#define | DDB2 2 |
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#define | DDB1 1 |
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#define | DDB0 0 |
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#define | PINB5 5 |
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#define | PINB4 4 |
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#define | PINB3 3 |
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#define | PINB2 2 |
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#define | PINB1 1 |
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#define | PINB0 0 |
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#define | ACD 7 |
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#define | GREF 6 |
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#define | ACO 5 |
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#define | ACI 4 |
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#define | ACIE 3 |
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#define | ACIS1 1 |
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#define | ACIS0 0 |
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#define | REFS1 7 |
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#define | REFS0 6 |
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#define | ADLAR 5 |
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#define | MUX2 2 |
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#define | MUX1 1 |
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#define | MUX0 0 |
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#define | ADEN 7 |
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#define | ADSC 6 |
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#define | ADFR 5 |
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#define | ADIF 4 |
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#define | ADIE 3 |
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#define | ADPS2 2 |
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#define | ADPS1 1 |
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#define | ADPS0 0 |
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#define | EERIE 3 |
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#define | EEMWE 2 |
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#define | EEWE 1 |
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#define | EERE 0 |
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#define | RAMEND 0x1F |
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#define | XRAMEND 0x0 |
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#define | E2END 0x3F |
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#define | E2PAGESIZE 2 |
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#define | FLASHEND 0x3FF |
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#define | FUSE_MEMORY_SIZE 1 |
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#define | FUSE_CKSEL0 (unsigned char)~_BV(0) |
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#define | FUSE_CKSEL1 (unsigned char)~_BV(1) |
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#define | FUSE_RSTDISBL (unsigned char)~_BV(4) |
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#define | FUSE_SPIEN (unsigned char)~_BV(5) |
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#define | FUSE_BODEN (unsigned char)~_BV(6) |
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#define | FUSE_BODLEVEL (unsigned char)~_BV(7) |
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#define | FUSE_DEFAULT (FUSE_CKSEL0 & FUSE_CKSEL1 & FUSE_SPIEN) |
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#define | __LOCK_BITS_EXIST |
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#define | SIGNATURE_0 0x1E |
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#define | SIGNATURE_1 0x90 |
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#define | SIGNATURE_2 0x06 |
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