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#define | _AVR_IOXXX_H_ "iom164.h" |
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#define | PINA _SFR_IO8(0X00) |
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#define | PINA7 7 |
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#define | PINA6 6 |
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#define | PINA5 5 |
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#define | PINA4 4 |
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#define | PINA3 3 |
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#define | PINA2 2 |
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#define | PINA1 1 |
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#define | PINA0 0 |
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#define | DDRA _SFR_IO8(0X01) |
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#define | DDA7 7 |
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#define | DDA6 6 |
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#define | DDA5 5 |
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#define | DDA4 4 |
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#define | DDA3 3 |
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#define | DDA2 2 |
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#define | DDA1 1 |
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#define | DDA0 0 |
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#define | PORTA _SFR_IO8(0X02) |
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#define | PA7 7 |
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#define | PA6 6 |
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#define | PA5 5 |
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#define | PA4 4 |
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#define | PA3 3 |
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#define | PA2 2 |
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#define | PA1 1 |
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#define | PA0 0 |
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#define | PINB _SFR_IO8(0X03) |
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#define | PINB7 7 |
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#define | PINB6 6 |
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#define | PINB5 5 |
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#define | PINB4 4 |
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#define | PINB3 3 |
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#define | PINB2 2 |
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#define | PINB1 1 |
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#define | PINB0 0 |
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#define | DDRB _SFR_IO8(0x04) |
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#define | DDB7 7 |
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#define | DDB6 6 |
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#define | DDB5 5 |
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#define | DDB4 4 |
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#define | DDB3 3 |
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#define | DDB2 2 |
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#define | DDB1 1 |
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#define | DDB0 0 |
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#define | PORTB _SFR_IO8(0x05) |
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#define | PB7 7 |
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#define | PB6 6 |
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#define | PB5 5 |
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#define | PB4 4 |
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#define | PB3 3 |
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#define | PB2 2 |
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#define | PB1 1 |
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#define | PB0 0 |
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#define | PINC _SFR_IO8(0x06) |
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#define | PINC7 7 |
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#define | PINC6 6 |
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#define | PINC5 5 |
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#define | PINC4 4 |
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#define | PINC3 3 |
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#define | PINC2 2 |
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#define | PINC1 1 |
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#define | PINC0 0 |
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#define | DDRC _SFR_IO8(0x07) |
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#define | DDC7 7 |
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#define | DDC6 6 |
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#define | DDC5 5 |
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#define | DDC4 4 |
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#define | DDC3 3 |
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#define | DDC2 2 |
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#define | DDC1 1 |
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#define | DDC0 0 |
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#define | PORTC _SFR_IO8(0x08) |
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#define | PC7 7 |
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#define | PC6 6 |
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#define | PC5 5 |
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#define | PC4 4 |
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#define | PC3 3 |
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#define | PC2 2 |
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#define | PC1 1 |
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#define | PC0 0 |
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#define | PIND _SFR_IO8(0x09) |
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#define | PIND7 7 |
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#define | PIND6 6 |
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#define | PIND5 5 |
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#define | PIND4 4 |
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#define | PIND3 3 |
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#define | PIND2 2 |
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#define | PIND1 1 |
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#define | PIND0 0 |
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#define | DDRD _SFR_IO8(0x0A) |
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#define | DDD7 7 |
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#define | DDD6 6 |
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#define | DDD5 5 |
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#define | DDD4 4 |
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#define | DDD3 3 |
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#define | DDD2 2 |
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#define | DDD1 1 |
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#define | DDD0 0 |
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#define | PORTD _SFR_IO8(0x0B) |
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#define | PD7 7 |
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#define | PD6 6 |
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#define | PD5 5 |
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#define | PD4 4 |
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#define | PD3 3 |
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#define | PD2 2 |
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#define | PD1 1 |
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#define | PD0 0 |
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#define | TIFR0 _SFR_IO8(0x15) |
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#define | OCF0B 2 |
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#define | OCF0A 1 |
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#define | TOV0 0 |
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#define | TIFR1 _SFR_IO8(0x16) |
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#define | ICF1 5 |
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#define | OCF1B 2 |
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#define | OCF1A 1 |
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#define | TOV1 0 |
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#define | TIFR2 _SFR_IO8(0x17) |
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#define | OCF2B 2 |
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#define | OCF2A 1 |
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#define | TOV2 0 |
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#define | PCIFR _SFR_IO8(0x1B) |
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#define | PCIF3 3 |
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#define | PCIF2 2 |
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#define | PCIF1 1 |
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#define | PCIF0 0 |
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#define | EIFR _SFR_IO8(0x1C) |
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#define | INTF2 2 |
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#define | INTF1 1 |
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#define | INTF0 0 |
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#define | EIMSK _SFR_IO8(0x1D) |
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#define | INT2 2 |
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#define | INT1 1 |
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#define | INT0 0 |
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#define | GPIOR0 _SFR_IO8(0x1E) |
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#define | EECR _SFR_IO8(0x1F) |
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#define | EEPM1 5 |
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#define | EEPM0 4 |
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#define | EERIE 3 |
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#define | EEMPE 2 |
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#define | EEPE 1 |
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#define | EERE 0 |
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#define | EEDR _SFR_IO8(0X20) |
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#define | EEAR _SFR_IO16(0x21) |
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#define | EEARL _SFR_IO8(0x21) |
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#define | EEARH _SFR_IO8(0X22) |
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#define | __EEPROM_REG_LOCATIONS__ 1F2021 |
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#define | GTCCR _SFR_IO8(0x23) |
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#define | TSM 7 |
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#define | PSRASY 1 |
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#define | PSRSYNC 0 |
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#define | TCCR0A _SFR_IO8(0x24) |
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#define | COM0A1 7 |
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#define | COM0A0 6 |
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#define | COM0B1 5 |
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#define | COM0B0 4 |
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#define | WGM01 1 |
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#define | WGM00 0 |
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#define | TCCR0B _SFR_IO8(0x25) |
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#define | FOC0A 7 |
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#define | FOC0B 6 |
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#define | WGM02 3 |
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#define | CS02 2 |
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#define | CS01 1 |
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#define | CS00 0 |
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#define | TCNT0 _SFR_IO8(0X26) |
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#define | OCR0A _SFR_IO8(0X27) |
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#define | OCR0B _SFR_IO8(0X28) |
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#define | GPIOR1 _SFR_IO8(0x2A) |
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#define | GPIOR2 _SFR_IO8(0x2B) |
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#define | SPCR _SFR_IO8(0x2C) |
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#define | SPIE 7 |
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#define | SPE 6 |
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#define | DORD 5 |
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#define | MSTR 4 |
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#define | CPOL 3 |
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#define | CPHA 2 |
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#define | SPR1 1 |
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#define | SPR0 0 |
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#define | SPSR _SFR_IO8(0x2D) |
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#define | SPIF 7 |
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#define | WCOL 6 |
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#define | SPI2X 0 |
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#define | SPDR _SFR_IO8(0x2E) |
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#define | ACSR _SFR_IO8(0x30) |
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#define | ACD 7 |
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#define | ACBG 6 |
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#define | ACO 5 |
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#define | ACI 4 |
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#define | ACIE 3 |
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#define | ACIC 2 |
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#define | ACIS1 1 |
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#define | ACIS0 0 |
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#define | MONDR _SFR_IO8(0x31) |
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#define | OCDR _SFR_IO8(0x31) |
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#define | IDRD 7 |
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#define | OCDR7 7 |
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#define | OCDR6 6 |
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#define | OCDR5 5 |
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#define | OCDR4 4 |
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#define | OCDR3 3 |
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#define | OCDR2 2 |
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#define | OCDR1 1 |
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#define | OCDR0 0 |
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#define | SMCR _SFR_IO8(0x33) |
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#define | SM2 3 |
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#define | SM1 2 |
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#define | SM0 1 |
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#define | SE 0 |
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#define | MCUSR _SFR_IO8(0x34) |
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#define | JTRF 4 |
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#define | WDRF 3 |
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#define | BORF 2 |
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#define | EXTRF 1 |
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#define | PORF 0 |
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#define | MCUCR _SFR_IO8(0X35) |
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#define | JTD 7 |
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#define | BODS 6 |
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#define | BODSE 5 |
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#define | PUD 4 |
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#define | IVSEL 1 |
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#define | IVCE 0 |
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#define | SPMCSR _SFR_IO8(0x37) |
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#define | SPMIE 7 |
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#define | RWWSB 6 |
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#define | SIGRD 5 |
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#define | RWWSRE 4 |
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#define | BLBSET 3 |
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#define | PGWRT 2 |
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#define | PGERS 1 |
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#define | SPMEN 0 |
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#define | WDTCSR _SFR_MEM8(0x60) |
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#define | WDIF 7 |
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#define | WDIE 6 |
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#define | WDP3 5 |
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#define | WDCE 4 |
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#define | WDE 3 |
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#define | WDP2 2 |
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#define | WDP1 1 |
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#define | WDP0 0 |
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#define | CLKPR _SFR_MEM8(0x61) |
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#define | CLKPCE 7 |
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#define | CLKPS3 3 |
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#define | CLKPS2 2 |
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#define | CLKPS1 1 |
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#define | CLKPS0 0 |
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| #define | PRR |
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#define | PRR0 _SFR_MEM8(0x64) /* AVR Studio 4.13, build 524. */ |
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#define | PRTWI 7 |
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#define | PRTIM2 6 |
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#define | PRTIM0 5 |
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#define | PRUSART1 4 |
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#define | PRTIM1 3 |
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#define | PRSPI 2 |
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#define | PRUSART0 1 |
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#define | PRADC 0 |
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#define | OSCCAL _SFR_MEM8(0x66) |
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#define | PCICR _SFR_MEM8(0x68) |
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#define | PCIE3 3 |
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#define | PCIE2 2 |
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#define | PCIE1 1 |
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#define | PCIE0 0 |
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#define | EICRA _SFR_MEM8(0x69) |
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#define | ISC21 5 |
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#define | ISC20 4 |
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#define | ISC11 3 |
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#define | ISC10 2 |
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#define | ISC01 1 |
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#define | ISC00 0 |
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#define | PCMSK0 _SFR_MEM8(0x6B) |
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#define | PCINT7 7 |
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#define | PCINT6 6 |
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#define | PCINT5 5 |
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#define | PCINT4 4 |
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#define | PCINT3 3 |
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#define | PCINT2 2 |
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#define | PCINT1 1 |
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#define | PCINT0 0 |
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#define | PCMSK1 _SFR_MEM8(0x6C) |
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#define | PCINT15 7 |
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#define | PCINT14 6 |
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#define | PCINT13 5 |
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#define | PCINT12 4 |
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#define | PCINT11 3 |
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#define | PCINT10 2 |
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#define | PCINT9 1 |
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#define | PCINT8 0 |
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#define | PCMSK2 _SFR_MEM8(0x6D) |
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#define | PCINT23 7 |
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#define | PCINT22 6 |
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#define | PCINT21 5 |
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#define | PCINT20 4 |
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#define | PCINT19 3 |
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#define | PCINT18 2 |
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#define | PCINT17 1 |
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#define | PCINT16 0 |
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#define | TIMSK0 _SFR_MEM8(0x6E) |
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#define | OCIE0B 2 |
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#define | OCIE0A 1 |
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#define | TOIE0 0 |
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#define | TIMSK1 _SFR_MEM8(0x6F) |
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#define | ICIE1 5 |
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#define | OCIE1B 2 |
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#define | OCIE1A 1 |
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#define | TOIE1 0 |
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#define | TIMSK2 _SFR_MEM8(0x70) |
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#define | OCIE2B 2 |
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#define | OCIE2A 1 |
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#define | TOIE2 0 |
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#define | PCMSK3 _SFR_MEM8(0x73) |
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#define | PCINT31 7 |
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#define | PCINT30 6 |
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#define | PCINT29 5 |
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#define | PCINT28 4 |
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#define | PCINT27 3 |
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#define | PCINT26 2 |
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#define | PCINT25 1 |
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#define | PCINT24 0 |
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#define | ADC _SFR_MEM16(0x78) |
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#define | ADCW _SFR_MEM16(0x78) |
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#define | ADCL _SFR_MEM8(0x78) |
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#define | ADCH _SFR_MEM8(0x79) |
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#define | ADCSRA _SFR_MEM8(0x7A) |
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#define | ADEN 7 |
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#define | ADSC 6 |
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#define | ADATE 5 |
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#define | ADIF 4 |
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#define | ADIE 3 |
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#define | ADPS2 2 |
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#define | ADPS1 1 |
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#define | ADPS0 0 |
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#define | ADCSRB _SFR_MEM8(0x7B) |
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#define | ACME 6 |
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#define | ADTS2 2 |
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#define | ADTS1 1 |
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#define | ADTS0 0 |
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#define | ADMUX _SFR_MEM8(0x7C) |
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#define | REFS1 7 |
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#define | REFS0 6 |
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#define | ADLAR 5 |
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#define | MUX4 4 |
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#define | MUX3 3 |
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#define | MUX2 2 |
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#define | MUX1 1 |
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#define | MUX0 0 |
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#define | DIDR0 _SFR_MEM8(0x7E) |
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#define | ADC7D 7 |
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#define | ADC6D 6 |
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#define | ADC5D 5 |
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#define | ADC4D 4 |
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#define | ADC3D 3 |
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#define | ADC2D 2 |
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#define | ADC1D 1 |
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#define | ADC0D 0 |
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#define | DIDR1 _SFR_MEM8(0x7F) |
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#define | AIN1D 1 |
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#define | AIN0D 0 |
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#define | TCCR1A _SFR_MEM8(0x80) |
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#define | COM1A1 7 |
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#define | COM1A0 6 |
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#define | COM1B1 5 |
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#define | COM1B0 4 |
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#define | WGM11 1 |
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#define | WGM10 0 |
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#define | TCCR1B _SFR_MEM8(0x81) |
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#define | ICNC1 7 |
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#define | ICES1 6 |
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#define | WGM13 4 |
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#define | WGM12 3 |
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#define | CS12 2 |
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#define | CS11 1 |
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#define | CS10 0 |
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#define | TCCR1C _SFR_MEM8(0x82) |
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#define | FOC1A 7 |
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#define | FOC1B 6 |
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#define | TCNT1 _SFR_MEM16(0x84) |
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#define | TCNT1L _SFR_MEM8(0x84) |
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#define | TCNT1H _SFR_MEM8(0x85) |
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#define | ICR1 _SFR_MEM16(0x86) |
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#define | ICR1L _SFR_MEM8(0x86) |
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#define | ICR1H _SFR_MEM8(0x87) |
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#define | OCR1A _SFR_MEM16(0x88) |
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#define | OCR1AL _SFR_MEM8(0x88) |
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#define | OCR1AH _SFR_MEM8(0x89) |
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#define | OCR1B _SFR_MEM16(0x8A) |
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#define | OCR1BL _SFR_MEM8(0x8A) |
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#define | OCR1BH _SFR_MEM8(0x8B) |
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#define | TCCR2A _SFR_MEM8(0xB0) |
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#define | COM2A1 7 |
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#define | COM2A0 6 |
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#define | COM2B1 5 |
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#define | COM2B0 4 |
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#define | WGM21 1 |
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#define | WGM20 0 |
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#define | TCCR2B _SFR_MEM8(0xB1) |
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#define | FOC2A 7 |
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#define | FOC2B 6 |
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#define | WGM22 3 |
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#define | CS22 2 |
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#define | CS21 1 |
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#define | CS20 0 |
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#define | TCNT2 _SFR_MEM8(0xB2) |
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#define | OCR2A _SFR_MEM8(0xB3) |
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#define | OCR2B _SFR_MEM8(0xB4) |
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#define | ASSR _SFR_MEM8(0xB6) |
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#define | EXCLK 6 |
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#define | AS2 5 |
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#define | TCN2UB 4 |
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#define | OCR2AUB 3 |
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#define | OCR2BUB 2 |
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#define | TCR2AUB 1 |
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#define | TCR2BUB 0 |
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#define | TWBR _SFR_MEM8(0xB8) |
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#define | TWSR _SFR_MEM8(0xB9) |
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#define | TWS7 7 |
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#define | TWS6 6 |
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#define | TWS5 5 |
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#define | TWS4 4 |
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#define | TWS3 3 |
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#define | TWPS1 1 |
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#define | TWPS0 0 |
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#define | TWAR _SFR_MEM8(0xBA) |
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#define | TWA6 7 |
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#define | TWA5 6 |
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#define | TWA4 5 |
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#define | TWA3 4 |
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#define | TWA2 3 |
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#define | TWA1 2 |
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#define | TWA0 1 |
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#define | TWGCE 0 |
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#define | TWDR _SFR_MEM8(0xBB) |
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#define | TWCR _SFR_MEM8(0xBC) |
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#define | TWINT 7 |
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#define | TWEA 6 |
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#define | TWSTA 5 |
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#define | TWSTO 4 |
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#define | TWWC 3 |
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#define | TWEN 2 |
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#define | TWIE 0 |
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#define | TWAMR _SFR_MEM8(0xBD) |
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#define | TWAM6 7 |
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#define | TWAM5 6 |
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#define | TWAM4 5 |
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#define | TWAM3 4 |
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#define | TWAM2 3 |
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#define | TWAM1 2 |
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#define | TWAM0 1 |
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#define | UCSR0A _SFR_MEM8(0xC0) |
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#define | RXC0 7 |
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#define | TXC0 6 |
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#define | UDRE0 5 |
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#define | FE0 4 |
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#define | DOR0 3 |
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#define | UPE0 2 |
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#define | U2X0 1 |
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#define | MPCM0 0 |
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#define | UCSR0B _SFR_MEM8(0XC1) |
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#define | RXCIE0 7 |
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#define | TXCIE0 6 |
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#define | UDRIE0 5 |
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#define | RXEN0 4 |
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#define | TXEN0 3 |
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#define | UCSZ02 2 |
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#define | RXB80 1 |
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#define | TXB80 0 |
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#define | UCSR0C _SFR_MEM8(0xC2) |
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#define | UMSEL01 7 |
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#define | UMSEL00 6 |
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#define | UPM01 5 |
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#define | UPM00 4 |
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#define | USBS0 3 |
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#define | UCSZ01 2 |
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#define | UCSZ00 1 |
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#define | UCPHA0 1 |
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#define | UCPOL0 0 |
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#define | UBRR0 _SFR_MEM16(0xC4) |
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#define | UBRR0L _SFR_MEM8(0xC4) |
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#define | UBRR0H _SFR_MEM8(0xC5) |
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#define | UDR0 _SFR_MEM8(0XC6) |
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#define | UCSR1A _SFR_MEM8(0xC8) |
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#define | RXC1 7 |
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#define | TXC1 6 |
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#define | UDRE1 5 |
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#define | FE1 4 |
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#define | DOR1 3 |
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#define | UPE1 2 |
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#define | U2X1 1 |
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#define | MPCM1 0 |
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#define | UCSR1B _SFR_MEM8(0XC9) |
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#define | RXCIE1 7 |
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#define | TXCIE1 6 |
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#define | UDRIE1 5 |
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#define | RXEN1 4 |
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#define | TXEN1 3 |
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#define | UCSZ12 2 |
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#define | RXB81 1 |
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#define | TXB81 0 |
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#define | UCSR1C _SFR_MEM8(0xCA) |
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#define | UMSEL11 7 |
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#define | UMSEL10 6 |
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#define | UPM11 5 |
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#define | UPM10 4 |
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#define | USBS1 3 |
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#define | UCSZ11 2 |
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#define | UCSZ10 1 |
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#define | UCPHA1 1 |
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#define | UCPOL1 0 |
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#define | UBRR1 _SFR_MEM16(0xCC) |
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#define | UBRR1L _SFR_MEM8(0xCC) |
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#define | UBRR1H _SFR_MEM8(0xCD) |
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#define | UDR1 _SFR_MEM8(0XCE) |
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#define | INT0_vect _VECTOR(1) |
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#define | SIG_INTERRUPT0 _VECTOR(1) |
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#define | INT1_vect _VECTOR(2) |
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#define | SIG_INTERRUPT1 _VECTOR(2) |
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#define | INT2_vect _VECTOR(3) |
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#define | SIG_INTERRUPT2 _VECTOR(3) |
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#define | PCINT0_vect _VECTOR(4) |
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#define | SIG_PIN_CHANGE0 _VECTOR(4) |
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#define | PCINT1_vect _VECTOR(5) |
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#define | SIG_PIN_CHANGE1 _VECTOR(5) |
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#define | PCINT2_vect _VECTOR(6) |
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#define | SIG_PIN_CHANGE2 _VECTOR(6) |
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#define | PCINT3_vect _VECTOR(7) |
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#define | SIG_PIN_CHANGE3 _VECTOR(7) |
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#define | WDT_vect _VECTOR(8) |
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#define | SIG_WATCHDOG_TIMEOUT _VECTOR(8) |
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#define | TIMER2_COMPA_vect _VECTOR(9) |
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#define | SIG_OUTPUT_COMPARE2A _VECTOR(9) |
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#define | TIMER2_COMPB_vect _VECTOR(10) |
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#define | SIG_OUTPUT_COMPARE2B _VECTOR(10) |
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#define | TIMER2_OVF_vect _VECTOR(11) |
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#define | SIG_OVERFLOW2 _VECTOR(11) |
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#define | TIMER1_CAPT_vect _VECTOR(12) |
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#define | SIG_INPUT_CAPTURE1 _VECTOR(12) |
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#define | TIMER1_COMPA_vect _VECTOR(13) |
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#define | SIG_OUTPUT_COMPARE1A _VECTOR(13) |
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#define | TIMER1_COMPB_vect _VECTOR(14) |
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#define | SIG_OUTPUT_COMPARE1B _VECTOR(14) |
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#define | TIMER1_OVF_vect _VECTOR(15) |
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#define | SIG_OVERFLOW1 _VECTOR(15) |
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#define | TIMER0_COMPA_vect _VECTOR(16) |
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#define | SIG_OUTPUT_COMPARE0A _VECTOR(16) |
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#define | TIMER0_COMPB_vect _VECTOR(17) |
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#define | SIG_OUTPUT_COMPARE0B _VECTOR(17) |
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#define | TIMER0_OVF_vect _VECTOR(18) |
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#define | SIG_OVERFLOW0 _VECTOR(18) |
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#define | SPI_STC_vect _VECTOR(19) |
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#define | SIG_SPI _VECTOR(19) |
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#define | USART0_RX_vect _VECTOR(20) |
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#define | SIG_USART_RECV _VECTOR(20) |
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#define | USART0_UDRE_vect _VECTOR(21) |
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#define | SIG_USART_DATA _VECTOR(21) |
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#define | USART0_TX_vect _VECTOR(22) |
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#define | SIG_USART_TRANS _VECTOR(22) |
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#define | ANALOG_COMP_vect _VECTOR(23) |
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#define | SIG_COMPARATOR _VECTOR(23) |
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#define | ADC_vect _VECTOR(24) |
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#define | SIG_ADC _VECTOR(24) |
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#define | EE_READY_vect _VECTOR(25) |
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#define | SIG_EEPROM_READY _VECTOR(25) |
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#define | TWI_vect _VECTOR(26) |
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#define | SIG_2WIRE_SERIAL _VECTOR(26) |
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#define | SPM_READY_vect _VECTOR(27) |
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#define | SIG_SPM_READY _VECTOR(27) |
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#define | USART1_RX_vect _VECTOR(28) |
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#define | SIG_USART1_RECV _VECTOR(28) |
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#define | USART1_UDRE_vect _VECTOR(29) |
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#define | SIG_USART1_DATA _VECTOR(29) |
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#define | USART1_TX_vect _VECTOR(30) |
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#define | SIG_USART1_TRANS _VECTOR(30) |
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#define | _VECTORS_SIZE 124 |
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