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#define | _AVR_AT90PWM81_H_ 1 |
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#define | ACSR _SFR_IO8(0x00) |
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#define | AC1O 1 |
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#define | AC2O 2 |
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#define | AC3O 3 |
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#define | AC1IF 5 |
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#define | AC2IF 6 |
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#define | AC3IF 7 |
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#define | TIMSK1 _SFR_IO8(0x01) |
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#define | TOIE1 0 |
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#define | ICIE1 5 |
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#define | TIFR1 _SFR_IO8(0x02) |
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#define | TOV1 0 |
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#define | ICF1 5 |
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#define | PINB _SFR_IO8(0x03) |
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#define | PINB0 0 |
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#define | PINB1 1 |
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#define | PINB2 2 |
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#define | PINB3 3 |
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#define | PINB4 4 |
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#define | PINB5 5 |
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#define | PINB6 6 |
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#define | PINB7 7 |
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#define | DDRB _SFR_IO8(0x04) |
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#define | DDB0 0 |
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#define | DDB1 1 |
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#define | DDB2 2 |
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#define | DDB3 3 |
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#define | DDB4 4 |
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#define | DDB5 5 |
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#define | DDB6 6 |
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#define | DDB7 7 |
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#define | PORTB _SFR_IO8(0x05) |
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#define | PORTB0 0 |
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#define | PORTB1 1 |
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#define | PORTB2 2 |
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#define | PORTB3 3 |
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#define | PORTB4 4 |
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#define | PORTB5 5 |
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#define | PORTB6 6 |
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#define | PORTB7 7 |
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#define | ADCSRA _SFR_IO8(0x06) |
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#define | ADPS0 0 |
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#define | ADPS1 1 |
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#define | ADPS2 2 |
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#define | ADIE 3 |
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#define | ADIF 4 |
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#define | ADATE 5 |
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#define | ADSC 6 |
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#define | ADEN 7 |
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#define | ADCSRB _SFR_IO8(0x07) |
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#define | ADTS0 0 |
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#define | ADTS1 1 |
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#define | ADTS2 2 |
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#define | ADTS3 3 |
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#define | ADSSEN 4 |
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#define | ADNCDIS 6 |
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#define | ADHSM 7 |
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#define | ADMUX _SFR_IO8(0x08) |
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#define | MUX0 0 |
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#define | MUX1 1 |
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#define | MUX2 2 |
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#define | MUX3 3 |
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#define | ADLAR 5 |
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#define | REFS0 6 |
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#define | REFS1 7 |
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#define | PIND _SFR_IO8(0x09) |
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#define | PIND0 0 |
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#define | PIND1 1 |
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#define | PIND2 2 |
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#define | PIND3 3 |
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#define | PIND4 4 |
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#define | PIND5 5 |
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#define | PIND6 6 |
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#define | PIND7 7 |
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#define | DDRD _SFR_IO8(0x0A) |
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#define | DDD0 0 |
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#define | DDD1 1 |
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#define | DDD2 2 |
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#define | DDD3 3 |
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#define | DDD4 4 |
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#define | DDD5 5 |
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#define | DDD6 6 |
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#define | DDD7 7 |
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#define | PORTD _SFR_IO8(0x0B) |
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#define | PORTD0 0 |
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#define | PORTD1 1 |
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#define | PORTD2 2 |
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#define | PORTD3 3 |
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#define | PORTD4 4 |
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#define | PORTD5 5 |
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#define | PORTD6 6 |
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#define | PORTD7 7 |
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#define | PINE _SFR_IO8(0x0C) |
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#define | PINE0 0 |
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#define | PINE1 1 |
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#define | PINE2 2 |
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#define | DDRE _SFR_IO8(0x0D) |
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#define | DDE0 0 |
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#define | DDE1 1 |
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#define | DDE2 2 |
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#define | PORTE _SFR_IO8(0x0E) |
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#define | PORTE0 0 |
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#define | PORTE1 1 |
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#define | PORTE2 2 |
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#define | PIM0 _SFR_IO8(0x0F) |
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#define | PEOPE0 0 |
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#define | PEOEPE0 1 |
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#define | PEVE0A 3 |
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#define | PEVE0B 4 |
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#define | PIFR0 _SFR_IO8(0x10) |
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#define | PEOP0 0 |
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#define | PRN00 1 |
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#define | PRN01 2 |
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#define | PEV0A 3 |
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#define | PEV0B 4 |
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#define | POAC0A 6 |
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#define | POAC0B 7 |
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#define | PCNF0 _SFR_IO8(0x11) |
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#define | PCLKSEL0 1 |
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#define | POP0 2 |
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#define | PMODE00 3 |
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#define | PMODE01 4 |
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#define | PLOCK0 5 |
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#define | PALOCK0 6 |
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#define | PFIFTY0 7 |
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#define | PCTL0 _SFR_IO8(0x12) |
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#define | PRUN0 0 |
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#define | PCCYC0 1 |
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#define | PBFM00 2 |
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#define | PAOC0A 3 |
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#define | PAOC0B 4 |
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#define | PBFM01 5 |
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#define | PPRE00 6 |
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#define | PPRE01 7 |
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#define | PIM2 _SFR_IO8(0x13) |
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#define | PEOPE2 0 |
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#define | PEOEPE2 1 |
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#define | PEVE2A 3 |
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#define | PEVE2B 4 |
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#define | PSEIE2 5 |
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#define | PIFR2 _SFR_IO8(0x14) |
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#define | PEOP2 0 |
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#define | PRN20 1 |
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#define | PRN21 2 |
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#define | PEV2A 3 |
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#define | PEV2B 4 |
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#define | PSEI2 5 |
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#define | POAC2A 6 |
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#define | POAC2B 7 |
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#define | PCNF2 _SFR_IO8(0x15) |
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#define | POME2 0 |
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#define | PCLKSEL2 1 |
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#define | POP2 2 |
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#define | PMODE20 3 |
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#define | PMODE21 4 |
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#define | PLOCK2 5 |
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#define | PALOCK2 6 |
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#define | PFIFTY2 7 |
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#define | PCTL2 _SFR_IO8(0x16) |
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#define | PRUN2 0 |
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#define | PCCYC2 1 |
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#define | PARUN2 2 |
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#define | PAOC2A 3 |
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#define | PAOC2B 4 |
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#define | PBFM2 5 |
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#define | PPRE20 6 |
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#define | PPRE21 7 |
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#define | SPCR _SFR_IO8(0x17) |
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#define | SPR0 0 |
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#define | SPR1 1 |
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#define | CPHA 2 |
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#define | CPOL 3 |
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#define | MSTR 4 |
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#define | DORD 5 |
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#define | SPE 6 |
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#define | SPIE 7 |
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#define | SPSR _SFR_IO8(0x18) |
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#define | SPI2X 0 |
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#define | WCOL 6 |
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#define | SPIF 7 |
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#define | GPIOR0 _SFR_IO8(0x19) |
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#define | GPIOR00 0 |
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#define | GPIOR01 1 |
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#define | GPIOR02 2 |
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#define | GPIOR03 3 |
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#define | GPIOR04 4 |
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#define | GPIOR05 5 |
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#define | GPIOR06 6 |
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#define | GPIOR07 7 |
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#define | GPIOR1 _SFR_IO8(0x1A) |
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#define | GPIOR10 0 |
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#define | GPIOR11 1 |
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#define | GPIOR12 2 |
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#define | GPIOR13 3 |
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#define | GPIOR14 4 |
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#define | GPIOR15 5 |
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#define | GPIOR16 6 |
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#define | GPIOR17 7 |
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#define | GPIOR2 _SFR_IO8(0x1B) |
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#define | GPIOR20 0 |
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#define | GPIOR21 1 |
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#define | GPIOR22 2 |
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#define | GPIOR23 3 |
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#define | GPIOR24 4 |
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#define | GPIOR25 5 |
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#define | GPIOR26 6 |
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#define | GPIOR27 7 |
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#define | EECR _SFR_IO8(0x1C) |
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#define | EERE 0 |
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#define | EEWE 1 |
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#define | EEMWE 2 |
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#define | EERIE 3 |
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#define | EEPM0 4 |
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#define | EEPM1 5 |
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#define | EEPAGE 6 |
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#define | NVMBSY 7 |
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#define | EEDR _SFR_IO8(0x1D) |
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#define | EEDR0 0 |
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#define | EEDR1 1 |
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#define | EEDR2 2 |
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#define | EEDR3 3 |
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#define | EEDR4 4 |
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#define | EEDR5 5 |
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#define | EEDR6 6 |
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#define | EEDR7 7 |
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#define | EEAR _SFR_IO16(0x1E) |
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#define | EEARL _SFR_IO8(0x1E) |
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#define | EEARL0 0 |
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#define | EEARL1 1 |
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#define | EEARL2 2 |
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#define | EEARL3 3 |
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#define | EEARL4 4 |
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#define | EEARL5 5 |
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#define | EEARL6 6 |
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#define | EEARL7 7 |
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#define | EEARH _SFR_IO8(0x1F) |
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#define | EEAR8 0 |
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#define | EIFR _SFR_IO8(0x20) |
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#define | INTF0 0 |
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#define | INTF1 1 |
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#define | INTF2 2 |
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#define | EIMSK _SFR_IO8(0x21) |
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#define | INT0 0 |
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#define | INT1 1 |
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#define | INT2 2 |
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#define | OCR0SB _SFR_IO16(0x22) |
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#define | OCR0SBL _SFR_IO8(0x22) |
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#define | OCR0SB_0 0 |
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#define | OCR0SB_1 1 |
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#define | OCR0SB_2 2 |
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#define | OCR0SB_3 3 |
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#define | OCR0SB_4 4 |
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#define | OCR0SB_5 5 |
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#define | OCR0SB_6 6 |
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#define | OCR0SB_7 7 |
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#define | OCR0SBH _SFR_IO8(0x23) |
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#define | OCR0SB_8 0 |
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#define | OCR0SB_9 1 |
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#define | OCR0SB_00 2 |
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#define | OCR0SB_01 3 |
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#define | OCR0RB _SFR_IO16(0x24) |
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#define | OCR0RBL _SFR_IO8(0x24) |
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#define | OCR0RB_0 0 |
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#define | OCR0RB_1 1 |
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#define | OCR0RB_2 2 |
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#define | OCR0RB_3 3 |
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#define | OCR0RB_4 4 |
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#define | OCR0RB_5 5 |
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#define | OCR0RB_6 6 |
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#define | OCR0RB_7 7 |
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#define | OCR0RBH _SFR_IO8(0x25) |
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#define | OCR0RB_8 0 |
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#define | OCR0RB_9 1 |
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#define | OCR0RB_00 2 |
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#define | OCR0RB_01 3 |
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#define | OCR0RB_02 4 |
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#define | OCR0RB_03 5 |
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#define | OCR0RB_04 6 |
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#define | OCR0RB_05 7 |
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#define | OCR2SB _SFR_IO16(0x26) |
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#define | OCR2SBL _SFR_IO8(0x26) |
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#define | OCR2SB_0 0 |
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#define | OCR2SB_1 1 |
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#define | OCR2SB_2 2 |
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#define | OCR2SB_3 3 |
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#define | OCR2SB_4 4 |
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#define | OCR2SB_5 5 |
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#define | OCR2SB_6 6 |
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#define | OCR2SB_7 7 |
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#define | OCR2SBH _SFR_IO8(0x27) |
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#define | OCR2SB_8 0 |
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#define | OCR2SB_9 1 |
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#define | OCR2SB_10 2 |
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#define | OCR2SB_11 3 |
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#define | OCR2RB _SFR_IO16(0x28) |
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#define | OCR2RBL _SFR_IO8(0x28) |
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#define | OCR2RB_0 0 |
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#define | OCR2RB_1 1 |
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#define | OCR2RB_2 2 |
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#define | OCR2RB_3 3 |
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#define | OCR2RB_4 4 |
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#define | OCR2RB_5 5 |
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#define | OCR2RB_6 6 |
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#define | OCR2RB_7 7 |
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#define | OCR2RBH _SFR_IO8(0x29) |
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#define | OCR2RB_8 0 |
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#define | OCR2RB_9 1 |
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#define | OCR2RB_10 2 |
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#define | OCR2RB_11 3 |
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#define | OCR2RB_12 4 |
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#define | OCR2RB_13 5 |
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#define | OCR2RB_14 6 |
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#define | OCR2RB_15 7 |
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#define | OCR0RA _SFR_IO16(0x2A) |
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#define | OCR0RAL _SFR_IO8(0x2A) |
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#define | OCR0RA_0 0 |
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#define | OCR0RA_1 1 |
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#define | OCR0RA_2 2 |
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#define | OCR0RA_3 3 |
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#define | OCR0RA_4 4 |
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#define | OCR0RA_5 5 |
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#define | OCR0RA_6 6 |
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#define | OCR0RA_7 7 |
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#define | OCR0RAH _SFR_IO8(0x2B) |
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#define | OCR0RA_8 0 |
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#define | OCR0RA_9 1 |
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#define | OCR0RA_00 2 |
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#define | OCR0RA_01 3 |
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#define | ADC _SFR_IO16(0x2C) |
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#define | ADCW _SFR_IO16(0x2C) |
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#define | ADCL _SFR_IO8(0x2C) |
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#define | ADCL0 0 |
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#define | ADCL1 1 |
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#define | ADCL2 2 |
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#define | ADCL3 3 |
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#define | ADCL4 4 |
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#define | ADCL5 5 |
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#define | ADCL6 6 |
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#define | ADCL7 7 |
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#define | ADCH _SFR_IO8(0x2D) |
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#define | ADCH0 0 |
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#define | ADCH1 1 |
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#define | ADCH2 2 |
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#define | ADCH3 3 |
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#define | ADCH4 4 |
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#define | ADCH5 5 |
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#define | ADCH6 6 |
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#define | ADCH7 7 |
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#define | OCR2RA _SFR_IO16(0x2E) |
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#define | OCR2RAL _SFR_IO8(0x2E) |
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#define | OCR2RA_0 0 |
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#define | OCR2RA_1 1 |
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#define | OCR2RA_2 2 |
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#define | OCR2RA_3 3 |
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#define | OCR2RA_4 4 |
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#define | OCR2RA_5 5 |
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#define | OCR2RA_6 6 |
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#define | OCR2RA_7 7 |
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#define | OCR2RAH _SFR_IO8(0x2F) |
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#define | OCR2RA_8 0 |
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#define | OCR2RA_9 1 |
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#define | OCR2RA_10 2 |
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#define | OCR2RA_11 3 |
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#define | DWDR _SFR_IO8(0x31) |
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#define | MSMCR _SFR_IO8(0x32) |
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#define | SMCR _SFR_IO8(0x33) |
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#define | SE 0 |
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#define | SM0 1 |
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#define | SM1 2 |
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#define | SM2 3 |
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#define | MCUSR _SFR_IO8(0x34) |
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#define | PORF 0 |
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#define | EXTRF 1 |
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#define | BORF 2 |
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#define | WDRF 3 |
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#define | MCUCR _SFR_IO8(0x35) |
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#define | IVCE 0 |
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#define | IVSEL 1 |
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#define | CKRC81 2 |
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#define | RSTDIS 3 |
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#define | PUD 4 |
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#define | SPDR _SFR_IO8(0x36) |
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#define | SPDR0 0 |
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#define | SPDR1 1 |
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#define | SPDR2 2 |
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#define | SPDR3 3 |
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#define | SPDR4 4 |
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#define | SPDR5 5 |
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#define | SPDR6 6 |
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#define | SPDR7 7 |
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#define | SPMCSR _SFR_IO8(0x37) |
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#define | SPMEN 0 |
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#define | PGERS 1 |
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#define | PGWRT 2 |
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#define | BLBSET 3 |
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#define | RWWSRE 4 |
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#define | SIGRD 5 |
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#define | RWWSB 6 |
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#define | SPMIE 7 |
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#define | DAC _SFR_IO16(0x38) |
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#define | DACL _SFR_IO8(0x38) |
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#define | DACL0 0 |
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#define | DACL1 1 |
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#define | DACL2 2 |
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#define | DACL3 3 |
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#define | DACL4 4 |
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#define | DACL5 5 |
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#define | DACL6 6 |
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#define | DACL7 7 |
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#define | DACH _SFR_IO8(0x39) |
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#define | DACH0 0 |
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#define | DACH1 1 |
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#define | DACH2 2 |
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#define | DACH3 3 |
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#define | DACH4 4 |
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#define | DACH5 5 |
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#define | DACH6 6 |
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#define | DACH7 7 |
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#define | TCNT1 _SFR_IO16(0x3A) |
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#define | TCNT1L _SFR_IO8(0x3A) |
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#define | TCNT1L0 0 |
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#define | TCNT1L1 1 |
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#define | TCNT1L2 2 |
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#define | TCNT1L3 3 |
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#define | TCNT1L4 4 |
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#define | TCNT1L5 5 |
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#define | TCNT1L6 6 |
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#define | TCNT1L7 7 |
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#define | TCNT1H _SFR_IO8(0x3B) |
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#define | TCNT1H0 0 |
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#define | TCNT1H1 1 |
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#define | TCNT1H2 2 |
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#define | TCNT1H3 3 |
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#define | TCNT1H4 4 |
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#define | TCNT1H5 5 |
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#define | TCNT1H6 6 |
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#define | TCNT1H7 7 |
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#define | OCR0SA _SFR_MEM16(0x60) |
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#define | OCR0SAL _SFR_MEM8(0x60) |
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#define | OCR0SA_0 0 |
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#define | OCR0SA_1 1 |
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#define | OCR0SA_2 2 |
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#define | OCR0SA_3 3 |
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#define | OCR0SA_4 4 |
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#define | OCR0SA_5 5 |
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#define | OCR0SA_6 6 |
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#define | OCR0SA_7 7 |
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#define | OCR0SAH _SFR_MEM8(0x61) |
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#define | OCR0SA_8 0 |
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#define | OCR0SA_9 1 |
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#define | OCR0SA_00 2 |
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#define | OCR0SA_01 3 |
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#define | PFRC0A _SFR_MEM8(0x62) |
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#define | PRFM0A0 0 |
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#define | PRFM0A1 1 |
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#define | PRFM0A2 2 |
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#define | PRFM0A3 3 |
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#define | PFLTE0A 4 |
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#define | PELEV0A 5 |
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#define | PISEL0A 6 |
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#define | PCAE0A 7 |
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#define | PFRC0B _SFR_MEM8(0x63) |
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#define | PRFM0B0 0 |
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#define | PRFM0B1 1 |
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#define | PRFM0B2 2 |
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#define | PRFM0B3 3 |
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#define | PFLTE0B 4 |
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#define | PELEV0B 5 |
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#define | PISEL0B 6 |
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#define | PCAE0B 7 |
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#define | OCR2SA _SFR_MEM16(0x64) |
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#define | OCR2SAL _SFR_MEM8(0x64) |
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#define | OCR2SA_0 0 |
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#define | OCR2SA_1 1 |
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#define | OCR2SA_2 2 |
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#define | OCR2SA_3 3 |
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#define | OCR2SA_4 4 |
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#define | OCR2SA_5 5 |
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#define | OCR2SA_6 6 |
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#define | OCR2SA_7 7 |
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#define | OCR2SAH _SFR_MEM8(0x65) |
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#define | OCR2SA_8 0 |
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#define | OCR2SA_9 1 |
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#define | OCR2SA_10 2 |
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#define | OCR2SA_11 3 |
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#define | PFRC2A _SFR_MEM8(0x66) |
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#define | PRFM2A0 0 |
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#define | PRFM2A1 1 |
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#define | PRFM2A2 2 |
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#define | PRFM2A3 3 |
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#define | PFLTE2A 4 |
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#define | PELEV2A 5 |
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#define | PISEL2A 6 |
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#define | PCAE2A 7 |
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#define | PFRC2B _SFR_MEM8(0x67) |
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#define | PRFM2B0 0 |
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#define | PRFM2B1 1 |
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#define | PRFM2B2 2 |
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#define | PRFM2B3 3 |
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#define | PFLTE2B 4 |
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#define | PELEV2B 5 |
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#define | PISEL2B 6 |
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#define | PCAE2B 7 |
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#define | PICR0 _SFR_MEM16(0x68) |
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#define | PICR0L _SFR_MEM8(0x68) |
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#define | PICR0_0 0 |
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#define | PICR0_1 1 |
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#define | PICR0_2 2 |
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#define | PICR0_3 3 |
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#define | PICR0_4 4 |
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#define | PICR0_5 5 |
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#define | PICR0_6 6 |
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#define | PICR0_7 7 |
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#define | PICR0H _SFR_MEM8(0x69) |
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#define | PICR0_8 0 |
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#define | PICR0_9 1 |
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#define | PICR0_10 2 |
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#define | PICR0_11 3 |
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#define | PCST0 7 |
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#define | PSOC0 _SFR_MEM8(0x6A) |
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#define | POEN0A 0 |
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#define | POEN0B 2 |
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#define | PSYNC00 4 |
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#define | PSYNC01 5 |
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#define | PISEL0B1 6 |
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#define | PISEL0A1 7 |
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#define | PICR2 _SFR_MEM16(0x6C) |
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#define | PICR2L _SFR_MEM8(0x6C) |
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#define | PICR2_0 0 |
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#define | PICR2_1 1 |
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#define | PICR2_2 2 |
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#define | PICR2_3 3 |
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#define | PICR2_4 4 |
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#define | PICR2_5 5 |
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#define | PICR2_6 6 |
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#define | PICR2_7 7 |
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#define | PICR2H _SFR_MEM8(0x6D) |
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#define | PICR2_8 0 |
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#define | PICR2_9 1 |
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#define | PICR2_10 2 |
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#define | PICR2_11 3 |
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#define | PCST2 7 |
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#define | PSOC2 _SFR_MEM8(0x6E) |
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#define | POEN2A 0 |
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#define | POEN2C 1 |
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#define | POEN2B 2 |
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#define | POEN2D 3 |
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#define | PSYNC2_0 4 |
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#define | PSYNC2_1 5 |
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#define | POS22 6 |
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#define | POS23 7 |
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#define | POM2 _SFR_MEM8(0x6F) |
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#define | POMV2A0 0 |
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#define | POMV2A1 1 |
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#define | POMV2A2 2 |
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#define | POMV2A3 3 |
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#define | POMV2B0 4 |
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#define | POMV2B1 5 |
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#define | POMV2B2 6 |
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#define | POMV2B3 7 |
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#define | PCNFE2 _SFR_MEM8(0x70) |
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#define | PISEL2B1 0 |
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#define | PISEL2A1 1 |
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#define | PELEV2B1 2 |
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#define | PELEV2A1 3 |
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#define | PBFM21 4 |
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#define | PASDLK20 5 |
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#define | PASDLK21 6 |
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#define | PASDLK22 7 |
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#define | PASDLY2 _SFR_MEM8(0x71) |
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#define | PASDLY2_0 0 |
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#define | PASDLY2_1 1 |
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#define | PASDLY2_2 2 |
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#define | PASDLY2_3 3 |
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#define | PASDLY2_4 4 |
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#define | PASDLY2_5 5 |
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#define | PASDLY2_6 6 |
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#define | PASDLY2_7 7 |
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#define | DACON _SFR_MEM8(0x76) |
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#define | DAEN 0 |
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#define | DALA 2 |
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#define | DATS0 4 |
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#define | DATS1 5 |
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#define | DATS2 6 |
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#define | DAATE 7 |
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#define | DIDR0 _SFR_MEM8(0x77) |
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#define | ADC0D 0 |
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#define | ADC1D 1 |
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#define | ADC2D 2 |
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#define | ADC3D 3 |
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#define | ADC4D 4 |
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#define | ADC5D 5 |
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#define | ADC7D 6 |
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#define | ADC8D 7 |
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#define | DIDR1 _SFR_MEM8(0x78) |
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#define | ADC9D 0 |
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#define | ADC10D 1 |
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#define | AMP0PD 2 |
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#define | ACMP1MD 3 |
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#define | AMP0CSR _SFR_MEM8(0x79) |
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#define | AMP0TS0 0 |
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#define | AMP0TS1 1 |
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#define | AMP0GS 3 |
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#define | AMP0G0 4 |
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#define | AMP0G1 5 |
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#define | AMP0IS 6 |
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#define | AMP0EN 7 |
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#define | AC1ECON _SFR_MEM8(0x7A) |
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#define | AC1H0 0 |
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#define | AC1H1 1 |
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#define | AC1H2 2 |
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#define | AC1ICE 3 |
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#define | AC1OE 4 |
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#define | AC1OI 5 |
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#define | AC2ECON _SFR_MEM8(0x7B) |
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#define | AC2H0 0 |
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#define | AC2H1 1 |
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#define | AC2H2 2 |
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#define | AC2OE 4 |
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#define | AC2OI 5 |
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#define | AC3ECON _SFR_MEM8(0x7C) |
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#define | AC3H0 0 |
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#define | AC3H1 1 |
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#define | AC3H2 2 |
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#define | AC3OE 4 |
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#define | AC3OI 5 |
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#define | AC1CON _SFR_MEM8(0x7D) |
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#define | AC1M0 0 |
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#define | AC1M1 1 |
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#define | AC1M2 2 |
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#define | AC1IS0 4 |
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#define | AC1IS1 5 |
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#define | AC1IE 6 |
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#define | AC1EN 7 |
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#define | AC2CON _SFR_MEM8(0x7E) |
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#define | AC2M0 0 |
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#define | AC2M1 1 |
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#define | AC2M2 2 |
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#define | AC2IS0 4 |
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#define | AC2IS1 5 |
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#define | AC2IE 6 |
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#define | AC2EN 7 |
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#define | AC3CON _SFR_MEM8(0x7F) |
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#define | AC3M0 0 |
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#define | AC3M1 1 |
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#define | AC3M2 2 |
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#define | AC3OEA 3 |
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#define | AC3IS0 4 |
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#define | AC3IS1 5 |
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#define | AC3IE 6 |
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#define | AC3EN 7 |
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#define | BGCRR _SFR_MEM8(0x80) |
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#define | BGCR0 0 |
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#define | BGCR1 1 |
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#define | BGCR2 2 |
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#define | BGCR3 3 |
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#define | BGCCR _SFR_MEM8(0x81) |
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#define | BGCC0 0 |
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#define | BGCC1 1 |
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#define | BGCC2 2 |
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#define | BGCC3 3 |
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#define | WDTCSR _SFR_MEM8(0x82) |
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#define | WDP0 0 |
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#define | WDP1 1 |
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#define | WDP2 2 |
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#define | WDE 3 |
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#define | WDCE 4 |
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#define | WDP3 5 |
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#define | WDIE 6 |
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#define | WDIF 7 |
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#define | CLKPR _SFR_MEM8(0x83) |
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#define | CLKPS0 0 |
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#define | CLKPS1 1 |
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#define | CLKPS2 2 |
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#define | CLKPS3 3 |
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#define | CLKPCE 7 |
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#define | CLKCSR _SFR_MEM8(0x84) |
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#define | CLKC0 0 |
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#define | CLKC1 1 |
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#define | CLKC2 2 |
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#define | CLKC3 3 |
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#define | CLKRDY 4 |
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#define | CLKCCE 7 |
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#define | CLKSELR _SFR_MEM8(0x85) |
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#define | CKSEL0 0 |
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#define | CKSEL1 1 |
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#define | CKSEL2 2 |
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#define | CKSEL3 3 |
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#define | CSUT0 4 |
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#define | CSUT1 5 |
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#define | COUT 6 |
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#define | PRR _SFR_MEM8(0x86) |
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#define | PRADC 0 |
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#define | PRSPI 2 |
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#define | PRTIM1 4 |
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#define | PRPSC0 5 |
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#define | PRPSC2 7 |
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#define | PLLCSR _SFR_MEM8(0x87) |
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#define | PLOCK 0 |
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#define | PLLE 1 |
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#define | PLLF0 2 |
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#define | PLLF1 3 |
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#define | PLLF2 4 |
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#define | PLLF3 5 |
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#define | OSCCAL _SFR_MEM8(0x88) |
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#define | CAL0 0 |
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#define | CAL1 1 |
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#define | CAL2 2 |
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#define | CAL3 3 |
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#define | CAL4 4 |
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#define | CAL5 5 |
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#define | CAL6 6 |
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#define | CAL7 7 |
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#define | EICRA _SFR_MEM8(0x89) |
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#define | ISC00 0 |
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#define | ISC01 1 |
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#define | ISC10 2 |
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#define | ISC11 3 |
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#define | ISC20 4 |
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#define | ISC21 5 |
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#define | TCCR1B _SFR_MEM8(0x8A) |
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#define | CS10 0 |
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#define | CS11 1 |
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#define | CS12 2 |
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#define | WGM13 4 |
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#define | ICES1 6 |
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#define | ICNC1 7 |
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#define | ICR1 _SFR_MEM16(0x8C) |
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#define | ICR1L _SFR_MEM8(0x8C) |
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#define | ICR1L0 0 |
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#define | ICR1L1 1 |
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#define | ICR1L2 2 |
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#define | ICR1L3 3 |
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#define | ICR1L4 4 |
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#define | ICR1L5 5 |
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#define | ICR1L6 6 |
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#define | ICR1L7 7 |
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#define | ICR1H _SFR_MEM8(0x8D) |
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#define | ICR1H0 0 |
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#define | ICR1H1 1 |
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#define | ICR1H2 2 |
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#define | ICR1H3 3 |
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#define | ICR1H4 4 |
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#define | ICR1H5 5 |
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#define | ICR1H6 6 |
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#define | ICR1H7 7 |
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#define | PSC2_CAPT_vect_num 1 |
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#define | PSC2_CAPT_vect _VECTOR(1) /* PSC2 Capture Event */ |
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#define | PSC2_EC_vect_num 2 |
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#define | PSC2_EC_vect _VECTOR(2) /* PSC2 End Cycle */ |
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#define | PSC2_EEC_vect_num 3 |
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#define | PSC2_EEC_vect _VECTOR(3) /* PSC2 End Of Enhanced Cycle */ |
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#define | PSC0_CAPT_vect_num 4 |
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#define | PSC0_CAPT_vect _VECTOR(4) /* PSC0 Capture Event */ |
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#define | PSC0_EC_vect_num 5 |
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#define | PSC0_EC_vect _VECTOR(5) /* PSC0 End Cycle */ |
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#define | PSC0_EEC_vect_num 6 |
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#define | PSC0_EEC_vect _VECTOR(6) /* PSC0 End Of Enhanced Cycle */ |
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#define | ANALOG_COMP_1_vect_num 7 |
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#define | ANALOG_COMP_1_vect _VECTOR(7) /* Analog Comparator 1 */ |
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#define | ANALOG_COMP_2_vect_num 8 |
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#define | ANALOG_COMP_2_vect _VECTOR(8) /* Analog Comparator 2 */ |
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#define | ANALOG_COMP_3_vect_num 9 |
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#define | ANALOG_COMP_3_vect _VECTOR(9) /* Analog Comparator 3 */ |
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#define | INT0_vect_num 10 |
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#define | INT0_vect _VECTOR(10) /* External Interrupt Request 0 */ |
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#define | TIMER1_CAPT_vect_num 11 |
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#define | TIMER1_CAPT_vect _VECTOR(11) /* Timer/Counter1 Capture Event */ |
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#define | TIMER1_OVF_vect_num 12 |
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#define | TIMER1_OVF_vect _VECTOR(12) /* Timer/Counter1 Overflow */ |
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#define | ADC_vect_num 13 |
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#define | ADC_vect _VECTOR(13) /* ADC Conversion Complete */ |
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#define | INT1_vect_num 14 |
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#define | INT1_vect _VECTOR(14) /* External Interrupt Request 1 */ |
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#define | SPI_STC_vect_num 15 |
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#define | SPI_STC_vect _VECTOR(15) /* SPI Serial Transfer Complet */ |
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#define | INT2_vect_num 16 |
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#define | INT2_vect _VECTOR(16) /* External Interrupt Request 2 */ |
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#define | WDT_vect_num 17 |
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#define | WDT_vect _VECTOR(17) /* Watchdog Timeout Interrupt */ |
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#define | EE_READY_vect_num 18 |
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#define | EE_READY_vect _VECTOR(18) /* EEPROM Ready */ |
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#define | SPM_READY_vect_num 19 |
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#define | SPM_READY_vect _VECTOR(19) /* Store Program Memory Read */ |
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#define | _VECTOR_SIZE 2 /* Size of individual vector. */ |
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#define | _VECTORS_SIZE (20 * _VECTOR_SIZE) |
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#define | SPM_PAGESIZE (64) |
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#define | RAMSTART (0x0100) |
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#define | RAMSIZE (256) |
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#define | RAMEND (RAMSTART + RAMSIZE - 1) |
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#define | XRAMSTART (NA) |
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#define | XRAMSIZE (0) |
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#define | XRAMEND (RAMEND) |
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#define | E2END (0x1FF) |
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#define | E2PAGESIZE (4) |
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#define | FLASHEND (0x1FFF) |
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#define | FUSE_MEMORY_SIZE 3 |
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#define | FUSE_CKSEL0 (unsigned char)~_BV(0) /* Select Clock Source */ |
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#define | FUSE_CKSEL1 (unsigned char)~_BV(1) /* Select Clock Source */ |
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#define | FUSE_CKSEL2 (unsigned char)~_BV(2) /* Select Clock Source */ |
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#define | FUSE_CKSEL3 (unsigned char)~_BV(3) /* Select Clock Source */ |
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#define | FUSE_SUT0 (unsigned char)~_BV(4) /* Select start-up time */ |
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#define | FUSE_SUT1 (unsigned char)~_BV(5) /* Select start-up time */ |
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#define | FUSE_CKOUT (unsigned char)~_BV(6) /* Clock Output */ |
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#define | FUSE_CKDIV8 (unsigned char)~_BV(7) /* Divide clock by 8 */ |
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#define | LFUSE_DEFAULT (FUSE_CKDIV8 & FUSE_SUT0 & FUSE_CKSEL3 & FUSE_CKSEL2 & FUSE_CKSEL0) |
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#define | FUSE_BOOTRST (unsigned char)~_BV(0) /* Select Reset Vector */ |
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#define | FUSE_BOOTSZ0 (unsigned char)~_BV(1) /* Select Boot Size */ |
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#define | FUSE_BOOTSZ1 (unsigned char)~_BV(2) /* Select Boot Size */ |
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#define | FUSE_EESAVE (unsigned char)~_BV(3) /* EEPROM memory is preserved through chip erase */ |
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#define | FUSE_WDTON (unsigned char)~_BV(4) /* Watchdog timer always on */ |
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#define | FUSE_SPIEN (unsigned char)~_BV(5) /* Enable Serial programming and Data Downloading */ |
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#define | FUSE_DWEN (unsigned char)~_BV(6) /* debugWIRE Enable */ |
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#define | FUSE_RSTDISBL (unsigned char)~_BV(7) /* External Reset Disable */ |
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#define | HFUSE_DEFAULT (FUSE_SPIEN & FUSE_BOOTSZ1 & FUSE_BOOTSZ0) |
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#define | FUSE_BODLEVEL0 (unsigned char)~_BV(0) /* Brown-out Detector trigger level */ |
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#define | FUSE_BODLEVEL1 (unsigned char)~_BV(1) /* Brown-out Detector trigger level */ |
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#define | FUSE_BODLEVEL2 (unsigned char)~_BV(2) /* Brown out detector trigger level */ |
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#define | FUSE_PSCINRB (unsigned char)~_BV(3) /* PSC2 & PSC0 Input Reset Behavior */ |
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#define | FUSE_PSCRV (unsigned char)~_BV(4) /* PSCOUT Reset Value */ |
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#define | FUSE_PSC0RB (unsigned char)~_BV(5) /* PSC0 Reset Behaviour */ |
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#define | FUSE_PSC2RBA (unsigned char)~_BV(6) /* PSC2 Rest Behavior for out OUT22 & 23 */ |
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#define | FUSE_PSC2RB (unsigned char)~_BV(7) /* PSC2 Reset Behaviour */ |
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#define | EFUSE_DEFAULT (0xFF) |
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#define | __LOCK_BITS_EXIST |
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#define | __BOOT_LOCK_BITS_0_EXIST |
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#define | __BOOT_LOCK_BITS_1_EXIST |
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#define | SIGNATURE_0 0x1E |
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#define | SIGNATURE_1 0x93 |
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#define | SIGNATURE_2 0x88 |
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