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#define | SPCR _SFR_IO8(0x0D) |
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#define | SPSR _SFR_IO8(0x0E) |
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#define | SPDR _SFR_IO8(0x0F) |
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#define | PIND _SFR_IO8(0x10) |
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#define | DDRD _SFR_IO8(0x11) |
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#define | PORTD _SFR_IO8(0x12) |
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#define | PERIPHEN _SFR_IO8(0x13) |
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#define | CLK_CNTR _SFR_IO8(0x14) |
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#define | PORTC _SFR_IO8(0x15) |
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#define | PINB _SFR_IO8(0x16) |
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#define | DDRB _SFR_IO8(0x17) |
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#define | PORTB _SFR_IO8(0x18) |
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#define | PINA _SFR_IO8(0x19) |
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#define | DDRA _SFR_IO8(0x1A) |
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#define | PORTA _SFR_IO8(0x1B) |
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#define | IRDAMOD _SFR_IO8(0x20) |
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#define | WDTCR _SFR_IO8(0x21) |
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#define | ICR1 _SFR_IO16(0x26) |
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#define | ICR1L _SFR_IO8(0x26) |
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#define | ICR1H _SFR_IO8(0x27) |
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#define | OCR1B _SFR_IO16(0x28) |
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#define | OCR1BL _SFR_IO8(0x28) |
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#define | OCR1BH _SFR_IO8(0x29) |
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#define | OCR1A _SFR_IO16(0x2A) |
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#define | OCR1AL _SFR_IO8(0x2A) |
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#define | OCR1AH _SFR_IO8(0x2B) |
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#define | TCNT1 _SFR_IO16(0x2C) |
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#define | TCNT1L _SFR_IO8(0x2C) |
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#define | TCNT1H _SFR_IO8(0x2D) |
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#define | TCCR1B _SFR_IO8(0x2E) |
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#define | TCCR1A _SFR_IO8(0x2F) |
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#define | PRELD _SFR_IO8(0x31) |
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#define | TCNT0 _SFR_IO8(0x32) |
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#define | TCCR0 _SFR_IO8(0x33) |
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#define | MCUSR _SFR_IO8(0x34) |
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#define | MCUCR _SFR_IO8(0x35) |
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#define | TIFR _SFR_IO8(0x36) |
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#define | TIMSK _SFR_IO8(0x37) |
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#define | EIMSK _SFR_IO8(0x39) |
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#define | SIG_SUSPEND_RESUME _VECTOR(1) |
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#define | SIG_INTERRUPT0 _VECTOR(2) |
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#define | SIG_INPUT_CAPTURE1 _VECTOR(3) |
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#define | SIG_OUTPUT_COMPARE1A _VECTOR(4) |
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#define | SIG_OUTPUT_COMPARE1B _VECTOR(5) |
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#define | SIG_OVERFLOW1 _VECTOR(6) |
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#define | SIG_OVERFLOW0 _VECTOR(7) |
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#define | SIG_SPI _VECTOR(8) |
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#define | SIG_TDMAC _VECTOR(9) |
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#define | SIG_UART0 _VECTOR(10) |
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#define | SIG_RDMAC _VECTOR(11) |
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#define | SIG_USB_HW _VECTOR(12) |
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#define | SIG_UART1 _VECTOR(13) |
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#define | SIG_INTERRUPT1 _VECTOR(14) |
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#define | _VECTORS_SIZE 60 |
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#define | POL1 3 |
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#define | POL0 2 |
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#define | INT1 1 |
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#define | INT0 0 |
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#define | TOIE1 7 |
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#define | OCIE1A 6 |
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#define | OCIE1B 5 |
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#define | TICIE1 3 |
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#define | TOIE0 1 |
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#define | TOV1 7 |
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#define | OCF1A 6 |
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#define | OCF1B 5 |
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#define | ICF1 3 |
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#define | TOV0 1 |
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#define | SE 5 |
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#define | SM1 4 |
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#define | SM0 3 |
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#define | EXTRF 1 |
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#define | PORF 0 |
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#define | COM01 5 |
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#define | COM00 4 |
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#define | CTC0 3 |
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#define | CS02 2 |
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#define | CS01 1 |
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#define | CS00 0 |
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#define | COM1A1 7 |
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#define | COM1A0 6 |
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#define | COM1B1 5 |
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#define | COM1B0 4 |
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#define | ICNC1 7 |
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#define | ICES1 6 |
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#define | CTC1 3 |
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#define | CS12 2 |
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#define | CS11 1 |
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#define | CS10 0 |
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#define | WDTOE 4 |
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#define | WDE 3 |
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#define | WDP2 2 |
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#define | WDP1 1 |
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#define | WDP0 0 |
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#define | POL 2 |
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#define | MODE 1 |
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#define | EN 0 |
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#define | PA7 7 |
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#define | PA6 6 |
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#define | PA5 5 |
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#define | PA4 4 |
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#define | PA3 3 |
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#define | PA2 2 |
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#define | PA1 1 |
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#define | PA0 0 |
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#define | DDA7 7 |
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#define | DDA6 6 |
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#define | DDA5 5 |
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#define | DDA4 4 |
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#define | DDA3 3 |
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#define | DDA2 2 |
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#define | DDA1 1 |
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#define | DDA0 0 |
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#define | PINA7 7 |
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#define | PINA6 6 |
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#define | PINA5 5 |
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#define | PINA4 4 |
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#define | PINA3 3 |
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#define | PINA2 2 |
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#define | PINA1 1 |
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#define | PINA0 0 |
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#define | PB7 7 |
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#define | PB6 6 |
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#define | PB5 5 |
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#define | PB4 4 |
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#define | PB3 3 |
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#define | PB2 2 |
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#define | PB1 1 |
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#define | PB0 0 |
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#define | DDB7 7 |
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#define | DDB6 6 |
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#define | DDB5 5 |
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#define | DDB4 4 |
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#define | DDB3 3 |
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#define | DDB2 2 |
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#define | DDB1 1 |
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#define | DDB0 0 |
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#define | PINB7 7 |
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#define | PINB6 6 |
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#define | PINB5 5 |
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#define | PINB4 4 |
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#define | PINB3 3 |
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#define | PINB2 2 |
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#define | PINB1 1 |
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#define | PINB0 0 |
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#define | PC3 3 |
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#define | PC2 2 |
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#define | PC1 1 |
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#define | PC0 0 |
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#define | PD7 7 |
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#define | PD6 6 |
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#define | PD5 5 |
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#define | PD4 4 |
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#define | PD3 3 |
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#define | PD2 2 |
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#define | PD1 1 |
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#define | PD0 0 |
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#define | DDD7 7 |
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#define | DDD6 6 |
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#define | DDD5 5 |
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#define | DDD4 4 |
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#define | DDD3 3 |
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#define | DDD2 2 |
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#define | DDD1 1 |
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#define | DDD0 0 |
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#define | PIND7 7 |
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#define | PIND6 6 |
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#define | PIND5 5 |
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#define | PIND4 4 |
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#define | PIND3 3 |
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#define | PIND2 2 |
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#define | PIND1 1 |
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#define | PIND0 0 |
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#define | UOSC 4 |
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#define | UCK 3 |
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#define | IRCK 2 |
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#define | IRDA 2 |
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#define | UART 1 |
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#define | USB 0 |
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#define | SPIF 7 |
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#define | WCOL 6 |
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#define | SPIE 7 |
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#define | SPE 6 |
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#define | DORD 5 |
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#define | MSTR 4 |
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#define | CPOL 3 |
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#define | CPHA 2 |
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#define | SPR1 1 |
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#define | SPR0 0 |
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#define | UART0_BASE 0x2020 |
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#define | UART1_BASE 0x2030 |
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#define | US_RHR 0x00 |
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#define | US_THR 0x00 |
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#define | US_IER 0x01 |
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#define | US_FCR 0x02 |
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#define | US_PMR 0x03 |
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#define | US_MR 0x04 |
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#define | US_CSR 0x05 |
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#define | US_CR 0x06 |
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#define | US_BL 0x07 |
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#define | US_BM 0x08 |
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#define | US_RTO 0x09 |
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#define | US_TTG 0x0A |
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#define | DMA_BASE 0x2000 |
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#define | TXTADL 0x01 |
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#define | TXPLL 0x03 |
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#define | TXPLM 0x04 |
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#define | TXTPLL 0x05 |
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#define | TXTPLM 0x06 |
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#define | RXTADL 0x07 |
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#define | RXTADMEN 0x08 |
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#define | RSPLL 0x09 |
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#define | RXPLM 0x0A |
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#define | RXTPLL 0x0B |
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#define | RXTPLM 0x0C |
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#define | INTCST 0x0D |
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#define | PROGRAM_MEMORY_CONTROL_BIT 0x2040 |
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#define | USB_BASE 0x1000 |
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#define | FRM_NUM_H 0x0FD |
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#define | FRM_NUM_L 0x0FC |
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#define | GLB_STATE 0x0FB |
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#define | SPRSR 0x0FA |
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#define | SPRSIE 0x0F9 |
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#define | UISR 0x0F7 |
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#define | UIAR 0x0F5 |
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#define | FADDR 0x0F2 |
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#define | ENDPPGPG 0x0F1 |
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#define | ECR0 0x0EF |
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#define | ECR1 0x0EE |
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#define | ECR2 0x0ED |
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#define | ECR3 0x0EC |
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#define | ECR4 0x0EB |
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#define | ECR5 0x0EA |
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#define | ECR6 0x0E9 |
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#define | ECR7 0x0E8 |
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#define | CSR0 0x0DF |
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#define | CSR1 0x0DE |
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#define | CSR2 0x0DD |
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#define | CSR3 0x0DC |
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#define | CSR4 0x0DB |
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#define | CSR5 0x0DA |
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#define | CSR6 0x0D9 |
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#define | CSR7 0x0D8 |
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#define | FDR0 0x0CF |
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#define | FDR1 0x0CE |
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#define | FDR2 0x0CD |
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#define | FDR3 0x0CC |
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#define | FDR4 0x0CB |
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#define | FDR5 0x0CA |
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#define | FDR6 0x0C9 |
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#define | FDR7 0x0C8 |
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#define | FBYTE_CNT0_L 0x0BF |
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#define | FBYTE_CNT1_L 0x0BE |
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#define | FBYTE_CNT2_L 0x0BD |
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#define | FBYTE_CNT3_L 0x0BC |
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#define | FBYTE_CNT4_L 0x0BB |
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#define | FBYTE_CNT5_L 0x0BA |
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#define | FBYTE_CNT6_L 0x0B9 |
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#define | FBYTE_CNT7_L 0x0B8 |
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#define | FBYTE_CNT0_H 0x0AF |
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#define | FBYTE_CNT1_H 0x0AE |
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#define | FBYTE_CNT2_H 0x0AD |
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#define | FBYTE_CNT3_H 0x0AC |
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#define | FBYTE_CNT4_H 0x0AB |
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#define | FBYTE_CNT5_H 0x0AA |
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#define | FBYTE_CNT6_H 0x0A9 |
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#define | FBYTE_CNT7_H 0x0A8 |
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#define | SLP_MD_EN 0x100 |
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#define | IRQ_EN 0x101 |
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#define | IRQ_STAT 0x102 |
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#define | SUSP_WUP 0x103 |
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#define | PA_EN 0x104 |
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#define | USB_DMA_ADL 0x105 |
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#define | USB_DMA_ADH 0x106 |
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#define | USB_DMA_PLR 0x107 |
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#define | USB_DMA_EAD 0x108 |
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#define | USB_DMA_PLT 0x109 |
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#define | USB_DMA_EN 0x10A |
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#define | RAMEND 0x07FF |
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#define | XRAMEND RAMEND |
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#define | E2END 0 |
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#define | FLASHEND 0x3FFF |
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