RTEMS CPU Kit with SuperCore
4.11.3
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data0
chrisj
rtems
releases
rtems-release.git
4.11.3
ws-rtems
rtems-4.11.3
cpukit
score
cpu
bfin
rtems
bfin
bfin.h
Go to the documentation of this file.
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/*
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* COPYRIGHT (c) 2006 by Atos Automacao Industrial Ltda.
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* modified by Alain Schaefer <alain.schaefer@easc.ch>
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* and Antonio Giovanini <antonio@atos.com.br>
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*
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* The license and distribution terms for this file may be
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* found in the file LICENSE in this distribution or at
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* http://www.rtems.org/license/LICENSE.
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*
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*/
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#ifndef _RTEMS_BFIN_BFIN_H
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#define _RTEMS_BFIN_BFIN_H
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#ifdef __cplusplus
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extern
"C"
{
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#endif
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/* Scratchpad SRAM */
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#define SCRATCH 0xFFB00000
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#define SCRATCH_SIZE 0x1000
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#define SCRATCH_TOP 0xFFB00ffc
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/* System Interrupt Controller Chapter 4*/
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#define SIC_RVECT 0xFFC00108
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#define SIC_IMASK 0xFFC0010C
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#define SIC_IAR0 0xFFC00110
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#define SIC_IAR1 0xFFC00114
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#define SIC_IAR2 0xFFC00118
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#define SIC_ISR 0xFFC00120
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#define SIC_IWR 0xFFC00124
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/* Event Vector Table Chapter 4 */
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#define EVT0 0xFFE02000
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#define EVT1 0xFFE02004
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#define EVT2 0xFFE02008
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#define EVT3 0xFFE0200C
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#define EVT4 0xFFE02010
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#define EVT5 0xFFE02014
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#define EVT6 0xFFE02018
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#define EVT7 0xFFE0201C
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#define EVT8 0xFFE02020
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#define EVT9 0xFFE02024
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#define EVT10 0xFFE02028
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#define EVT11 0xFFE0202C
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#define EVT12 0xFFE02030
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#define EVT13 0xFFE02034
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#define EVT14 0xFFE02038
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#define EVT15 0xFFE0203C
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#define IMASK 0xFFE02104
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#define IPEND 0xFFE02108
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#define ILAT 0xFFE0210C
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#define IPRIO 0xFFE02110
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#define TCNTL 0xFFE03000
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#define TPERIOD 0xFFE03004
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#define TSCALE 0xFFE03008
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#define TCOUNT 0xFFE0300C
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/* Masks for Timer Control */
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#define TMPWR 0x00000001
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#define TMREN 0x00000002
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#define TAUTORLD 0x00000004
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#define TINT 0x00000008
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/* Event Bit Positions */
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#define EVT_IVTMR_P 0x00000006
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#define EVT_IVTMR (1 << EVT_IVTMR_P)
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#ifdef __cplusplus
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}
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#endif
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#endif
/* _RTEMS_SCORE_BFIN_H */
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