RTEMS CPU Kit with SuperCore
4.11.3
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rtems
releases
rtems-release.git
4.11.3
ws-rtems
rtems-4.11.3
cpukit
score
cpu
bfin
rtems
bfin
bf52x.h
Go to the documentation of this file.
1
14
/*
15
* COPYRIGHT (c) 2006.
16
* Atos Automacao Industrial LTDA.
17
* modified by Alain Schaefer <alain.schaefer@easc.ch>
18
* and Antonio Giovanini <antonio@atos.com.br>
19
*
20
* The license and distribution terms for this file may be
21
* found in the file LICENSE in this distribution or at
22
* http://www.rtems.org/license/LICENSE.
23
*
24
*
25
* Author: Rohan Kangralkar, ECE Department Northeastern University
26
* Date: 02/15/2011
27
*/
28
29
#ifndef _RTEMS_BFIN_52x_H
30
#define _RTEMS_BFIN_52x_H
31
32
#include <
rtems/bfin/bfin.h
>
33
34
#ifdef __cplusplus
35
extern
"C"
{
36
#endif
37
38
39
/* Clock and System Control Chapter 8 */
40
#define PLL_CTL 0xFFC00000L
41
#define PLL_DIV 0xFFC00004L
42
#define VR_CTL 0xFFC00008L
43
#define PLL_STAT 0xFFC0000CL
44
#define PLL_LOCKCNT 0xFFC00010L
45
#define SWRST 0xFFC00100L
46
#define SYSCR 0xFFC00104L
47
48
/* SPI Controller Chapter 10 */
49
#define SPI_CTL 0xFFC00500L
50
#define SPI_FLG 0xFFC00504L
51
#define SPI_STAT 0xFFC00508L
52
#define SPI_TDBR 0xFFC0050CL
53
#define SPI_RDBR 0xFFC00510L
54
#define SPI_BAUD 0xFFC00514L
55
#define SPI_SHADOW 0xFFC00518L
56
57
/* SPORT0 Controller */
58
#define SPORT0_TCR1 0xFFC00800L
59
#define SPORT0_TCR2 0xFFC00804L
60
#define SPORT0_TCLKDIV 0xFFC00808L
61
#define SPORT0_TFSDIV 0xFFC0080CL
62
#define SPORT0_TX 0xFFC00810L
63
#define SPORT0_RX 0xFFC00818L
64
#define SPORT0_RCR1 0xFFC00820L
65
#define SPORT0_RCR2 0xFFC00824L
66
#define SPORT0_RCLKDIV 0xFFC00828L
67
#define SPORT0_RFSDIV 0xFFC0082CL
68
#define SPORT0_STAT 0xFFC00830L
69
#define SPORT0_CHNL 0xFFC00834L
70
#define SPORT0_MCMC1 0xFFC00838L
71
#define SPORT0_MCMC2 0xFFC0083CL
72
#define SPORT0_MTCS0 0xFFC00840L
73
#define SPORT0_MTCS1 0xFFC00844L
74
#define SPORT0_MTCS2 0xFFC00848L
75
#define SPORT0_MTCS3 0xFFC0084CL
76
#define SPORT0_MRCS0 0xFFC00850L
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#define SPORT0_MRCS1 0xFFC00854L
78
#define SPORT0_MRCS2 0xFFC00858L
79
#define SPORT0_MRCS3 0xFFC0085CL
80
81
/* Parallel Peripheral Interface (PPI) Chapter 11 */
82
83
#define PPI_CONTROL 0xFFC01000L
84
#define PPI_STATUS 0xFFC01004L
85
#define PPI_COUNT 0xFFC01008L
86
#define PPI_DELAY 0xFFC0100CL
87
#define PPI_FRAME 0xFFC01010L
88
89
/********* PPI MASKS ***********/
90
/* PPI_CONTROL Masks */
91
#define PORT_EN 0x00000001
92
#define PORT_DIR 0x00000002
93
#define XFR_TYPE 0x0000000C
94
#define PORT_CFG 0x00000030
95
#define FLD_SEL 0x00000040
96
#define PACK_EN 0x00000080
97
#define DMA32 0x00000100
98
#define SKIP_EN 0x00000200
99
#define SKIP_EO 0x00000400
100
#define DLENGTH 0x00003800
101
#define DLEN_8 0x0
102
#define DLEN(x) (((x-9) & 0x07) << 11)
103
#define POL 0x0000C000
104
105
/* PPI_STATUS Masks */
106
#define FLD 0x00000400
107
#define FT_ERR 0x00000800
108
#define OVR 0x00001000
109
#define UNDR 0x00002000
110
#define ERR_DET 0x00004000
111
#define ERR_NCOR 0x00008000
112
113
/* SPORT1 Controller Chapter 12 */
114
#define SPORT1_TCR1 0xFFC00900L
115
#define SPORT1_TCR2 0xFFC00904L
116
#define SPORT1_TCLKDIV 0xFFC00908L
117
#define SPORT1_TFSDIV 0xFFC0090CL
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#define SPORT1_TX 0xFFC00910L
119
#define SPORT1_RX 0xFFC00918L
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#define SPORT1_RCR1 0xFFC00920L
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#define SPORT1_RCR2 0xFFC00924L
122
#define SPORT1_RCLKDIV 0xFFC00928L
123
#define SPORT1_RFSDIV 0xFFC0092CL
124
#define SPORT1_STAT 0xFFC00930L
125
#define SPORT1_CHNL 0xFFC00934L
126
#define SPORT1_MCMC1 0xFFC00938L
127
#define SPORT1_MCMC2 0xFFC0093CL
128
#define SPORT1_MTCS0 0xFFC00940L
129
#define SPORT1_MTCS1 0xFFC00944L
130
#define SPORT1_MTCS2 0xFFC00948L
131
#define SPORT1_MTCS3 0xFFC0094CL
132
#define SPORT1_MRCS0 0xFFC00950L
133
#define SPORT1_MRCS1 0xFFC00954L
134
#define SPORT1_MRCS2 0xFFC00958L
135
#define SPORT1_MRCS3 0xFFC0095CL
136
137
/* SPORTx_TCR1 Masks */
138
#define TSPEN 0x0001
139
#define ITCLK 0x0002
140
#define TDTYPE 0x000C
141
#define TLSBIT 0x0010
142
#define ITFS 0x0200
143
#define TFSR 0x0400
144
#define DITFS 0x0800
145
#define LTFS 0x1000
146
#define LATFS 0x2000
147
#define TCKFE 0x4000
148
149
/* SPORTx_TCR2 Masks */
150
#define SLEN 0x001F
151
#define TXSE 0x0100
152
#define TSFSE 0x0200
153
#define TRFST 0x0400
154
155
/* SPORTx_RCR1 Masks */
156
#define RSPEN 0x0001
157
#define IRCLK 0x0002
158
#define RDTYPE 0x000C
159
#define RULAW 0x0008
160
#define RALAW 0x000C
161
#define RLSBIT 0x0010
162
#define IRFS 0x0200
163
#define RFSR 0x0400
164
#define LRFS 0x1000
165
#define LARFS 0x2000
166
#define RCKFE 0x4000
167
168
/* SPORTx_RCR2 Masks */
169
#define SLEN 0x001F
170
#define RXSE 0x0100
171
#define RSFSE 0x0200
172
#define RRFST 0x0400
173
174
/* SPORTx_STAT Masks */
175
#define RXNE 0x0001
176
#define RUVF 0x0002
177
#define ROVF 0x0004
178
#define TXF 0x0008
179
#define TUVF 0x0010
180
#define TOVF 0x0020
181
#define TXHRE 0x0040
182
183
/* SPORTx_MCMC1 Masks */
184
#define WSIZE 0x0000F000
185
#define WOFF 0x000003FF
186
187
/* SPORTx_MCMC2 Masks */
188
#define MCCRM 0x00000003
189
#define MCDTXPE 0x00000004
190
#define MCDRXPE 0x00000008
191
#define MCMEN 0x00000010
192
#define FSDR 0x00000080
193
#define MFD 0x0000F000
194
195
/* UART Controller Chapter 13 */
196
#define UART_THR 0xFFC00400L
197
#define UART_RBR 0xFFC00400L
198
#define UART_DLL 0xFFC00400L
199
#define UART_IER 0xFFC00404L
200
#define UART_DLH 0xFFC00404L
201
#define UART_IIR 0xFFC00408L
202
#define UART_LCR 0xFFC0040CL
203
#define UART_MCR 0xFFC00410L
204
#define UART_LSR 0xFFC00414L
205
#define UART_SCR 0xFFC0041CL
206
#define UART_GCTL 0xFFC00424L
207
208
/*
209
* UART CONTROLLER MASKS
210
*/
211
212
/* UART_LCR */
213
#define DLAB 0x80
214
#define SB 0x40
215
#define STP 0x20
216
#define EPS 0x10
217
#define PEN 0x08
218
#define STB 0x04
219
#define WLS(x) ((x-5) & 0x03)
220
221
#define DLAB_P 0x07
222
#define SB_P 0x06
223
#define STP_P 0x05
224
#define EPS_P 0x04
225
#define PEN_P 0x03
226
#define STB_P 0x02
227
#define WLS_P1 0x01
228
#define WLS_P0 0x00
229
230
/* UART_MCR */
231
#define LOOP_ENA 0x10
232
#define LOOP_ENA_P 0x04
233
234
/* UART_LSR */
235
#define TEMT 0x40
236
#define THRE 0x20
237
#define BI 0x10
238
#define FE 0x08
239
#define PE 0x04
240
#define OE 0x02
241
#define DR 0x01
242
243
#define TEMP_P 0x06
244
#define THRE_P 0x05
245
#define BI_P 0x04
246
#define FE_P 0x03
247
#define PE_P 0x02
248
#define OE_P 0x01
249
#define DR_P 0x00
250
251
/* UART_IER */
252
#define ELSI 0x04
253
#define ETBEI 0x02
254
#define ERBFI 0x01
255
256
#define ELSI_P 0x02
257
#define ETBEI_P 0x01
258
#define ERBFI_P 0x00
259
260
/* UART_IIR */
261
#define STATUS(x) ((x << 1) & 0x06)
262
#define NINT 0x01
263
#define STATUS_P1 0x02
264
#define STATUS_P0 0x01
265
#define NINT_P 0x00
266
267
/* UART_GCTL */
268
#define FFE 0x20
269
#define FPE 0x10
270
#define RPOLC 0x08
271
#define TPOLC 0x04
272
#define IREN 0x02
273
#define UCEN 0x01
274
275
#define FFE_P 0x05
276
#define FPE_P 0x04
277
#define RPOLC_P 0x03
278
#define TPOLC_P 0x02
279
#define IREN_P 0x01
280
#define UCEN_P 0x00
281
282
/* General Purpose IO Chapter 14*/
283
#define FIO_FLAG_D 0xFFC00700L
284
#define FIO_FLAG_C 0xFFC00704L
285
#define FIO_FLAG_S 0xFFC00708L
286
#define FIO_FLAG_T 0xFFC0070CL
287
#define FIO_MASKA_D 0xFFC00710L
288
#define FIO_MASKA_C 0xFFC00714L
289
#define FIO_MASKA_S 0xFFC00718L
290
#define FIO_MASKA_T 0xFFC0071CL
291
#define FIO_MASKB_D 0xFFC00720L
292
#define FIO_MASKB_C 0xFFC00724L
293
#define FIO_MASKB_S 0xFFC00728L
294
#define FIO_MASKB_T 0xFFC0072CL
295
#define FIO_DIR 0xFFC00730L
296
#define FIO_POLAR 0xFFC00734L
297
#define FIO_EDGE 0xFFC00738L
298
#define FIO_BOTH 0xFFC0073CL
299
#define FIO_INEN 0xFFC00740L
300
301
302
/* General Purpose IO Chapter 9*/
303
#define PORTH_FER 0xFFC03208
304
#define PORTH_MUX 0xFFC03218
305
#define PORTHIO_DIR 0xFFC01730
306
#define PORTHIO_INEN 0xFFC01740
307
#define PORTHIO 0xFFC01700
308
#define PORTHIO_SET 0xFFC01708
309
#define PORTHIO_CLEAR 0xFFC01704
310
#define PORTHIO_TOGGLE 0xFFC0170C
311
312
313
#define FIO_INEN 0xFFC00740L
314
#define FIO_POLAR 0xFFC00734L
315
#define FIO_EDGE 0xFFC00738L
316
#define FIO_BOTH 0xFFC0073CL
317
318
319
320
#define FIO_FLAG_C 0xFFC00704L
321
#define FIO_FLAG_S 0xFFC00708L
322
#define FIO_FLAG_T 0xFFC0070CL
323
#define FIO_MASKA_D 0xFFC00710L
324
#define FIO_MASKA_C 0xFFC00714L
325
#define FIO_MASKA_S 0xFFC00718L
326
#define FIO_MASKA_T 0xFFC0071CL
327
#define FIO_MASKB_D 0xFFC00720L
328
#define FIO_MASKB_C 0xFFC00724L
329
#define FIO_MASKB_S 0xFFC00728L
330
#define FIO_MASKB_T 0xFFC0072CL
331
332
333
/* General Purpose IO Masks */
334
#define PF0 0x0001
335
#define PF1 0x0002
336
#define PF2 0x0004
337
#define PF3 0x0008
338
#define PF4 0x0010
339
#define PF5 0x0020
340
#define PF6 0x0040
341
#define PF7 0x0080
342
#define PF8 0x0100
343
#define PF9 0x0200
344
#define PF10 0x0400
345
#define PF11 0x0800
346
#define PF12 0x1000
347
#define PF13 0x2000
348
#define PF14 0x4000
349
#define PF15 0x8000
350
351
352
/* TIMER 0, 1, 2 Chapter 15 */
353
#define TIMER0_CONFIG 0xFFC00600L
354
#define TIMER0_COUNTER 0xFFC00604L
355
#define TIMER0_PERIOD 0xFFC00608L
356
#define TIMER0_WIDTH 0xFFC0060CL
357
358
#define TIMER1_CONFIG 0xFFC00610L
359
#define TIMER1_COUNTER 0xFFC00614L
360
#define TIMER1_PERIOD 0xFFC00618L
361
#define TIMER1_WIDTH 0xFFC0061CL
362
363
#define TIMER2_CONFIG 0xFFC00620L
364
#define TIMER2_COUNTER 0xFFC00624L
365
#define TIMER2_PERIOD 0xFFC00628L
366
#define TIMER2_WIDTH 0xFFC0062CL
367
368
#define TIMER_ENABLE 0xFFC00640L
369
#define TIMER_DISABLE 0xFFC00644L
370
#define TIMER_STATUS 0xFFC00648L
371
372
/* Real Time Clock Chapter 16 */
373
#define RTC_STAT 0xFFC00300L
374
#define RTC_ICTL 0xFFC00304L
375
#define RTC_ISTAT 0xFFC00308L
376
#define RTC_SWCNT 0xFFC0030CL
377
#define RTC_ALARM 0xFFC00310L
378
#define RTC_FAST 0xFFC00314L
379
#define RTC_PREN 0xFFC00314L
380
381
/* RTC_FAST Mask (RTC_PREN Mask) */
382
#define ENABLE_PRESCALE 0x00000001
383
#define PREN 0x00000001
384
385
/* Asynchronous Memory Controller EBUI, Chapter 17*/
386
#define EBIU_AMGCTL 0xFFC00A00L
387
#define EBIU_AMBCTL0 0xFFC00A04L
388
#define EBIU_AMBCTL1 0xFFC00A08L
389
390
/* SDRAM Controller External Bus Interface Unit */
391
392
#define EBIU_SDGCTL 0xFFC00A10L
393
#define EBIU_SDBCTL 0xFFC00A14L
394
#define EBIU_SDRRC 0xFFC00A18L
395
#define EBIU_SDSTAT 0xFFC00A1CL
396
397
398
399
400
/* DCPLB_DATA and ICPLB_DATA Registers */
401
/*** Bit Positions */
402
#define CPLB_VALID_P 0x00000000
/* 0=invalid entry, 1=valid entry */
403
#define CPLB_LOCK_P 0x00000001
/* 0=entry may be replaced, 1=entry locked */
404
#define CPLB_USER_RD_P 0x00000002
/* 0=no read access, 1=read access allowed (user mode) */
405
/*** Masks */
406
#define CPLB_VALID 0x00000001
/* 0=invalid entry, 1=valid entry */
407
#define CPLB_LOCK 0x00000002
/* 0=entry may be replaced, 1=entry locked */
408
#define CPLB_USER_RD 0x00000004
/* 0=no read access, 1=read access allowed (user mode) */
409
#define PAGE_SIZE_1KB 0x00000000
/* 1 KB page size */
410
#define PAGE_SIZE_4KB 0x00010000
/* 4 KB page size */
411
#define PAGE_SIZE_1MB 0x00020000
/* 1 MB page size */
412
#define PAGE_SIZE_4MB 0x00030000
/* 4 MB page size */
413
#define CPLB_PORTPRIO 0x00000200
/* 0=low priority port, 1= high priority port */
414
#define CPLB_L1_CHBL 0x00001000
/* 0=non-cacheable in L1, 1=cacheable in L1 */
415
/*** ICPLB_DATA only */
416
#define CPLB_LRUPRIO 0x00000100
/* 0=can be replaced by any line, 1=priority for non-replacement */
417
/*** DCPLB_DATA only */
418
#define CPLB_USER_WR 0x00000008
/* 0=no write access, 0=write access allowed (user mode) */
419
#define CPLB_SUPV_WR 0x00000010
/* 0=no write access, 0=write access allowed (supervisor mode) */
420
#define CPLB_DIRTY 0x00000080
/* 1=dirty, 0=clean */
421
#define CPLB_L1_AOW 0x00008000
/* 0=do not allocate cache lines on write-through writes, */
422
/* 1= allocate cache lines on write-through writes. */
423
#define CPLB_WT 0x00004000
/* 0=write-back, 1=write-through */
424
425
426
#ifdef __cplusplus
427
}
428
#endif
429
430
#endif
/* _RTEMS_SCORE_BFIN_H */
bfin.h
Macros for MMR register common to all Blackfin Processors.
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