20 #ifndef _RTEMS_SCORE_CPU_H 21 #define _RTEMS_SCORE_CPU_H 27 #include <rtems/score/types.h> 33 #define CPU_INLINE_ENABLE_DISPATCH FALSE 35 #define CPU_HAS_SOFTWARE_INTERRUPT_STACK TRUE 37 #define CPU_SIMPLE_VECTORED_INTERRUPTS TRUE 39 #define CPU_INTERRUPT_NUMBER_OF_VECTORS 32 41 #define CPU_INTERRUPT_MAXIMUM_VECTOR_NUMBER (CPU_INTERRUPT_NUMBER_OF_VECTORS - 1) 43 #define CPU_PROVIDES_ISR_IS_IN_PROGRESS TRUE 45 #define CPU_HAS_HARDWARE_INTERRUPT_STACK FALSE 47 #define CPU_ALLOCATE_INTERRUPT_STACK TRUE 49 #define CPU_ISR_PASSES_FRAME_POINTER FALSE 51 #define CPU_HARDWARE_FP FALSE 53 #define CPU_SOFTWARE_FP FALSE 55 #define CPU_CONTEXT_FP_SIZE 0 57 #define CPU_ALL_TASKS_ARE_FP FALSE 59 #define CPU_IDLE_TASK_IS_FP FALSE 61 #define CPU_USE_DEFERRED_FP_SWITCH FALSE 63 #define CPU_PROVIDES_IDLE_THREAD_BODY FALSE 65 #define CPU_STACK_GROWS_UP FALSE 67 #define CPU_STRUCTURE_ALIGNMENT __attribute__((section(".sdata"), aligned(32))) 69 #define CPU_TIMESTAMP_USE_INT64_INLINE TRUE 71 #define CPU_BIG_ENDIAN FALSE 73 #define CPU_LITTLE_ENDIAN TRUE 75 #define CPU_STACK_MINIMUM_SIZE (4 * 1024) 77 #define CPU_SIZEOF_POINTER 4 83 #define CPU_ALIGNMENT 4 85 #define CPU_HEAP_ALIGNMENT CPU_ALIGNMENT 87 #define CPU_PARTITION_ALIGNMENT CPU_ALIGNMENT 93 #define CPU_STACK_ALIGNMENT 4 102 #define CPU_MODES_INTERRUPT_MASK 0x3f 104 #define CPU_USE_GENERIC_BITFIELD_CODE TRUE 106 #define CPU_USE_GENERIC_BITFIELD_DATA TRUE 108 #define CPU_MPCI_RECEIVE_SERVER_EXTRA_STACK 0 110 #define CPU_PER_CPU_CONTROL_SIZE 0 141 uint32_t thread_dispatch_disabled;
142 uint32_t stack_mpubase;
143 uint32_t stack_mpuacc;
146 #define _CPU_Context_Get_SP( _context ) \ 149 typedef void CPU_Interrupt_frame;
186 #define _CPU_Initialize_vectors() 208 #define _CPU_ISR_Disable( _isr_cookie ) \ 212 "rdctl %0, status\n" \ 213 "movhi %1, %%hiadj(_Nios2_ISR_Status_mask)\n" \ 214 "addi %1, %1, %%lo(_Nios2_ISR_Status_mask)\n" \ 216 "ori %1, %1, %%lo(_Nios2_ISR_Status_bits)\n" \ 218 : "=&r" (_isr_cookie), "=&r" (_tmp) \ 228 #define _CPU_ISR_Enable( _isr_cookie ) \ 229 __builtin_wrctl( 0, (int) _isr_cookie ) 242 #define _CPU_ISR_Flash( _isr_cookie ) \ 244 int _status = __builtin_rdctl( 0 ); \ 245 __builtin_wrctl( 0, (int) _isr_cookie ); \ 246 __builtin_wrctl( 0, _status ); \ 293 void *stack_area_begin,
294 size_t stack_area_size,
296 void (*entry_point)(
void ),
301 #define _CPU_Context_Restart_self( _the_context ) \ 302 _CPU_Context_restore( (_the_context) ); 342 static inline uint32_t CPU_swap_u32( uint32_t value )
344 uint32_t byte1, byte2, byte3, byte4, swapped;
346 byte4 = (value >> 24) & 0xff;
347 byte3 = (value >> 16) & 0xff;
348 byte2 = (value >> 8) & 0xff;
349 byte1 = value & 0xff;
351 swapped = (byte1 << 24) | (byte2 << 16) | (byte3 << 8) | byte4;
356 #define CPU_swap_u16( value ) \ 357 (((value&0xff) << 8) | ((value >> 8)&0xff)) 364 CPU_Counter_ticks second,
365 CPU_Counter_ticks first
368 return second - first;
void _CPU_ISR_install_vector(uint32_t vector, proc_ptr new_handler, proc_ptr *old_handler)
This routine installs an interrupt vector.
Definition: cpu.c:69
void _CPU_Context_validate(uintptr_t pattern)
Initializes and validates the CPU context with values derived from the pattern parameter.
Definition: cpu.h:1109
uint32_t _CPU_ISR_Get_level(void)
Return the current interrupt disable level for this task in the format used by the interrupt level po...
Definition: cpu.c:39
void _CPU_Context_restore(Context_Control *new_context)
This routine is generally used only to restart self in an efficient manner.
Definition: cpu_asm.c:112
void _CPU_Context_switch(Context_Control *run, Context_Control *heir)
CPU switch context.
Definition: cpu_asm.c:92
void _CPU_Context_volatile_clobber(uintptr_t pattern)
Clobbers all volatile registers with values derived from the pattern parameter.
Definition: cpu.h:1104
This defines the minimal set of integer and processor state registers that must be saved during a vol...
Definition: cpu.h:248
void _CPU_Initialize(void)
CPU initialization.
Definition: cpu.c:26
uint32_t CPU_Counter_ticks
Unsigned integer type for CPU counter values.
Definition: cpu.h:1461
void _CPU_ISR_install_raw_handler(uint32_t vector, proc_ptr new_handler, proc_ptr *old_handler)
This routine installs a "raw" interrupt handler directly into the processor's vector table...
Definition: cpu.c:57
void _CPU_ISR_Set_level(uint32_t level)
Sets the hardware interrupt level by the level value.
Definition: cpu.c:62
NIOS II Set up Basic CPU Dependency Settings Based on Compiler Settings.
void _CPU_Context_Initialize(Context_Control *the_context, uint32_t *stack_base, uint32_t size, uint32_t new_level, void *entry_point, bool is_fp, void *tls_area)
Initialize the context to a state suitable for starting a task after a context restore operation...
Definition: cpu.c:183
CPU_Counter_ticks _CPU_Counter_read(void)
Returns the current CPU counter value.
Definition: cpu.c:96
CPU_Counter_ticks _CPU_Counter_difference(CPU_Counter_ticks second, CPU_Counter_ticks first)
Returns the difference between the second and first CPU counter value.
Definition: cpu.h:1160
void _CPU_Fatal_halt(uint32_t source, uint32_t error)
This routine copies _error into a known place – typically a stack location or a register, optionally disables interrupts, and halts/stops the CPU.
Definition: nios2-fatal-halt.c:18
#define RTEMS_COMPILER_NO_RETURN_ATTRIBUTE
The following macro is a compiler specific way to indicate that the method will NOT return to the cal...
Definition: basedefs.h:162
void _CPU_Exception_frame_print(const CPU_Exception_frame *frame)
Prints the exception frame via printk().
Definition: arm-exception-frame-print.c:46
The set of registers that specifies the complete processor state.
Definition: cpu.h:671
void * proc_ptr
XXX: Eventually proc_ptr needs to disappear!!!
Definition: basedefs.h:329