RTEMS CPU Kit with SuperCore  4.11.2
cpu.h
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1 
7 /*
8  * Copyright (c) 2011 embedded brains GmbH
9  *
10  * Copyright (c) 2006 Kolja Waschk (rtemsdev/ixo.de)
11  *
12  * COPYRIGHT (c) 1989-2004.
13  * On-Line Applications Research Corporation (OAR).
14  *
15  * The license and distribution terms for this file may be
16  * found in the file LICENSE in this distribution or at
17  * http://www.rtems.org/license/LICENSE.
18  */
19 
20 #ifndef _RTEMS_SCORE_CPU_H
21 #define _RTEMS_SCORE_CPU_H
22 
23 #ifdef __cplusplus
24 extern "C" {
25 #endif
26 
27 #include <rtems/score/types.h>
28 #include <rtems/score/nios2.h>
29 
30 /*
31  * TODO: Run the timing tests and figure out what is better.
32  */
33 #define CPU_INLINE_ENABLE_DISPATCH FALSE
34 
35 #define CPU_HAS_SOFTWARE_INTERRUPT_STACK TRUE
36 
37 #define CPU_SIMPLE_VECTORED_INTERRUPTS TRUE
38 
39 #define CPU_INTERRUPT_NUMBER_OF_VECTORS 32
40 
41 #define CPU_INTERRUPT_MAXIMUM_VECTOR_NUMBER (CPU_INTERRUPT_NUMBER_OF_VECTORS - 1)
42 
43 #define CPU_PROVIDES_ISR_IS_IN_PROGRESS TRUE
44 
45 #define CPU_HAS_HARDWARE_INTERRUPT_STACK FALSE
46 
47 #define CPU_ALLOCATE_INTERRUPT_STACK TRUE
48 
49 #define CPU_ISR_PASSES_FRAME_POINTER FALSE
50 
51 #define CPU_HARDWARE_FP FALSE
52 
53 #define CPU_SOFTWARE_FP FALSE
54 
55 #define CPU_CONTEXT_FP_SIZE 0
56 
57 #define CPU_ALL_TASKS_ARE_FP FALSE
58 
59 #define CPU_IDLE_TASK_IS_FP FALSE
60 
61 #define CPU_USE_DEFERRED_FP_SWITCH FALSE
62 
63 #define CPU_PROVIDES_IDLE_THREAD_BODY FALSE
64 
65 #define CPU_STACK_GROWS_UP FALSE
66 
67 #define CPU_STRUCTURE_ALIGNMENT __attribute__((section(".sdata"), aligned(32)))
68 
69 #define CPU_TIMESTAMP_USE_INT64_INLINE TRUE
70 
71 #define CPU_BIG_ENDIAN FALSE
72 
73 #define CPU_LITTLE_ENDIAN TRUE
74 
75 #define CPU_STACK_MINIMUM_SIZE (4 * 1024)
76 
77 #define CPU_SIZEOF_POINTER 4
78 
79 /*
80  * Alignment value according to "Nios II Processor Reference" chapter 7
81  * "Application Binary Interface" section "Memory Alignment".
82  */
83 #define CPU_ALIGNMENT 4
84 
85 #define CPU_HEAP_ALIGNMENT CPU_ALIGNMENT
86 
87 #define CPU_PARTITION_ALIGNMENT CPU_ALIGNMENT
88 
89 /*
90  * Alignment value according to "Nios II Processor Reference" chapter 7
91  * "Application Binary Interface" section "Stacks".
92  */
93 #define CPU_STACK_ALIGNMENT 4
94 
95 /*
96  * A Nios II configuration with an external interrupt controller (EIC) supports
97  * up to 64 interrupt levels. A Nios II configuration with an internal
98  * interrupt controller (IIC) has only two interrupt levels (enabled and
99  * disabled). The _CPU_ISR_Get_level() and _CPU_ISR_Set_level() functions will
100  * take care about configuration specific mappings.
101  */
102 #define CPU_MODES_INTERRUPT_MASK 0x3f
103 
104 #define CPU_USE_GENERIC_BITFIELD_CODE TRUE
105 
106 #define CPU_USE_GENERIC_BITFIELD_DATA TRUE
107 
108 #define CPU_MPCI_RECEIVE_SERVER_EXTRA_STACK 0
109 
110 #define CPU_PER_CPU_CONTROL_SIZE 0
111 
112 #ifndef ASM
113 
128 typedef struct {
129  uint32_t r16;
130  uint32_t r17;
131  uint32_t r18;
132  uint32_t r19;
133  uint32_t r20;
134  uint32_t r21;
135  uint32_t r22;
136  uint32_t r23;
137  uint32_t fp;
138  uint32_t status;
139  uint32_t sp;
140  uint32_t ra;
141  uint32_t thread_dispatch_disabled;
142  uint32_t stack_mpubase;
143  uint32_t stack_mpuacc;
145 
146 #define _CPU_Context_Get_SP( _context ) \
147  (_context)->sp
148 
149 typedef void CPU_Interrupt_frame;
150 
151 typedef struct {
152  uint32_t r1;
153  uint32_t r2;
154  uint32_t r3;
155  uint32_t r4;
156  uint32_t r5;
157  uint32_t r6;
158  uint32_t r7;
159  uint32_t r8;
160  uint32_t r9;
161  uint32_t r10;
162  uint32_t r11;
163  uint32_t r12;
164  uint32_t r13;
165  uint32_t r14;
166  uint32_t r15;
167  uint32_t r16;
168  uint32_t r17;
169  uint32_t r18;
170  uint32_t r19;
171  uint32_t r20;
172  uint32_t r21;
173  uint32_t r22;
174  uint32_t r23;
175  uint32_t gp;
176  uint32_t fp;
177  uint32_t sp;
178  uint32_t ra;
179  uint32_t et;
180  uint32_t ea;
181  uint32_t status;
182  uint32_t ienable;
183  uint32_t ipending;
185 
186 #define _CPU_Initialize_vectors()
187 
208 #define _CPU_ISR_Disable( _isr_cookie ) \
209  do { \
210  int _tmp; \
211  __asm__ volatile ( \
212  "rdctl %0, status\n" \
213  "movhi %1, %%hiadj(_Nios2_ISR_Status_mask)\n" \
214  "addi %1, %1, %%lo(_Nios2_ISR_Status_mask)\n" \
215  "and %1, %0, %1\n" \
216  "ori %1, %1, %%lo(_Nios2_ISR_Status_bits)\n" \
217  "wrctl status, %1" \
218  : "=&r" (_isr_cookie), "=&r" (_tmp) \
219  ); \
220  } while ( 0 )
221 
228 #define _CPU_ISR_Enable( _isr_cookie ) \
229  __builtin_wrctl( 0, (int) _isr_cookie )
230 
242 #define _CPU_ISR_Flash( _isr_cookie ) \
243  do { \
244  int _status = __builtin_rdctl( 0 ); \
245  __builtin_wrctl( 0, (int) _isr_cookie ); \
246  __builtin_wrctl( 0, _status ); \
247  } while ( 0 )
248 
257 void _CPU_ISR_Set_level( uint32_t new_level );
258 
272 uint32_t _CPU_ISR_Get_level( void );
273 
292  Context_Control *context,
293  void *stack_area_begin,
294  size_t stack_area_size,
295  uint32_t new_level,
296  void (*entry_point)( void ),
297  bool is_fp,
298  void *tls_area
299 );
300 
301 #define _CPU_Context_Restart_self( _the_context ) \
302  _CPU_Context_restore( (_the_context) );
303 
304 void _CPU_Fatal_halt( uint32_t _source, uint32_t _error )
306 
310 void _CPU_Initialize( void );
311 
316  uint32_t vector,
317  proc_ptr new_handler,
318  proc_ptr *old_handler
319 );
320 
325  uint32_t vector,
326  proc_ptr new_handler,
327  proc_ptr *old_handler
328 );
329 
331 
333  Context_Control *new_context
335 
336 void _CPU_Context_volatile_clobber( uintptr_t pattern );
337 
338 void _CPU_Context_validate( uintptr_t pattern );
339 
341 
342 static inline uint32_t CPU_swap_u32( uint32_t value )
343 {
344  uint32_t byte1, byte2, byte3, byte4, swapped;
345 
346  byte4 = (value >> 24) & 0xff;
347  byte3 = (value >> 16) & 0xff;
348  byte2 = (value >> 8) & 0xff;
349  byte1 = value & 0xff;
350 
351  swapped = (byte1 << 24) | (byte2 << 16) | (byte3 << 8) | byte4;
352 
353  return swapped;
354 }
355 
356 #define CPU_swap_u16( value ) \
357  (((value&0xff) << 8) | ((value >> 8)&0xff))
358 
359 typedef uint32_t CPU_Counter_ticks;
360 
361 CPU_Counter_ticks _CPU_Counter_read( void );
362 
363 static inline CPU_Counter_ticks _CPU_Counter_difference(
364  CPU_Counter_ticks second,
365  CPU_Counter_ticks first
366 )
367 {
368  return second - first;
369 }
370 
371 #endif /* ASM */
372 
373 #ifdef __cplusplus
374 }
375 #endif
376 
377 #endif
void _CPU_ISR_install_vector(uint32_t vector, proc_ptr new_handler, proc_ptr *old_handler)
This routine installs an interrupt vector.
Definition: cpu.c:69
void _CPU_Context_validate(uintptr_t pattern)
Initializes and validates the CPU context with values derived from the pattern parameter.
Definition: cpu.h:1109
uint32_t _CPU_ISR_Get_level(void)
Return the current interrupt disable level for this task in the format used by the interrupt level po...
Definition: cpu.c:39
void _CPU_Context_restore(Context_Control *new_context)
This routine is generally used only to restart self in an efficient manner.
Definition: cpu_asm.c:112
void _CPU_Context_switch(Context_Control *run, Context_Control *heir)
CPU switch context.
Definition: cpu_asm.c:92
void _CPU_Context_volatile_clobber(uintptr_t pattern)
Clobbers all volatile registers with values derived from the pattern parameter.
Definition: cpu.h:1104
This defines the minimal set of integer and processor state registers that must be saved during a vol...
Definition: cpu.h:248
void _CPU_Initialize(void)
CPU initialization.
Definition: cpu.c:26
uint32_t CPU_Counter_ticks
Unsigned integer type for CPU counter values.
Definition: cpu.h:1461
void _CPU_ISR_install_raw_handler(uint32_t vector, proc_ptr new_handler, proc_ptr *old_handler)
This routine installs a "raw" interrupt handler directly into the processor&#39;s vector table...
Definition: cpu.c:57
void _CPU_ISR_Set_level(uint32_t level)
Sets the hardware interrupt level by the level value.
Definition: cpu.c:62
NIOS II Set up Basic CPU Dependency Settings Based on Compiler Settings.
void _CPU_Context_Initialize(Context_Control *the_context, uint32_t *stack_base, uint32_t size, uint32_t new_level, void *entry_point, bool is_fp, void *tls_area)
Initialize the context to a state suitable for starting a task after a context restore operation...
Definition: cpu.c:183
CPU_Counter_ticks _CPU_Counter_read(void)
Returns the current CPU counter value.
Definition: cpu.c:96
CPU_Counter_ticks _CPU_Counter_difference(CPU_Counter_ticks second, CPU_Counter_ticks first)
Returns the difference between the second and first CPU counter value.
Definition: cpu.h:1160
void _CPU_Fatal_halt(uint32_t source, uint32_t error)
This routine copies _error into a known place – typically a stack location or a register, optionally disables interrupts, and halts/stops the CPU.
Definition: nios2-fatal-halt.c:18
#define RTEMS_COMPILER_NO_RETURN_ATTRIBUTE
The following macro is a compiler specific way to indicate that the method will NOT return to the cal...
Definition: basedefs.h:162
void _CPU_Exception_frame_print(const CPU_Exception_frame *frame)
Prints the exception frame via printk().
Definition: arm-exception-frame-print.c:46
The set of registers that specifies the complete processor state.
Definition: cpu.h:671
void * proc_ptr
XXX: Eventually proc_ptr needs to disappear!!!
Definition: basedefs.h:329