RTEMS CPU Kit with SuperCore  4.11.2
cpu.h
Go to the documentation of this file.
1 
7 /*
8  * Conversion to MIPS port by Alan Cudmore <alanc@linuxstart.com> and
9  * Joel Sherrill <joel@OARcorp.com>.
10  *
11  * These changes made the code conditional on standard cpp predefines,
12  * merged the mips1 and mips3 code sequences as much as possible,
13  * and moved some of the assembly code to C. Alan did much of the
14  * initial analysis and rework. Joel took over from there and
15  * wrote the JMR3904 BSP so this could be tested. Joel also
16  * added the new interrupt vectoring support in libcpu and
17  * tried to better support the various interrupt controllers.
18  *
19  */
20 
21 /*
22  * Original MIP64ORION port by Craig Lebakken <craigl@transition.com>
23  * COPYRIGHT (c) 1996 by Transition Networks Inc.
24  *
25  * To anyone who acknowledges that this file is provided "AS IS"
26  * without any express or implied warranty:
27  * permission to use, copy, modify, and distribute this file
28  * for any purpose is hereby granted without fee, provided that
29  * the above copyright notice and this notice appears in all
30  * copies, and that the name of Transition Networks not be used in
31  * advertising or publicity pertaining to distribution of the
32  * software without specific, written prior permission.
33  * Transition Networks makes no representations about the suitability
34  * of this software for any purpose.
35  *
36  * COPYRIGHT (c) 1989-2012.
37  * On-Line Applications Research Corporation (OAR).
38  *
39  * The license and distribution terms for this file may be
40  * found in the file LICENSE in this distribution or at
41  * http://www.rtems.org/license/LICENSE.
42  */
43 
44 #ifndef _RTEMS_SCORE_CPU_H
45 #define _RTEMS_SCORE_CPU_H
46 
55 #ifdef __cplusplus
56 extern "C" {
57 #endif
58 
59 #include <rtems/score/types.h>
60 #include <rtems/score/mips.h>
61 
62 /* conditional compilation parameters */
63 
64 /*
65  * Should the calls to _Thread_Enable_dispatch be inlined?
66  *
67  * If TRUE, then they are inlined.
68  * If FALSE, then a subroutine call is made.
69  *
70  * Basically this is an example of the classic trade-off of size
71  * versus speed. Inlining the call (TRUE) typically increases the
72  * size of RTEMS while speeding up the enabling of dispatching.
73  * [NOTE: In general, the _Thread_Dispatch_disable_level will
74  * only be 0 or 1 unless you are in an interrupt handler and that
75  * interrupt handler invokes the executive.] When not inlined
76  * something calls _Thread_Enable_dispatch which in turns calls
77  * _Thread_Dispatch. If the enable dispatch is inlined, then
78  * one subroutine call is avoided entirely.]
79  */
80 
81 #define CPU_INLINE_ENABLE_DISPATCH FALSE
82 
83 /*
84  * Does RTEMS manage a dedicated interrupt stack in software?
85  *
86  * If TRUE, then a stack is allocated in _Interrupt_Manager_initialization.
87  * If FALSE, nothing is done.
88  *
89  * If the CPU supports a dedicated interrupt stack in hardware,
90  * then it is generally the responsibility of the BSP to allocate it
91  * and set it up.
92  *
93  * If the CPU does not support a dedicated interrupt stack, then
94  * the porter has two options: (1) execute interrupts on the
95  * stack of the interrupted task, and (2) have RTEMS manage a dedicated
96  * interrupt stack.
97  *
98  * If this is TRUE, CPU_ALLOCATE_INTERRUPT_STACK should also be TRUE.
99  *
100  * Only one of CPU_HAS_SOFTWARE_INTERRUPT_STACK and
101  * CPU_HAS_HARDWARE_INTERRUPT_STACK should be set to TRUE. It is
102  * possible that both are FALSE for a particular CPU. Although it
103  * is unclear what that would imply about the interrupt processing
104  * procedure on that CPU.
105  */
106 
107 #define CPU_HAS_SOFTWARE_INTERRUPT_STACK FALSE
108 
109 /*
110  * Does the CPU follow the simple vectored interrupt model?
111  *
112  * If TRUE, then RTEMS allocates the vector table it internally manages.
113  * If FALSE, then the BSP is assumed to allocate and manage the vector
114  * table
115  *
116  * MIPS Specific Information:
117  *
118  * Up to and including RTEMS 4.10, the MIPS port used simple vectored
119  * interrupts. But this was changed to the PIC model after 4.10.
120  */
121 #define CPU_SIMPLE_VECTORED_INTERRUPTS FALSE
122 
123 /*
124  * Does this CPU have hardware support for a dedicated interrupt stack?
125  *
126  * If TRUE, then it must be installed during initialization.
127  * If FALSE, then no installation is performed.
128  *
129  * If this is TRUE, CPU_ALLOCATE_INTERRUPT_STACK should also be TRUE.
130  *
131  * Only one of CPU_HAS_SOFTWARE_INTERRUPT_STACK and
132  * CPU_HAS_HARDWARE_INTERRUPT_STACK should be set to TRUE. It is
133  * possible that both are FALSE for a particular CPU. Although it
134  * is unclear what that would imply about the interrupt processing
135  * procedure on that CPU.
136  */
137 
138 #define CPU_HAS_HARDWARE_INTERRUPT_STACK FALSE
139 
140 /*
141  * Does RTEMS allocate a dedicated interrupt stack in the Interrupt Manager?
142  *
143  * If TRUE, then the memory is allocated during initialization.
144  * If FALSE, then the memory is allocated during initialization.
145  *
146  * This should be TRUE is CPU_HAS_SOFTWARE_INTERRUPT_STACK is TRUE.
147  */
148 
149 #define CPU_ALLOCATE_INTERRUPT_STACK FALSE
150 
151 /*
152  * Does the RTEMS invoke the user's ISR with the vector number and
153  * a pointer to the saved interrupt frame (1) or just the vector
154  * number (0)?
155  *
156  */
157 
158 #define CPU_ISR_PASSES_FRAME_POINTER 1
159 
160 
161 
162 /*
163  * Does the CPU have hardware floating point?
164  *
165  * If TRUE, then the RTEMS_FLOATING_POINT task attribute is supported.
166  * If FALSE, then the RTEMS_FLOATING_POINT task attribute is ignored.
167  *
168  * If there is a FP coprocessor such as the i387 or mc68881, then
169  * the answer is TRUE.
170  *
171  * The macro name "MIPS_HAS_FPU" should be made CPU specific.
172  * It indicates whether or not this CPU model has FP support. For
173  * example, it would be possible to have an i386_nofp CPU model
174  * which set this to false to indicate that you have an i386 without
175  * an i387 and wish to leave floating point support out of RTEMS.
176  */
177 
178 #if ( MIPS_HAS_FPU == 1 )
179 #define CPU_HARDWARE_FP TRUE
180 #else
181 #define CPU_HARDWARE_FP FALSE
182 #endif
183 
184 /*
185  * Are all tasks RTEMS_FLOATING_POINT tasks implicitly?
186  *
187  * If TRUE, then the RTEMS_FLOATING_POINT task attribute is assumed.
188  * If FALSE, then the RTEMS_FLOATING_POINT task attribute is followed.
189  *
190  * So far, the only CPU in which this option has been used is the
191  * HP PA-RISC. The HP C compiler and gcc both implicitly use the
192  * floating point registers to perform integer multiplies. If
193  * a function which you would not think utilize the FP unit DOES,
194  * then one can not easily predict which tasks will use the FP hardware.
195  * In this case, this option should be TRUE.
196  *
197  * If CPU_HARDWARE_FP is FALSE, then this should be FALSE as well.
198  *
199  * Mips Note: It appears the GCC can implicitly generate FPU
200  * and Altivec instructions when you least expect them. So make
201  * all tasks floating point.
202  */
203 
204 #define CPU_ALL_TASKS_ARE_FP CPU_HARDWARE_FP
205 
206 /*
207  * Should the IDLE task have a floating point context?
208  *
209  * If TRUE, then the IDLE task is created as a RTEMS_FLOATING_POINT task
210  * and it has a floating point context which is switched in and out.
211  * If FALSE, then the IDLE task does not have a floating point context.
212  *
213  * Setting this to TRUE negatively impacts the time required to preempt
214  * the IDLE task from an interrupt because the floating point context
215  * must be saved as part of the preemption.
216  */
217 
218 #define CPU_IDLE_TASK_IS_FP FALSE
219 
220 /*
221  * Should the saving of the floating point registers be deferred
222  * until a context switch is made to another different floating point
223  * task?
224  *
225  * If TRUE, then the floating point context will not be stored until
226  * necessary. It will remain in the floating point registers and not
227  * disturned until another floating point task is switched to.
228  *
229  * If FALSE, then the floating point context is saved when a floating
230  * point task is switched out and restored when the next floating point
231  * task is restored. The state of the floating point registers between
232  * those two operations is not specified.
233  *
234  * If the floating point context does NOT have to be saved as part of
235  * interrupt dispatching, then it should be safe to set this to TRUE.
236  *
237  * Setting this flag to TRUE results in using a different algorithm
238  * for deciding when to save and restore the floating point context.
239  * The deferred FP switch algorithm minimizes the number of times
240  * the FP context is saved and restored. The FP context is not saved
241  * until a context switch is made to another, different FP task.
242  * Thus in a system with only one FP task, the FP context will never
243  * be saved or restored.
244  */
245 
246 #define CPU_USE_DEFERRED_FP_SWITCH TRUE
247 
248 /*
249  * Does this port provide a CPU dependent IDLE task implementation?
250  *
251  * If TRUE, then the routine _CPU_Internal_threads_Idle_thread_body
252  * must be provided and is the default IDLE thread body instead of
253  * _Internal_threads_Idle_thread_body.
254  *
255  * If FALSE, then use the generic IDLE thread body if the BSP does
256  * not provide one.
257  *
258  * This is intended to allow for supporting processors which have
259  * a low power or idle mode. When the IDLE thread is executed, then
260  * the CPU can be powered down.
261  *
262  * The order of precedence for selecting the IDLE thread body is:
263  *
264  * 1. BSP provided
265  * 2. CPU dependent (if provided)
266  * 3. generic (if no BSP and no CPU dependent)
267  */
268 
269 /* we can use the low power wait instruction for the IDLE thread */
270 #define CPU_PROVIDES_IDLE_THREAD_BODY TRUE
271 
272 /*
273  * Does the stack grow up (toward higher addresses) or down
274  * (toward lower addresses)?
275  *
276  * If TRUE, then the grows upward.
277  * If FALSE, then the grows toward smaller addresses.
278  */
279 
280 /* our stack grows down */
281 #define CPU_STACK_GROWS_UP FALSE
282 
283 /*
284  * The following is the variable attribute used to force alignment
285  * of critical RTEMS structures. On some processors it may make
286  * sense to have these aligned on tighter boundaries than
287  * the minimum requirements of the compiler in order to have as
288  * much of the critical data area as possible in a cache line.
289  *
290  * The placement of this macro in the declaration of the variables
291  * is based on the syntactically requirements of the GNU C
292  * "__attribute__" extension. For example with GNU C, use
293  * the following to force a structures to a 32 byte boundary.
294  *
295  * __attribute__ ((aligned (32)))
296  *
297  * NOTE: Currently only the Priority Bit Map table uses this feature.
298  * To benefit from using this, the data must be heavily
299  * used so it will stay in the cache and used frequently enough
300  * in the executive to justify turning this on.
301  */
302 
303 /* our cache line size is 16 bytes */
304 #if __GNUC__
305 #define CPU_STRUCTURE_ALIGNMENT __attribute__ ((aligned (16)))
306 #else
307 #define CPU_STRUCTURE_ALIGNMENT
308 #endif
309 
310 #define CPU_TIMESTAMP_USE_INT64_INLINE TRUE
311 
312 /*
313  * Define what is required to specify how the network to host conversion
314  * routines are handled.
315  */
316 
317 /* __MIPSEB__ or __MIPSEL__ is defined by GCC based on -EB or -EL command line options */
318 #if defined(__MIPSEB__)
319 #define CPU_BIG_ENDIAN TRUE
320 #define CPU_LITTLE_ENDIAN FALSE
321 #elif defined(__MIPSEL__)
322 #define CPU_BIG_ENDIAN FALSE
323 #define CPU_LITTLE_ENDIAN TRUE
324 #else
325 #error "Unknown endianness"
326 #endif
327 
328 /*
329  * The following defines the number of bits actually used in the
330  * interrupt field of the task mode. How those bits map to the
331  * CPU interrupt levels is defined by the routine _CPU_ISR_Set_level().
332  */
333 
334 #define CPU_MODES_INTERRUPT_MASK 0x000000ff
335 
336 #define CPU_SIZEOF_POINTER 4
337 
338 #define CPU_PER_CPU_CONTROL_SIZE 0
339 
340 /*
341  * Processor defined structures
342  *
343  * Examples structures include the descriptor tables from the i386
344  * and the processor control structure on the i960ca.
345  */
346 
347 /* may need to put some structures here. */
348 
349 /*
350  * Contexts
351  *
352  * Generally there are 2 types of context to save.
353  * 1. Interrupt registers to save
354  * 2. Task level registers to save
355  *
356  * This means we have the following 3 context items:
357  * 1. task level context stuff:: Context_Control
358  * 2. floating point task stuff:: Context_Control_fp
359  * 3. special interrupt level context :: Context_Control_interrupt
360  *
361  * On some processors, it is cost-effective to save only the callee
362  * preserved registers during a task context switch. This means
363  * that the ISR code needs to save those registers which do not
364  * persist across function calls. It is not mandatory to make this
365  * distinctions between the caller/callee saves registers for the
366  * purpose of minimizing context saved during task switch and on interrupts.
367  * If the cost of saving extra registers is minimal, simplicity is the
368  * choice. Save the same context on interrupt entry as for tasks in
369  * this case.
370  *
371  * Additionally, if gdb is to be made aware of RTEMS tasks for this CPU, then
372  * care should be used in designing the context area.
373  *
374  * On some CPUs with hardware floating point support, the Context_Control_fp
375  * structure will not be used or it simply consist of an array of a
376  * fixed number of bytes. This is done when the floating point context
377  * is dumped by a "FP save context" type instruction and the format
378  * is not really defined by the CPU. In this case, there is no need
379  * to figure out the exact format -- only the size. Of course, although
380  * this is enough information for RTEMS, it is probably not enough for
381  * a debugger such as gdb. But that is another problem.
382  */
383 
384 #ifndef ASM
385 
386 /* WARNING: If this structure is modified, the constants in cpu.h must be updated. */
387 #if (__mips == 1) || (__mips == 32)
388 #define __MIPS_REGISTER_TYPE uint32_t
389 #define __MIPS_FPU_REGISTER_TYPE uint32_t
390 #elif __mips == 3
391 #define __MIPS_REGISTER_TYPE uint64_t
392 #define __MIPS_FPU_REGISTER_TYPE uint64_t
393 #else
394 #error "mips register size: unknown architecture level!!"
395 #endif
396 typedef struct {
397  __MIPS_REGISTER_TYPE s0;
398  __MIPS_REGISTER_TYPE s1;
399  __MIPS_REGISTER_TYPE s2;
400  __MIPS_REGISTER_TYPE s3;
401  __MIPS_REGISTER_TYPE s4;
402  __MIPS_REGISTER_TYPE s5;
403  __MIPS_REGISTER_TYPE s6;
404  __MIPS_REGISTER_TYPE s7;
405  __MIPS_REGISTER_TYPE sp;
406  __MIPS_REGISTER_TYPE fp;
407  __MIPS_REGISTER_TYPE ra;
408  __MIPS_REGISTER_TYPE c0_sr;
409  __MIPS_REGISTER_TYPE c0_epc;
411 
412 #define _CPU_Context_Get_SP( _context ) \
413  (uintptr_t) (_context)->sp
414 
415 /* WARNING: If this structure is modified, the constants in cpu.h
416  * must also be updated.
417  */
418 
419 typedef struct {
420 #if ( CPU_HARDWARE_FP == TRUE )
421  __MIPS_FPU_REGISTER_TYPE fp0;
422  __MIPS_FPU_REGISTER_TYPE fp1;
423  __MIPS_FPU_REGISTER_TYPE fp2;
424  __MIPS_FPU_REGISTER_TYPE fp3;
425  __MIPS_FPU_REGISTER_TYPE fp4;
426  __MIPS_FPU_REGISTER_TYPE fp5;
427  __MIPS_FPU_REGISTER_TYPE fp6;
428  __MIPS_FPU_REGISTER_TYPE fp7;
429  __MIPS_FPU_REGISTER_TYPE fp8;
430  __MIPS_FPU_REGISTER_TYPE fp9;
431  __MIPS_FPU_REGISTER_TYPE fp10;
432  __MIPS_FPU_REGISTER_TYPE fp11;
433  __MIPS_FPU_REGISTER_TYPE fp12;
434  __MIPS_FPU_REGISTER_TYPE fp13;
435  __MIPS_FPU_REGISTER_TYPE fp14;
436  __MIPS_FPU_REGISTER_TYPE fp15;
437  __MIPS_FPU_REGISTER_TYPE fp16;
438  __MIPS_FPU_REGISTER_TYPE fp17;
439  __MIPS_FPU_REGISTER_TYPE fp18;
440  __MIPS_FPU_REGISTER_TYPE fp19;
441  __MIPS_FPU_REGISTER_TYPE fp20;
442  __MIPS_FPU_REGISTER_TYPE fp21;
443  __MIPS_FPU_REGISTER_TYPE fp22;
444  __MIPS_FPU_REGISTER_TYPE fp23;
445  __MIPS_FPU_REGISTER_TYPE fp24;
446  __MIPS_FPU_REGISTER_TYPE fp25;
447  __MIPS_FPU_REGISTER_TYPE fp26;
448  __MIPS_FPU_REGISTER_TYPE fp27;
449  __MIPS_FPU_REGISTER_TYPE fp28;
450  __MIPS_FPU_REGISTER_TYPE fp29;
451  __MIPS_FPU_REGISTER_TYPE fp30;
452  __MIPS_FPU_REGISTER_TYPE fp31;
453  uint32_t fpcs;
454 #endif
456 
457 /*
458  * This struct reflects the stack frame employed in ISR_Handler. Note
459  * that the ISR routine save some of the registers to this frame for
460  * all interrupts and exceptions. Other registers are saved only on
461  * exceptions, while others are not touched at all. The untouched
462  * registers are not normally disturbed by high-level language
463  * programs so they can be accessed when required.
464  *
465  * The registers and their ordering in this struct must directly
466  * correspond to the layout and ordering of * shown in iregdef.h,
467  * as cpu_asm.S uses those definitions to fill the stack frame.
468  * This struct provides access to the stack frame for C code.
469  *
470  * Similarly, this structure is used by debugger stubs and exception
471  * processing routines so be careful when changing the format.
472  *
473  * NOTE: The comments with this structure and cpu_asm.S should be kept
474  * in sync. When in doubt, look in the code to see if the
475  * registers you're interested in are actually treated as expected.
476  * The order of the first portion of this structure follows the
477  * order of registers expected by gdb.
478  */
479 
480 typedef struct
481 {
482  __MIPS_REGISTER_TYPE r0; /* 0 -- NOT FILLED IN */
483  __MIPS_REGISTER_TYPE at; /* 1 -- saved always */
484  __MIPS_REGISTER_TYPE v0; /* 2 -- saved always */
485  __MIPS_REGISTER_TYPE v1; /* 3 -- saved always */
486  __MIPS_REGISTER_TYPE a0; /* 4 -- saved always */
487  __MIPS_REGISTER_TYPE a1; /* 5 -- saved always */
488  __MIPS_REGISTER_TYPE a2; /* 6 -- saved always */
489  __MIPS_REGISTER_TYPE a3; /* 7 -- saved always */
490  __MIPS_REGISTER_TYPE t0; /* 8 -- saved always */
491  __MIPS_REGISTER_TYPE t1; /* 9 -- saved always */
492  __MIPS_REGISTER_TYPE t2; /* 10 -- saved always */
493  __MIPS_REGISTER_TYPE t3; /* 11 -- saved always */
494  __MIPS_REGISTER_TYPE t4; /* 12 -- saved always */
495  __MIPS_REGISTER_TYPE t5; /* 13 -- saved always */
496  __MIPS_REGISTER_TYPE t6; /* 14 -- saved always */
497  __MIPS_REGISTER_TYPE t7; /* 15 -- saved always */
498  __MIPS_REGISTER_TYPE s0; /* 16 -- saved on exceptions */
499  __MIPS_REGISTER_TYPE s1; /* 17 -- saved on exceptions */
500  __MIPS_REGISTER_TYPE s2; /* 18 -- saved on exceptions */
501  __MIPS_REGISTER_TYPE s3; /* 19 -- saved on exceptions */
502  __MIPS_REGISTER_TYPE s4; /* 20 -- saved on exceptions */
503  __MIPS_REGISTER_TYPE s5; /* 21 -- saved on exceptions */
504  __MIPS_REGISTER_TYPE s6; /* 22 -- saved on exceptions */
505  __MIPS_REGISTER_TYPE s7; /* 23 -- saved on exceptions */
506  __MIPS_REGISTER_TYPE t8; /* 24 -- saved always */
507  __MIPS_REGISTER_TYPE t9; /* 25 -- saved always */
508  __MIPS_REGISTER_TYPE k0; /* 26 -- NOT FILLED IN, kernel tmp reg */
509  __MIPS_REGISTER_TYPE k1; /* 27 -- NOT FILLED IN, kernel tmp reg */
510  __MIPS_REGISTER_TYPE gp; /* 28 -- saved always */
511  __MIPS_REGISTER_TYPE sp; /* 29 -- saved on exceptions NOT RESTORED */
512  __MIPS_REGISTER_TYPE fp; /* 30 -- saved always */
513  __MIPS_REGISTER_TYPE ra; /* 31 -- saved always */
514  __MIPS_REGISTER_TYPE c0_sr; /* 32 -- saved always, some bits are */
515  /* manipulated per-thread */
516  __MIPS_REGISTER_TYPE mdlo; /* 33 -- saved always */
517  __MIPS_REGISTER_TYPE mdhi; /* 34 -- saved always */
518  __MIPS_REGISTER_TYPE badvaddr; /* 35 -- saved on exceptions, read-only */
519  __MIPS_REGISTER_TYPE cause; /* 36 -- saved on exceptions NOT restored */
520  __MIPS_REGISTER_TYPE epc; /* 37 -- saved always, read-only register */
521  /* but logically restored */
522  __MIPS_FPU_REGISTER_TYPE f0; /* 38 -- saved if FP enabled */
523  __MIPS_FPU_REGISTER_TYPE f1; /* 39 -- saved if FP enabled */
524  __MIPS_FPU_REGISTER_TYPE f2; /* 40 -- saved if FP enabled */
525  __MIPS_FPU_REGISTER_TYPE f3; /* 41 -- saved if FP enabled */
526  __MIPS_FPU_REGISTER_TYPE f4; /* 42 -- saved if FP enabled */
527  __MIPS_FPU_REGISTER_TYPE f5; /* 43 -- saved if FP enabled */
528  __MIPS_FPU_REGISTER_TYPE f6; /* 44 -- saved if FP enabled */
529  __MIPS_FPU_REGISTER_TYPE f7; /* 45 -- saved if FP enabled */
530  __MIPS_FPU_REGISTER_TYPE f8; /* 46 -- saved if FP enabled */
531  __MIPS_FPU_REGISTER_TYPE f9; /* 47 -- saved if FP enabled */
532  __MIPS_FPU_REGISTER_TYPE f10; /* 48 -- saved if FP enabled */
533  __MIPS_FPU_REGISTER_TYPE f11; /* 49 -- saved if FP enabled */
534  __MIPS_FPU_REGISTER_TYPE f12; /* 50 -- saved if FP enabled */
535  __MIPS_FPU_REGISTER_TYPE f13; /* 51 -- saved if FP enabled */
536  __MIPS_FPU_REGISTER_TYPE f14; /* 52 -- saved if FP enabled */
537  __MIPS_FPU_REGISTER_TYPE f15; /* 53 -- saved if FP enabled */
538  __MIPS_FPU_REGISTER_TYPE f16; /* 54 -- saved if FP enabled */
539  __MIPS_FPU_REGISTER_TYPE f17; /* 55 -- saved if FP enabled */
540  __MIPS_FPU_REGISTER_TYPE f18; /* 56 -- saved if FP enabled */
541  __MIPS_FPU_REGISTER_TYPE f19; /* 57 -- saved if FP enabled */
542  __MIPS_FPU_REGISTER_TYPE f20; /* 58 -- saved if FP enabled */
543  __MIPS_FPU_REGISTER_TYPE f21; /* 59 -- saved if FP enabled */
544  __MIPS_FPU_REGISTER_TYPE f22; /* 60 -- saved if FP enabled */
545  __MIPS_FPU_REGISTER_TYPE f23; /* 61 -- saved if FP enabled */
546  __MIPS_FPU_REGISTER_TYPE f24; /* 62 -- saved if FP enabled */
547  __MIPS_FPU_REGISTER_TYPE f25; /* 63 -- saved if FP enabled */
548  __MIPS_FPU_REGISTER_TYPE f26; /* 64 -- saved if FP enabled */
549  __MIPS_FPU_REGISTER_TYPE f27; /* 65 -- saved if FP enabled */
550  __MIPS_FPU_REGISTER_TYPE f28; /* 66 -- saved if FP enabled */
551  __MIPS_FPU_REGISTER_TYPE f29; /* 67 -- saved if FP enabled */
552  __MIPS_FPU_REGISTER_TYPE f30; /* 68 -- saved if FP enabled */
553  __MIPS_FPU_REGISTER_TYPE f31; /* 69 -- saved if FP enabled */
554  __MIPS_REGISTER_TYPE fcsr; /* 70 -- saved on exceptions */
555  /* (oddly not documented on MGV) */
556  __MIPS_REGISTER_TYPE feir; /* 71 -- saved on exceptions */
557  /* (oddly not documented on MGV) */
558 
559  /* GDB does not seem to care about anything past this point */
560 
561  __MIPS_REGISTER_TYPE tlbhi; /* 72 - NOT FILLED IN, doesn't exist on */
562  /* all MIPS CPUs (at least MGV) */
563 #if __mips == 1
564  __MIPS_REGISTER_TYPE tlblo; /* 73 - NOT FILLED IN, doesn't exist on */
565  /* all MIPS CPUs (at least MGV) */
566 #endif
567 #if (__mips == 3) || (__mips == 32)
568  __MIPS_REGISTER_TYPE tlblo0; /* 73 - NOT FILLED IN, doesn't exist on */
569  /* all MIPS CPUs (at least MGV) */
570 #endif
571 
572  __MIPS_REGISTER_TYPE inx; /* 74 -- NOT FILLED IN, doesn't exist on */
573  /* all MIPS CPUs (at least MGV) */
574  __MIPS_REGISTER_TYPE rand; /* 75 -- NOT FILLED IN, doesn't exist on */
575  /* all MIPS CPUs (at least MGV) */
576  __MIPS_REGISTER_TYPE ctxt; /* 76 -- NOT FILLED IN, doesn't exist on */
577  /* all MIPS CPUs (at least MGV) */
578  __MIPS_REGISTER_TYPE exctype; /* 77 -- NOT FILLED IN (not enough info) */
579  __MIPS_REGISTER_TYPE mode; /* 78 -- NOT FILLED IN (not enough info) */
580  __MIPS_REGISTER_TYPE prid; /* 79 -- NOT FILLED IN (not need to do so) */
581  __MIPS_REGISTER_TYPE tar ; /* 80 -- target address register, filled on exceptions */
582  /* end of __mips == 1 so NREGS == 81 */
583 #if (__mips == 3) || (__mips == 32)
584  __MIPS_REGISTER_TYPE tlblo1; /* 81 -- NOT FILLED IN */
585  __MIPS_REGISTER_TYPE pagemask; /* 82 -- NOT FILLED IN */
586  __MIPS_REGISTER_TYPE wired; /* 83 -- NOT FILLED IN */
587  __MIPS_REGISTER_TYPE count; /* 84 -- NOT FILLED IN */
588  __MIPS_REGISTER_TYPE compare; /* 85 -- NOT FILLED IN */
589  __MIPS_REGISTER_TYPE config; /* 86 -- NOT FILLED IN */
590  __MIPS_REGISTER_TYPE lladdr; /* 87 -- NOT FILLED IN */
591  __MIPS_REGISTER_TYPE watchlo; /* 88 -- NOT FILLED IN */
592  __MIPS_REGISTER_TYPE watchhi; /* 89 -- NOT FILLED IN */
593  __MIPS_REGISTER_TYPE ecc; /* 90 -- NOT FILLED IN */
594  __MIPS_REGISTER_TYPE cacheerr; /* 91 -- NOT FILLED IN */
595  __MIPS_REGISTER_TYPE taglo; /* 92 -- NOT FILLED IN */
596  __MIPS_REGISTER_TYPE taghi; /* 93 -- NOT FILLED IN */
597  __MIPS_REGISTER_TYPE errpc; /* 94 -- NOT FILLED IN */
598  __MIPS_REGISTER_TYPE xctxt; /* 95 -- NOT FILLED IN */
599  /* end of __mips == 3 so NREGS == 96 */
600 #endif
601 
603 
605 
606 /*
607  * This variable is optional. It is used on CPUs on which it is difficult
608  * to generate an "uninitialized" FP context. It is filled in by
609  * _CPU_Initialize and copied into the task's FP context area during
610  * _CPU_Context_Initialize.
611  */
612 
614 
615 /*
616  * Nothing prevents the porter from declaring more CPU specific variables.
617  */
618 
619 /* XXX: if needed, put more variables here */
620 
621 /*
622  * The size of the floating point context area. On some CPUs this
623  * will not be a "sizeof" because the format of the floating point
624  * area is not defined -- only the size is. This is usually on
625  * CPUs with a "floating point save context" instruction.
626  */
627 
628 #define CPU_CONTEXT_FP_SIZE sizeof( Context_Control_fp )
629 
630 /*
631  * Amount of extra stack (above minimum stack size) required by
632  * system initialization thread. Remember that in a multiprocessor
633  * system the system intialization thread becomes the MP server thread.
634  */
635 
636 #define CPU_MPCI_RECEIVE_SERVER_EXTRA_STACK 0
637 
638 /*
639  * Should be large enough to run all RTEMS tests. This ensures
640  * that a "reasonable" small application should not have any problems.
641  */
642 
643 #define CPU_STACK_MINIMUM_SIZE (8 * 1024)
644 
645 /*
646  * CPU's worst alignment requirement for data types on a byte boundary. This
647  * alignment does not take into account the requirements for the stack.
648  */
649 
650 #define CPU_ALIGNMENT 8
651 
652 /*
653  * This number corresponds to the byte alignment requirement for the
654  * heap handler. This alignment requirement may be stricter than that
655  * for the data types alignment specified by CPU_ALIGNMENT. It is
656  * common for the heap to follow the same alignment requirement as
657  * CPU_ALIGNMENT. If the CPU_ALIGNMENT is strict enough for the heap,
658  * then this should be set to CPU_ALIGNMENT.
659  *
660  * NOTE: This does not have to be a power of 2. It does have to
661  * be greater or equal to than CPU_ALIGNMENT.
662  */
663 
664 #define CPU_HEAP_ALIGNMENT CPU_ALIGNMENT
665 
666 /*
667  * This number corresponds to the byte alignment requirement for memory
668  * buffers allocated by the partition manager. This alignment requirement
669  * may be stricter than that for the data types alignment specified by
670  * CPU_ALIGNMENT. It is common for the partition to follow the same
671  * alignment requirement as CPU_ALIGNMENT. If the CPU_ALIGNMENT is strict
672  * enough for the partition, then this should be set to CPU_ALIGNMENT.
673  *
674  * NOTE: This does not have to be a power of 2. It does have to
675  * be greater or equal to than CPU_ALIGNMENT.
676  */
677 
678 #define CPU_PARTITION_ALIGNMENT CPU_ALIGNMENT
679 
680 /*
681  * This number corresponds to the byte alignment requirement for the
682  * stack. This alignment requirement may be stricter than that for the
683  * data types alignment specified by CPU_ALIGNMENT. If the CPU_ALIGNMENT
684  * is strict enough for the stack, then this should be set to 0.
685  *
686  * NOTE: This must be a power of 2 either 0 or greater than CPU_ALIGNMENT.
687  */
688 
689 #define CPU_STACK_ALIGNMENT CPU_ALIGNMENT
690 
691 void mips_vector_exceptions( CPU_Interrupt_frame *frame );
692 
693 /*
694  * ISR handler macros
695  */
696 
697 /*
698  * Declare the function that is present in the shared libcpu directory,
699  * that returns the processor dependent interrupt mask.
700  */
701 
702 uint32_t mips_interrupt_mask( void );
703 
704 /*
705  * Disable all interrupts for an RTEMS critical section. The previous
706  * level is returned in _level.
707  */
708 
709 #define _CPU_ISR_Disable( _level ) \
710  do { \
711  unsigned int _scratch; \
712  mips_get_sr( _scratch ); \
713  mips_set_sr( _scratch & ~SR_INTERRUPT_ENABLE_BITS ); \
714  _level = _scratch & SR_INTERRUPT_ENABLE_BITS; \
715  } while(0)
716 
717 /*
718  * Enable interrupts to the previous level (returned by _CPU_ISR_Disable).
719  * This indicates the end of an RTEMS critical section. The parameter
720  * _level is not modified.
721  */
722 
723 #define _CPU_ISR_Enable( _level ) \
724  do { \
725  unsigned int _scratch; \
726  mips_get_sr( _scratch ); \
727  mips_set_sr( (_scratch & ~SR_INTERRUPT_ENABLE_BITS) | (_level & SR_INTERRUPT_ENABLE_BITS) ); \
728  } while(0)
729 
730 /*
731  * This temporarily restores the interrupt to _level before immediately
732  * disabling them again. This is used to divide long RTEMS critical
733  * sections into two or more parts. The parameter _level is not
734  * modified.
735  */
736 
737 #define _CPU_ISR_Flash( _xlevel ) \
738  do { \
739  unsigned int _scratch2 = _xlevel; \
740  _CPU_ISR_Enable( _scratch2 ); \
741  _CPU_ISR_Disable( _scratch2 ); \
742  _xlevel = _scratch2; \
743  } while(0)
744 
745 /*
746  * Map interrupt level in task mode onto the hardware that the CPU
747  * actually provides. Currently, interrupt levels which do not
748  * map onto the CPU in a generic fashion are undefined. Someday,
749  * it would be nice if these were "mapped" by the application
750  * via a callout. For example, m68k has 8 levels 0 - 7, levels
751  * 8 - 255 would be available for bsp/application specific meaning.
752  * This could be used to manage a programmable interrupt controller
753  * via the rtems_task_mode directive.
754  *
755  * On the MIPS, 0 is all on. Non-zero is all off. This only
756  * manipulates the IEC.
757  */
758 
759 uint32_t _CPU_ISR_Get_level( void ); /* in cpu.c */
760 
761 void _CPU_ISR_Set_level( uint32_t ); /* in cpu.c */
762 
763 /* end of ISR handler macros */
764 
765 /* Context handler macros */
766 
767 /*
768  * Initialize the context to a state suitable for starting a
769  * task after a context restore operation. Generally, this
770  * involves:
771  *
772  * - setting a starting address
773  * - preparing the stack
774  * - preparing the stack and frame pointers
775  * - setting the proper interrupt level in the context
776  * - initializing the floating point context
777  *
778  * This routine generally does not set any unnecessary register
779  * in the context. The state of the "general data" registers is
780  * undefined at task start time.
781  *
782  * NOTE: This is_fp parameter is TRUE if the thread is to be a floating
783  * point thread. This is typically only used on CPUs where the
784  * FPU may be easily disabled by software such as on the SPARC
785  * where the PSR contains an enable FPU bit.
786  *
787  * The per-thread status register holds the interrupt enable, FP enable
788  * and global interrupt enable for that thread. It means each thread can
789  * enable its own set of interrupts. If interrupts are disabled, RTEMS
790  * can still dispatch via blocking calls. This is the function of the
791  * "Interrupt Level", and on the MIPS, it controls the IEC bit and all
792  * the hardware interrupts as defined in the SR. Software ints
793  * are automatically enabled for all threads, as they will only occur under
794  * program control anyhow. Besides, the interrupt level parm is only 8 bits,
795  * and controlling the software ints plus the others would require 9.
796  *
797  * If the Interrupt Level is 0, all ints are on. Otherwise, the
798  * Interrupt Level should supply a bit pattern to impose on the SR
799  * interrupt bits; bit 0 applies to the mips1 IEC bit/mips3 EXL&IE, bits 1 thru 6
800  * apply to the SR register Intr bits from bit 10 thru bit 15. Bit 7 of
801  * the Interrupt Level parameter is unused at this time.
802  *
803  * These are the only per-thread SR bits, the others are maintained
804  * globally & explicitly preserved by the Context Switch code in cpu_asm.s
805  */
806 
807 
808 #if (__mips == 3) || (__mips == 32)
809 #define _INTON SR_IE
810 #if __mips_fpr==64
811 #define _EXTRABITS SR_FR
812 #else
813 #define _EXTRABITS 0
814 #endif /* __mips_fpr==64 */
815 #endif /* __mips == 3 */
816 #if __mips == 1
817 #define _INTON SR_IEC
818 #define _EXTRABITS 0 /* make sure we're in user mode on MIPS1 processors */
819 #endif /* __mips == 1 */
820 
821 
823  Context_Control *the_context,
824  uintptr_t *stack_base,
825  uint32_t size,
826  uint32_t new_level,
827  void *entry_point,
828  bool is_fp,
829  void *tls_area
830 );
831 
832 
833 /*
834  * This routine is responsible for somehow restarting the currently
835  * executing task. If you are lucky, then all that is necessary
836  * is restoring the context. Otherwise, there will need to be
837  * a special assembly routine which does something special in this
838  * case. Context_Restore should work most of the time. It will
839  * not work if restarting self conflicts with the stack frame
840  * assumptions of restoring a context.
841  */
842 
843 #define _CPU_Context_Restart_self( _the_context ) \
844  _CPU_Context_restore( (_the_context) );
845 
846 /*
847  * The purpose of this macro is to allow the initial pointer into
848  * A floating point context area (used to save the floating point
849  * context) to be at an arbitrary place in the floating point
850  * context area.
851  *
852  * This is necessary because some FP units are designed to have
853  * their context saved as a stack which grows into lower addresses.
854  * Other FP units can be saved by simply moving registers into offsets
855  * from the base of the context area. Finally some FP units provide
856  * a "dump context" instruction which could fill in from high to low
857  * or low to high based on the whim of the CPU designers.
858  */
859 
860 #define _CPU_Context_Fp_start( _base, _offset ) \
861  ( (void *) _Addresses_Add_offset( (_base), (_offset) ) )
862 
863 /*
864  * This routine initializes the FP context area passed to it to.
865  * There are a few standard ways in which to initialize the
866  * floating point context. The code included for this macro assumes
867  * that this is a CPU in which a "initial" FP context was saved into
868  * _CPU_Null_fp_context and it simply copies it to the destination
869  * context passed to it.
870  *
871  * Other models include (1) not doing anything, and (2) putting
872  * a "null FP status word" in the correct place in the FP context.
873  */
874 
875 #if ( CPU_HARDWARE_FP == TRUE )
876 #define _CPU_Context_Initialize_fp( _destination ) \
877  { \
878  *(*(_destination)) = _CPU_Null_fp_context; \
879  }
880 #endif
881 
882 /* end of Context handler macros */
883 
884 /* Fatal Error manager macros */
885 
886 /*
887  * This routine copies _error into a known place -- typically a stack
888  * location or a register, optionally disables interrupts, and
889  * halts/stops the CPU.
890  */
891 
892 #define _CPU_Fatal_halt( _source, _error ) \
893  do { \
894  unsigned int _level; \
895  _CPU_ISR_Disable(_level); \
896  (void)_level; \
897  loop: goto loop; \
898  } while (0)
899 
900 
901 extern void mips_break( int error );
902 
903 /* Bitfield handler macros */
904 
905 /*
906  * This routine sets _output to the bit number of the first bit
907  * set in _value. _value is of CPU dependent type Priority_bit_map_Word.
908  * This type may be either 16 or 32 bits wide although only the 16
909  * least significant bits will be used.
910  *
911  * There are a number of variables in using a "find first bit" type
912  * instruction.
913  *
914  * (1) What happens when run on a value of zero?
915  * (2) Bits may be numbered from MSB to LSB or vice-versa.
916  * (3) The numbering may be zero or one based.
917  * (4) The "find first bit" instruction may search from MSB or LSB.
918  *
919  * RTEMS guarantees that (1) will never happen so it is not a concern.
920  * (2),(3), (4) are handled by the macros _CPU_Priority_mask() and
921  * _CPU_Priority_bits_index(). These three form a set of routines
922  * which must logically operate together. Bits in the _value are
923  * set and cleared based on masks built by _CPU_Priority_mask().
924  * The basic major and minor values calculated by _Priority_Major()
925  * and _Priority_Minor() are "massaged" by _CPU_Priority_bits_index()
926  * to properly range between the values returned by the "find first bit"
927  * instruction. This makes it possible for _Priority_Get_highest() to
928  * calculate the major and directly index into the minor table.
929  * This mapping is necessary to ensure that 0 (a high priority major/minor)
930  * is the first bit found.
931  *
932  * This entire "find first bit" and mapping process depends heavily
933  * on the manner in which a priority is broken into a major and minor
934  * components with the major being the 4 MSB of a priority and minor
935  * the 4 LSB. Thus (0 << 4) + 0 corresponds to priority 0 -- the highest
936  * priority. And (15 << 4) + 14 corresponds to priority 254 -- the next
937  * to the lowest priority.
938  *
939  * If your CPU does not have a "find first bit" instruction, then
940  * there are ways to make do without it. Here are a handful of ways
941  * to implement this in software:
942  *
943  * - a series of 16 bit test instructions
944  * - a "binary search using if's"
945  * - _number = 0
946  * if _value > 0x00ff
947  * _value >>=8
948  * _number = 8;
949  *
950  * if _value > 0x0000f
951  * _value >=8
952  * _number += 4
953  *
954  * _number += bit_set_table[ _value ]
955  *
956  * where bit_set_table[ 16 ] has values which indicate the first
957  * bit set
958  */
959 
960 #define CPU_USE_GENERIC_BITFIELD_CODE TRUE
961 #define CPU_USE_GENERIC_BITFIELD_DATA TRUE
962 
963 #if (CPU_USE_GENERIC_BITFIELD_CODE == FALSE)
964 
965 #define _CPU_Bitfield_Find_first_bit( _value, _output ) \
966  { \
967  (_output) = 0; /* do something to prevent warnings */ \
968  }
969 
970 #endif
971 
972 /* end of Bitfield handler macros */
973 
974 /*
975  * This routine builds the mask which corresponds to the bit fields
976  * as searched by _CPU_Bitfield_Find_first_bit(). See the discussion
977  * for that routine.
978  */
979 
980 #if (CPU_USE_GENERIC_BITFIELD_CODE == FALSE)
981 
982 #define _CPU_Priority_Mask( _bit_number ) \
983  ( 1 << (_bit_number) )
984 
985 #endif
986 
987 /*
988  * This routine translates the bit numbers returned by
989  * _CPU_Bitfield_Find_first_bit() into something suitable for use as
990  * a major or minor component of a priority. See the discussion
991  * for that routine.
992  */
993 
994 #if (CPU_USE_GENERIC_BITFIELD_CODE == FALSE)
995 
996 #define _CPU_Priority_bits_index( _priority ) \
997  (_priority)
998 
999 #endif
1000 
1001 /* end of Priority handler macros */
1002 
1003 /* functions */
1004 
1005 /*
1006  * _CPU_Initialize
1007  *
1008  * This routine performs CPU dependent initialization.
1009  */
1010 
1011 void _CPU_Initialize(void);
1012 
1013 /*
1014  * _CPU_ISR_install_raw_handler
1015  *
1016  * This routine installs a "raw" interrupt handler directly into the
1017  * processor's vector table.
1018  */
1019 
1021  uint32_t vector,
1022  proc_ptr new_handler,
1023  proc_ptr *old_handler
1024 );
1025 
1026 /*
1027  * _CPU_ISR_install_vector
1028  *
1029  * This routine installs an interrupt vector.
1030  */
1031 
1033  uint32_t vector,
1034  proc_ptr new_handler,
1035  proc_ptr *old_handler
1036 );
1037 
1038 /*
1039  * _CPU_Install_interrupt_stack
1040  *
1041  * This routine installs the hardware interrupt stack pointer.
1042  *
1043  * NOTE: It need only be provided if CPU_HAS_HARDWARE_INTERRUPT_STACK
1044  * is TRUE.
1045  */
1046 
1047 void _CPU_Install_interrupt_stack( void );
1048 
1049 /*
1050  * _CPU_Internal_threads_Idle_thread_body
1051  *
1052  * This routine is the CPU dependent IDLE thread body.
1053  *
1054  * NOTE: It need only be provided if CPU_PROVIDES_IDLE_THREAD_BODY
1055  * is TRUE.
1056  */
1057 
1058 void *_CPU_Thread_Idle_body( uintptr_t ignored );
1059 
1060 /*
1061  * _CPU_Context_switch
1062  *
1063  * This routine switches from the run context to the heir context.
1064  */
1065 
1066 void _CPU_Context_switch(
1067  Context_Control *run,
1068  Context_Control *heir
1069 );
1070 
1071 /*
1072  * _CPU_Context_restore
1073  *
1074  * This routine is generally used only to restart self in an
1075  * efficient manner. It may simply be a label in _CPU_Context_switch.
1076  *
1077  * NOTE: May be unnecessary to reload some registers.
1078  */
1079 
1081  Context_Control *new_context
1083 
1084 /*
1085  * _CPU_Context_save_fp
1086  *
1087  * This routine saves the floating point context passed to it.
1088  */
1089 
1091  Context_Control_fp **fp_context_ptr
1092 );
1093 
1094 /*
1095  * _CPU_Context_restore_fp
1096  *
1097  * This routine restores the floating point context passed to it.
1098  */
1099 
1101  Context_Control_fp **fp_context_ptr
1102 );
1103 
1104 static inline void _CPU_Context_volatile_clobber( uintptr_t pattern )
1105 {
1106  /* TODO */
1107 }
1108 
1109 static inline void _CPU_Context_validate( uintptr_t pattern )
1110 {
1111  while (1) {
1112  /* TODO */
1113  }
1114 }
1115 
1116 void _CPU_Exception_frame_print( const CPU_Exception_frame *frame );
1117 
1118 /* The following routine swaps the endian format of an unsigned int.
1119  * It must be static because it is referenced indirectly.
1120  *
1121  * This version will work on any processor, but if there is a better
1122  * way for your CPU PLEASE use it. The most common way to do this is to:
1123  *
1124  * swap least significant two bytes with 16-bit rotate
1125  * swap upper and lower 16-bits
1126  * swap most significant two bytes with 16-bit rotate
1127  *
1128  * Some CPUs have special instructions which swap a 32-bit quantity in
1129  * a single instruction (e.g. i486). It is probably best to avoid
1130  * an "endian swapping control bit" in the CPU. One good reason is
1131  * that interrupts would probably have to be disabled to ensure that
1132  * an interrupt does not try to access the same "chunk" with the wrong
1133  * endian. Another good reason is that on some CPUs, the endian bit
1134  * endianness for ALL fetches -- both code and data -- so the code
1135  * will be fetched incorrectly.
1136  */
1137 
1138 static inline uint32_t CPU_swap_u32(
1139  uint32_t value
1140 )
1141 {
1142  uint32_t byte1, byte2, byte3, byte4, swapped;
1143 
1144  byte4 = (value >> 24) & 0xff;
1145  byte3 = (value >> 16) & 0xff;
1146  byte2 = (value >> 8) & 0xff;
1147  byte1 = value & 0xff;
1148 
1149  swapped = (byte1 << 24) | (byte2 << 16) | (byte3 << 8) | byte4;
1150  return( swapped );
1151 }
1152 
1153 #define CPU_swap_u16( value ) \
1154  (((value&0xff) << 8) | ((value >> 8)&0xff))
1155 
1156 typedef uint32_t CPU_Counter_ticks;
1157 
1158 CPU_Counter_ticks _CPU_Counter_read( void );
1159 
1160 static inline CPU_Counter_ticks _CPU_Counter_difference(
1161  CPU_Counter_ticks second,
1162  CPU_Counter_ticks first
1163 )
1164 {
1165  return second - first;
1166 }
1167 
1168 #endif
1169 
1170 
1171 
1172 #ifdef __cplusplus
1173 }
1174 #endif
1175 
1177 #endif
void _CPU_ISR_install_vector(uint32_t vector, proc_ptr new_handler, proc_ptr *old_handler)
This routine installs an interrupt vector.
Definition: cpu.c:69
void _CPU_Context_validate(uintptr_t pattern)
Initializes and validates the CPU context with values derived from the pattern parameter.
Definition: cpu.h:1109
uint32_t _CPU_ISR_Get_level(void)
Return the current interrupt disable level for this task in the format used by the interrupt level po...
Definition: cpu.c:39
void _CPU_Context_restore(Context_Control *new_context)
This routine is generally used only to restart self in an efficient manner.
Definition: cpu_asm.c:112
Definition: deflate.c:116
void _CPU_Context_switch(Context_Control *run, Context_Control *heir)
CPU switch context.
Definition: cpu_asm.c:92
void _CPU_Context_volatile_clobber(uintptr_t pattern)
Clobbers all volatile registers with values derived from the pattern parameter.
Definition: cpu.h:1104
This defines the minimal set of integer and processor state registers that must be saved during a vol...
Definition: cpu.h:248
void _CPU_Initialize(void)
CPU initialization.
Definition: cpu.c:26
void _CPU_Install_interrupt_stack(void)
This routine installs the hardware interrupt stack pointer.
Definition: cpu.c:101
SCORE_EXTERN Context_Control_fp _CPU_Null_fp_context
This variable is optional.
Definition: cpu.h:494
uint32_t CPU_Counter_ticks
Unsigned integer type for CPU counter values.
Definition: cpu.h:1461
This defines the set of integer and processor state registers that must be saved during an interrupt...
Definition: cpu.h:425
void _CPU_ISR_install_raw_handler(uint32_t vector, proc_ptr new_handler, proc_ptr *old_handler)
This routine installs a "raw" interrupt handler directly into the processor&#39;s vector table...
Definition: cpu.c:57
void _CPU_ISR_Set_level(uint32_t level)
Sets the hardware interrupt level by the level value.
Definition: cpu.c:62
void _CPU_Context_restore_fp(Context_Control_fp **fp_context_ptr)
This routine restores the floating point context passed to it.
Definition: cpu.c:176
void _CPU_Context_Initialize(Context_Control *the_context, uint32_t *stack_base, uint32_t size, uint32_t new_level, void *entry_point, bool is_fp, void *tls_area)
Initialize the context to a state suitable for starting a task after a context restore operation...
Definition: cpu.c:183
CPU_Counter_ticks _CPU_Counter_read(void)
Returns the current CPU counter value.
Definition: cpu.c:96
CPU_Counter_ticks _CPU_Counter_difference(CPU_Counter_ticks second, CPU_Counter_ticks first)
Returns the difference between the second and first CPU counter value.
Definition: cpu.h:1160
This defines the complete set of floating point registers that must be saved during any context switc...
Definition: cpu.h:294
void _CPU_Context_save_fp(Context_Control_fp **fp_context_ptr)
This routine saves the floating point context passed to it.
Definition: cpu.c:167
#define RTEMS_COMPILER_NO_RETURN_ATTRIBUTE
The following macro is a compiler specific way to indicate that the method will NOT return to the cal...
Definition: basedefs.h:162
void _CPU_Exception_frame_print(const CPU_Exception_frame *frame)
Prints the exception frame via printk().
Definition: arm-exception-frame-print.c:46
void * _CPU_Thread_Idle_body(uintptr_t ignored)
This routine is the CPU dependent IDLE thread body.
Definition: cpu.c:125
The set of registers that specifies the complete processor state.
Definition: cpu.h:671
Information to build RTEMS for a "no cpu" while in protected mode.
#define SCORE_EXTERN
The following ensures that all data is declared in the space of the initialization routine for either...
Definition: basedefs.h:81
void * proc_ptr
XXX: Eventually proc_ptr needs to disappear!!!
Definition: basedefs.h:329