44 #ifndef _RTEMS_SCORE_CPU_H 45 #define _RTEMS_SCORE_CPU_H 59 #include <rtems/score/types.h> 81 #define CPU_INLINE_ENABLE_DISPATCH FALSE 107 #define CPU_HAS_SOFTWARE_INTERRUPT_STACK FALSE 121 #define CPU_SIMPLE_VECTORED_INTERRUPTS FALSE 138 #define CPU_HAS_HARDWARE_INTERRUPT_STACK FALSE 149 #define CPU_ALLOCATE_INTERRUPT_STACK FALSE 158 #define CPU_ISR_PASSES_FRAME_POINTER 1 178 #if ( MIPS_HAS_FPU == 1 ) 179 #define CPU_HARDWARE_FP TRUE 181 #define CPU_HARDWARE_FP FALSE 204 #define CPU_ALL_TASKS_ARE_FP CPU_HARDWARE_FP 218 #define CPU_IDLE_TASK_IS_FP FALSE 246 #define CPU_USE_DEFERRED_FP_SWITCH TRUE 270 #define CPU_PROVIDES_IDLE_THREAD_BODY TRUE 281 #define CPU_STACK_GROWS_UP FALSE 305 #define CPU_STRUCTURE_ALIGNMENT __attribute__ ((aligned (16))) 307 #define CPU_STRUCTURE_ALIGNMENT 310 #define CPU_TIMESTAMP_USE_INT64_INLINE TRUE 318 #if defined(__MIPSEB__) 319 #define CPU_BIG_ENDIAN TRUE 320 #define CPU_LITTLE_ENDIAN FALSE 321 #elif defined(__MIPSEL__) 322 #define CPU_BIG_ENDIAN FALSE 323 #define CPU_LITTLE_ENDIAN TRUE 325 #error "Unknown endianness" 334 #define CPU_MODES_INTERRUPT_MASK 0x000000ff 336 #define CPU_SIZEOF_POINTER 4 338 #define CPU_PER_CPU_CONTROL_SIZE 0 387 #if (__mips == 1) || (__mips == 32) 388 #define __MIPS_REGISTER_TYPE uint32_t 389 #define __MIPS_FPU_REGISTER_TYPE uint32_t 391 #define __MIPS_REGISTER_TYPE uint64_t 392 #define __MIPS_FPU_REGISTER_TYPE uint64_t 394 #error "mips register size: unknown architecture level!!" 397 __MIPS_REGISTER_TYPE s0;
398 __MIPS_REGISTER_TYPE s1;
399 __MIPS_REGISTER_TYPE s2;
400 __MIPS_REGISTER_TYPE s3;
401 __MIPS_REGISTER_TYPE s4;
402 __MIPS_REGISTER_TYPE s5;
403 __MIPS_REGISTER_TYPE s6;
404 __MIPS_REGISTER_TYPE s7;
405 __MIPS_REGISTER_TYPE sp;
406 __MIPS_REGISTER_TYPE fp;
407 __MIPS_REGISTER_TYPE ra;
408 __MIPS_REGISTER_TYPE c0_sr;
409 __MIPS_REGISTER_TYPE c0_epc;
412 #define _CPU_Context_Get_SP( _context ) \ 413 (uintptr_t) (_context)->sp 420 #if ( CPU_HARDWARE_FP == TRUE ) 421 __MIPS_FPU_REGISTER_TYPE fp0;
422 __MIPS_FPU_REGISTER_TYPE fp1;
423 __MIPS_FPU_REGISTER_TYPE fp2;
424 __MIPS_FPU_REGISTER_TYPE fp3;
425 __MIPS_FPU_REGISTER_TYPE fp4;
426 __MIPS_FPU_REGISTER_TYPE fp5;
427 __MIPS_FPU_REGISTER_TYPE fp6;
428 __MIPS_FPU_REGISTER_TYPE fp7;
429 __MIPS_FPU_REGISTER_TYPE fp8;
430 __MIPS_FPU_REGISTER_TYPE fp9;
431 __MIPS_FPU_REGISTER_TYPE fp10;
432 __MIPS_FPU_REGISTER_TYPE fp11;
433 __MIPS_FPU_REGISTER_TYPE fp12;
434 __MIPS_FPU_REGISTER_TYPE fp13;
435 __MIPS_FPU_REGISTER_TYPE fp14;
436 __MIPS_FPU_REGISTER_TYPE fp15;
437 __MIPS_FPU_REGISTER_TYPE fp16;
438 __MIPS_FPU_REGISTER_TYPE fp17;
439 __MIPS_FPU_REGISTER_TYPE fp18;
440 __MIPS_FPU_REGISTER_TYPE fp19;
441 __MIPS_FPU_REGISTER_TYPE fp20;
442 __MIPS_FPU_REGISTER_TYPE fp21;
443 __MIPS_FPU_REGISTER_TYPE fp22;
444 __MIPS_FPU_REGISTER_TYPE fp23;
445 __MIPS_FPU_REGISTER_TYPE fp24;
446 __MIPS_FPU_REGISTER_TYPE fp25;
447 __MIPS_FPU_REGISTER_TYPE fp26;
448 __MIPS_FPU_REGISTER_TYPE fp27;
449 __MIPS_FPU_REGISTER_TYPE fp28;
450 __MIPS_FPU_REGISTER_TYPE fp29;
451 __MIPS_FPU_REGISTER_TYPE fp30;
452 __MIPS_FPU_REGISTER_TYPE fp31;
482 __MIPS_REGISTER_TYPE r0;
483 __MIPS_REGISTER_TYPE at;
484 __MIPS_REGISTER_TYPE v0;
485 __MIPS_REGISTER_TYPE v1;
486 __MIPS_REGISTER_TYPE a0;
487 __MIPS_REGISTER_TYPE a1;
488 __MIPS_REGISTER_TYPE a2;
489 __MIPS_REGISTER_TYPE a3;
490 __MIPS_REGISTER_TYPE t0;
491 __MIPS_REGISTER_TYPE t1;
492 __MIPS_REGISTER_TYPE t2;
493 __MIPS_REGISTER_TYPE t3;
494 __MIPS_REGISTER_TYPE t4;
495 __MIPS_REGISTER_TYPE t5;
496 __MIPS_REGISTER_TYPE t6;
497 __MIPS_REGISTER_TYPE t7;
498 __MIPS_REGISTER_TYPE s0;
499 __MIPS_REGISTER_TYPE s1;
500 __MIPS_REGISTER_TYPE s2;
501 __MIPS_REGISTER_TYPE s3;
502 __MIPS_REGISTER_TYPE s4;
503 __MIPS_REGISTER_TYPE s5;
504 __MIPS_REGISTER_TYPE s6;
505 __MIPS_REGISTER_TYPE s7;
506 __MIPS_REGISTER_TYPE t8;
507 __MIPS_REGISTER_TYPE t9;
508 __MIPS_REGISTER_TYPE k0;
509 __MIPS_REGISTER_TYPE k1;
510 __MIPS_REGISTER_TYPE gp;
511 __MIPS_REGISTER_TYPE sp;
512 __MIPS_REGISTER_TYPE fp;
513 __MIPS_REGISTER_TYPE ra;
514 __MIPS_REGISTER_TYPE c0_sr;
516 __MIPS_REGISTER_TYPE mdlo;
517 __MIPS_REGISTER_TYPE mdhi;
518 __MIPS_REGISTER_TYPE badvaddr;
519 __MIPS_REGISTER_TYPE cause;
520 __MIPS_REGISTER_TYPE epc;
522 __MIPS_FPU_REGISTER_TYPE f0;
523 __MIPS_FPU_REGISTER_TYPE f1;
524 __MIPS_FPU_REGISTER_TYPE f2;
525 __MIPS_FPU_REGISTER_TYPE f3;
526 __MIPS_FPU_REGISTER_TYPE f4;
527 __MIPS_FPU_REGISTER_TYPE f5;
528 __MIPS_FPU_REGISTER_TYPE f6;
529 __MIPS_FPU_REGISTER_TYPE f7;
530 __MIPS_FPU_REGISTER_TYPE f8;
531 __MIPS_FPU_REGISTER_TYPE f9;
532 __MIPS_FPU_REGISTER_TYPE f10;
533 __MIPS_FPU_REGISTER_TYPE f11;
534 __MIPS_FPU_REGISTER_TYPE f12;
535 __MIPS_FPU_REGISTER_TYPE f13;
536 __MIPS_FPU_REGISTER_TYPE f14;
537 __MIPS_FPU_REGISTER_TYPE f15;
538 __MIPS_FPU_REGISTER_TYPE f16;
539 __MIPS_FPU_REGISTER_TYPE f17;
540 __MIPS_FPU_REGISTER_TYPE f18;
541 __MIPS_FPU_REGISTER_TYPE f19;
542 __MIPS_FPU_REGISTER_TYPE f20;
543 __MIPS_FPU_REGISTER_TYPE f21;
544 __MIPS_FPU_REGISTER_TYPE f22;
545 __MIPS_FPU_REGISTER_TYPE f23;
546 __MIPS_FPU_REGISTER_TYPE f24;
547 __MIPS_FPU_REGISTER_TYPE f25;
548 __MIPS_FPU_REGISTER_TYPE f26;
549 __MIPS_FPU_REGISTER_TYPE f27;
550 __MIPS_FPU_REGISTER_TYPE f28;
551 __MIPS_FPU_REGISTER_TYPE f29;
552 __MIPS_FPU_REGISTER_TYPE f30;
553 __MIPS_FPU_REGISTER_TYPE f31;
554 __MIPS_REGISTER_TYPE fcsr;
556 __MIPS_REGISTER_TYPE feir;
561 __MIPS_REGISTER_TYPE tlbhi;
564 __MIPS_REGISTER_TYPE tlblo;
567 #if (__mips == 3) || (__mips == 32) 568 __MIPS_REGISTER_TYPE tlblo0;
572 __MIPS_REGISTER_TYPE inx;
574 __MIPS_REGISTER_TYPE rand;
576 __MIPS_REGISTER_TYPE ctxt;
578 __MIPS_REGISTER_TYPE exctype;
579 __MIPS_REGISTER_TYPE mode;
580 __MIPS_REGISTER_TYPE prid;
581 __MIPS_REGISTER_TYPE tar ;
583 #if (__mips == 3) || (__mips == 32) 584 __MIPS_REGISTER_TYPE tlblo1;
585 __MIPS_REGISTER_TYPE pagemask;
586 __MIPS_REGISTER_TYPE wired;
587 __MIPS_REGISTER_TYPE count;
588 __MIPS_REGISTER_TYPE compare;
589 __MIPS_REGISTER_TYPE
config;
590 __MIPS_REGISTER_TYPE lladdr;
591 __MIPS_REGISTER_TYPE watchlo;
592 __MIPS_REGISTER_TYPE watchhi;
593 __MIPS_REGISTER_TYPE ecc;
594 __MIPS_REGISTER_TYPE cacheerr;
595 __MIPS_REGISTER_TYPE taglo;
596 __MIPS_REGISTER_TYPE taghi;
597 __MIPS_REGISTER_TYPE errpc;
598 __MIPS_REGISTER_TYPE xctxt;
628 #define CPU_CONTEXT_FP_SIZE sizeof( Context_Control_fp ) 636 #define CPU_MPCI_RECEIVE_SERVER_EXTRA_STACK 0 643 #define CPU_STACK_MINIMUM_SIZE (8 * 1024) 650 #define CPU_ALIGNMENT 8 664 #define CPU_HEAP_ALIGNMENT CPU_ALIGNMENT 678 #define CPU_PARTITION_ALIGNMENT CPU_ALIGNMENT 689 #define CPU_STACK_ALIGNMENT CPU_ALIGNMENT 702 uint32_t mips_interrupt_mask(
void );
709 #define _CPU_ISR_Disable( _level ) \ 711 unsigned int _scratch; \ 712 mips_get_sr( _scratch ); \ 713 mips_set_sr( _scratch & ~SR_INTERRUPT_ENABLE_BITS ); \ 714 _level = _scratch & SR_INTERRUPT_ENABLE_BITS; \ 723 #define _CPU_ISR_Enable( _level ) \ 725 unsigned int _scratch; \ 726 mips_get_sr( _scratch ); \ 727 mips_set_sr( (_scratch & ~SR_INTERRUPT_ENABLE_BITS) | (_level & SR_INTERRUPT_ENABLE_BITS) ); \ 737 #define _CPU_ISR_Flash( _xlevel ) \ 739 unsigned int _scratch2 = _xlevel; \ 740 _CPU_ISR_Enable( _scratch2 ); \ 741 _CPU_ISR_Disable( _scratch2 ); \ 742 _xlevel = _scratch2; \ 808 #if (__mips == 3) || (__mips == 32) 811 #define _EXTRABITS SR_FR 817 #define _INTON SR_IEC 824 uintptr_t *stack_base,
843 #define _CPU_Context_Restart_self( _the_context ) \ 844 _CPU_Context_restore( (_the_context) ); 860 #define _CPU_Context_Fp_start( _base, _offset ) \ 861 ( (void *) _Addresses_Add_offset( (_base), (_offset) ) ) 875 #if ( CPU_HARDWARE_FP == TRUE ) 876 #define _CPU_Context_Initialize_fp( _destination ) \ 878 *(*(_destination)) = _CPU_Null_fp_context; \ 892 #define _CPU_Fatal_halt( _source, _error ) \ 894 unsigned int _level; \ 895 _CPU_ISR_Disable(_level); \ 901 extern void mips_break(
int error );
960 #define CPU_USE_GENERIC_BITFIELD_CODE TRUE 961 #define CPU_USE_GENERIC_BITFIELD_DATA TRUE 963 #if (CPU_USE_GENERIC_BITFIELD_CODE == FALSE) 965 #define _CPU_Bitfield_Find_first_bit( _value, _output ) \ 980 #if (CPU_USE_GENERIC_BITFIELD_CODE == FALSE) 982 #define _CPU_Priority_Mask( _bit_number ) \ 983 ( 1 << (_bit_number) ) 994 #if (CPU_USE_GENERIC_BITFIELD_CODE == FALSE) 996 #define _CPU_Priority_bits_index( _priority ) \ 1138 static inline uint32_t CPU_swap_u32(
1142 uint32_t byte1, byte2, byte3, byte4, swapped;
1144 byte4 = (value >> 24) & 0xff;
1145 byte3 = (value >> 16) & 0xff;
1146 byte2 = (value >> 8) & 0xff;
1147 byte1 = value & 0xff;
1149 swapped = (byte1 << 24) | (byte2 << 16) | (byte3 << 8) | byte4;
1153 #define CPU_swap_u16( value ) \ 1154 (((value&0xff) << 8) | ((value >> 8)&0xff)) 1161 CPU_Counter_ticks second,
1162 CPU_Counter_ticks first
1165 return second - first;
void _CPU_ISR_install_vector(uint32_t vector, proc_ptr new_handler, proc_ptr *old_handler)
This routine installs an interrupt vector.
Definition: cpu.c:69
void _CPU_Context_validate(uintptr_t pattern)
Initializes and validates the CPU context with values derived from the pattern parameter.
Definition: cpu.h:1109
uint32_t _CPU_ISR_Get_level(void)
Return the current interrupt disable level for this task in the format used by the interrupt level po...
Definition: cpu.c:39
void _CPU_Context_restore(Context_Control *new_context)
This routine is generally used only to restart self in an efficient manner.
Definition: cpu_asm.c:112
Definition: deflate.c:116
void _CPU_Context_switch(Context_Control *run, Context_Control *heir)
CPU switch context.
Definition: cpu_asm.c:92
void _CPU_Context_volatile_clobber(uintptr_t pattern)
Clobbers all volatile registers with values derived from the pattern parameter.
Definition: cpu.h:1104
This defines the minimal set of integer and processor state registers that must be saved during a vol...
Definition: cpu.h:248
void _CPU_Initialize(void)
CPU initialization.
Definition: cpu.c:26
void _CPU_Install_interrupt_stack(void)
This routine installs the hardware interrupt stack pointer.
Definition: cpu.c:101
SCORE_EXTERN Context_Control_fp _CPU_Null_fp_context
This variable is optional.
Definition: cpu.h:494
uint32_t CPU_Counter_ticks
Unsigned integer type for CPU counter values.
Definition: cpu.h:1461
This defines the set of integer and processor state registers that must be saved during an interrupt...
Definition: cpu.h:425
void _CPU_ISR_install_raw_handler(uint32_t vector, proc_ptr new_handler, proc_ptr *old_handler)
This routine installs a "raw" interrupt handler directly into the processor's vector table...
Definition: cpu.c:57
void _CPU_ISR_Set_level(uint32_t level)
Sets the hardware interrupt level by the level value.
Definition: cpu.c:62
void _CPU_Context_restore_fp(Context_Control_fp **fp_context_ptr)
This routine restores the floating point context passed to it.
Definition: cpu.c:176
void _CPU_Context_Initialize(Context_Control *the_context, uint32_t *stack_base, uint32_t size, uint32_t new_level, void *entry_point, bool is_fp, void *tls_area)
Initialize the context to a state suitable for starting a task after a context restore operation...
Definition: cpu.c:183
CPU_Counter_ticks _CPU_Counter_read(void)
Returns the current CPU counter value.
Definition: cpu.c:96
CPU_Counter_ticks _CPU_Counter_difference(CPU_Counter_ticks second, CPU_Counter_ticks first)
Returns the difference between the second and first CPU counter value.
Definition: cpu.h:1160
This defines the complete set of floating point registers that must be saved during any context switc...
Definition: cpu.h:294
void _CPU_Context_save_fp(Context_Control_fp **fp_context_ptr)
This routine saves the floating point context passed to it.
Definition: cpu.c:167
#define RTEMS_COMPILER_NO_RETURN_ATTRIBUTE
The following macro is a compiler specific way to indicate that the method will NOT return to the cal...
Definition: basedefs.h:162
void _CPU_Exception_frame_print(const CPU_Exception_frame *frame)
Prints the exception frame via printk().
Definition: arm-exception-frame-print.c:46
void * _CPU_Thread_Idle_body(uintptr_t ignored)
This routine is the CPU dependent IDLE thread body.
Definition: cpu.c:125
The set of registers that specifies the complete processor state.
Definition: cpu.h:671
Information to build RTEMS for a "no cpu" while in protected mode.
#define SCORE_EXTERN
The following ensures that all data is declared in the space of the initialization routine for either...
Definition: basedefs.h:81
void * proc_ptr
XXX: Eventually proc_ptr needs to disappear!!!
Definition: basedefs.h:329