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#define | _AVR_IOXXX_H_ "iox32a4.h" |
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#define | _AVR_ATxmega32A4_H_ 1 |
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#define | GPIO0 _SFR_MEM8(0x0000) /* General Purpose IO Register 0 */ |
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#define | GPIO1 _SFR_MEM8(0x0001) /* General Purpose IO Register 1 */ |
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#define | GPIO2 _SFR_MEM8(0x0002) /* General Purpose IO Register 2 */ |
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#define | GPIO3 _SFR_MEM8(0x0003) /* General Purpose IO Register 3 */ |
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#define | GPIO4 _SFR_MEM8(0x0004) /* General Purpose IO Register 4 */ |
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#define | GPIO5 _SFR_MEM8(0x0005) /* General Purpose IO Register 5 */ |
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#define | GPIO6 _SFR_MEM8(0x0006) /* General Purpose IO Register 6 */ |
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#define | GPIO7 _SFR_MEM8(0x0007) /* General Purpose IO Register 7 */ |
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#define | GPIO8 _SFR_MEM8(0x0008) /* General Purpose IO Register 8 */ |
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#define | GPIO9 _SFR_MEM8(0x0009) /* General Purpose IO Register 9 */ |
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#define | GPIOA _SFR_MEM8(0x000A) /* General Purpose IO Register 10 */ |
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#define | GPIOB _SFR_MEM8(0x000B) /* General Purpose IO Register 11 */ |
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#define | GPIOC _SFR_MEM8(0x000C) /* General Purpose IO Register 12 */ |
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#define | GPIOD _SFR_MEM8(0x000D) /* General Purpose IO Register 13 */ |
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#define | GPIOE _SFR_MEM8(0x000E) /* General Purpose IO Register 14 */ |
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#define | GPIOF _SFR_MEM8(0x000F) /* General Purpose IO Register 15 */ |
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#define | CCP _SFR_MEM8(0x0034) /* Configuration Change Protection */ |
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#define | RAMPD _SFR_MEM8(0x0038) /* Ramp D */ |
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#define | RAMPX _SFR_MEM8(0x0039) /* Ramp X */ |
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#define | RAMPY _SFR_MEM8(0x003A) /* Ramp Y */ |
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#define | RAMPZ _SFR_MEM8(0x003B) /* Ramp Z */ |
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#define | EIND _SFR_MEM8(0x003C) /* Extended Indirect Jump */ |
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#define | SPL _SFR_MEM8(0x003D) /* Stack Pointer Low */ |
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#define | SPH _SFR_MEM8(0x003E) /* Stack Pointer High */ |
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#define | SREG _SFR_MEM8(0x003F) /* Status Register */ |
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#define | _WORDREGISTER(regname) |
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#define | _DWORDREGISTER(regname) |
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#define | GPIO (*(GPIO_t *) 0x0000) /* General Purpose IO Registers */ |
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#define | VPORT0 (*(VPORT_t *) 0x0010) /* Virtual Port 0 */ |
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#define | VPORT1 (*(VPORT_t *) 0x0014) /* Virtual Port 1 */ |
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#define | VPORT2 (*(VPORT_t *) 0x0018) /* Virtual Port 2 */ |
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#define | VPORT3 (*(VPORT_t *) 0x001C) /* Virtual Port 3 */ |
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#define | OCD (*(OCD_t *) 0x002E) /* On-Chip Debug System */ |
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#define | CPU (*(CPU_t *) 0x0030) /* CPU Registers */ |
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#define | CLK (*(CLK_t *) 0x0040) /* Clock System */ |
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#define | SLEEP (*(SLEEP_t *) 0x0048) /* Sleep Controller */ |
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#define | OSC (*(OSC_t *) 0x0050) /* Oscillator Control */ |
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#define | DFLLRC32M (*(DFLL_t *) 0x0060) /* DFLL for 32MHz RC Oscillator */ |
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#define | DFLLRC2M (*(DFLL_t *) 0x0068) /* DFLL for 2MHz RC Oscillator */ |
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#define | PR (*(PR_t *) 0x0070) /* Power Reduction */ |
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#define | RST (*(RST_t *) 0x0078) /* Reset Controller */ |
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#define | WDT (*(WDT_t *) 0x0080) /* Watch-Dog Timer */ |
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#define | MCU (*(MCU_t *) 0x0090) /* MCU Control */ |
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#define | PMIC (*(PMIC_t *) 0x00A0) /* Programmable Interrupt Controller */ |
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#define | PORTCFG (*(PORTCFG_t *) 0x00B0) /* Port Configuration */ |
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#define | AES (*(AES_t *) 0x00C0) /* AES Crypto Module */ |
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#define | DMA (*(DMA_t *) 0x0100) /* DMA Controller */ |
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#define | EVSYS (*(EVSYS_t *) 0x0180) /* Event System */ |
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#define | NVM (*(NVM_t *) 0x01C0) /* Non Volatile Memory Controller */ |
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#define | ADCA (*(ADC_t *) 0x0200) /* Analog to Digital Converter A */ |
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#define | DACB (*(DAC_t *) 0x0320) /* Digital to Analog Converter B */ |
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#define | ACA (*(AC_t *) 0x0380) /* Analog Comparator A */ |
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#define | RTC (*(RTC_t *) 0x0400) /* Real-Time Counter */ |
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#define | TWIC (*(TWI_t *) 0x0480) /* Two-Wire Interface C */ |
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#define | TWIE (*(TWI_t *) 0x04A0) /* Two-Wire Interface E */ |
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#define | PORTA (*(PORT_t *) 0x0600) /* Port A */ |
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#define | PORTB (*(PORT_t *) 0x0620) /* Port B */ |
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#define | PORTC (*(PORT_t *) 0x0640) /* Port C */ |
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#define | PORTD (*(PORT_t *) 0x0660) /* Port D */ |
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#define | PORTE (*(PORT_t *) 0x0680) /* Port E */ |
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#define | PORTR (*(PORT_t *) 0x07E0) /* Port R */ |
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#define | TCC0 (*(TC0_t *) 0x0800) /* Timer/Counter C0 */ |
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#define | TCC1 (*(TC1_t *) 0x0840) /* Timer/Counter C1 */ |
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#define | AWEXC (*(AWEX_t *) 0x0880) /* Advanced Waveform Extension C */ |
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#define | HIRESC (*(HIRES_t *) 0x0890) /* High-Resolution Extension C */ |
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#define | USARTC0 (*(USART_t *) 0x08A0) /* Universal Asynchronous Receiver-Transmitter C0 */ |
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#define | USARTC1 (*(USART_t *) 0x08B0) /* Universal Asynchronous Receiver-Transmitter C1 */ |
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#define | SPIC (*(SPI_t *) 0x08C0) /* Serial Peripheral Interface C */ |
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#define | IRCOM (*(IRCOM_t *) 0x08F8) /* IR Communication Module */ |
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#define | TCD0 (*(TC0_t *) 0x0900) /* Timer/Counter D0 */ |
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#define | TCD1 (*(TC1_t *) 0x0940) /* Timer/Counter D1 */ |
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#define | HIRESD (*(HIRES_t *) 0x0990) /* High-Resolution Extension D */ |
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#define | USARTD0 (*(USART_t *) 0x09A0) /* Universal Asynchronous Receiver-Transmitter D0 */ |
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#define | USARTD1 (*(USART_t *) 0x09B0) /* Universal Asynchronous Receiver-Transmitter D1 */ |
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#define | SPID (*(SPI_t *) 0x09C0) /* Serial Peripheral Interface D */ |
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#define | TCE0 (*(TC0_t *) 0x0A00) /* Timer/Counter E0 */ |
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#define | HIRESE (*(HIRES_t *) 0x0A90) /* High-Resolution Extension E */ |
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#define | USARTE0 (*(USART_t *) 0x0AA0) /* Universal Asynchronous Receiver-Transmitter E0 */ |
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#define | GPIO_GPIO0 _SFR_MEM8(0x0000) |
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#define | GPIO_GPIO1 _SFR_MEM8(0x0001) |
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#define | GPIO_GPIO2 _SFR_MEM8(0x0002) |
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#define | GPIO_GPIO3 _SFR_MEM8(0x0003) |
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#define | GPIO_GPIO4 _SFR_MEM8(0x0004) |
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#define | GPIO_GPIO5 _SFR_MEM8(0x0005) |
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#define | GPIO_GPIO6 _SFR_MEM8(0x0006) |
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#define | GPIO_GPIO7 _SFR_MEM8(0x0007) |
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#define | GPIO_GPIO8 _SFR_MEM8(0x0008) |
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#define | GPIO_GPIO9 _SFR_MEM8(0x0009) |
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#define | GPIO_GPIOA _SFR_MEM8(0x000A) |
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#define | GPIO_GPIOB _SFR_MEM8(0x000B) |
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#define | GPIO_GPIOC _SFR_MEM8(0x000C) |
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#define | GPIO_GPIOD _SFR_MEM8(0x000D) |
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#define | GPIO_GPIOE _SFR_MEM8(0x000E) |
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#define | GPIO_GPIOF _SFR_MEM8(0x000F) |
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#define | VPORT0_DIR _SFR_MEM8(0x0010) |
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#define | VPORT0_OUT _SFR_MEM8(0x0011) |
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#define | VPORT0_IN _SFR_MEM8(0x0012) |
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#define | VPORT0_INTFLAGS _SFR_MEM8(0x0013) |
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#define | VPORT1_DIR _SFR_MEM8(0x0014) |
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#define | VPORT1_OUT _SFR_MEM8(0x0015) |
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#define | VPORT1_IN _SFR_MEM8(0x0016) |
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#define | VPORT1_INTFLAGS _SFR_MEM8(0x0017) |
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#define | VPORT2_DIR _SFR_MEM8(0x0018) |
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#define | VPORT2_OUT _SFR_MEM8(0x0019) |
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#define | VPORT2_IN _SFR_MEM8(0x001A) |
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#define | VPORT2_INTFLAGS _SFR_MEM8(0x001B) |
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#define | VPORT3_DIR _SFR_MEM8(0x001C) |
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#define | VPORT3_OUT _SFR_MEM8(0x001D) |
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#define | VPORT3_IN _SFR_MEM8(0x001E) |
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#define | VPORT3_INTFLAGS _SFR_MEM8(0x001F) |
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#define | OCD_OCDR0 _SFR_MEM8(0x002E) |
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#define | OCD_OCDR1 _SFR_MEM8(0x002F) |
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#define | CPU_CCP _SFR_MEM8(0x0034) |
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#define | CPU_RAMPD _SFR_MEM8(0x0038) |
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#define | CPU_RAMPX _SFR_MEM8(0x0039) |
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#define | CPU_RAMPY _SFR_MEM8(0x003A) |
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#define | CPU_RAMPZ _SFR_MEM8(0x003B) |
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#define | CPU_EIND _SFR_MEM8(0x003C) |
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#define | CPU_SPL _SFR_MEM8(0x003D) |
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#define | CPU_SPH _SFR_MEM8(0x003E) |
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#define | CPU_SREG _SFR_MEM8(0x003F) |
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#define | CLK_CTRL _SFR_MEM8(0x0040) |
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#define | CLK_PSCTRL _SFR_MEM8(0x0041) |
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#define | CLK_LOCK _SFR_MEM8(0x0042) |
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#define | CLK_RTCCTRL _SFR_MEM8(0x0043) |
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#define | SLEEP_CTRL _SFR_MEM8(0x0048) |
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#define | OSC_CTRL _SFR_MEM8(0x0050) |
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#define | OSC_STATUS _SFR_MEM8(0x0051) |
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#define | OSC_XOSCCTRL _SFR_MEM8(0x0052) |
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#define | OSC_XOSCFAIL _SFR_MEM8(0x0053) |
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#define | OSC_RC32KCAL _SFR_MEM8(0x0054) |
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#define | OSC_PLLCTRL _SFR_MEM8(0x0055) |
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#define | OSC_DFLLCTRL _SFR_MEM8(0x0056) |
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#define | DFLLRC32M_CTRL _SFR_MEM8(0x0060) |
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#define | DFLLRC32M_CALA _SFR_MEM8(0x0062) |
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#define | DFLLRC32M_CALB _SFR_MEM8(0x0063) |
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#define | DFLLRC32M_COMP0 _SFR_MEM8(0x0064) |
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#define | DFLLRC32M_COMP1 _SFR_MEM8(0x0065) |
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#define | DFLLRC32M_COMP2 _SFR_MEM8(0x0066) |
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#define | DFLLRC2M_CTRL _SFR_MEM8(0x0068) |
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#define | DFLLRC2M_CALA _SFR_MEM8(0x006A) |
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#define | DFLLRC2M_CALB _SFR_MEM8(0x006B) |
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#define | DFLLRC2M_COMP0 _SFR_MEM8(0x006C) |
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#define | DFLLRC2M_COMP1 _SFR_MEM8(0x006D) |
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#define | DFLLRC2M_COMP2 _SFR_MEM8(0x006E) |
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#define | PR_PRGEN _SFR_MEM8(0x0070) |
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#define | PR_PRPA _SFR_MEM8(0x0071) |
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#define | PR_PRPB _SFR_MEM8(0x0072) |
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#define | PR_PRPC _SFR_MEM8(0x0073) |
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#define | PR_PRPD _SFR_MEM8(0x0074) |
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#define | PR_PRPE _SFR_MEM8(0x0075) |
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#define | PR_PRPF _SFR_MEM8(0x0076) |
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#define | RST_STATUS _SFR_MEM8(0x0078) |
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#define | RST_CTRL _SFR_MEM8(0x0079) |
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#define | WDT_CTRL _SFR_MEM8(0x0080) |
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#define | WDT_WINCTRL _SFR_MEM8(0x0081) |
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#define | WDT_STATUS _SFR_MEM8(0x0082) |
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#define | MCU_DEVID0 _SFR_MEM8(0x0090) |
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#define | MCU_DEVID1 _SFR_MEM8(0x0091) |
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#define | MCU_DEVID2 _SFR_MEM8(0x0092) |
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#define | MCU_REVID _SFR_MEM8(0x0093) |
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#define | MCU_JTAGUID _SFR_MEM8(0x0094) |
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#define | MCU_MCUCR _SFR_MEM8(0x0096) |
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#define | MCU_EVSYSLOCK _SFR_MEM8(0x0098) |
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#define | MCU_AWEXLOCK _SFR_MEM8(0x0099) |
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#define | PMIC_STATUS _SFR_MEM8(0x00A0) |
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#define | PMIC_INTPRI _SFR_MEM8(0x00A1) |
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#define | PMIC_CTRL _SFR_MEM8(0x00A2) |
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#define | PORTCFG_MPCMASK _SFR_MEM8(0x00B0) |
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#define | PORTCFG_VPCTRLA _SFR_MEM8(0x00B2) |
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#define | PORTCFG_VPCTRLB _SFR_MEM8(0x00B3) |
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#define | PORTCFG_CLKEVOUT _SFR_MEM8(0x00B4) |
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#define | AES_CTRL _SFR_MEM8(0x00C0) |
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#define | AES_STATUS _SFR_MEM8(0x00C1) |
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#define | AES_STATE _SFR_MEM8(0x00C2) |
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#define | AES_KEY _SFR_MEM8(0x00C3) |
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#define | AES_INTCTRL _SFR_MEM8(0x00C4) |
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#define | DMA_CTRL _SFR_MEM8(0x0100) |
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#define | DMA_INTFLAGS _SFR_MEM8(0x0103) |
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#define | DMA_STATUS _SFR_MEM8(0x0104) |
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#define | DMA_TEMP _SFR_MEM16(0x0106) |
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#define | DMA_CH0_CTRLA _SFR_MEM8(0x0110) |
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#define | DMA_CH0_CTRLB _SFR_MEM8(0x0111) |
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#define | DMA_CH0_ADDRCTRL _SFR_MEM8(0x0112) |
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#define | DMA_CH0_TRIGSRC _SFR_MEM8(0x0113) |
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#define | DMA_CH0_TRFCNT _SFR_MEM16(0x0114) |
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#define | DMA_CH0_REPCNT _SFR_MEM8(0x0116) |
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#define | DMA_CH0_SRCADDR0 _SFR_MEM8(0x0118) |
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#define | DMA_CH0_SRCADDR1 _SFR_MEM8(0x0119) |
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#define | DMA_CH0_SRCADDR2 _SFR_MEM8(0x011A) |
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#define | DMA_CH0_DESTADDR0 _SFR_MEM8(0x011C) |
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#define | DMA_CH0_DESTADDR1 _SFR_MEM8(0x011D) |
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#define | DMA_CH0_DESTADDR2 _SFR_MEM8(0x011E) |
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#define | DMA_CH1_CTRLA _SFR_MEM8(0x0120) |
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#define | DMA_CH1_CTRLB _SFR_MEM8(0x0121) |
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#define | DMA_CH1_ADDRCTRL _SFR_MEM8(0x0122) |
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#define | DMA_CH1_TRIGSRC _SFR_MEM8(0x0123) |
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#define | DMA_CH1_TRFCNT _SFR_MEM16(0x0124) |
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#define | DMA_CH1_REPCNT _SFR_MEM8(0x0126) |
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#define | DMA_CH1_SRCADDR0 _SFR_MEM8(0x0128) |
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#define | DMA_CH1_SRCADDR1 _SFR_MEM8(0x0129) |
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#define | DMA_CH1_SRCADDR2 _SFR_MEM8(0x012A) |
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#define | DMA_CH1_DESTADDR0 _SFR_MEM8(0x012C) |
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#define | DMA_CH1_DESTADDR1 _SFR_MEM8(0x012D) |
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#define | DMA_CH1_DESTADDR2 _SFR_MEM8(0x012E) |
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#define | DMA_CH2_CTRLA _SFR_MEM8(0x0130) |
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#define | DMA_CH2_CTRLB _SFR_MEM8(0x0131) |
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#define | DMA_CH2_ADDRCTRL _SFR_MEM8(0x0132) |
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#define | DMA_CH2_TRIGSRC _SFR_MEM8(0x0133) |
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#define | DMA_CH2_TRFCNT _SFR_MEM16(0x0134) |
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#define | DMA_CH2_REPCNT _SFR_MEM8(0x0136) |
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#define | DMA_CH2_SRCADDR0 _SFR_MEM8(0x0138) |
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#define | DMA_CH2_SRCADDR1 _SFR_MEM8(0x0139) |
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#define | DMA_CH2_SRCADDR2 _SFR_MEM8(0x013A) |
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#define | DMA_CH2_DESTADDR0 _SFR_MEM8(0x013C) |
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#define | DMA_CH2_DESTADDR1 _SFR_MEM8(0x013D) |
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#define | DMA_CH2_DESTADDR2 _SFR_MEM8(0x013E) |
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#define | DMA_CH3_CTRLA _SFR_MEM8(0x0140) |
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#define | DMA_CH3_CTRLB _SFR_MEM8(0x0141) |
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#define | DMA_CH3_ADDRCTRL _SFR_MEM8(0x0142) |
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#define | DMA_CH3_TRIGSRC _SFR_MEM8(0x0143) |
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#define | DMA_CH3_TRFCNT _SFR_MEM16(0x0144) |
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#define | DMA_CH3_REPCNT _SFR_MEM8(0x0146) |
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#define | DMA_CH3_SRCADDR0 _SFR_MEM8(0x0148) |
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#define | DMA_CH3_SRCADDR1 _SFR_MEM8(0x0149) |
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#define | DMA_CH3_SRCADDR2 _SFR_MEM8(0x014A) |
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#define | DMA_CH3_DESTADDR0 _SFR_MEM8(0x014C) |
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#define | DMA_CH3_DESTADDR1 _SFR_MEM8(0x014D) |
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#define | DMA_CH3_DESTADDR2 _SFR_MEM8(0x014E) |
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#define | EVSYS_CH0MUX _SFR_MEM8(0x0180) |
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#define | EVSYS_CH1MUX _SFR_MEM8(0x0181) |
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#define | EVSYS_CH2MUX _SFR_MEM8(0x0182) |
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#define | EVSYS_CH3MUX _SFR_MEM8(0x0183) |
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#define | EVSYS_CH4MUX _SFR_MEM8(0x0184) |
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#define | EVSYS_CH5MUX _SFR_MEM8(0x0185) |
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#define | EVSYS_CH6MUX _SFR_MEM8(0x0186) |
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#define | EVSYS_CH7MUX _SFR_MEM8(0x0187) |
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#define | EVSYS_CH0CTRL _SFR_MEM8(0x0188) |
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#define | EVSYS_CH1CTRL _SFR_MEM8(0x0189) |
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#define | EVSYS_CH2CTRL _SFR_MEM8(0x018A) |
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#define | EVSYS_CH3CTRL _SFR_MEM8(0x018B) |
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#define | EVSYS_CH4CTRL _SFR_MEM8(0x018C) |
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#define | EVSYS_CH5CTRL _SFR_MEM8(0x018D) |
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#define | EVSYS_CH6CTRL _SFR_MEM8(0x018E) |
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#define | EVSYS_CH7CTRL _SFR_MEM8(0x018F) |
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#define | EVSYS_STROBE _SFR_MEM8(0x0190) |
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#define | EVSYS_DATA _SFR_MEM8(0x0191) |
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#define | NVM_ADDR0 _SFR_MEM8(0x01C0) |
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#define | NVM_ADDR1 _SFR_MEM8(0x01C1) |
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#define | NVM_ADDR2 _SFR_MEM8(0x01C2) |
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#define | NVM_DATA0 _SFR_MEM8(0x01C4) |
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#define | NVM_DATA1 _SFR_MEM8(0x01C5) |
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#define | NVM_DATA2 _SFR_MEM8(0x01C6) |
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#define | NVM_CMD _SFR_MEM8(0x01CA) |
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#define | NVM_CTRLA _SFR_MEM8(0x01CB) |
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#define | NVM_CTRLB _SFR_MEM8(0x01CC) |
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#define | NVM_INTCTRL _SFR_MEM8(0x01CD) |
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#define | NVM_STATUS _SFR_MEM8(0x01CF) |
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#define | NVM_LOCKBITS _SFR_MEM8(0x01D0) |
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#define | ADCA_CTRLA _SFR_MEM8(0x0200) |
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#define | ADCA_CTRLB _SFR_MEM8(0x0201) |
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#define | ADCA_REFCTRL _SFR_MEM8(0x0202) |
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#define | ADCA_EVCTRL _SFR_MEM8(0x0203) |
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#define | ADCA_PRESCALER _SFR_MEM8(0x0204) |
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#define | ADCA_CALCTRL _SFR_MEM8(0x0205) |
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#define | ADCA_INTFLAGS _SFR_MEM8(0x0206) |
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#define | ADCA_CAL _SFR_MEM16(0x020C) |
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#define | ADCA_CH0RES _SFR_MEM16(0x0210) |
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#define | ADCA_CH1RES _SFR_MEM16(0x0212) |
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#define | ADCA_CH2RES _SFR_MEM16(0x0214) |
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#define | ADCA_CH3RES _SFR_MEM16(0x0216) |
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#define | ADCA_CMP _SFR_MEM16(0x0218) |
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#define | ADCA_CH0_CTRL _SFR_MEM8(0x0220) |
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#define | ADCA_CH0_MUXCTRL _SFR_MEM8(0x0221) |
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#define | ADCA_CH0_INTCTRL _SFR_MEM8(0x0222) |
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#define | ADCA_CH0_INTFLAGS _SFR_MEM8(0x0223) |
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#define | ADCA_CH0_RES _SFR_MEM16(0x0224) |
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#define | ADCA_CH1_CTRL _SFR_MEM8(0x0228) |
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#define | ADCA_CH1_MUXCTRL _SFR_MEM8(0x0229) |
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#define | ADCA_CH1_INTCTRL _SFR_MEM8(0x022A) |
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#define | ADCA_CH1_INTFLAGS _SFR_MEM8(0x022B) |
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#define | ADCA_CH1_RES _SFR_MEM16(0x022C) |
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#define | ADCA_CH2_CTRL _SFR_MEM8(0x0230) |
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#define | ADCA_CH2_MUXCTRL _SFR_MEM8(0x0231) |
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#define | ADCA_CH2_INTCTRL _SFR_MEM8(0x0232) |
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#define | ADCA_CH2_INTFLAGS _SFR_MEM8(0x0233) |
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#define | ADCA_CH2_RES _SFR_MEM16(0x0234) |
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#define | ADCA_CH3_CTRL _SFR_MEM8(0x0238) |
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#define | ADCA_CH3_MUXCTRL _SFR_MEM8(0x0239) |
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#define | ADCA_CH3_INTCTRL _SFR_MEM8(0x023A) |
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#define | ADCA_CH3_INTFLAGS _SFR_MEM8(0x023B) |
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#define | ADCA_CH3_RES _SFR_MEM16(0x023C) |
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#define | DACB_CTRLA _SFR_MEM8(0x0320) |
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#define | DACB_CTRLB _SFR_MEM8(0x0321) |
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#define | DACB_CTRLC _SFR_MEM8(0x0322) |
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#define | DACB_EVCTRL _SFR_MEM8(0x0323) |
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#define | DACB_TIMCTRL _SFR_MEM8(0x0324) |
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#define | DACB_STATUS _SFR_MEM8(0x0325) |
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#define | DACB_GAINCAL _SFR_MEM8(0x0328) |
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#define | DACB_OFFSETCAL _SFR_MEM8(0x0329) |
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#define | DACB_CH0DATA _SFR_MEM16(0x0338) |
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#define | DACB_CH1DATA _SFR_MEM16(0x033A) |
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#define | ACA_AC0CTRL _SFR_MEM8(0x0380) |
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#define | ACA_AC1CTRL _SFR_MEM8(0x0381) |
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#define | ACA_AC0MUXCTRL _SFR_MEM8(0x0382) |
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#define | ACA_AC1MUXCTRL _SFR_MEM8(0x0383) |
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#define | ACA_CTRLA _SFR_MEM8(0x0384) |
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#define | ACA_CTRLB _SFR_MEM8(0x0385) |
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#define | ACA_WINCTRL _SFR_MEM8(0x0386) |
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#define | ACA_STATUS _SFR_MEM8(0x0387) |
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#define | RTC_CTRL _SFR_MEM8(0x0400) |
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#define | RTC_STATUS _SFR_MEM8(0x0401) |
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#define | RTC_INTCTRL _SFR_MEM8(0x0402) |
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#define | RTC_INTFLAGS _SFR_MEM8(0x0403) |
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#define | RTC_TEMP _SFR_MEM8(0x0404) |
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#define | RTC_CNT _SFR_MEM16(0x0408) |
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#define | RTC_PER _SFR_MEM16(0x040A) |
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#define | RTC_COMP _SFR_MEM16(0x040C) |
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#define | TWIC_CTRL _SFR_MEM8(0x0480) |
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#define | TWIC_MASTER_CTRLA _SFR_MEM8(0x0481) |
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#define | TWIC_MASTER_CTRLB _SFR_MEM8(0x0482) |
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#define | TWIC_MASTER_CTRLC _SFR_MEM8(0x0483) |
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#define | TWIC_MASTER_STATUS _SFR_MEM8(0x0484) |
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#define | TWIC_MASTER_BAUD _SFR_MEM8(0x0485) |
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#define | TWIC_MASTER_ADDR _SFR_MEM8(0x0486) |
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#define | TWIC_MASTER_DATA _SFR_MEM8(0x0487) |
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#define | TWIC_SLAVE_CTRLA _SFR_MEM8(0x0488) |
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#define | TWIC_SLAVE_CTRLB _SFR_MEM8(0x0489) |
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#define | TWIC_SLAVE_STATUS _SFR_MEM8(0x048A) |
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#define | TWIC_SLAVE_ADDR _SFR_MEM8(0x048B) |
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#define | TWIC_SLAVE_DATA _SFR_MEM8(0x048C) |
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#define | TWIC_SLAVE_ADDRMASK _SFR_MEM8(0x048D) |
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#define | TWIE_CTRL _SFR_MEM8(0x04A0) |
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#define | TWIE_MASTER_CTRLA _SFR_MEM8(0x04A1) |
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#define | TWIE_MASTER_CTRLB _SFR_MEM8(0x04A2) |
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#define | TWIE_MASTER_CTRLC _SFR_MEM8(0x04A3) |
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#define | TWIE_MASTER_STATUS _SFR_MEM8(0x04A4) |
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#define | TWIE_MASTER_BAUD _SFR_MEM8(0x04A5) |
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#define | TWIE_MASTER_ADDR _SFR_MEM8(0x04A6) |
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#define | TWIE_MASTER_DATA _SFR_MEM8(0x04A7) |
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#define | TWIE_SLAVE_CTRLA _SFR_MEM8(0x04A8) |
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#define | TWIE_SLAVE_CTRLB _SFR_MEM8(0x04A9) |
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#define | TWIE_SLAVE_STATUS _SFR_MEM8(0x04AA) |
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#define | TWIE_SLAVE_ADDR _SFR_MEM8(0x04AB) |
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#define | TWIE_SLAVE_DATA _SFR_MEM8(0x04AC) |
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#define | TWIE_SLAVE_ADDRMASK _SFR_MEM8(0x04AD) |
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#define | PORTA_DIR _SFR_MEM8(0x0600) |
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#define | PORTA_DIRSET _SFR_MEM8(0x0601) |
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#define | PORTA_DIRCLR _SFR_MEM8(0x0602) |
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#define | PORTA_DIRTGL _SFR_MEM8(0x0603) |
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#define | PORTA_OUT _SFR_MEM8(0x0604) |
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#define | PORTA_OUTSET _SFR_MEM8(0x0605) |
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#define | PORTA_OUTCLR _SFR_MEM8(0x0606) |
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#define | PORTA_OUTTGL _SFR_MEM8(0x0607) |
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#define | PORTA_IN _SFR_MEM8(0x0608) |
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#define | PORTA_INTCTRL _SFR_MEM8(0x0609) |
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#define | PORTA_INT0MASK _SFR_MEM8(0x060A) |
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#define | PORTA_INT1MASK _SFR_MEM8(0x060B) |
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#define | PORTA_INTFLAGS _SFR_MEM8(0x060C) |
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#define | PORTA_PIN0CTRL _SFR_MEM8(0x0610) |
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#define | PORTA_PIN1CTRL _SFR_MEM8(0x0611) |
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#define | PORTA_PIN2CTRL _SFR_MEM8(0x0612) |
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#define | PORTA_PIN3CTRL _SFR_MEM8(0x0613) |
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#define | PORTA_PIN4CTRL _SFR_MEM8(0x0614) |
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#define | PORTA_PIN5CTRL _SFR_MEM8(0x0615) |
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#define | PORTA_PIN6CTRL _SFR_MEM8(0x0616) |
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#define | PORTA_PIN7CTRL _SFR_MEM8(0x0617) |
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#define | PORTB_DIR _SFR_MEM8(0x0620) |
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#define | PORTB_DIRSET _SFR_MEM8(0x0621) |
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#define | PORTB_DIRCLR _SFR_MEM8(0x0622) |
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#define | PORTB_DIRTGL _SFR_MEM8(0x0623) |
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#define | PORTB_OUT _SFR_MEM8(0x0624) |
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#define | PORTB_OUTSET _SFR_MEM8(0x0625) |
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#define | PORTB_OUTCLR _SFR_MEM8(0x0626) |
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#define | PORTB_OUTTGL _SFR_MEM8(0x0627) |
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#define | PORTB_IN _SFR_MEM8(0x0628) |
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#define | PORTB_INTCTRL _SFR_MEM8(0x0629) |
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#define | PORTB_INT0MASK _SFR_MEM8(0x062A) |
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#define | PORTB_INT1MASK _SFR_MEM8(0x062B) |
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#define | PORTB_INTFLAGS _SFR_MEM8(0x062C) |
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#define | PORTB_PIN0CTRL _SFR_MEM8(0x0630) |
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#define | PORTB_PIN1CTRL _SFR_MEM8(0x0631) |
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#define | PORTB_PIN2CTRL _SFR_MEM8(0x0632) |
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#define | PORTB_PIN3CTRL _SFR_MEM8(0x0633) |
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#define | PORTB_PIN4CTRL _SFR_MEM8(0x0634) |
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#define | PORTB_PIN5CTRL _SFR_MEM8(0x0635) |
|
#define | PORTB_PIN6CTRL _SFR_MEM8(0x0636) |
|
#define | PORTB_PIN7CTRL _SFR_MEM8(0x0637) |
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#define | PORTC_DIR _SFR_MEM8(0x0640) |
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#define | PORTC_DIRSET _SFR_MEM8(0x0641) |
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#define | PORTC_DIRCLR _SFR_MEM8(0x0642) |
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#define | PORTC_DIRTGL _SFR_MEM8(0x0643) |
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#define | PORTC_OUT _SFR_MEM8(0x0644) |
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#define | PORTC_OUTSET _SFR_MEM8(0x0645) |
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#define | PORTC_OUTCLR _SFR_MEM8(0x0646) |
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#define | PORTC_OUTTGL _SFR_MEM8(0x0647) |
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#define | PORTC_IN _SFR_MEM8(0x0648) |
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#define | PORTC_INTCTRL _SFR_MEM8(0x0649) |
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#define | PORTC_INT0MASK _SFR_MEM8(0x064A) |
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#define | PORTC_INT1MASK _SFR_MEM8(0x064B) |
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#define | PORTC_INTFLAGS _SFR_MEM8(0x064C) |
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#define | PORTC_PIN0CTRL _SFR_MEM8(0x0650) |
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#define | PORTC_PIN1CTRL _SFR_MEM8(0x0651) |
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#define | PORTC_PIN2CTRL _SFR_MEM8(0x0652) |
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#define | PORTC_PIN3CTRL _SFR_MEM8(0x0653) |
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#define | PORTC_PIN4CTRL _SFR_MEM8(0x0654) |
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#define | PORTC_PIN5CTRL _SFR_MEM8(0x0655) |
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#define | PORTC_PIN6CTRL _SFR_MEM8(0x0656) |
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#define | PORTC_PIN7CTRL _SFR_MEM8(0x0657) |
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#define | PORTD_DIR _SFR_MEM8(0x0660) |
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#define | PORTD_DIRSET _SFR_MEM8(0x0661) |
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#define | PORTD_DIRCLR _SFR_MEM8(0x0662) |
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#define | PORTD_DIRTGL _SFR_MEM8(0x0663) |
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#define | PORTD_OUT _SFR_MEM8(0x0664) |
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#define | PORTD_OUTSET _SFR_MEM8(0x0665) |
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#define | PORTD_OUTCLR _SFR_MEM8(0x0666) |
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#define | PORTD_OUTTGL _SFR_MEM8(0x0667) |
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#define | PORTD_IN _SFR_MEM8(0x0668) |
|
#define | PORTD_INTCTRL _SFR_MEM8(0x0669) |
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#define | PORTD_INT0MASK _SFR_MEM8(0x066A) |
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#define | PORTD_INT1MASK _SFR_MEM8(0x066B) |
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#define | PORTD_INTFLAGS _SFR_MEM8(0x066C) |
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#define | PORTD_PIN0CTRL _SFR_MEM8(0x0670) |
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#define | PORTD_PIN1CTRL _SFR_MEM8(0x0671) |
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#define | PORTD_PIN2CTRL _SFR_MEM8(0x0672) |
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#define | PORTD_PIN3CTRL _SFR_MEM8(0x0673) |
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#define | PORTD_PIN4CTRL _SFR_MEM8(0x0674) |
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#define | PORTD_PIN5CTRL _SFR_MEM8(0x0675) |
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#define | PORTD_PIN6CTRL _SFR_MEM8(0x0676) |
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#define | PORTD_PIN7CTRL _SFR_MEM8(0x0677) |
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#define | PORTE_DIR _SFR_MEM8(0x0680) |
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#define | PORTE_DIRSET _SFR_MEM8(0x0681) |
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#define | PORTE_DIRCLR _SFR_MEM8(0x0682) |
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#define | PORTE_DIRTGL _SFR_MEM8(0x0683) |
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#define | PORTE_OUT _SFR_MEM8(0x0684) |
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#define | PORTE_OUTSET _SFR_MEM8(0x0685) |
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#define | PORTE_OUTCLR _SFR_MEM8(0x0686) |
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#define | PORTE_OUTTGL _SFR_MEM8(0x0687) |
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#define | PORTE_IN _SFR_MEM8(0x0688) |
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#define | PORTE_INTCTRL _SFR_MEM8(0x0689) |
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#define | PORTE_INT0MASK _SFR_MEM8(0x068A) |
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#define | PORTE_INT1MASK _SFR_MEM8(0x068B) |
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#define | PORTE_INTFLAGS _SFR_MEM8(0x068C) |
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#define | PORTE_PIN0CTRL _SFR_MEM8(0x0690) |
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#define | PORTE_PIN1CTRL _SFR_MEM8(0x0691) |
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#define | PORTE_PIN2CTRL _SFR_MEM8(0x0692) |
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#define | PORTE_PIN3CTRL _SFR_MEM8(0x0693) |
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#define | PORTE_PIN4CTRL _SFR_MEM8(0x0694) |
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#define | PORTE_PIN5CTRL _SFR_MEM8(0x0695) |
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#define | PORTE_PIN6CTRL _SFR_MEM8(0x0696) |
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#define | PORTE_PIN7CTRL _SFR_MEM8(0x0697) |
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#define | PORTR_DIR _SFR_MEM8(0x07E0) |
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#define | PORTR_DIRSET _SFR_MEM8(0x07E1) |
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#define | PORTR_DIRCLR _SFR_MEM8(0x07E2) |
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#define | PORTR_DIRTGL _SFR_MEM8(0x07E3) |
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#define | PORTR_OUT _SFR_MEM8(0x07E4) |
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#define | PORTR_OUTSET _SFR_MEM8(0x07E5) |
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#define | PORTR_OUTCLR _SFR_MEM8(0x07E6) |
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#define | PORTR_OUTTGL _SFR_MEM8(0x07E7) |
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#define | PORTR_IN _SFR_MEM8(0x07E8) |
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#define | PORTR_INTCTRL _SFR_MEM8(0x07E9) |
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#define | PORTR_INT0MASK _SFR_MEM8(0x07EA) |
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#define | PORTR_INT1MASK _SFR_MEM8(0x07EB) |
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#define | PORTR_INTFLAGS _SFR_MEM8(0x07EC) |
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#define | PORTR_PIN0CTRL _SFR_MEM8(0x07F0) |
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#define | PORTR_PIN1CTRL _SFR_MEM8(0x07F1) |
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#define | PORTR_PIN2CTRL _SFR_MEM8(0x07F2) |
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#define | PORTR_PIN3CTRL _SFR_MEM8(0x07F3) |
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#define | PORTR_PIN4CTRL _SFR_MEM8(0x07F4) |
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#define | PORTR_PIN5CTRL _SFR_MEM8(0x07F5) |
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#define | PORTR_PIN6CTRL _SFR_MEM8(0x07F6) |
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#define | PORTR_PIN7CTRL _SFR_MEM8(0x07F7) |
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#define | TCC0_CTRLA _SFR_MEM8(0x0800) |
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#define | TCC0_CTRLB _SFR_MEM8(0x0801) |
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#define | TCC0_CTRLC _SFR_MEM8(0x0802) |
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#define | TCC0_CTRLD _SFR_MEM8(0x0803) |
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#define | TCC0_CTRLE _SFR_MEM8(0x0804) |
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#define | TCC0_INTCTRLA _SFR_MEM8(0x0806) |
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#define | TCC0_INTCTRLB _SFR_MEM8(0x0807) |
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#define | TCC0_CTRLFCLR _SFR_MEM8(0x0808) |
|
#define | TCC0_CTRLFSET _SFR_MEM8(0x0809) |
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#define | TCC0_CTRLGCLR _SFR_MEM8(0x080A) |
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#define | TCC0_CTRLGSET _SFR_MEM8(0x080B) |
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#define | TCC0_INTFLAGS _SFR_MEM8(0x080C) |
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#define | TCC0_TEMP _SFR_MEM8(0x080F) |
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#define | TCC0_CNT _SFR_MEM16(0x0820) |
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#define | TCC0_PER _SFR_MEM16(0x0826) |
|
#define | TCC0_CCA _SFR_MEM16(0x0828) |
|
#define | TCC0_CCB _SFR_MEM16(0x082A) |
|
#define | TCC0_CCC _SFR_MEM16(0x082C) |
|
#define | TCC0_CCD _SFR_MEM16(0x082E) |
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#define | TCC0_PERBUF _SFR_MEM16(0x0836) |
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#define | TCC0_CCABUF _SFR_MEM16(0x0838) |
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#define | TCC0_CCBBUF _SFR_MEM16(0x083A) |
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#define | TCC0_CCCBUF _SFR_MEM16(0x083C) |
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#define | TCC0_CCDBUF _SFR_MEM16(0x083E) |
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#define | TCC1_CTRLA _SFR_MEM8(0x0840) |
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#define | TCC1_CTRLB _SFR_MEM8(0x0841) |
|
#define | TCC1_CTRLC _SFR_MEM8(0x0842) |
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#define | TCC1_CTRLD _SFR_MEM8(0x0843) |
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#define | TCC1_CTRLE _SFR_MEM8(0x0844) |
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#define | TCC1_INTCTRLA _SFR_MEM8(0x0846) |
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#define | TCC1_INTCTRLB _SFR_MEM8(0x0847) |
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#define | TCC1_CTRLFCLR _SFR_MEM8(0x0848) |
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#define | TCC1_CTRLFSET _SFR_MEM8(0x0849) |
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#define | TCC1_CTRLGCLR _SFR_MEM8(0x084A) |
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#define | TCC1_CTRLGSET _SFR_MEM8(0x084B) |
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#define | TCC1_INTFLAGS _SFR_MEM8(0x084C) |
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#define | TCC1_TEMP _SFR_MEM8(0x084F) |
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#define | TCC1_CNT _SFR_MEM16(0x0860) |
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#define | TCC1_PER _SFR_MEM16(0x0866) |
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#define | TCC1_CCA _SFR_MEM16(0x0868) |
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#define | TCC1_CCB _SFR_MEM16(0x086A) |
|
#define | TCC1_PERBUF _SFR_MEM16(0x0876) |
|
#define | TCC1_CCABUF _SFR_MEM16(0x0878) |
|
#define | TCC1_CCBBUF _SFR_MEM16(0x087A) |
|
#define | AWEXC_CTRL _SFR_MEM8(0x0880) |
|
#define | AWEXC_FDEVMASK _SFR_MEM8(0x0882) |
|
#define | AWEXC_FDCTRL _SFR_MEM8(0x0883) |
|
#define | AWEXC_STATUS _SFR_MEM8(0x0884) |
|
#define | AWEXC_DTBOTH _SFR_MEM8(0x0886) |
|
#define | AWEXC_DTBOTHBUF _SFR_MEM8(0x0887) |
|
#define | AWEXC_DTLS _SFR_MEM8(0x0888) |
|
#define | AWEXC_DTHS _SFR_MEM8(0x0889) |
|
#define | AWEXC_DTLSBUF _SFR_MEM8(0x088A) |
|
#define | AWEXC_DTHSBUF _SFR_MEM8(0x088B) |
|
#define | AWEXC_OUTOVEN _SFR_MEM8(0x088C) |
|
#define | HIRESC_CTRL _SFR_MEM8(0x0890) |
|
#define | USARTC0_DATA _SFR_MEM8(0x08A0) |
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#define | USARTC0_STATUS _SFR_MEM8(0x08A1) |
|
#define | USARTC0_CTRLA _SFR_MEM8(0x08A3) |
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#define | USARTC0_CTRLB _SFR_MEM8(0x08A4) |
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#define | USARTC0_CTRLC _SFR_MEM8(0x08A5) |
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#define | USARTC0_BAUDCTRLA _SFR_MEM8(0x08A6) |
|
#define | USARTC0_BAUDCTRLB _SFR_MEM8(0x08A7) |
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#define | USARTC1_DATA _SFR_MEM8(0x08B0) |
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#define | USARTC1_STATUS _SFR_MEM8(0x08B1) |
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#define | USARTC1_CTRLA _SFR_MEM8(0x08B3) |
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#define | USARTC1_CTRLB _SFR_MEM8(0x08B4) |
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#define | USARTC1_CTRLC _SFR_MEM8(0x08B5) |
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#define | USARTC1_BAUDCTRLA _SFR_MEM8(0x08B6) |
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#define | USARTC1_BAUDCTRLB _SFR_MEM8(0x08B7) |
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#define | SPIC_CTRL _SFR_MEM8(0x08C0) |
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#define | SPIC_INTCTRL _SFR_MEM8(0x08C1) |
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#define | SPIC_STATUS _SFR_MEM8(0x08C2) |
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#define | SPIC_DATA _SFR_MEM8(0x08C3) |
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#define | IRCOM_CTRL _SFR_MEM8(0x08F8) |
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#define | IRCOM_TXPLCTRL _SFR_MEM8(0x08F9) |
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#define | IRCOM_RXPLCTRL _SFR_MEM8(0x08FA) |
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#define | TCD0_CTRLA _SFR_MEM8(0x0900) |
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#define | TCD0_CTRLB _SFR_MEM8(0x0901) |
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#define | TCD0_CTRLC _SFR_MEM8(0x0902) |
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#define | TCD0_CTRLD _SFR_MEM8(0x0903) |
|
#define | TCD0_CTRLE _SFR_MEM8(0x0904) |
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#define | TCD0_INTCTRLA _SFR_MEM8(0x0906) |
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#define | TCD0_INTCTRLB _SFR_MEM8(0x0907) |
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#define | TCD0_CTRLFCLR _SFR_MEM8(0x0908) |
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#define | TCD0_CTRLFSET _SFR_MEM8(0x0909) |
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#define | TCD0_CTRLGCLR _SFR_MEM8(0x090A) |
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#define | TCD0_CTRLGSET _SFR_MEM8(0x090B) |
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#define | TCD0_INTFLAGS _SFR_MEM8(0x090C) |
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#define | TCD0_TEMP _SFR_MEM8(0x090F) |
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#define | TCD0_CNT _SFR_MEM16(0x0920) |
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#define | TCD0_PER _SFR_MEM16(0x0926) |
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#define | TCD0_CCA _SFR_MEM16(0x0928) |
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#define | TCD0_CCB _SFR_MEM16(0x092A) |
|
#define | TCD0_CCC _SFR_MEM16(0x092C) |
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#define | TCD0_CCD _SFR_MEM16(0x092E) |
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#define | TCD0_PERBUF _SFR_MEM16(0x0936) |
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#define | TCD0_CCABUF _SFR_MEM16(0x0938) |
|
#define | TCD0_CCBBUF _SFR_MEM16(0x093A) |
|
#define | TCD0_CCCBUF _SFR_MEM16(0x093C) |
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#define | TCD0_CCDBUF _SFR_MEM16(0x093E) |
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#define | TCD1_CTRLA _SFR_MEM8(0x0940) |
|
#define | TCD1_CTRLB _SFR_MEM8(0x0941) |
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#define | TCD1_CTRLC _SFR_MEM8(0x0942) |
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#define | TCD1_CTRLD _SFR_MEM8(0x0943) |
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#define | TCD1_CTRLE _SFR_MEM8(0x0944) |
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#define | TCD1_INTCTRLA _SFR_MEM8(0x0946) |
|
#define | TCD1_INTCTRLB _SFR_MEM8(0x0947) |
|
#define | TCD1_CTRLFCLR _SFR_MEM8(0x0948) |
|
#define | TCD1_CTRLFSET _SFR_MEM8(0x0949) |
|
#define | TCD1_CTRLGCLR _SFR_MEM8(0x094A) |
|
#define | TCD1_CTRLGSET _SFR_MEM8(0x094B) |
|
#define | TCD1_INTFLAGS _SFR_MEM8(0x094C) |
|
#define | TCD1_TEMP _SFR_MEM8(0x094F) |
|
#define | TCD1_CNT _SFR_MEM16(0x0960) |
|
#define | TCD1_PER _SFR_MEM16(0x0966) |
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#define | TCD1_CCA _SFR_MEM16(0x0968) |
|
#define | TCD1_CCB _SFR_MEM16(0x096A) |
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#define | TCD1_PERBUF _SFR_MEM16(0x0976) |
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#define | TCD1_CCABUF _SFR_MEM16(0x0978) |
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#define | TCD1_CCBBUF _SFR_MEM16(0x097A) |
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#define | HIRESD_CTRL _SFR_MEM8(0x0990) |
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#define | USARTD0_DATA _SFR_MEM8(0x09A0) |
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#define | USARTD0_STATUS _SFR_MEM8(0x09A1) |
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#define | USARTD0_CTRLA _SFR_MEM8(0x09A3) |
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#define | USARTD0_CTRLB _SFR_MEM8(0x09A4) |
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#define | USARTD0_CTRLC _SFR_MEM8(0x09A5) |
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#define | USARTD0_BAUDCTRLA _SFR_MEM8(0x09A6) |
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#define | USARTD0_BAUDCTRLB _SFR_MEM8(0x09A7) |
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#define | USARTD1_DATA _SFR_MEM8(0x09B0) |
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#define | USARTD1_STATUS _SFR_MEM8(0x09B1) |
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#define | USARTD1_CTRLA _SFR_MEM8(0x09B3) |
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#define | USARTD1_CTRLB _SFR_MEM8(0x09B4) |
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#define | USARTD1_CTRLC _SFR_MEM8(0x09B5) |
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#define | USARTD1_BAUDCTRLA _SFR_MEM8(0x09B6) |
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#define | USARTD1_BAUDCTRLB _SFR_MEM8(0x09B7) |
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#define | SPID_CTRL _SFR_MEM8(0x09C0) |
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#define | SPID_INTCTRL _SFR_MEM8(0x09C1) |
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#define | SPID_STATUS _SFR_MEM8(0x09C2) |
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#define | SPID_DATA _SFR_MEM8(0x09C3) |
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#define | TCE0_CTRLA _SFR_MEM8(0x0A00) |
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#define | TCE0_CTRLB _SFR_MEM8(0x0A01) |
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#define | TCE0_CTRLC _SFR_MEM8(0x0A02) |
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#define | TCE0_CTRLD _SFR_MEM8(0x0A03) |
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#define | TCE0_CTRLE _SFR_MEM8(0x0A04) |
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#define | TCE0_INTCTRLA _SFR_MEM8(0x0A06) |
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#define | TCE0_INTCTRLB _SFR_MEM8(0x0A07) |
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#define | TCE0_CTRLFCLR _SFR_MEM8(0x0A08) |
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#define | TCE0_CTRLFSET _SFR_MEM8(0x0A09) |
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#define | TCE0_CTRLGCLR _SFR_MEM8(0x0A0A) |
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#define | TCE0_CTRLGSET _SFR_MEM8(0x0A0B) |
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#define | TCE0_INTFLAGS _SFR_MEM8(0x0A0C) |
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#define | TCE0_TEMP _SFR_MEM8(0x0A0F) |
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#define | TCE0_CNT _SFR_MEM16(0x0A20) |
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#define | TCE0_PER _SFR_MEM16(0x0A26) |
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#define | TCE0_CCA _SFR_MEM16(0x0A28) |
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#define | TCE0_CCB _SFR_MEM16(0x0A2A) |
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#define | TCE0_CCC _SFR_MEM16(0x0A2C) |
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#define | TCE0_CCD _SFR_MEM16(0x0A2E) |
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#define | TCE0_PERBUF _SFR_MEM16(0x0A36) |
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#define | TCE0_CCABUF _SFR_MEM16(0x0A38) |
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#define | TCE0_CCBBUF _SFR_MEM16(0x0A3A) |
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#define | TCE0_CCCBUF _SFR_MEM16(0x0A3C) |
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#define | TCE0_CCDBUF _SFR_MEM16(0x0A3E) |
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#define | HIRESE_CTRL _SFR_MEM8(0x0A90) |
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#define | USARTE0_DATA _SFR_MEM8(0x0AA0) |
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#define | USARTE0_STATUS _SFR_MEM8(0x0AA1) |
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#define | USARTE0_CTRLA _SFR_MEM8(0x0AA3) |
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#define | USARTE0_CTRLB _SFR_MEM8(0x0AA4) |
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#define | USARTE0_CTRLC _SFR_MEM8(0x0AA5) |
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#define | USARTE0_BAUDCTRLA _SFR_MEM8(0x0AA6) |
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#define | USARTE0_BAUDCTRLB _SFR_MEM8(0x0AA7) |
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#define | OCD_OCDRD_bm 0x01 /* OCDR Dirty bit mask. */ |
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#define | OCD_OCDRD_bp 0 /* OCDR Dirty bit position. */ |
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#define | CPU_CCP_gm 0xFF /* CCP signature group mask. */ |
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#define | CPU_CCP_gp 0 /* CCP signature group position. */ |
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#define | CPU_CCP0_bm (1<<0) /* CCP signature bit 0 mask. */ |
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#define | CPU_CCP0_bp 0 /* CCP signature bit 0 position. */ |
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#define | CPU_CCP1_bm (1<<1) /* CCP signature bit 1 mask. */ |
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#define | CPU_CCP1_bp 1 /* CCP signature bit 1 position. */ |
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#define | CPU_CCP2_bm (1<<2) /* CCP signature bit 2 mask. */ |
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#define | CPU_CCP2_bp 2 /* CCP signature bit 2 position. */ |
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#define | CPU_CCP3_bm (1<<3) /* CCP signature bit 3 mask. */ |
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#define | CPU_CCP3_bp 3 /* CCP signature bit 3 position. */ |
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#define | CPU_CCP4_bm (1<<4) /* CCP signature bit 4 mask. */ |
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#define | CPU_CCP4_bp 4 /* CCP signature bit 4 position. */ |
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#define | CPU_CCP5_bm (1<<5) /* CCP signature bit 5 mask. */ |
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#define | CPU_CCP5_bp 5 /* CCP signature bit 5 position. */ |
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#define | CPU_CCP6_bm (1<<6) /* CCP signature bit 6 mask. */ |
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#define | CPU_CCP6_bp 6 /* CCP signature bit 6 position. */ |
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#define | CPU_CCP7_bm (1<<7) /* CCP signature bit 7 mask. */ |
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#define | CPU_CCP7_bp 7 /* CCP signature bit 7 position. */ |
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#define | CPU_I_bm 0x80 /* Global Interrupt Enable Flag bit mask. */ |
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#define | CPU_I_bp 7 /* Global Interrupt Enable Flag bit position. */ |
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#define | CPU_T_bm 0x40 /* Transfer Bit bit mask. */ |
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#define | CPU_T_bp 6 /* Transfer Bit bit position. */ |
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#define | CPU_H_bm 0x20 /* Half Carry Flag bit mask. */ |
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#define | CPU_H_bp 5 /* Half Carry Flag bit position. */ |
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#define | CPU_S_bm 0x10 /* N Exclusive Or V Flag bit mask. */ |
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#define | CPU_S_bp 4 /* N Exclusive Or V Flag bit position. */ |
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#define | CPU_V_bm 0x08 /* Two's Complement Overflow Flag bit mask. */ |
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#define | CPU_V_bp 3 /* Two's Complement Overflow Flag bit position. */ |
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#define | CPU_N_bm 0x04 /* Negative Flag bit mask. */ |
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#define | CPU_N_bp 2 /* Negative Flag bit position. */ |
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#define | CPU_Z_bm 0x02 /* Zero Flag bit mask. */ |
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#define | CPU_Z_bp 1 /* Zero Flag bit position. */ |
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#define | CPU_C_bm 0x01 /* Carry Flag bit mask. */ |
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#define | CPU_C_bp 0 /* Carry Flag bit position. */ |
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#define | CLK_SCLKSEL_gm 0x07 /* System Clock Selection group mask. */ |
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#define | CLK_SCLKSEL_gp 0 /* System Clock Selection group position. */ |
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#define | CLK_SCLKSEL0_bm (1<<0) /* System Clock Selection bit 0 mask. */ |
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#define | CLK_SCLKSEL0_bp 0 /* System Clock Selection bit 0 position. */ |
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#define | CLK_SCLKSEL1_bm (1<<1) /* System Clock Selection bit 1 mask. */ |
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#define | CLK_SCLKSEL1_bp 1 /* System Clock Selection bit 1 position. */ |
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#define | CLK_SCLKSEL2_bm (1<<2) /* System Clock Selection bit 2 mask. */ |
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#define | CLK_SCLKSEL2_bp 2 /* System Clock Selection bit 2 position. */ |
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#define | CLK_PSADIV_gm 0x7C /* Prescaler A Division Factor group mask. */ |
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#define | CLK_PSADIV_gp 2 /* Prescaler A Division Factor group position. */ |
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#define | CLK_PSADIV0_bm (1<<2) /* Prescaler A Division Factor bit 0 mask. */ |
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#define | CLK_PSADIV0_bp 2 /* Prescaler A Division Factor bit 0 position. */ |
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#define | CLK_PSADIV1_bm (1<<3) /* Prescaler A Division Factor bit 1 mask. */ |
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#define | CLK_PSADIV1_bp 3 /* Prescaler A Division Factor bit 1 position. */ |
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#define | CLK_PSADIV2_bm (1<<4) /* Prescaler A Division Factor bit 2 mask. */ |
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#define | CLK_PSADIV2_bp 4 /* Prescaler A Division Factor bit 2 position. */ |
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#define | CLK_PSADIV3_bm (1<<5) /* Prescaler A Division Factor bit 3 mask. */ |
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#define | CLK_PSADIV3_bp 5 /* Prescaler A Division Factor bit 3 position. */ |
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#define | CLK_PSADIV4_bm (1<<6) /* Prescaler A Division Factor bit 4 mask. */ |
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#define | CLK_PSADIV4_bp 6 /* Prescaler A Division Factor bit 4 position. */ |
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#define | CLK_PSBCDIV_gm 0x03 /* Prescaler B and C Division factor group mask. */ |
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#define | CLK_PSBCDIV_gp 0 /* Prescaler B and C Division factor group position. */ |
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#define | CLK_PSBCDIV0_bm (1<<0) /* Prescaler B and C Division factor bit 0 mask. */ |
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#define | CLK_PSBCDIV0_bp 0 /* Prescaler B and C Division factor bit 0 position. */ |
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#define | CLK_PSBCDIV1_bm (1<<1) /* Prescaler B and C Division factor bit 1 mask. */ |
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#define | CLK_PSBCDIV1_bp 1 /* Prescaler B and C Division factor bit 1 position. */ |
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#define | CLK_LOCK_bm 0x01 /* Clock System Lock bit mask. */ |
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#define | CLK_LOCK_bp 0 /* Clock System Lock bit position. */ |
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#define | CLK_RTCSRC_gm 0x0E /* Clock Source group mask. */ |
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#define | CLK_RTCSRC_gp 1 /* Clock Source group position. */ |
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#define | CLK_RTCSRC0_bm (1<<1) /* Clock Source bit 0 mask. */ |
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#define | CLK_RTCSRC0_bp 1 /* Clock Source bit 0 position. */ |
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#define | CLK_RTCSRC1_bm (1<<2) /* Clock Source bit 1 mask. */ |
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#define | CLK_RTCSRC1_bp 2 /* Clock Source bit 1 position. */ |
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#define | CLK_RTCSRC2_bm (1<<3) /* Clock Source bit 2 mask. */ |
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#define | CLK_RTCSRC2_bp 3 /* Clock Source bit 2 position. */ |
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#define | CLK_RTCEN_bm 0x01 /* RTC Clock Source Enable bit mask. */ |
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#define | CLK_RTCEN_bp 0 /* RTC Clock Source Enable bit position. */ |
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#define | PR_AES_bm 0x10 /* AES bit mask. */ |
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#define | PR_AES_bp 4 /* AES bit position. */ |
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#define | PR_EBI_bm 0x08 /* External Bus Interface bit mask. */ |
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#define | PR_EBI_bp 3 /* External Bus Interface bit position. */ |
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#define | PR_RTC_bm 0x04 /* Real-time Counter bit mask. */ |
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#define | PR_RTC_bp 2 /* Real-time Counter bit position. */ |
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#define | PR_EVSYS_bm 0x02 /* Event System bit mask. */ |
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#define | PR_EVSYS_bp 1 /* Event System bit position. */ |
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#define | PR_DMA_bm 0x01 /* DMA-Controller bit mask. */ |
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#define | PR_DMA_bp 0 /* DMA-Controller bit position. */ |
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#define | PR_DAC_bm 0x04 /* Port A DAC bit mask. */ |
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#define | PR_DAC_bp 2 /* Port A DAC bit position. */ |
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#define | PR_ADC_bm 0x02 /* Port A ADC bit mask. */ |
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#define | PR_ADC_bp 1 /* Port A ADC bit position. */ |
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#define | PR_AC_bm 0x01 /* Port A Analog Comparator bit mask. */ |
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#define | PR_AC_bp 0 /* Port A Analog Comparator bit position. */ |
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#define | PR_TWI_bm 0x40 /* Port C Two-wire Interface bit mask. */ |
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#define | PR_TWI_bp 6 /* Port C Two-wire Interface bit position. */ |
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#define | PR_USART1_bm 0x20 /* Port C USART1 bit mask. */ |
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#define | PR_USART1_bp 5 /* Port C USART1 bit position. */ |
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#define | PR_USART0_bm 0x10 /* Port C USART0 bit mask. */ |
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#define | PR_USART0_bp 4 /* Port C USART0 bit position. */ |
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#define | PR_SPI_bm 0x08 /* Port C SPI bit mask. */ |
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#define | PR_SPI_bp 3 /* Port C SPI bit position. */ |
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#define | PR_HIRES_bm 0x04 /* Port C AWEX bit mask. */ |
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#define | PR_HIRES_bp 2 /* Port C AWEX bit position. */ |
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#define | PR_TC1_bm 0x02 /* Port C Timer/Counter1 bit mask. */ |
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#define | PR_TC1_bp 1 /* Port C Timer/Counter1 bit position. */ |
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#define | PR_TC0_bm 0x01 /* Port C Timer/Counter0 bit mask. */ |
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#define | PR_TC0_bp 0 /* Port C Timer/Counter0 bit position. */ |
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#define | SLEEP_SMODE_gm 0x0E /* Sleep Mode group mask. */ |
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#define | SLEEP_SMODE_gp 1 /* Sleep Mode group position. */ |
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#define | SLEEP_SMODE0_bm (1<<1) /* Sleep Mode bit 0 mask. */ |
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#define | SLEEP_SMODE0_bp 1 /* Sleep Mode bit 0 position. */ |
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#define | SLEEP_SMODE1_bm (1<<2) /* Sleep Mode bit 1 mask. */ |
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#define | SLEEP_SMODE1_bp 2 /* Sleep Mode bit 1 position. */ |
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#define | SLEEP_SMODE2_bm (1<<3) /* Sleep Mode bit 2 mask. */ |
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#define | SLEEP_SMODE2_bp 3 /* Sleep Mode bit 2 position. */ |
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#define | SLEEP_SEN_bm 0x01 /* Sleep Enable bit mask. */ |
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#define | SLEEP_SEN_bp 0 /* Sleep Enable bit position. */ |
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#define | OSC_PLLEN_bm 0x10 /* PLL Enable bit mask. */ |
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#define | OSC_PLLEN_bp 4 /* PLL Enable bit position. */ |
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#define | OSC_XOSCEN_bm 0x08 /* External Oscillator Enable bit mask. */ |
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#define | OSC_XOSCEN_bp 3 /* External Oscillator Enable bit position. */ |
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#define | OSC_RC32KEN_bm 0x04 /* Internal 32kHz RC Oscillator Enable bit mask. */ |
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#define | OSC_RC32KEN_bp 2 /* Internal 32kHz RC Oscillator Enable bit position. */ |
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#define | OSC_RC32MEN_bm 0x02 /* Internal 32MHz RC Oscillator Enable bit mask. */ |
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#define | OSC_RC32MEN_bp 1 /* Internal 32MHz RC Oscillator Enable bit position. */ |
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#define | OSC_RC2MEN_bm 0x01 /* Internal 2MHz RC Oscillator Enable bit mask. */ |
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#define | OSC_RC2MEN_bp 0 /* Internal 2MHz RC Oscillator Enable bit position. */ |
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#define | OSC_PLLRDY_bm 0x10 /* PLL Ready bit mask. */ |
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#define | OSC_PLLRDY_bp 4 /* PLL Ready bit position. */ |
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#define | OSC_XOSCRDY_bm 0x08 /* External Oscillator Ready bit mask. */ |
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#define | OSC_XOSCRDY_bp 3 /* External Oscillator Ready bit position. */ |
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#define | OSC_RC32KRDY_bm 0x04 /* Internal 32kHz RC Oscillator Ready bit mask. */ |
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#define | OSC_RC32KRDY_bp 2 /* Internal 32kHz RC Oscillator Ready bit position. */ |
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#define | OSC_RC32MRDY_bm 0x02 /* Internal 32MHz RC Oscillator Ready bit mask. */ |
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#define | OSC_RC32MRDY_bp 1 /* Internal 32MHz RC Oscillator Ready bit position. */ |
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#define | OSC_RC2MRDY_bm 0x01 /* Internal 2MHz RC Oscillator Ready bit mask. */ |
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#define | OSC_RC2MRDY_bp 0 /* Internal 2MHz RC Oscillator Ready bit position. */ |
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#define | OSC_FRQRANGE_gm 0xC0 /* Frequency Range group mask. */ |
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#define | OSC_FRQRANGE_gp 6 /* Frequency Range group position. */ |
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#define | OSC_FRQRANGE0_bm (1<<6) /* Frequency Range bit 0 mask. */ |
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#define | OSC_FRQRANGE0_bp 6 /* Frequency Range bit 0 position. */ |
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#define | OSC_FRQRANGE1_bm (1<<7) /* Frequency Range bit 1 mask. */ |
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#define | OSC_FRQRANGE1_bp 7 /* Frequency Range bit 1 position. */ |
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#define | OSC_X32KLPM_bm 0x20 /* 32kHz XTAL OSC Low-power Mode bit mask. */ |
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#define | OSC_X32KLPM_bp 5 /* 32kHz XTAL OSC Low-power Mode bit position. */ |
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#define | OSC_XOSCSEL_gm 0x0F /* External Oscillator Selection and Startup Time group mask. */ |
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#define | OSC_XOSCSEL_gp 0 /* External Oscillator Selection and Startup Time group position. */ |
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#define | OSC_XOSCSEL0_bm (1<<0) /* External Oscillator Selection and Startup Time bit 0 mask. */ |
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#define | OSC_XOSCSEL0_bp 0 /* External Oscillator Selection and Startup Time bit 0 position. */ |
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#define | OSC_XOSCSEL1_bm (1<<1) /* External Oscillator Selection and Startup Time bit 1 mask. */ |
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#define | OSC_XOSCSEL1_bp 1 /* External Oscillator Selection and Startup Time bit 1 position. */ |
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#define | OSC_XOSCSEL2_bm (1<<2) /* External Oscillator Selection and Startup Time bit 2 mask. */ |
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#define | OSC_XOSCSEL2_bp 2 /* External Oscillator Selection and Startup Time bit 2 position. */ |
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#define | OSC_XOSCSEL3_bm (1<<3) /* External Oscillator Selection and Startup Time bit 3 mask. */ |
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#define | OSC_XOSCSEL3_bp 3 /* External Oscillator Selection and Startup Time bit 3 position. */ |
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#define | OSC_XOSCFDIF_bm 0x02 /* Failure Detection Interrupt Flag bit mask. */ |
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#define | OSC_XOSCFDIF_bp 1 /* Failure Detection Interrupt Flag bit position. */ |
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#define | OSC_XOSCFDEN_bm 0x01 /* Failure Detection Enable bit mask. */ |
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#define | OSC_XOSCFDEN_bp 0 /* Failure Detection Enable bit position. */ |
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#define | OSC_PLLSRC_gm 0xC0 /* Clock Source group mask. */ |
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#define | OSC_PLLSRC_gp 6 /* Clock Source group position. */ |
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#define | OSC_PLLSRC0_bm (1<<6) /* Clock Source bit 0 mask. */ |
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#define | OSC_PLLSRC0_bp 6 /* Clock Source bit 0 position. */ |
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#define | OSC_PLLSRC1_bm (1<<7) /* Clock Source bit 1 mask. */ |
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#define | OSC_PLLSRC1_bp 7 /* Clock Source bit 1 position. */ |
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#define | OSC_PLLFAC_gm 0x1F /* Multiplication Factor group mask. */ |
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#define | OSC_PLLFAC_gp 0 /* Multiplication Factor group position. */ |
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#define | OSC_PLLFAC0_bm (1<<0) /* Multiplication Factor bit 0 mask. */ |
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#define | OSC_PLLFAC0_bp 0 /* Multiplication Factor bit 0 position. */ |
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#define | OSC_PLLFAC1_bm (1<<1) /* Multiplication Factor bit 1 mask. */ |
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#define | OSC_PLLFAC1_bp 1 /* Multiplication Factor bit 1 position. */ |
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#define | OSC_PLLFAC2_bm (1<<2) /* Multiplication Factor bit 2 mask. */ |
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#define | OSC_PLLFAC2_bp 2 /* Multiplication Factor bit 2 position. */ |
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#define | OSC_PLLFAC3_bm (1<<3) /* Multiplication Factor bit 3 mask. */ |
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#define | OSC_PLLFAC3_bp 3 /* Multiplication Factor bit 3 position. */ |
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#define | OSC_PLLFAC4_bm (1<<4) /* Multiplication Factor bit 4 mask. */ |
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#define | OSC_PLLFAC4_bp 4 /* Multiplication Factor bit 4 position. */ |
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#define | OSC_RC32MCREF_bm 0x02 /* 32MHz Calibration Reference bit mask. */ |
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#define | OSC_RC32MCREF_bp 1 /* 32MHz Calibration Reference bit position. */ |
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#define | OSC_RC2MCREF_bm 0x01 /* 2MHz Calibration Reference bit mask. */ |
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#define | OSC_RC2MCREF_bp 0 /* 2MHz Calibration Reference bit position. */ |
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#define | DFLL_ENABLE_bm 0x01 /* DFLL Enable bit mask. */ |
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#define | DFLL_ENABLE_bp 0 /* DFLL Enable bit position. */ |
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#define | DFLL_CALL_gm 0x7F /* DFLL Calibration bits [6:0] group mask. */ |
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#define | DFLL_CALL_gp 0 /* DFLL Calibration bits [6:0] group position. */ |
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#define | DFLL_CALL0_bm (1<<0) /* DFLL Calibration bits [6:0] bit 0 mask. */ |
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#define | DFLL_CALL0_bp 0 /* DFLL Calibration bits [6:0] bit 0 position. */ |
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#define | DFLL_CALL1_bm (1<<1) /* DFLL Calibration bits [6:0] bit 1 mask. */ |
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#define | DFLL_CALL1_bp 1 /* DFLL Calibration bits [6:0] bit 1 position. */ |
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#define | DFLL_CALL2_bm (1<<2) /* DFLL Calibration bits [6:0] bit 2 mask. */ |
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#define | DFLL_CALL2_bp 2 /* DFLL Calibration bits [6:0] bit 2 position. */ |
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#define | DFLL_CALL3_bm (1<<3) /* DFLL Calibration bits [6:0] bit 3 mask. */ |
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#define | DFLL_CALL3_bp 3 /* DFLL Calibration bits [6:0] bit 3 position. */ |
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#define | DFLL_CALL4_bm (1<<4) /* DFLL Calibration bits [6:0] bit 4 mask. */ |
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#define | DFLL_CALL4_bp 4 /* DFLL Calibration bits [6:0] bit 4 position. */ |
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#define | DFLL_CALL5_bm (1<<5) /* DFLL Calibration bits [6:0] bit 5 mask. */ |
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#define | DFLL_CALL5_bp 5 /* DFLL Calibration bits [6:0] bit 5 position. */ |
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#define | DFLL_CALL6_bm (1<<6) /* DFLL Calibration bits [6:0] bit 6 mask. */ |
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#define | DFLL_CALL6_bp 6 /* DFLL Calibration bits [6:0] bit 6 position. */ |
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#define | DFLL_CALH_gm 0x3F /* DFLL Calibration bits [12:7] group mask. */ |
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#define | DFLL_CALH_gp 0 /* DFLL Calibration bits [12:7] group position. */ |
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#define | DFLL_CALH0_bm (1<<0) /* DFLL Calibration bits [12:7] bit 0 mask. */ |
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#define | DFLL_CALH0_bp 0 /* DFLL Calibration bits [12:7] bit 0 position. */ |
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#define | DFLL_CALH1_bm (1<<1) /* DFLL Calibration bits [12:7] bit 1 mask. */ |
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#define | DFLL_CALH1_bp 1 /* DFLL Calibration bits [12:7] bit 1 position. */ |
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#define | DFLL_CALH2_bm (1<<2) /* DFLL Calibration bits [12:7] bit 2 mask. */ |
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#define | DFLL_CALH2_bp 2 /* DFLL Calibration bits [12:7] bit 2 position. */ |
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#define | DFLL_CALH3_bm (1<<3) /* DFLL Calibration bits [12:7] bit 3 mask. */ |
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#define | DFLL_CALH3_bp 3 /* DFLL Calibration bits [12:7] bit 3 position. */ |
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#define | DFLL_CALH4_bm (1<<4) /* DFLL Calibration bits [12:7] bit 4 mask. */ |
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#define | DFLL_CALH4_bp 4 /* DFLL Calibration bits [12:7] bit 4 position. */ |
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#define | DFLL_CALH5_bm (1<<5) /* DFLL Calibration bits [12:7] bit 5 mask. */ |
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#define | DFLL_CALH5_bp 5 /* DFLL Calibration bits [12:7] bit 5 position. */ |
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#define | RST_SDRF_bm 0x40 /* Spike Detection Reset Flag bit mask. */ |
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#define | RST_SDRF_bp 6 /* Spike Detection Reset Flag bit position. */ |
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#define | RST_SRF_bm 0x20 /* Software Reset Flag bit mask. */ |
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#define | RST_SRF_bp 5 /* Software Reset Flag bit position. */ |
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#define | RST_PDIRF_bm 0x10 /* Programming and Debug Interface Interface Reset Flag bit mask. */ |
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#define | RST_PDIRF_bp 4 /* Programming and Debug Interface Interface Reset Flag bit position. */ |
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#define | RST_WDRF_bm 0x08 /* Watchdog Reset Flag bit mask. */ |
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#define | RST_WDRF_bp 3 /* Watchdog Reset Flag bit position. */ |
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#define | RST_BORF_bm 0x04 /* Brown-out Reset Flag bit mask. */ |
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#define | RST_BORF_bp 2 /* Brown-out Reset Flag bit position. */ |
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#define | RST_EXTRF_bm 0x02 /* External Reset Flag bit mask. */ |
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#define | RST_EXTRF_bp 1 /* External Reset Flag bit position. */ |
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#define | RST_PORF_bm 0x01 /* Power-on Reset Flag bit mask. */ |
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#define | RST_PORF_bp 0 /* Power-on Reset Flag bit position. */ |
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#define | RST_SWRST_bm 0x01 /* Software Reset bit mask. */ |
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#define | RST_SWRST_bp 0 /* Software Reset bit position. */ |
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#define | WDT_PER_gm 0x3C /* Period group mask. */ |
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#define | WDT_PER_gp 2 /* Period group position. */ |
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#define | WDT_PER0_bm (1<<2) /* Period bit 0 mask. */ |
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#define | WDT_PER0_bp 2 /* Period bit 0 position. */ |
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#define | WDT_PER1_bm (1<<3) /* Period bit 1 mask. */ |
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#define | WDT_PER1_bp 3 /* Period bit 1 position. */ |
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#define | WDT_PER2_bm (1<<4) /* Period bit 2 mask. */ |
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#define | WDT_PER2_bp 4 /* Period bit 2 position. */ |
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#define | WDT_PER3_bm (1<<5) /* Period bit 3 mask. */ |
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#define | WDT_PER3_bp 5 /* Period bit 3 position. */ |
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#define | WDT_ENABLE_bm 0x02 /* Enable bit mask. */ |
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#define | WDT_ENABLE_bp 1 /* Enable bit position. */ |
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#define | WDT_CEN_bm 0x01 /* Change Enable bit mask. */ |
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#define | WDT_CEN_bp 0 /* Change Enable bit position. */ |
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#define | WDT_WPER_gm 0x3C /* Windowed Mode Period group mask. */ |
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#define | WDT_WPER_gp 2 /* Windowed Mode Period group position. */ |
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#define | WDT_WPER0_bm (1<<2) /* Windowed Mode Period bit 0 mask. */ |
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#define | WDT_WPER0_bp 2 /* Windowed Mode Period bit 0 position. */ |
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#define | WDT_WPER1_bm (1<<3) /* Windowed Mode Period bit 1 mask. */ |
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#define | WDT_WPER1_bp 3 /* Windowed Mode Period bit 1 position. */ |
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#define | WDT_WPER2_bm (1<<4) /* Windowed Mode Period bit 2 mask. */ |
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#define | WDT_WPER2_bp 4 /* Windowed Mode Period bit 2 position. */ |
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#define | WDT_WPER3_bm (1<<5) /* Windowed Mode Period bit 3 mask. */ |
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#define | WDT_WPER3_bp 5 /* Windowed Mode Period bit 3 position. */ |
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#define | WDT_WEN_bm 0x02 /* Windowed Mode Enable bit mask. */ |
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#define | WDT_WEN_bp 1 /* Windowed Mode Enable bit position. */ |
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#define | WDT_WCEN_bm 0x01 /* Windowed Mode Change Enable bit mask. */ |
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#define | WDT_WCEN_bp 0 /* Windowed Mode Change Enable bit position. */ |
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#define | WDT_SYNCBUSY_bm 0x01 /* Syncronization busy bit mask. */ |
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#define | WDT_SYNCBUSY_bp 0 /* Syncronization busy bit position. */ |
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#define | MCU_JTAGD_bm 0x01 /* JTAG Disable bit mask. */ |
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#define | MCU_JTAGD_bp 0 /* JTAG Disable bit position. */ |
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#define | MCU_EVSYS1LOCK_bm 0x10 /* Event Channel 4-7 Lock bit mask. */ |
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#define | MCU_EVSYS1LOCK_bp 4 /* Event Channel 4-7 Lock bit position. */ |
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#define | MCU_EVSYS0LOCK_bm 0x01 /* Event Channel 0-3 Lock bit mask. */ |
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#define | MCU_EVSYS0LOCK_bp 0 /* Event Channel 0-3 Lock bit position. */ |
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#define | MCU_AWEXELOCK_bm 0x04 /* AWeX on T/C E0 Lock bit mask. */ |
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#define | MCU_AWEXELOCK_bp 2 /* AWeX on T/C E0 Lock bit position. */ |
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#define | MCU_AWEXCLOCK_bm 0x01 /* AWeX on T/C C0 Lock bit mask. */ |
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#define | MCU_AWEXCLOCK_bp 0 /* AWeX on T/C C0 Lock bit position. */ |
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#define | PMIC_NMIEX_bm 0x80 /* Non-maskable Interrupt Executing bit mask. */ |
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#define | PMIC_NMIEX_bp 7 /* Non-maskable Interrupt Executing bit position. */ |
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#define | PMIC_HILVLEX_bm 0x04 /* High Level Interrupt Executing bit mask. */ |
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#define | PMIC_HILVLEX_bp 2 /* High Level Interrupt Executing bit position. */ |
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#define | PMIC_MEDLVLEX_bm 0x02 /* Medium Level Interrupt Executing bit mask. */ |
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#define | PMIC_MEDLVLEX_bp 1 /* Medium Level Interrupt Executing bit position. */ |
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#define | PMIC_LOLVLEX_bm 0x01 /* Low Level Interrupt Executing bit mask. */ |
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#define | PMIC_LOLVLEX_bp 0 /* Low Level Interrupt Executing bit position. */ |
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#define | PMIC_RREN_bm 0x80 /* Round-Robin Priority Enable bit mask. */ |
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#define | PMIC_RREN_bp 7 /* Round-Robin Priority Enable bit position. */ |
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#define | PMIC_IVSEL_bm 0x40 /* Interrupt Vector Select bit mask. */ |
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#define | PMIC_IVSEL_bp 6 /* Interrupt Vector Select bit position. */ |
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#define | PMIC_HILVLEN_bm 0x04 /* High Level Enable bit mask. */ |
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#define | PMIC_HILVLEN_bp 2 /* High Level Enable bit position. */ |
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#define | PMIC_MEDLVLEN_bm 0x02 /* Medium Level Enable bit mask. */ |
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#define | PMIC_MEDLVLEN_bp 1 /* Medium Level Enable bit position. */ |
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#define | PMIC_LOLVLEN_bm 0x01 /* Low Level Enable bit mask. */ |
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#define | PMIC_LOLVLEN_bp 0 /* Low Level Enable bit position. */ |
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#define | DMA_CH_ENABLE_bm 0x80 /* Channel Enable bit mask. */ |
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#define | DMA_CH_ENABLE_bp 7 /* Channel Enable bit position. */ |
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#define | DMA_CH_RESET_bm 0x40 /* Channel Software Reset bit mask. */ |
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#define | DMA_CH_RESET_bp 6 /* Channel Software Reset bit position. */ |
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#define | DMA_CH_REPEAT_bm 0x20 /* Channel Repeat Mode bit mask. */ |
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#define | DMA_CH_REPEAT_bp 5 /* Channel Repeat Mode bit position. */ |
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#define | DMA_CH_TRFREQ_bm 0x10 /* Channel Transfer Request bit mask. */ |
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#define | DMA_CH_TRFREQ_bp 4 /* Channel Transfer Request bit position. */ |
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#define | DMA_CH_SINGLE_bm 0x04 /* Channel Single Shot Data Transfer bit mask. */ |
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#define | DMA_CH_SINGLE_bp 2 /* Channel Single Shot Data Transfer bit position. */ |
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#define | DMA_CH_BURSTLEN_gm 0x03 /* Channel Transfer Mode group mask. */ |
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#define | DMA_CH_BURSTLEN_gp 0 /* Channel Transfer Mode group position. */ |
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#define | DMA_CH_BURSTLEN0_bm (1<<0) /* Channel Transfer Mode bit 0 mask. */ |
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#define | DMA_CH_BURSTLEN0_bp 0 /* Channel Transfer Mode bit 0 position. */ |
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#define | DMA_CH_BURSTLEN1_bm (1<<1) /* Channel Transfer Mode bit 1 mask. */ |
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#define | DMA_CH_BURSTLEN1_bp 1 /* Channel Transfer Mode bit 1 position. */ |
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#define | DMA_CH_CHBUSY_bm 0x80 /* Block Transfer Busy bit mask. */ |
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#define | DMA_CH_CHBUSY_bp 7 /* Block Transfer Busy bit position. */ |
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#define | DMA_CH_CHPEND_bm 0x40 /* Block Transfer Pending bit mask. */ |
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#define | DMA_CH_CHPEND_bp 6 /* Block Transfer Pending bit position. */ |
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#define | DMA_CH_ERRIF_bm 0x20 /* Block Transfer Error Interrupt Flag bit mask. */ |
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#define | DMA_CH_ERRIF_bp 5 /* Block Transfer Error Interrupt Flag bit position. */ |
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#define | DMA_CH_TRNIF_bm 0x10 /* Transaction Complete Interrup Flag bit mask. */ |
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#define | DMA_CH_TRNIF_bp 4 /* Transaction Complete Interrup Flag bit position. */ |
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#define | DMA_CH_ERRINTLVL_gm 0x0C /* Transfer Error Interrupt Level group mask. */ |
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#define | DMA_CH_ERRINTLVL_gp 2 /* Transfer Error Interrupt Level group position. */ |
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#define | DMA_CH_ERRINTLVL0_bm (1<<2) /* Transfer Error Interrupt Level bit 0 mask. */ |
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#define | DMA_CH_ERRINTLVL0_bp 2 /* Transfer Error Interrupt Level bit 0 position. */ |
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#define | DMA_CH_ERRINTLVL1_bm (1<<3) /* Transfer Error Interrupt Level bit 1 mask. */ |
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#define | DMA_CH_ERRINTLVL1_bp 3 /* Transfer Error Interrupt Level bit 1 position. */ |
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#define | DMA_CH_TRNINTLVL_gm 0x03 /* Transaction Complete Interrupt Level group mask. */ |
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#define | DMA_CH_TRNINTLVL_gp 0 /* Transaction Complete Interrupt Level group position. */ |
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#define | DMA_CH_TRNINTLVL0_bm (1<<0) /* Transaction Complete Interrupt Level bit 0 mask. */ |
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#define | DMA_CH_TRNINTLVL0_bp 0 /* Transaction Complete Interrupt Level bit 0 position. */ |
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#define | DMA_CH_TRNINTLVL1_bm (1<<1) /* Transaction Complete Interrupt Level bit 1 mask. */ |
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#define | DMA_CH_TRNINTLVL1_bp 1 /* Transaction Complete Interrupt Level bit 1 position. */ |
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#define | DMA_CH_SRCRELOAD_gm 0xC0 /* Channel Source Address Reload group mask. */ |
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#define | DMA_CH_SRCRELOAD_gp 6 /* Channel Source Address Reload group position. */ |
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#define | DMA_CH_SRCRELOAD0_bm (1<<6) /* Channel Source Address Reload bit 0 mask. */ |
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#define | DMA_CH_SRCRELOAD0_bp 6 /* Channel Source Address Reload bit 0 position. */ |
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#define | DMA_CH_SRCRELOAD1_bm (1<<7) /* Channel Source Address Reload bit 1 mask. */ |
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#define | DMA_CH_SRCRELOAD1_bp 7 /* Channel Source Address Reload bit 1 position. */ |
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#define | DMA_CH_SRCDIR_gm 0x30 /* Channel Source Address Mode group mask. */ |
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#define | DMA_CH_SRCDIR_gp 4 /* Channel Source Address Mode group position. */ |
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#define | DMA_CH_SRCDIR0_bm (1<<4) /* Channel Source Address Mode bit 0 mask. */ |
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#define | DMA_CH_SRCDIR0_bp 4 /* Channel Source Address Mode bit 0 position. */ |
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#define | DMA_CH_SRCDIR1_bm (1<<5) /* Channel Source Address Mode bit 1 mask. */ |
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#define | DMA_CH_SRCDIR1_bp 5 /* Channel Source Address Mode bit 1 position. */ |
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#define | DMA_CH_DESTRELOAD_gm 0x0C /* Channel Destination Address Reload group mask. */ |
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#define | DMA_CH_DESTRELOAD_gp 2 /* Channel Destination Address Reload group position. */ |
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#define | DMA_CH_DESTRELOAD0_bm (1<<2) /* Channel Destination Address Reload bit 0 mask. */ |
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#define | DMA_CH_DESTRELOAD0_bp 2 /* Channel Destination Address Reload bit 0 position. */ |
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#define | DMA_CH_DESTRELOAD1_bm (1<<3) /* Channel Destination Address Reload bit 1 mask. */ |
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#define | DMA_CH_DESTRELOAD1_bp 3 /* Channel Destination Address Reload bit 1 position. */ |
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#define | DMA_CH_DESTDIR_gm 0x03 /* Channel Destination Address Mode group mask. */ |
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#define | DMA_CH_DESTDIR_gp 0 /* Channel Destination Address Mode group position. */ |
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#define | DMA_CH_DESTDIR0_bm (1<<0) /* Channel Destination Address Mode bit 0 mask. */ |
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#define | DMA_CH_DESTDIR0_bp 0 /* Channel Destination Address Mode bit 0 position. */ |
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#define | DMA_CH_DESTDIR1_bm (1<<1) /* Channel Destination Address Mode bit 1 mask. */ |
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#define | DMA_CH_DESTDIR1_bp 1 /* Channel Destination Address Mode bit 1 position. */ |
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#define | DMA_CH_TRIGSRC_gm 0xFF /* Channel Trigger Source group mask. */ |
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#define | DMA_CH_TRIGSRC_gp 0 /* Channel Trigger Source group position. */ |
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#define | DMA_CH_TRIGSRC0_bm (1<<0) /* Channel Trigger Source bit 0 mask. */ |
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#define | DMA_CH_TRIGSRC0_bp 0 /* Channel Trigger Source bit 0 position. */ |
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#define | DMA_CH_TRIGSRC1_bm (1<<1) /* Channel Trigger Source bit 1 mask. */ |
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#define | DMA_CH_TRIGSRC1_bp 1 /* Channel Trigger Source bit 1 position. */ |
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#define | DMA_CH_TRIGSRC2_bm (1<<2) /* Channel Trigger Source bit 2 mask. */ |
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#define | DMA_CH_TRIGSRC2_bp 2 /* Channel Trigger Source bit 2 position. */ |
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#define | DMA_CH_TRIGSRC3_bm (1<<3) /* Channel Trigger Source bit 3 mask. */ |
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#define | DMA_CH_TRIGSRC3_bp 3 /* Channel Trigger Source bit 3 position. */ |
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#define | DMA_CH_TRIGSRC4_bm (1<<4) /* Channel Trigger Source bit 4 mask. */ |
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#define | DMA_CH_TRIGSRC4_bp 4 /* Channel Trigger Source bit 4 position. */ |
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#define | DMA_CH_TRIGSRC5_bm (1<<5) /* Channel Trigger Source bit 5 mask. */ |
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#define | DMA_CH_TRIGSRC5_bp 5 /* Channel Trigger Source bit 5 position. */ |
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#define | DMA_CH_TRIGSRC6_bm (1<<6) /* Channel Trigger Source bit 6 mask. */ |
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#define | DMA_CH_TRIGSRC6_bp 6 /* Channel Trigger Source bit 6 position. */ |
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#define | DMA_CH_TRIGSRC7_bm (1<<7) /* Channel Trigger Source bit 7 mask. */ |
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#define | DMA_CH_TRIGSRC7_bp 7 /* Channel Trigger Source bit 7 position. */ |
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#define | DMA_ENABLE_bm 0x80 /* Enable bit mask. */ |
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#define | DMA_ENABLE_bp 7 /* Enable bit position. */ |
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#define | DMA_RESET_bm 0x40 /* Software Reset bit mask. */ |
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#define | DMA_RESET_bp 6 /* Software Reset bit position. */ |
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#define | DMA_DBUFMODE_gm 0x0C /* Double Buffering Mode group mask. */ |
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#define | DMA_DBUFMODE_gp 2 /* Double Buffering Mode group position. */ |
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#define | DMA_DBUFMODE0_bm (1<<2) /* Double Buffering Mode bit 0 mask. */ |
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#define | DMA_DBUFMODE0_bp 2 /* Double Buffering Mode bit 0 position. */ |
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#define | DMA_DBUFMODE1_bm (1<<3) /* Double Buffering Mode bit 1 mask. */ |
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#define | DMA_DBUFMODE1_bp 3 /* Double Buffering Mode bit 1 position. */ |
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#define | DMA_PRIMODE_gm 0x03 /* Channel Priority Mode group mask. */ |
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#define | DMA_PRIMODE_gp 0 /* Channel Priority Mode group position. */ |
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#define | DMA_PRIMODE0_bm (1<<0) /* Channel Priority Mode bit 0 mask. */ |
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#define | DMA_PRIMODE0_bp 0 /* Channel Priority Mode bit 0 position. */ |
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#define | DMA_PRIMODE1_bm (1<<1) /* Channel Priority Mode bit 1 mask. */ |
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#define | DMA_PRIMODE1_bp 1 /* Channel Priority Mode bit 1 position. */ |
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#define | DMA_CH3ERRIF_bm 0x80 /* Channel 3 Block Transfer Error Interrupt Flag bit mask. */ |
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#define | DMA_CH3ERRIF_bp 7 /* Channel 3 Block Transfer Error Interrupt Flag bit position. */ |
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#define | DMA_CH2ERRIF_bm 0x40 /* Channel 2 Block Transfer Error Interrupt Flag bit mask. */ |
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#define | DMA_CH2ERRIF_bp 6 /* Channel 2 Block Transfer Error Interrupt Flag bit position. */ |
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#define | DMA_CH1ERRIF_bm 0x20 /* Channel 1 Block Transfer Error Interrupt Flag bit mask. */ |
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#define | DMA_CH1ERRIF_bp 5 /* Channel 1 Block Transfer Error Interrupt Flag bit position. */ |
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#define | DMA_CH0ERRIF_bm 0x10 /* Channel 0 Block Transfer Error Interrupt Flag bit mask. */ |
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#define | DMA_CH0ERRIF_bp 4 /* Channel 0 Block Transfer Error Interrupt Flag bit position. */ |
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#define | DMA_CH3TRNIF_bm 0x08 /* Channel 3 Transaction Complete Interrupt Flag bit mask. */ |
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#define | DMA_CH3TRNIF_bp 3 /* Channel 3 Transaction Complete Interrupt Flag bit position. */ |
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#define | DMA_CH2TRNIF_bm 0x04 /* Channel 2 Transaction Complete Interrupt Flag bit mask. */ |
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#define | DMA_CH2TRNIF_bp 2 /* Channel 2 Transaction Complete Interrupt Flag bit position. */ |
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#define | DMA_CH1TRNIF_bm 0x02 /* Channel 1 Transaction Complete Interrupt Flag bit mask. */ |
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#define | DMA_CH1TRNIF_bp 1 /* Channel 1 Transaction Complete Interrupt Flag bit position. */ |
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#define | DMA_CH0TRNIF_bm 0x01 /* Channel 0 Transaction Complete Interrupt Flag bit mask. */ |
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#define | DMA_CH0TRNIF_bp 0 /* Channel 0 Transaction Complete Interrupt Flag bit position. */ |
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#define | DMA_CH3BUSY_bm 0x80 /* Channel 3 Block Transfer Busy bit mask. */ |
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#define | DMA_CH3BUSY_bp 7 /* Channel 3 Block Transfer Busy bit position. */ |
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#define | DMA_CH2BUSY_bm 0x40 /* Channel 2 Block Transfer Busy bit mask. */ |
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#define | DMA_CH2BUSY_bp 6 /* Channel 2 Block Transfer Busy bit position. */ |
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#define | DMA_CH1BUSY_bm 0x20 /* Channel 1 Block Transfer Busy bit mask. */ |
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#define | DMA_CH1BUSY_bp 5 /* Channel 1 Block Transfer Busy bit position. */ |
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#define | DMA_CH0BUSY_bm 0x10 /* Channel 0 Block Transfer Busy bit mask. */ |
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#define | DMA_CH0BUSY_bp 4 /* Channel 0 Block Transfer Busy bit position. */ |
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#define | DMA_CH3PEND_bm 0x08 /* Channel 3 Block Transfer Pending bit mask. */ |
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#define | DMA_CH3PEND_bp 3 /* Channel 3 Block Transfer Pending bit position. */ |
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#define | DMA_CH2PEND_bm 0x04 /* Channel 2 Block Transfer Pending bit mask. */ |
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#define | DMA_CH2PEND_bp 2 /* Channel 2 Block Transfer Pending bit position. */ |
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#define | DMA_CH1PEND_bm 0x02 /* Channel 1 Block Transfer Pending bit mask. */ |
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#define | DMA_CH1PEND_bp 1 /* Channel 1 Block Transfer Pending bit position. */ |
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#define | DMA_CH0PEND_bm 0x01 /* Channel 0 Block Transfer Pending bit mask. */ |
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#define | DMA_CH0PEND_bp 0 /* Channel 0 Block Transfer Pending bit position. */ |
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#define | EVSYS_CHMUX_gm 0xFF /* Event Channel 0 Multiplexer group mask. */ |
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#define | EVSYS_CHMUX_gp 0 /* Event Channel 0 Multiplexer group position. */ |
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#define | EVSYS_CHMUX0_bm (1<<0) /* Event Channel 0 Multiplexer bit 0 mask. */ |
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#define | EVSYS_CHMUX0_bp 0 /* Event Channel 0 Multiplexer bit 0 position. */ |
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#define | EVSYS_CHMUX1_bm (1<<1) /* Event Channel 0 Multiplexer bit 1 mask. */ |
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#define | EVSYS_CHMUX1_bp 1 /* Event Channel 0 Multiplexer bit 1 position. */ |
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#define | EVSYS_CHMUX2_bm (1<<2) /* Event Channel 0 Multiplexer bit 2 mask. */ |
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#define | EVSYS_CHMUX2_bp 2 /* Event Channel 0 Multiplexer bit 2 position. */ |
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#define | EVSYS_CHMUX3_bm (1<<3) /* Event Channel 0 Multiplexer bit 3 mask. */ |
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#define | EVSYS_CHMUX3_bp 3 /* Event Channel 0 Multiplexer bit 3 position. */ |
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#define | EVSYS_CHMUX4_bm (1<<4) /* Event Channel 0 Multiplexer bit 4 mask. */ |
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#define | EVSYS_CHMUX4_bp 4 /* Event Channel 0 Multiplexer bit 4 position. */ |
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#define | EVSYS_CHMUX5_bm (1<<5) /* Event Channel 0 Multiplexer bit 5 mask. */ |
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#define | EVSYS_CHMUX5_bp 5 /* Event Channel 0 Multiplexer bit 5 position. */ |
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#define | EVSYS_CHMUX6_bm (1<<6) /* Event Channel 0 Multiplexer bit 6 mask. */ |
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#define | EVSYS_CHMUX6_bp 6 /* Event Channel 0 Multiplexer bit 6 position. */ |
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#define | EVSYS_CHMUX7_bm (1<<7) /* Event Channel 0 Multiplexer bit 7 mask. */ |
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#define | EVSYS_CHMUX7_bp 7 /* Event Channel 0 Multiplexer bit 7 position. */ |
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#define | EVSYS_QDIRM_gm 0x60 /* Quadrature Decoder Index Recognition Mode group mask. */ |
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#define | EVSYS_QDIRM_gp 5 /* Quadrature Decoder Index Recognition Mode group position. */ |
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#define | EVSYS_QDIRM0_bm (1<<5) /* Quadrature Decoder Index Recognition Mode bit 0 mask. */ |
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#define | EVSYS_QDIRM0_bp 5 /* Quadrature Decoder Index Recognition Mode bit 0 position. */ |
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#define | EVSYS_QDIRM1_bm (1<<6) /* Quadrature Decoder Index Recognition Mode bit 1 mask. */ |
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#define | EVSYS_QDIRM1_bp 6 /* Quadrature Decoder Index Recognition Mode bit 1 position. */ |
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#define | EVSYS_QDIEN_bm 0x10 /* Quadrature Decoder Index Enable bit mask. */ |
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#define | EVSYS_QDIEN_bp 4 /* Quadrature Decoder Index Enable bit position. */ |
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#define | EVSYS_QDEN_bm 0x08 /* Quadrature Decoder Enable bit mask. */ |
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#define | EVSYS_QDEN_bp 3 /* Quadrature Decoder Enable bit position. */ |
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#define | EVSYS_DIGFILT_gm 0x07 /* Digital Filter group mask. */ |
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#define | EVSYS_DIGFILT_gp 0 /* Digital Filter group position. */ |
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#define | EVSYS_DIGFILT0_bm (1<<0) /* Digital Filter bit 0 mask. */ |
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#define | EVSYS_DIGFILT0_bp 0 /* Digital Filter bit 0 position. */ |
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#define | EVSYS_DIGFILT1_bm (1<<1) /* Digital Filter bit 1 mask. */ |
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#define | EVSYS_DIGFILT1_bp 1 /* Digital Filter bit 1 position. */ |
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#define | EVSYS_DIGFILT2_bm (1<<2) /* Digital Filter bit 2 mask. */ |
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#define | EVSYS_DIGFILT2_bp 2 /* Digital Filter bit 2 position. */ |
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#define | NVM_CMD_gm 0xFF /* Command group mask. */ |
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#define | NVM_CMD_gp 0 /* Command group position. */ |
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#define | NVM_CMD0_bm (1<<0) /* Command bit 0 mask. */ |
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#define | NVM_CMD0_bp 0 /* Command bit 0 position. */ |
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#define | NVM_CMD1_bm (1<<1) /* Command bit 1 mask. */ |
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#define | NVM_CMD1_bp 1 /* Command bit 1 position. */ |
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#define | NVM_CMD2_bm (1<<2) /* Command bit 2 mask. */ |
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#define | NVM_CMD2_bp 2 /* Command bit 2 position. */ |
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#define | NVM_CMD3_bm (1<<3) /* Command bit 3 mask. */ |
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#define | NVM_CMD3_bp 3 /* Command bit 3 position. */ |
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#define | NVM_CMD4_bm (1<<4) /* Command bit 4 mask. */ |
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#define | NVM_CMD4_bp 4 /* Command bit 4 position. */ |
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#define | NVM_CMD5_bm (1<<5) /* Command bit 5 mask. */ |
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#define | NVM_CMD5_bp 5 /* Command bit 5 position. */ |
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#define | NVM_CMD6_bm (1<<6) /* Command bit 6 mask. */ |
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#define | NVM_CMD6_bp 6 /* Command bit 6 position. */ |
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#define | NVM_CMD7_bm (1<<7) /* Command bit 7 mask. */ |
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#define | NVM_CMD7_bp 7 /* Command bit 7 position. */ |
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#define | NVM_CMDEX_bm 0x01 /* Command Execute bit mask. */ |
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#define | NVM_CMDEX_bp 0 /* Command Execute bit position. */ |
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#define | NVM_EEMAPEN_bm 0x08 /* EEPROM Mapping Enable bit mask. */ |
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#define | NVM_EEMAPEN_bp 3 /* EEPROM Mapping Enable bit position. */ |
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#define | NVM_FPRM_bm 0x04 /* Flash Power Reduction Enable bit mask. */ |
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#define | NVM_FPRM_bp 2 /* Flash Power Reduction Enable bit position. */ |
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#define | NVM_EPRM_bm 0x02 /* EEPROM Power Reduction Enable bit mask. */ |
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#define | NVM_EPRM_bp 1 /* EEPROM Power Reduction Enable bit position. */ |
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#define | NVM_SPMLOCK_bm 0x01 /* SPM Lock bit mask. */ |
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#define | NVM_SPMLOCK_bp 0 /* SPM Lock bit position. */ |
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#define | NVM_SPMLVL_gm 0x0C /* SPM Interrupt Level group mask. */ |
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#define | NVM_SPMLVL_gp 2 /* SPM Interrupt Level group position. */ |
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#define | NVM_SPMLVL0_bm (1<<2) /* SPM Interrupt Level bit 0 mask. */ |
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#define | NVM_SPMLVL0_bp 2 /* SPM Interrupt Level bit 0 position. */ |
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#define | NVM_SPMLVL1_bm (1<<3) /* SPM Interrupt Level bit 1 mask. */ |
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#define | NVM_SPMLVL1_bp 3 /* SPM Interrupt Level bit 1 position. */ |
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#define | NVM_EELVL_gm 0x03 /* EEPROM Interrupt Level group mask. */ |
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#define | NVM_EELVL_gp 0 /* EEPROM Interrupt Level group position. */ |
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#define | NVM_EELVL0_bm (1<<0) /* EEPROM Interrupt Level bit 0 mask. */ |
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#define | NVM_EELVL0_bp 0 /* EEPROM Interrupt Level bit 0 position. */ |
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#define | NVM_EELVL1_bm (1<<1) /* EEPROM Interrupt Level bit 1 mask. */ |
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#define | NVM_EELVL1_bp 1 /* EEPROM Interrupt Level bit 1 position. */ |
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#define | NVM_NVMBUSY_bm 0x80 /* Non-volatile Memory Busy bit mask. */ |
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#define | NVM_NVMBUSY_bp 7 /* Non-volatile Memory Busy bit position. */ |
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#define | NVM_FBUSY_bm 0x40 /* Flash Memory Busy bit mask. */ |
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#define | NVM_FBUSY_bp 6 /* Flash Memory Busy bit position. */ |
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#define | NVM_EELOAD_bm 0x02 /* EEPROM Page Buffer Active Loading bit mask. */ |
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#define | NVM_EELOAD_bp 1 /* EEPROM Page Buffer Active Loading bit position. */ |
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#define | NVM_FLOAD_bm 0x01 /* Flash Page Buffer Active Loading bit mask. */ |
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#define | NVM_FLOAD_bp 0 /* Flash Page Buffer Active Loading bit position. */ |
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#define | NVM_BLBB_gm 0xC0 /* Boot Lock Bits - Boot Section group mask. */ |
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#define | NVM_BLBB_gp 6 /* Boot Lock Bits - Boot Section group position. */ |
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#define | NVM_BLBB0_bm (1<<6) /* Boot Lock Bits - Boot Section bit 0 mask. */ |
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#define | NVM_BLBB0_bp 6 /* Boot Lock Bits - Boot Section bit 0 position. */ |
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#define | NVM_BLBB1_bm (1<<7) /* Boot Lock Bits - Boot Section bit 1 mask. */ |
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#define | NVM_BLBB1_bp 7 /* Boot Lock Bits - Boot Section bit 1 position. */ |
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#define | NVM_BLBA_gm 0x30 /* Boot Lock Bits - Application Section group mask. */ |
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#define | NVM_BLBA_gp 4 /* Boot Lock Bits - Application Section group position. */ |
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#define | NVM_BLBA0_bm (1<<4) /* Boot Lock Bits - Application Section bit 0 mask. */ |
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#define | NVM_BLBA0_bp 4 /* Boot Lock Bits - Application Section bit 0 position. */ |
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#define | NVM_BLBA1_bm (1<<5) /* Boot Lock Bits - Application Section bit 1 mask. */ |
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#define | NVM_BLBA1_bp 5 /* Boot Lock Bits - Application Section bit 1 position. */ |
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#define | NVM_BLBAT_gm 0x0C /* Boot Lock Bits - Application Table group mask. */ |
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#define | NVM_BLBAT_gp 2 /* Boot Lock Bits - Application Table group position. */ |
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#define | NVM_BLBAT0_bm (1<<2) /* Boot Lock Bits - Application Table bit 0 mask. */ |
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#define | NVM_BLBAT0_bp 2 /* Boot Lock Bits - Application Table bit 0 position. */ |
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#define | NVM_BLBAT1_bm (1<<3) /* Boot Lock Bits - Application Table bit 1 mask. */ |
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#define | NVM_BLBAT1_bp 3 /* Boot Lock Bits - Application Table bit 1 position. */ |
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#define | NVM_LB_gm 0x03 /* Lock Bits group mask. */ |
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#define | NVM_LB_gp 0 /* Lock Bits group position. */ |
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#define | NVM_LB0_bm (1<<0) /* Lock Bits bit 0 mask. */ |
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#define | NVM_LB0_bp 0 /* Lock Bits bit 0 position. */ |
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#define | NVM_LB1_bm (1<<1) /* Lock Bits bit 1 mask. */ |
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#define | NVM_LB1_bp 1 /* Lock Bits bit 1 position. */ |
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#define | NVM_LOCKBITS_BLBB_gm 0xC0 /* Boot Lock Bits - Boot Section group mask. */ |
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#define | NVM_LOCKBITS_BLBB_gp 6 /* Boot Lock Bits - Boot Section group position. */ |
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#define | NVM_LOCKBITS_BLBB0_bm (1<<6) /* Boot Lock Bits - Boot Section bit 0 mask. */ |
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#define | NVM_LOCKBITS_BLBB0_bp 6 /* Boot Lock Bits - Boot Section bit 0 position. */ |
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#define | NVM_LOCKBITS_BLBB1_bm (1<<7) /* Boot Lock Bits - Boot Section bit 1 mask. */ |
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#define | NVM_LOCKBITS_BLBB1_bp 7 /* Boot Lock Bits - Boot Section bit 1 position. */ |
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#define | NVM_LOCKBITS_BLBA_gm 0x30 /* Boot Lock Bits - Application Section group mask. */ |
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#define | NVM_LOCKBITS_BLBA_gp 4 /* Boot Lock Bits - Application Section group position. */ |
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#define | NVM_LOCKBITS_BLBA0_bm (1<<4) /* Boot Lock Bits - Application Section bit 0 mask. */ |
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#define | NVM_LOCKBITS_BLBA0_bp 4 /* Boot Lock Bits - Application Section bit 0 position. */ |
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#define | NVM_LOCKBITS_BLBA1_bm (1<<5) /* Boot Lock Bits - Application Section bit 1 mask. */ |
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#define | NVM_LOCKBITS_BLBA1_bp 5 /* Boot Lock Bits - Application Section bit 1 position. */ |
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#define | NVM_LOCKBITS_BLBAT_gm 0x0C /* Boot Lock Bits - Application Table group mask. */ |
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#define | NVM_LOCKBITS_BLBAT_gp 2 /* Boot Lock Bits - Application Table group position. */ |
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#define | NVM_LOCKBITS_BLBAT0_bm (1<<2) /* Boot Lock Bits - Application Table bit 0 mask. */ |
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#define | NVM_LOCKBITS_BLBAT0_bp 2 /* Boot Lock Bits - Application Table bit 0 position. */ |
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#define | NVM_LOCKBITS_BLBAT1_bm (1<<3) /* Boot Lock Bits - Application Table bit 1 mask. */ |
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#define | NVM_LOCKBITS_BLBAT1_bp 3 /* Boot Lock Bits - Application Table bit 1 position. */ |
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#define | NVM_LOCKBITS_LB_gm 0x03 /* Lock Bits group mask. */ |
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#define | NVM_LOCKBITS_LB_gp 0 /* Lock Bits group position. */ |
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#define | NVM_LOCKBITS_LB0_bm (1<<0) /* Lock Bits bit 0 mask. */ |
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#define | NVM_LOCKBITS_LB0_bp 0 /* Lock Bits bit 0 position. */ |
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#define | NVM_LOCKBITS_LB1_bm (1<<1) /* Lock Bits bit 1 mask. */ |
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#define | NVM_LOCKBITS_LB1_bp 1 /* Lock Bits bit 1 position. */ |
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#define | NVM_FUSES_USERID_gm 0xFF /* User ID group mask. */ |
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#define | NVM_FUSES_USERID_gp 0 /* User ID group position. */ |
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#define | NVM_FUSES_USERID0_bm (1<<0) /* User ID bit 0 mask. */ |
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#define | NVM_FUSES_USERID0_bp 0 /* User ID bit 0 position. */ |
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#define | NVM_FUSES_USERID1_bm (1<<1) /* User ID bit 1 mask. */ |
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#define | NVM_FUSES_USERID1_bp 1 /* User ID bit 1 position. */ |
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#define | NVM_FUSES_USERID2_bm (1<<2) /* User ID bit 2 mask. */ |
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#define | NVM_FUSES_USERID2_bp 2 /* User ID bit 2 position. */ |
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#define | NVM_FUSES_USERID3_bm (1<<3) /* User ID bit 3 mask. */ |
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#define | NVM_FUSES_USERID3_bp 3 /* User ID bit 3 position. */ |
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#define | NVM_FUSES_USERID4_bm (1<<4) /* User ID bit 4 mask. */ |
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#define | NVM_FUSES_USERID4_bp 4 /* User ID bit 4 position. */ |
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#define | NVM_FUSES_USERID5_bm (1<<5) /* User ID bit 5 mask. */ |
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#define | NVM_FUSES_USERID5_bp 5 /* User ID bit 5 position. */ |
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#define | NVM_FUSES_USERID6_bm (1<<6) /* User ID bit 6 mask. */ |
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#define | NVM_FUSES_USERID6_bp 6 /* User ID bit 6 position. */ |
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#define | NVM_FUSES_USERID7_bm (1<<7) /* User ID bit 7 mask. */ |
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#define | NVM_FUSES_USERID7_bp 7 /* User ID bit 7 position. */ |
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#define | NVM_FUSES_WDWP_gm 0xF0 /* Watchdog Window Timeout Period group mask. */ |
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#define | NVM_FUSES_WDWP_gp 4 /* Watchdog Window Timeout Period group position. */ |
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#define | NVM_FUSES_WDWP0_bm (1<<4) /* Watchdog Window Timeout Period bit 0 mask. */ |
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#define | NVM_FUSES_WDWP0_bp 4 /* Watchdog Window Timeout Period bit 0 position. */ |
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#define | NVM_FUSES_WDWP1_bm (1<<5) /* Watchdog Window Timeout Period bit 1 mask. */ |
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#define | NVM_FUSES_WDWP1_bp 5 /* Watchdog Window Timeout Period bit 1 position. */ |
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#define | NVM_FUSES_WDWP2_bm (1<<6) /* Watchdog Window Timeout Period bit 2 mask. */ |
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#define | NVM_FUSES_WDWP2_bp 6 /* Watchdog Window Timeout Period bit 2 position. */ |
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#define | NVM_FUSES_WDWP3_bm (1<<7) /* Watchdog Window Timeout Period bit 3 mask. */ |
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#define | NVM_FUSES_WDWP3_bp 7 /* Watchdog Window Timeout Period bit 3 position. */ |
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#define | NVM_FUSES_WDP_gm 0x0F /* Watchdog Timeout Period group mask. */ |
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#define | NVM_FUSES_WDP_gp 0 /* Watchdog Timeout Period group position. */ |
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#define | NVM_FUSES_WDP0_bm (1<<0) /* Watchdog Timeout Period bit 0 mask. */ |
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#define | NVM_FUSES_WDP0_bp 0 /* Watchdog Timeout Period bit 0 position. */ |
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#define | NVM_FUSES_WDP1_bm (1<<1) /* Watchdog Timeout Period bit 1 mask. */ |
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#define | NVM_FUSES_WDP1_bp 1 /* Watchdog Timeout Period bit 1 position. */ |
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#define | NVM_FUSES_WDP2_bm (1<<2) /* Watchdog Timeout Period bit 2 mask. */ |
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#define | NVM_FUSES_WDP2_bp 2 /* Watchdog Timeout Period bit 2 position. */ |
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#define | NVM_FUSES_WDP3_bm (1<<3) /* Watchdog Timeout Period bit 3 mask. */ |
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#define | NVM_FUSES_WDP3_bp 3 /* Watchdog Timeout Period bit 3 position. */ |
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#define | NVM_FUSES_DVSDON_bm 0x80 /* Spike Detector Enable bit mask. */ |
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#define | NVM_FUSES_DVSDON_bp 7 /* Spike Detector Enable bit position. */ |
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#define | NVM_FUSES_BOOTRST_bm 0x40 /* Boot Loader Section Reset Vector bit mask. */ |
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#define | NVM_FUSES_BOOTRST_bp 6 /* Boot Loader Section Reset Vector bit position. */ |
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#define | NVM_FUSES_BODPD_gm 0x03 /* BOD Operation in Power-Down Mode group mask. */ |
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#define | NVM_FUSES_BODPD_gp 0 /* BOD Operation in Power-Down Mode group position. */ |
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#define | NVM_FUSES_BODPD0_bm (1<<0) /* BOD Operation in Power-Down Mode bit 0 mask. */ |
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#define | NVM_FUSES_BODPD0_bp 0 /* BOD Operation in Power-Down Mode bit 0 position. */ |
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#define | NVM_FUSES_BODPD1_bm (1<<1) /* BOD Operation in Power-Down Mode bit 1 mask. */ |
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#define | NVM_FUSES_BODPD1_bp 1 /* BOD Operation in Power-Down Mode bit 1 position. */ |
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#define | NVM_FUSES_SUT_gm 0x0C /* Start-up Time group mask. */ |
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#define | NVM_FUSES_SUT_gp 2 /* Start-up Time group position. */ |
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#define | NVM_FUSES_SUT0_bm (1<<2) /* Start-up Time bit 0 mask. */ |
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#define | NVM_FUSES_SUT0_bp 2 /* Start-up Time bit 0 position. */ |
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#define | NVM_FUSES_SUT1_bm (1<<3) /* Start-up Time bit 1 mask. */ |
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#define | NVM_FUSES_SUT1_bp 3 /* Start-up Time bit 1 position. */ |
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#define | NVM_FUSES_WDLOCK_bm 0x02 /* Watchdog Timer Lock bit mask. */ |
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#define | NVM_FUSES_WDLOCK_bp 1 /* Watchdog Timer Lock bit position. */ |
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#define | NVM_FUSES_BODACT_gm 0x30 /* BOD Operation in Active Mode group mask. */ |
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#define | NVM_FUSES_BODACT_gp 4 /* BOD Operation in Active Mode group position. */ |
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#define | NVM_FUSES_BODACT0_bm (1<<4) /* BOD Operation in Active Mode bit 0 mask. */ |
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#define | NVM_FUSES_BODACT0_bp 4 /* BOD Operation in Active Mode bit 0 position. */ |
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#define | NVM_FUSES_BODACT1_bm (1<<5) /* BOD Operation in Active Mode bit 1 mask. */ |
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#define | NVM_FUSES_BODACT1_bp 5 /* BOD Operation in Active Mode bit 1 position. */ |
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#define | NVM_FUSES_EESAVE_bm 0x08 /* Preserve EEPROM Through Chip Erase bit mask. */ |
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#define | NVM_FUSES_EESAVE_bp 3 /* Preserve EEPROM Through Chip Erase bit position. */ |
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#define | NVM_FUSES_BODLVL_gm 0x07 /* Brown Out Detection Voltage Level group mask. */ |
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#define | NVM_FUSES_BODLVL_gp 0 /* Brown Out Detection Voltage Level group position. */ |
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#define | NVM_FUSES_BODLVL0_bm (1<<0) /* Brown Out Detection Voltage Level bit 0 mask. */ |
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#define | NVM_FUSES_BODLVL0_bp 0 /* Brown Out Detection Voltage Level bit 0 position. */ |
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#define | NVM_FUSES_BODLVL1_bm (1<<1) /* Brown Out Detection Voltage Level bit 1 mask. */ |
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#define | NVM_FUSES_BODLVL1_bp 1 /* Brown Out Detection Voltage Level bit 1 position. */ |
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#define | NVM_FUSES_BODLVL2_bm (1<<2) /* Brown Out Detection Voltage Level bit 2 mask. */ |
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#define | NVM_FUSES_BODLVL2_bp 2 /* Brown Out Detection Voltage Level bit 2 position. */ |
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#define | AC_INTMODE_gm 0xC0 /* Interrupt Mode group mask. */ |
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#define | AC_INTMODE_gp 6 /* Interrupt Mode group position. */ |
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#define | AC_INTMODE0_bm (1<<6) /* Interrupt Mode bit 0 mask. */ |
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#define | AC_INTMODE0_bp 6 /* Interrupt Mode bit 0 position. */ |
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#define | AC_INTMODE1_bm (1<<7) /* Interrupt Mode bit 1 mask. */ |
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#define | AC_INTMODE1_bp 7 /* Interrupt Mode bit 1 position. */ |
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#define | AC_INTLVL_gm 0x30 /* Interrupt Level group mask. */ |
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#define | AC_INTLVL_gp 4 /* Interrupt Level group position. */ |
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#define | AC_INTLVL0_bm (1<<4) /* Interrupt Level bit 0 mask. */ |
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#define | AC_INTLVL0_bp 4 /* Interrupt Level bit 0 position. */ |
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#define | AC_INTLVL1_bm (1<<5) /* Interrupt Level bit 1 mask. */ |
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#define | AC_INTLVL1_bp 5 /* Interrupt Level bit 1 position. */ |
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#define | AC_HSMODE_bm 0x08 /* High-speed Mode bit mask. */ |
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#define | AC_HSMODE_bp 3 /* High-speed Mode bit position. */ |
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#define | AC_HYSMODE_gm 0x06 /* Hysteresis Mode group mask. */ |
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#define | AC_HYSMODE_gp 1 /* Hysteresis Mode group position. */ |
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#define | AC_HYSMODE0_bm (1<<1) /* Hysteresis Mode bit 0 mask. */ |
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#define | AC_HYSMODE0_bp 1 /* Hysteresis Mode bit 0 position. */ |
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#define | AC_HYSMODE1_bm (1<<2) /* Hysteresis Mode bit 1 mask. */ |
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#define | AC_HYSMODE1_bp 2 /* Hysteresis Mode bit 1 position. */ |
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#define | AC_ENABLE_bm 0x01 /* Enable bit mask. */ |
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#define | AC_ENABLE_bp 0 /* Enable bit position. */ |
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#define | AC_MUXPOS_gm 0x38 /* MUX Positive Input group mask. */ |
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#define | AC_MUXPOS_gp 3 /* MUX Positive Input group position. */ |
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#define | AC_MUXPOS0_bm (1<<3) /* MUX Positive Input bit 0 mask. */ |
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#define | AC_MUXPOS0_bp 3 /* MUX Positive Input bit 0 position. */ |
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#define | AC_MUXPOS1_bm (1<<4) /* MUX Positive Input bit 1 mask. */ |
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#define | AC_MUXPOS1_bp 4 /* MUX Positive Input bit 1 position. */ |
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#define | AC_MUXPOS2_bm (1<<5) /* MUX Positive Input bit 2 mask. */ |
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#define | AC_MUXPOS2_bp 5 /* MUX Positive Input bit 2 position. */ |
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#define | AC_MUXNEG_gm 0x07 /* MUX Negative Input group mask. */ |
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#define | AC_MUXNEG_gp 0 /* MUX Negative Input group position. */ |
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#define | AC_MUXNEG0_bm (1<<0) /* MUX Negative Input bit 0 mask. */ |
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#define | AC_MUXNEG0_bp 0 /* MUX Negative Input bit 0 position. */ |
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#define | AC_MUXNEG1_bm (1<<1) /* MUX Negative Input bit 1 mask. */ |
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#define | AC_MUXNEG1_bp 1 /* MUX Negative Input bit 1 position. */ |
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#define | AC_MUXNEG2_bm (1<<2) /* MUX Negative Input bit 2 mask. */ |
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#define | AC_MUXNEG2_bp 2 /* MUX Negative Input bit 2 position. */ |
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#define | AC_AC0OUT_bm 0x01 /* Comparator 0 Output Enable bit mask. */ |
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#define | AC_AC0OUT_bp 0 /* Comparator 0 Output Enable bit position. */ |
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#define | AC_SCALEFAC_gm 0x3F /* VCC Voltage Scaler Factor group mask. */ |
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#define | AC_SCALEFAC_gp 0 /* VCC Voltage Scaler Factor group position. */ |
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#define | AC_SCALEFAC0_bm (1<<0) /* VCC Voltage Scaler Factor bit 0 mask. */ |
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#define | AC_SCALEFAC0_bp 0 /* VCC Voltage Scaler Factor bit 0 position. */ |
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#define | AC_SCALEFAC1_bm (1<<1) /* VCC Voltage Scaler Factor bit 1 mask. */ |
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#define | AC_SCALEFAC1_bp 1 /* VCC Voltage Scaler Factor bit 1 position. */ |
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#define | AC_SCALEFAC2_bm (1<<2) /* VCC Voltage Scaler Factor bit 2 mask. */ |
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#define | AC_SCALEFAC2_bp 2 /* VCC Voltage Scaler Factor bit 2 position. */ |
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#define | AC_SCALEFAC3_bm (1<<3) /* VCC Voltage Scaler Factor bit 3 mask. */ |
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#define | AC_SCALEFAC3_bp 3 /* VCC Voltage Scaler Factor bit 3 position. */ |
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#define | AC_SCALEFAC4_bm (1<<4) /* VCC Voltage Scaler Factor bit 4 mask. */ |
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#define | AC_SCALEFAC4_bp 4 /* VCC Voltage Scaler Factor bit 4 position. */ |
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#define | AC_SCALEFAC5_bm (1<<5) /* VCC Voltage Scaler Factor bit 5 mask. */ |
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#define | AC_SCALEFAC5_bp 5 /* VCC Voltage Scaler Factor bit 5 position. */ |
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#define | AC_WEN_bm 0x10 /* Window Mode Enable bit mask. */ |
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#define | AC_WEN_bp 4 /* Window Mode Enable bit position. */ |
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#define | AC_WINTMODE_gm 0x0C /* Window Interrupt Mode group mask. */ |
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#define | AC_WINTMODE_gp 2 /* Window Interrupt Mode group position. */ |
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#define | AC_WINTMODE0_bm (1<<2) /* Window Interrupt Mode bit 0 mask. */ |
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#define | AC_WINTMODE0_bp 2 /* Window Interrupt Mode bit 0 position. */ |
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#define | AC_WINTMODE1_bm (1<<3) /* Window Interrupt Mode bit 1 mask. */ |
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#define | AC_WINTMODE1_bp 3 /* Window Interrupt Mode bit 1 position. */ |
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#define | AC_WINTLVL_gm 0x03 /* Window Interrupt Level group mask. */ |
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#define | AC_WINTLVL_gp 0 /* Window Interrupt Level group position. */ |
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#define | AC_WINTLVL0_bm (1<<0) /* Window Interrupt Level bit 0 mask. */ |
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#define | AC_WINTLVL0_bp 0 /* Window Interrupt Level bit 0 position. */ |
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#define | AC_WINTLVL1_bm (1<<1) /* Window Interrupt Level bit 1 mask. */ |
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#define | AC_WINTLVL1_bp 1 /* Window Interrupt Level bit 1 position. */ |
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#define | AC_WSTATE_gm 0xC0 /* Window Mode State group mask. */ |
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#define | AC_WSTATE_gp 6 /* Window Mode State group position. */ |
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#define | AC_WSTATE0_bm (1<<6) /* Window Mode State bit 0 mask. */ |
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#define | AC_WSTATE0_bp 6 /* Window Mode State bit 0 position. */ |
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#define | AC_WSTATE1_bm (1<<7) /* Window Mode State bit 1 mask. */ |
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#define | AC_WSTATE1_bp 7 /* Window Mode State bit 1 position. */ |
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#define | AC_AC1STATE_bm 0x20 /* Comparator 1 State bit mask. */ |
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#define | AC_AC1STATE_bp 5 /* Comparator 1 State bit position. */ |
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#define | AC_AC0STATE_bm 0x10 /* Comparator 0 State bit mask. */ |
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#define | AC_AC0STATE_bp 4 /* Comparator 0 State bit position. */ |
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#define | AC_WIF_bm 0x04 /* Window Mode Interrupt Flag bit mask. */ |
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#define | AC_WIF_bp 2 /* Window Mode Interrupt Flag bit position. */ |
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#define | AC_AC1IF_bm 0x02 /* Comparator 1 Interrupt Flag bit mask. */ |
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#define | AC_AC1IF_bp 1 /* Comparator 1 Interrupt Flag bit position. */ |
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#define | AC_AC0IF_bm 0x01 /* Comparator 0 Interrupt Flag bit mask. */ |
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#define | AC_AC0IF_bp 0 /* Comparator 0 Interrupt Flag bit position. */ |
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#define | ADC_CH_START_bm 0x80 /* Channel Start Conversion bit mask. */ |
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#define | ADC_CH_START_bp 7 /* Channel Start Conversion bit position. */ |
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#define | ADC_CH_GAINFAC_gm 0x1C /* Gain Factor group mask. */ |
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#define | ADC_CH_GAINFAC_gp 2 /* Gain Factor group position. */ |
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#define | ADC_CH_GAINFAC0_bm (1<<2) /* Gain Factor bit 0 mask. */ |
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#define | ADC_CH_GAINFAC0_bp 2 /* Gain Factor bit 0 position. */ |
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#define | ADC_CH_GAINFAC1_bm (1<<3) /* Gain Factor bit 1 mask. */ |
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#define | ADC_CH_GAINFAC1_bp 3 /* Gain Factor bit 1 position. */ |
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#define | ADC_CH_GAINFAC2_bm (1<<4) /* Gain Factor bit 2 mask. */ |
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#define | ADC_CH_GAINFAC2_bp 4 /* Gain Factor bit 2 position. */ |
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#define | ADC_CH_INPUTMODE_gm 0x03 /* Input Mode Select group mask. */ |
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#define | ADC_CH_INPUTMODE_gp 0 /* Input Mode Select group position. */ |
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#define | ADC_CH_INPUTMODE0_bm (1<<0) /* Input Mode Select bit 0 mask. */ |
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#define | ADC_CH_INPUTMODE0_bp 0 /* Input Mode Select bit 0 position. */ |
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#define | ADC_CH_INPUTMODE1_bm (1<<1) /* Input Mode Select bit 1 mask. */ |
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#define | ADC_CH_INPUTMODE1_bp 1 /* Input Mode Select bit 1 position. */ |
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#define | ADC_CH_MUXPOS_gm 0x78 /* Positive Input Select group mask. */ |
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#define | ADC_CH_MUXPOS_gp 3 /* Positive Input Select group position. */ |
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#define | ADC_CH_MUXPOS0_bm (1<<3) /* Positive Input Select bit 0 mask. */ |
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#define | ADC_CH_MUXPOS0_bp 3 /* Positive Input Select bit 0 position. */ |
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#define | ADC_CH_MUXPOS1_bm (1<<4) /* Positive Input Select bit 1 mask. */ |
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#define | ADC_CH_MUXPOS1_bp 4 /* Positive Input Select bit 1 position. */ |
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#define | ADC_CH_MUXPOS2_bm (1<<5) /* Positive Input Select bit 2 mask. */ |
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#define | ADC_CH_MUXPOS2_bp 5 /* Positive Input Select bit 2 position. */ |
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#define | ADC_CH_MUXPOS3_bm (1<<6) /* Positive Input Select bit 3 mask. */ |
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#define | ADC_CH_MUXPOS3_bp 6 /* Positive Input Select bit 3 position. */ |
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#define | ADC_CH_MUXINT_gm 0x78 /* Internal Input Select group mask. */ |
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#define | ADC_CH_MUXINT_gp 3 /* Internal Input Select group position. */ |
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#define | ADC_CH_MUXINT0_bm (1<<3) /* Internal Input Select bit 0 mask. */ |
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#define | ADC_CH_MUXINT0_bp 3 /* Internal Input Select bit 0 position. */ |
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#define | ADC_CH_MUXINT1_bm (1<<4) /* Internal Input Select bit 1 mask. */ |
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#define | ADC_CH_MUXINT1_bp 4 /* Internal Input Select bit 1 position. */ |
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#define | ADC_CH_MUXINT2_bm (1<<5) /* Internal Input Select bit 2 mask. */ |
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#define | ADC_CH_MUXINT2_bp 5 /* Internal Input Select bit 2 position. */ |
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#define | ADC_CH_MUXINT3_bm (1<<6) /* Internal Input Select bit 3 mask. */ |
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#define | ADC_CH_MUXINT3_bp 6 /* Internal Input Select bit 3 position. */ |
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#define | ADC_CH_MUXNEG_gm 0x03 /* Negative Input Select group mask. */ |
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#define | ADC_CH_MUXNEG_gp 0 /* Negative Input Select group position. */ |
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#define | ADC_CH_MUXNEG0_bm (1<<0) /* Negative Input Select bit 0 mask. */ |
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#define | ADC_CH_MUXNEG0_bp 0 /* Negative Input Select bit 0 position. */ |
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#define | ADC_CH_MUXNEG1_bm (1<<1) /* Negative Input Select bit 1 mask. */ |
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#define | ADC_CH_MUXNEG1_bp 1 /* Negative Input Select bit 1 position. */ |
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#define | ADC_CH_INTMODE_gm 0x0C /* Interrupt Mode group mask. */ |
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#define | ADC_CH_INTMODE_gp 2 /* Interrupt Mode group position. */ |
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#define | ADC_CH_INTMODE0_bm (1<<2) /* Interrupt Mode bit 0 mask. */ |
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#define | ADC_CH_INTMODE0_bp 2 /* Interrupt Mode bit 0 position. */ |
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#define | ADC_CH_INTMODE1_bm (1<<3) /* Interrupt Mode bit 1 mask. */ |
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#define | ADC_CH_INTMODE1_bp 3 /* Interrupt Mode bit 1 position. */ |
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#define | ADC_CH_INTLVL_gm 0x03 /* Interrupt Level group mask. */ |
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#define | ADC_CH_INTLVL_gp 0 /* Interrupt Level group position. */ |
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#define | ADC_CH_INTLVL0_bm (1<<0) /* Interrupt Level bit 0 mask. */ |
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#define | ADC_CH_INTLVL0_bp 0 /* Interrupt Level bit 0 position. */ |
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#define | ADC_CH_INTLVL1_bm (1<<1) /* Interrupt Level bit 1 mask. */ |
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#define | ADC_CH_INTLVL1_bp 1 /* Interrupt Level bit 1 position. */ |
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#define | ADC_CH_CHIF_bm 0x01 /* Channel Interrupt Flag bit mask. */ |
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#define | ADC_CH_CHIF_bp 0 /* Channel Interrupt Flag bit position. */ |
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#define | ADC_DMASEL_gm 0xC0 /* DMA Selection group mask. */ |
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#define | ADC_DMASEL_gp 6 /* DMA Selection group position. */ |
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#define | ADC_DMASEL0_bm (1<<6) /* DMA Selection bit 0 mask. */ |
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#define | ADC_DMASEL0_bp 6 /* DMA Selection bit 0 position. */ |
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#define | ADC_DMASEL1_bm (1<<7) /* DMA Selection bit 1 mask. */ |
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#define | ADC_DMASEL1_bp 7 /* DMA Selection bit 1 position. */ |
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#define | ADC_CH3START_bm 0x20 /* Channel 3 Start Conversion bit mask. */ |
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#define | ADC_CH3START_bp 5 /* Channel 3 Start Conversion bit position. */ |
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#define | ADC_CH2START_bm 0x10 /* Channel 2 Start Conversion bit mask. */ |
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#define | ADC_CH2START_bp 4 /* Channel 2 Start Conversion bit position. */ |
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#define | ADC_CH1START_bm 0x08 /* Channel 1 Start Conversion bit mask. */ |
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#define | ADC_CH1START_bp 3 /* Channel 1 Start Conversion bit position. */ |
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#define | ADC_CH0START_bm 0x04 /* Channel 0 Start Conversion bit mask. */ |
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#define | ADC_CH0START_bp 2 /* Channel 0 Start Conversion bit position. */ |
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#define | ADC_FLUSH_bm 0x02 /* Flush Pipeline bit mask. */ |
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#define | ADC_FLUSH_bp 1 /* Flush Pipeline bit position. */ |
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#define | ADC_ENABLE_bm 0x01 /* Enable ADC bit mask. */ |
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#define | ADC_ENABLE_bp 0 /* Enable ADC bit position. */ |
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#define | ADC_CONMODE_bm 0x10 /* Conversion Mode bit mask. */ |
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#define | ADC_CONMODE_bp 4 /* Conversion Mode bit position. */ |
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#define | ADC_FREERUN_bm 0x08 /* Free Running Mode Enable bit mask. */ |
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#define | ADC_FREERUN_bp 3 /* Free Running Mode Enable bit position. */ |
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#define | ADC_RESOLUTION_gm 0x06 /* Result Resolution group mask. */ |
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#define | ADC_RESOLUTION_gp 1 /* Result Resolution group position. */ |
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#define | ADC_RESOLUTION0_bm (1<<1) /* Result Resolution bit 0 mask. */ |
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#define | ADC_RESOLUTION0_bp 1 /* Result Resolution bit 0 position. */ |
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#define | ADC_RESOLUTION1_bm (1<<2) /* Result Resolution bit 1 mask. */ |
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#define | ADC_RESOLUTION1_bp 2 /* Result Resolution bit 1 position. */ |
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#define | ADC_REFSEL_gm 0x30 /* Reference Selection group mask. */ |
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#define | ADC_REFSEL_gp 4 /* Reference Selection group position. */ |
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#define | ADC_REFSEL0_bm (1<<4) /* Reference Selection bit 0 mask. */ |
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#define | ADC_REFSEL0_bp 4 /* Reference Selection bit 0 position. */ |
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#define | ADC_REFSEL1_bm (1<<5) /* Reference Selection bit 1 mask. */ |
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#define | ADC_REFSEL1_bp 5 /* Reference Selection bit 1 position. */ |
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#define | ADC_BANDGAP_bm 0x02 /* Bandgap enable bit mask. */ |
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#define | ADC_BANDGAP_bp 1 /* Bandgap enable bit position. */ |
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#define | ADC_TEMPREF_bm 0x01 /* Temperature Reference Enable bit mask. */ |
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#define | ADC_TEMPREF_bp 0 /* Temperature Reference Enable bit position. */ |
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#define | ADC_SWEEP_gm 0xC0 /* Channel Sweep Selection group mask. */ |
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#define | ADC_SWEEP_gp 6 /* Channel Sweep Selection group position. */ |
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#define | ADC_SWEEP0_bm (1<<6) /* Channel Sweep Selection bit 0 mask. */ |
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#define | ADC_SWEEP0_bp 6 /* Channel Sweep Selection bit 0 position. */ |
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#define | ADC_SWEEP1_bm (1<<7) /* Channel Sweep Selection bit 1 mask. */ |
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#define | ADC_SWEEP1_bp 7 /* Channel Sweep Selection bit 1 position. */ |
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#define | ADC_EVSEL_gm 0x38 /* Event Input Select group mask. */ |
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#define | ADC_EVSEL_gp 3 /* Event Input Select group position. */ |
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#define | ADC_EVSEL0_bm (1<<3) /* Event Input Select bit 0 mask. */ |
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#define | ADC_EVSEL0_bp 3 /* Event Input Select bit 0 position. */ |
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#define | ADC_EVSEL1_bm (1<<4) /* Event Input Select bit 1 mask. */ |
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#define | ADC_EVSEL1_bp 4 /* Event Input Select bit 1 position. */ |
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#define | ADC_EVSEL2_bm (1<<5) /* Event Input Select bit 2 mask. */ |
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#define | ADC_EVSEL2_bp 5 /* Event Input Select bit 2 position. */ |
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#define | ADC_EVACT_gm 0x07 /* Event Action Select group mask. */ |
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#define | ADC_EVACT_gp 0 /* Event Action Select group position. */ |
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#define | ADC_EVACT0_bm (1<<0) /* Event Action Select bit 0 mask. */ |
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#define | ADC_EVACT0_bp 0 /* Event Action Select bit 0 position. */ |
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#define | ADC_EVACT1_bm (1<<1) /* Event Action Select bit 1 mask. */ |
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#define | ADC_EVACT1_bp 1 /* Event Action Select bit 1 position. */ |
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#define | ADC_EVACT2_bm (1<<2) /* Event Action Select bit 2 mask. */ |
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#define | ADC_EVACT2_bp 2 /* Event Action Select bit 2 position. */ |
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#define | ADC_PRESCALER_gm 0x07 /* Clock Prescaler Selection group mask. */ |
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#define | ADC_PRESCALER_gp 0 /* Clock Prescaler Selection group position. */ |
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#define | ADC_PRESCALER0_bm (1<<0) /* Clock Prescaler Selection bit 0 mask. */ |
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#define | ADC_PRESCALER0_bp 0 /* Clock Prescaler Selection bit 0 position. */ |
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#define | ADC_PRESCALER1_bm (1<<1) /* Clock Prescaler Selection bit 1 mask. */ |
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#define | ADC_PRESCALER1_bp 1 /* Clock Prescaler Selection bit 1 position. */ |
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#define | ADC_PRESCALER2_bm (1<<2) /* Clock Prescaler Selection bit 2 mask. */ |
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#define | ADC_PRESCALER2_bp 2 /* Clock Prescaler Selection bit 2 position. */ |
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#define | ADC_CAL_bm 0x01 /* ADC Calibration Start bit mask. */ |
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#define | ADC_CAL_bp 0 /* ADC Calibration Start bit position. */ |
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#define | ADC_CH3IF_bm 0x08 /* Channel 3 Interrupt Flag bit mask. */ |
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#define | ADC_CH3IF_bp 3 /* Channel 3 Interrupt Flag bit position. */ |
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#define | ADC_CH2IF_bm 0x04 /* Channel 2 Interrupt Flag bit mask. */ |
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#define | ADC_CH2IF_bp 2 /* Channel 2 Interrupt Flag bit position. */ |
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#define | ADC_CH1IF_bm 0x02 /* Channel 1 Interrupt Flag bit mask. */ |
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#define | ADC_CH1IF_bp 1 /* Channel 1 Interrupt Flag bit position. */ |
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#define | ADC_CH0IF_bm 0x01 /* Channel 0 Interrupt Flag bit mask. */ |
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#define | ADC_CH0IF_bp 0 /* Channel 0 Interrupt Flag bit position. */ |
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#define | DAC_IDOEN_bm 0x10 /* Internal Output Enable bit mask. */ |
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#define | DAC_IDOEN_bp 4 /* Internal Output Enable bit position. */ |
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#define | DAC_CH1EN_bm 0x08 /* Channel 1 Output Enable bit mask. */ |
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#define | DAC_CH1EN_bp 3 /* Channel 1 Output Enable bit position. */ |
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#define | DAC_CH0EN_bm 0x04 /* Channel 0 Output Enable bit mask. */ |
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#define | DAC_CH0EN_bp 2 /* Channel 0 Output Enable bit position. */ |
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#define | DAC_LPMODE_bm 0x02 /* Low Power Mode bit mask. */ |
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#define | DAC_LPMODE_bp 1 /* Low Power Mode bit position. */ |
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#define | DAC_ENABLE_bm 0x01 /* Enable bit mask. */ |
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#define | DAC_ENABLE_bp 0 /* Enable bit position. */ |
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#define | DAC_CHSEL_gm 0x60 /* Channel Select group mask. */ |
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#define | DAC_CHSEL_gp 5 /* Channel Select group position. */ |
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#define | DAC_CHSEL0_bm (1<<5) /* Channel Select bit 0 mask. */ |
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#define | DAC_CHSEL0_bp 5 /* Channel Select bit 0 position. */ |
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#define | DAC_CHSEL1_bm (1<<6) /* Channel Select bit 1 mask. */ |
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#define | DAC_CHSEL1_bp 6 /* Channel Select bit 1 position. */ |
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#define | DAC_CH1TRIG_bm 0x02 /* Channel 1 Event Trig Enable bit mask. */ |
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#define | DAC_CH1TRIG_bp 1 /* Channel 1 Event Trig Enable bit position. */ |
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#define | DAC_CH0TRIG_bm 0x01 /* Channel 0 Event Trig Enable bit mask. */ |
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#define | DAC_CH0TRIG_bp 0 /* Channel 0 Event Trig Enable bit position. */ |
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#define | DAC_REFSEL_gm 0x18 /* Reference Select group mask. */ |
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#define | DAC_REFSEL_gp 3 /* Reference Select group position. */ |
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#define | DAC_REFSEL0_bm (1<<3) /* Reference Select bit 0 mask. */ |
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#define | DAC_REFSEL0_bp 3 /* Reference Select bit 0 position. */ |
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#define | DAC_REFSEL1_bm (1<<4) /* Reference Select bit 1 mask. */ |
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#define | DAC_REFSEL1_bp 4 /* Reference Select bit 1 position. */ |
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#define | DAC_LEFTADJ_bm 0x01 /* Left-adjust Result bit mask. */ |
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#define | DAC_LEFTADJ_bp 0 /* Left-adjust Result bit position. */ |
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#define | DAC_EVSEL_gm 0x07 /* Event Input Selection group mask. */ |
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#define | DAC_EVSEL_gp 0 /* Event Input Selection group position. */ |
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#define | DAC_EVSEL0_bm (1<<0) /* Event Input Selection bit 0 mask. */ |
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#define | DAC_EVSEL0_bp 0 /* Event Input Selection bit 0 position. */ |
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#define | DAC_EVSEL1_bm (1<<1) /* Event Input Selection bit 1 mask. */ |
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#define | DAC_EVSEL1_bp 1 /* Event Input Selection bit 1 position. */ |
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#define | DAC_EVSEL2_bm (1<<2) /* Event Input Selection bit 2 mask. */ |
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#define | DAC_EVSEL2_bp 2 /* Event Input Selection bit 2 position. */ |
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#define | DAC_CONINTVAL_gm 0x70 /* Conversion Intercal group mask. */ |
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#define | DAC_CONINTVAL_gp 4 /* Conversion Intercal group position. */ |
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#define | DAC_CONINTVAL0_bm (1<<4) /* Conversion Intercal bit 0 mask. */ |
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#define | DAC_CONINTVAL0_bp 4 /* Conversion Intercal bit 0 position. */ |
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#define | DAC_CONINTVAL1_bm (1<<5) /* Conversion Intercal bit 1 mask. */ |
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#define | DAC_CONINTVAL1_bp 5 /* Conversion Intercal bit 1 position. */ |
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#define | DAC_CONINTVAL2_bm (1<<6) /* Conversion Intercal bit 2 mask. */ |
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#define | DAC_CONINTVAL2_bp 6 /* Conversion Intercal bit 2 position. */ |
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#define | DAC_REFRESH_gm 0x0F /* Refresh Timing Control group mask. */ |
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#define | DAC_REFRESH_gp 0 /* Refresh Timing Control group position. */ |
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#define | DAC_REFRESH0_bm (1<<0) /* Refresh Timing Control bit 0 mask. */ |
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#define | DAC_REFRESH0_bp 0 /* Refresh Timing Control bit 0 position. */ |
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#define | DAC_REFRESH1_bm (1<<1) /* Refresh Timing Control bit 1 mask. */ |
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#define | DAC_REFRESH1_bp 1 /* Refresh Timing Control bit 1 position. */ |
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#define | DAC_REFRESH2_bm (1<<2) /* Refresh Timing Control bit 2 mask. */ |
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#define | DAC_REFRESH2_bp 2 /* Refresh Timing Control bit 2 position. */ |
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#define | DAC_REFRESH3_bm (1<<3) /* Refresh Timing Control bit 3 mask. */ |
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#define | DAC_REFRESH3_bp 3 /* Refresh Timing Control bit 3 position. */ |
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#define | DAC_CH1DRE_bm 0x02 /* Channel 1 Data Register Empty bit mask. */ |
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#define | DAC_CH1DRE_bp 1 /* Channel 1 Data Register Empty bit position. */ |
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#define | DAC_CH0DRE_bm 0x01 /* Channel 0 Data Register Empty bit mask. */ |
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#define | DAC_CH0DRE_bp 0 /* Channel 0 Data Register Empty bit position. */ |
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#define | RTC_PRESCALER_gm 0x07 /* Prescaling Factor group mask. */ |
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#define | RTC_PRESCALER_gp 0 /* Prescaling Factor group position. */ |
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#define | RTC_PRESCALER0_bm (1<<0) /* Prescaling Factor bit 0 mask. */ |
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#define | RTC_PRESCALER0_bp 0 /* Prescaling Factor bit 0 position. */ |
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#define | RTC_PRESCALER1_bm (1<<1) /* Prescaling Factor bit 1 mask. */ |
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#define | RTC_PRESCALER1_bp 1 /* Prescaling Factor bit 1 position. */ |
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#define | RTC_PRESCALER2_bm (1<<2) /* Prescaling Factor bit 2 mask. */ |
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#define | RTC_PRESCALER2_bp 2 /* Prescaling Factor bit 2 position. */ |
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#define | RTC_SYNCBUSY_bm 0x01 /* Synchronization Busy Flag bit mask. */ |
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#define | RTC_SYNCBUSY_bp 0 /* Synchronization Busy Flag bit position. */ |
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#define | RTC_COMPINTLVL_gm 0x0C /* Compare Match Interrupt Level group mask. */ |
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#define | RTC_COMPINTLVL_gp 2 /* Compare Match Interrupt Level group position. */ |
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#define | RTC_COMPINTLVL0_bm (1<<2) /* Compare Match Interrupt Level bit 0 mask. */ |
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#define | RTC_COMPINTLVL0_bp 2 /* Compare Match Interrupt Level bit 0 position. */ |
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#define | RTC_COMPINTLVL1_bm (1<<3) /* Compare Match Interrupt Level bit 1 mask. */ |
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#define | RTC_COMPINTLVL1_bp 3 /* Compare Match Interrupt Level bit 1 position. */ |
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#define | RTC_OVFINTLVL_gm 0x03 /* Overflow Interrupt Level group mask. */ |
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#define | RTC_OVFINTLVL_gp 0 /* Overflow Interrupt Level group position. */ |
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#define | RTC_OVFINTLVL0_bm (1<<0) /* Overflow Interrupt Level bit 0 mask. */ |
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#define | RTC_OVFINTLVL0_bp 0 /* Overflow Interrupt Level bit 0 position. */ |
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#define | RTC_OVFINTLVL1_bm (1<<1) /* Overflow Interrupt Level bit 1 mask. */ |
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#define | RTC_OVFINTLVL1_bp 1 /* Overflow Interrupt Level bit 1 position. */ |
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#define | RTC_COMPIF_bm 0x02 /* Compare Match Interrupt Flag bit mask. */ |
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#define | RTC_COMPIF_bp 1 /* Compare Match Interrupt Flag bit position. */ |
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#define | RTC_OVFIF_bm 0x01 /* Overflow Interrupt Flag bit mask. */ |
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#define | RTC_OVFIF_bp 0 /* Overflow Interrupt Flag bit position. */ |
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#define | EBI_CS_ASPACE_gm 0x7C /* Address Space group mask. */ |
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#define | EBI_CS_ASPACE_gp 2 /* Address Space group position. */ |
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#define | EBI_CS_ASPACE0_bm (1<<2) /* Address Space bit 0 mask. */ |
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#define | EBI_CS_ASPACE0_bp 2 /* Address Space bit 0 position. */ |
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#define | EBI_CS_ASPACE1_bm (1<<3) /* Address Space bit 1 mask. */ |
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#define | EBI_CS_ASPACE1_bp 3 /* Address Space bit 1 position. */ |
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#define | EBI_CS_ASPACE2_bm (1<<4) /* Address Space bit 2 mask. */ |
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#define | EBI_CS_ASPACE2_bp 4 /* Address Space bit 2 position. */ |
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#define | EBI_CS_ASPACE3_bm (1<<5) /* Address Space bit 3 mask. */ |
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#define | EBI_CS_ASPACE3_bp 5 /* Address Space bit 3 position. */ |
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#define | EBI_CS_ASPACE4_bm (1<<6) /* Address Space bit 4 mask. */ |
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#define | EBI_CS_ASPACE4_bp 6 /* Address Space bit 4 position. */ |
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#define | EBI_CS_MODE_gm 0x03 /* Memory Mode group mask. */ |
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#define | EBI_CS_MODE_gp 0 /* Memory Mode group position. */ |
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#define | EBI_CS_MODE0_bm (1<<0) /* Memory Mode bit 0 mask. */ |
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#define | EBI_CS_MODE0_bp 0 /* Memory Mode bit 0 position. */ |
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#define | EBI_CS_MODE1_bm (1<<1) /* Memory Mode bit 1 mask. */ |
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#define | EBI_CS_MODE1_bp 1 /* Memory Mode bit 1 position. */ |
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#define | EBI_CS_SRWS_gm 0x07 /* SRAM Wait State Cycles group mask. */ |
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#define | EBI_CS_SRWS_gp 0 /* SRAM Wait State Cycles group position. */ |
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#define | EBI_CS_SRWS0_bm (1<<0) /* SRAM Wait State Cycles bit 0 mask. */ |
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#define | EBI_CS_SRWS0_bp 0 /* SRAM Wait State Cycles bit 0 position. */ |
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#define | EBI_CS_SRWS1_bm (1<<1) /* SRAM Wait State Cycles bit 1 mask. */ |
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#define | EBI_CS_SRWS1_bp 1 /* SRAM Wait State Cycles bit 1 position. */ |
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#define | EBI_CS_SRWS2_bm (1<<2) /* SRAM Wait State Cycles bit 2 mask. */ |
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#define | EBI_CS_SRWS2_bp 2 /* SRAM Wait State Cycles bit 2 position. */ |
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#define | EBI_CS_SDINITDONE_bm 0x80 /* SDRAM Initialization Done bit mask. */ |
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#define | EBI_CS_SDINITDONE_bp 7 /* SDRAM Initialization Done bit position. */ |
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#define | EBI_CS_SDSREN_bm 0x04 /* SDRAM Self-refresh Enable bit mask. */ |
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#define | EBI_CS_SDSREN_bp 2 /* SDRAM Self-refresh Enable bit position. */ |
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#define | EBI_CS_SDMODE_gm 0x03 /* SDRAM Mode group mask. */ |
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#define | EBI_CS_SDMODE_gp 0 /* SDRAM Mode group position. */ |
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#define | EBI_CS_SDMODE0_bm (1<<0) /* SDRAM Mode bit 0 mask. */ |
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#define | EBI_CS_SDMODE0_bp 0 /* SDRAM Mode bit 0 position. */ |
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#define | EBI_CS_SDMODE1_bm (1<<1) /* SDRAM Mode bit 1 mask. */ |
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#define | EBI_CS_SDMODE1_bp 1 /* SDRAM Mode bit 1 position. */ |
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#define | EBI_SDDATAW_gm 0xC0 /* SDRAM Data Width Setting group mask. */ |
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#define | EBI_SDDATAW_gp 6 /* SDRAM Data Width Setting group position. */ |
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#define | EBI_SDDATAW0_bm (1<<6) /* SDRAM Data Width Setting bit 0 mask. */ |
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#define | EBI_SDDATAW0_bp 6 /* SDRAM Data Width Setting bit 0 position. */ |
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#define | EBI_SDDATAW1_bm (1<<7) /* SDRAM Data Width Setting bit 1 mask. */ |
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#define | EBI_SDDATAW1_bp 7 /* SDRAM Data Width Setting bit 1 position. */ |
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#define | EBI_LPCMODE_gm 0x30 /* SRAM LPC Mode group mask. */ |
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#define | EBI_LPCMODE_gp 4 /* SRAM LPC Mode group position. */ |
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#define | EBI_LPCMODE0_bm (1<<4) /* SRAM LPC Mode bit 0 mask. */ |
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#define | EBI_LPCMODE0_bp 4 /* SRAM LPC Mode bit 0 position. */ |
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#define | EBI_LPCMODE1_bm (1<<5) /* SRAM LPC Mode bit 1 mask. */ |
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#define | EBI_LPCMODE1_bp 5 /* SRAM LPC Mode bit 1 position. */ |
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#define | EBI_SRMODE_gm 0x0C /* SRAM Mode group mask. */ |
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#define | EBI_SRMODE_gp 2 /* SRAM Mode group position. */ |
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#define | EBI_SRMODE0_bm (1<<2) /* SRAM Mode bit 0 mask. */ |
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#define | EBI_SRMODE0_bp 2 /* SRAM Mode bit 0 position. */ |
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#define | EBI_SRMODE1_bm (1<<3) /* SRAM Mode bit 1 mask. */ |
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#define | EBI_SRMODE1_bp 3 /* SRAM Mode bit 1 position. */ |
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#define | EBI_IFMODE_gm 0x03 /* Interface Mode group mask. */ |
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#define | EBI_IFMODE_gp 0 /* Interface Mode group position. */ |
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#define | EBI_IFMODE0_bm (1<<0) /* Interface Mode bit 0 mask. */ |
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#define | EBI_IFMODE0_bp 0 /* Interface Mode bit 0 position. */ |
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#define | EBI_IFMODE1_bm (1<<1) /* Interface Mode bit 1 mask. */ |
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#define | EBI_IFMODE1_bp 1 /* Interface Mode bit 1 position. */ |
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#define | EBI_SDCAS_bm 0x08 /* SDRAM CAS Latency Setting bit mask. */ |
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#define | EBI_SDCAS_bp 3 /* SDRAM CAS Latency Setting bit position. */ |
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#define | EBI_SDROW_bm 0x04 /* SDRAM ROW Bits Setting bit mask. */ |
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#define | EBI_SDROW_bp 2 /* SDRAM ROW Bits Setting bit position. */ |
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#define | EBI_SDCOL_gm 0x03 /* SDRAM Column Bits Setting group mask. */ |
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#define | EBI_SDCOL_gp 0 /* SDRAM Column Bits Setting group position. */ |
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#define | EBI_SDCOL0_bm (1<<0) /* SDRAM Column Bits Setting bit 0 mask. */ |
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#define | EBI_SDCOL0_bp 0 /* SDRAM Column Bits Setting bit 0 position. */ |
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#define | EBI_SDCOL1_bm (1<<1) /* SDRAM Column Bits Setting bit 1 mask. */ |
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#define | EBI_SDCOL1_bp 1 /* SDRAM Column Bits Setting bit 1 position. */ |
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#define | EBI_MRDLY_gm 0xC0 /* SDRAM Mode Register Delay group mask. */ |
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#define | EBI_MRDLY_gp 6 /* SDRAM Mode Register Delay group position. */ |
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#define | EBI_MRDLY0_bm (1<<6) /* SDRAM Mode Register Delay bit 0 mask. */ |
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#define | EBI_MRDLY0_bp 6 /* SDRAM Mode Register Delay bit 0 position. */ |
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#define | EBI_MRDLY1_bm (1<<7) /* SDRAM Mode Register Delay bit 1 mask. */ |
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#define | EBI_MRDLY1_bp 7 /* SDRAM Mode Register Delay bit 1 position. */ |
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#define | EBI_ROWCYCDLY_gm 0x38 /* SDRAM Row Cycle Delay group mask. */ |
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#define | EBI_ROWCYCDLY_gp 3 /* SDRAM Row Cycle Delay group position. */ |
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#define | EBI_ROWCYCDLY0_bm (1<<3) /* SDRAM Row Cycle Delay bit 0 mask. */ |
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#define | EBI_ROWCYCDLY0_bp 3 /* SDRAM Row Cycle Delay bit 0 position. */ |
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#define | EBI_ROWCYCDLY1_bm (1<<4) /* SDRAM Row Cycle Delay bit 1 mask. */ |
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#define | EBI_ROWCYCDLY1_bp 4 /* SDRAM Row Cycle Delay bit 1 position. */ |
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#define | EBI_ROWCYCDLY2_bm (1<<5) /* SDRAM Row Cycle Delay bit 2 mask. */ |
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#define | EBI_ROWCYCDLY2_bp 5 /* SDRAM Row Cycle Delay bit 2 position. */ |
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#define | EBI_RPDLY_gm 0x07 /* SDRAM Row-to-Precharge Delay group mask. */ |
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#define | EBI_RPDLY_gp 0 /* SDRAM Row-to-Precharge Delay group position. */ |
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#define | EBI_RPDLY0_bm (1<<0) /* SDRAM Row-to-Precharge Delay bit 0 mask. */ |
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#define | EBI_RPDLY0_bp 0 /* SDRAM Row-to-Precharge Delay bit 0 position. */ |
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#define | EBI_RPDLY1_bm (1<<1) /* SDRAM Row-to-Precharge Delay bit 1 mask. */ |
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#define | EBI_RPDLY1_bp 1 /* SDRAM Row-to-Precharge Delay bit 1 position. */ |
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#define | EBI_RPDLY2_bm (1<<2) /* SDRAM Row-to-Precharge Delay bit 2 mask. */ |
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#define | EBI_RPDLY2_bp 2 /* SDRAM Row-to-Precharge Delay bit 2 position. */ |
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#define | EBI_WRDLY_gm 0xC0 /* SDRAM Write Recovery Delay group mask. */ |
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#define | EBI_WRDLY_gp 6 /* SDRAM Write Recovery Delay group position. */ |
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#define | EBI_WRDLY0_bm (1<<6) /* SDRAM Write Recovery Delay bit 0 mask. */ |
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#define | EBI_WRDLY0_bp 6 /* SDRAM Write Recovery Delay bit 0 position. */ |
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#define | EBI_WRDLY1_bm (1<<7) /* SDRAM Write Recovery Delay bit 1 mask. */ |
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#define | EBI_WRDLY1_bp 7 /* SDRAM Write Recovery Delay bit 1 position. */ |
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#define | EBI_ESRDLY_gm 0x38 /* SDRAM Exit-Self-refresh-to-Active Delay group mask. */ |
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#define | EBI_ESRDLY_gp 3 /* SDRAM Exit-Self-refresh-to-Active Delay group position. */ |
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#define | EBI_ESRDLY0_bm (1<<3) /* SDRAM Exit-Self-refresh-to-Active Delay bit 0 mask. */ |
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#define | EBI_ESRDLY0_bp 3 /* SDRAM Exit-Self-refresh-to-Active Delay bit 0 position. */ |
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#define | EBI_ESRDLY1_bm (1<<4) /* SDRAM Exit-Self-refresh-to-Active Delay bit 1 mask. */ |
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#define | EBI_ESRDLY1_bp 4 /* SDRAM Exit-Self-refresh-to-Active Delay bit 1 position. */ |
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#define | EBI_ESRDLY2_bm (1<<5) /* SDRAM Exit-Self-refresh-to-Active Delay bit 2 mask. */ |
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#define | EBI_ESRDLY2_bp 5 /* SDRAM Exit-Self-refresh-to-Active Delay bit 2 position. */ |
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#define | EBI_ROWCOLDLY_gm 0x07 /* SDRAM Row-to-Column Delay group mask. */ |
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#define | EBI_ROWCOLDLY_gp 0 /* SDRAM Row-to-Column Delay group position. */ |
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#define | EBI_ROWCOLDLY0_bm (1<<0) /* SDRAM Row-to-Column Delay bit 0 mask. */ |
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#define | EBI_ROWCOLDLY0_bp 0 /* SDRAM Row-to-Column Delay bit 0 position. */ |
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#define | EBI_ROWCOLDLY1_bm (1<<1) /* SDRAM Row-to-Column Delay bit 1 mask. */ |
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#define | EBI_ROWCOLDLY1_bp 1 /* SDRAM Row-to-Column Delay bit 1 position. */ |
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#define | EBI_ROWCOLDLY2_bm (1<<2) /* SDRAM Row-to-Column Delay bit 2 mask. */ |
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#define | EBI_ROWCOLDLY2_bp 2 /* SDRAM Row-to-Column Delay bit 2 position. */ |
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#define | TWI_MASTER_INTLVL_gm 0xC0 /* Interrupt Level group mask. */ |
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#define | TWI_MASTER_INTLVL_gp 6 /* Interrupt Level group position. */ |
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#define | TWI_MASTER_INTLVL0_bm (1<<6) /* Interrupt Level bit 0 mask. */ |
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#define | TWI_MASTER_INTLVL0_bp 6 /* Interrupt Level bit 0 position. */ |
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#define | TWI_MASTER_INTLVL1_bm (1<<7) /* Interrupt Level bit 1 mask. */ |
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#define | TWI_MASTER_INTLVL1_bp 7 /* Interrupt Level bit 1 position. */ |
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#define | TWI_MASTER_RIEN_bm 0x20 /* Read Interrupt Enable bit mask. */ |
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#define | TWI_MASTER_RIEN_bp 5 /* Read Interrupt Enable bit position. */ |
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#define | TWI_MASTER_WIEN_bm 0x10 /* Write Interrupt Enable bit mask. */ |
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#define | TWI_MASTER_WIEN_bp 4 /* Write Interrupt Enable bit position. */ |
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#define | TWI_MASTER_ENABLE_bm 0x08 /* Enable TWI Master bit mask. */ |
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#define | TWI_MASTER_ENABLE_bp 3 /* Enable TWI Master bit position. */ |
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#define | TWI_MASTER_TIMEOUT_gm 0x0C /* Inactive Bus Timeout group mask. */ |
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#define | TWI_MASTER_TIMEOUT_gp 2 /* Inactive Bus Timeout group position. */ |
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#define | TWI_MASTER_TIMEOUT0_bm (1<<2) /* Inactive Bus Timeout bit 0 mask. */ |
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#define | TWI_MASTER_TIMEOUT0_bp 2 /* Inactive Bus Timeout bit 0 position. */ |
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#define | TWI_MASTER_TIMEOUT1_bm (1<<3) /* Inactive Bus Timeout bit 1 mask. */ |
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#define | TWI_MASTER_TIMEOUT1_bp 3 /* Inactive Bus Timeout bit 1 position. */ |
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#define | TWI_MASTER_QCEN_bm 0x02 /* Quick Command Enable bit mask. */ |
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#define | TWI_MASTER_QCEN_bp 1 /* Quick Command Enable bit position. */ |
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#define | TWI_MASTER_SMEN_bm 0x01 /* Smart Mode Enable bit mask. */ |
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#define | TWI_MASTER_SMEN_bp 0 /* Smart Mode Enable bit position. */ |
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#define | TWI_MASTER_ACKACT_bm 0x04 /* Acknowledge Action bit mask. */ |
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#define | TWI_MASTER_ACKACT_bp 2 /* Acknowledge Action bit position. */ |
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#define | TWI_MASTER_CMD_gm 0x03 /* Command group mask. */ |
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#define | TWI_MASTER_CMD_gp 0 /* Command group position. */ |
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#define | TWI_MASTER_CMD0_bm (1<<0) /* Command bit 0 mask. */ |
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#define | TWI_MASTER_CMD0_bp 0 /* Command bit 0 position. */ |
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#define | TWI_MASTER_CMD1_bm (1<<1) /* Command bit 1 mask. */ |
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#define | TWI_MASTER_CMD1_bp 1 /* Command bit 1 position. */ |
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#define | TWI_MASTER_RIF_bm 0x80 /* Read Interrupt Flag bit mask. */ |
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#define | TWI_MASTER_RIF_bp 7 /* Read Interrupt Flag bit position. */ |
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#define | TWI_MASTER_WIF_bm 0x40 /* Write Interrupt Flag bit mask. */ |
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#define | TWI_MASTER_WIF_bp 6 /* Write Interrupt Flag bit position. */ |
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#define | TWI_MASTER_CLKHOLD_bm 0x20 /* Clock Hold bit mask. */ |
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#define | TWI_MASTER_CLKHOLD_bp 5 /* Clock Hold bit position. */ |
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#define | TWI_MASTER_RXACK_bm 0x10 /* Received Acknowledge bit mask. */ |
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#define | TWI_MASTER_RXACK_bp 4 /* Received Acknowledge bit position. */ |
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#define | TWI_MASTER_ARBLOST_bm 0x08 /* Arbitration Lost bit mask. */ |
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#define | TWI_MASTER_ARBLOST_bp 3 /* Arbitration Lost bit position. */ |
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#define | TWI_MASTER_BUSERR_bm 0x04 /* Bus Error bit mask. */ |
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#define | TWI_MASTER_BUSERR_bp 2 /* Bus Error bit position. */ |
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#define | TWI_MASTER_BUSSTATE_gm 0x03 /* Bus State group mask. */ |
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#define | TWI_MASTER_BUSSTATE_gp 0 /* Bus State group position. */ |
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#define | TWI_MASTER_BUSSTATE0_bm (1<<0) /* Bus State bit 0 mask. */ |
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#define | TWI_MASTER_BUSSTATE0_bp 0 /* Bus State bit 0 position. */ |
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#define | TWI_MASTER_BUSSTATE1_bm (1<<1) /* Bus State bit 1 mask. */ |
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#define | TWI_MASTER_BUSSTATE1_bp 1 /* Bus State bit 1 position. */ |
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#define | TWI_SLAVE_INTLVL_gm 0xC0 /* Interrupt Level group mask. */ |
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#define | TWI_SLAVE_INTLVL_gp 6 /* Interrupt Level group position. */ |
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#define | TWI_SLAVE_INTLVL0_bm (1<<6) /* Interrupt Level bit 0 mask. */ |
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#define | TWI_SLAVE_INTLVL0_bp 6 /* Interrupt Level bit 0 position. */ |
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#define | TWI_SLAVE_INTLVL1_bm (1<<7) /* Interrupt Level bit 1 mask. */ |
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#define | TWI_SLAVE_INTLVL1_bp 7 /* Interrupt Level bit 1 position. */ |
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#define | TWI_SLAVE_DIEN_bm 0x20 /* Data Interrupt Enable bit mask. */ |
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#define | TWI_SLAVE_DIEN_bp 5 /* Data Interrupt Enable bit position. */ |
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#define | TWI_SLAVE_APIEN_bm 0x10 /* Address/Stop Interrupt Enable bit mask. */ |
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#define | TWI_SLAVE_APIEN_bp 4 /* Address/Stop Interrupt Enable bit position. */ |
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#define | TWI_SLAVE_ENABLE_bm 0x08 /* Enable TWI Slave bit mask. */ |
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#define | TWI_SLAVE_ENABLE_bp 3 /* Enable TWI Slave bit position. */ |
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#define | TWI_SLAVE_PIEN_bm 0x04 /* Stop Interrupt Enable bit mask. */ |
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#define | TWI_SLAVE_PIEN_bp 2 /* Stop Interrupt Enable bit position. */ |
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#define | TWI_SLAVE_PMEN_bm 0x02 /* Promiscuous Mode Enable bit mask. */ |
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#define | TWI_SLAVE_PMEN_bp 1 /* Promiscuous Mode Enable bit position. */ |
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#define | TWI_SLAVE_SMEN_bm 0x01 /* Smart Mode Enable bit mask. */ |
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#define | TWI_SLAVE_SMEN_bp 0 /* Smart Mode Enable bit position. */ |
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#define | TWI_SLAVE_ACKACT_bm 0x04 /* Acknowledge Action bit mask. */ |
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#define | TWI_SLAVE_ACKACT_bp 2 /* Acknowledge Action bit position. */ |
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#define | TWI_SLAVE_CMD_gm 0x03 /* Command group mask. */ |
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#define | TWI_SLAVE_CMD_gp 0 /* Command group position. */ |
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#define | TWI_SLAVE_CMD0_bm (1<<0) /* Command bit 0 mask. */ |
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#define | TWI_SLAVE_CMD0_bp 0 /* Command bit 0 position. */ |
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#define | TWI_SLAVE_CMD1_bm (1<<1) /* Command bit 1 mask. */ |
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#define | TWI_SLAVE_CMD1_bp 1 /* Command bit 1 position. */ |
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#define | TWI_SLAVE_DIF_bm 0x80 /* Data Interrupt Flag bit mask. */ |
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#define | TWI_SLAVE_DIF_bp 7 /* Data Interrupt Flag bit position. */ |
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#define | TWI_SLAVE_APIF_bm 0x40 /* Address/Stop Interrupt Flag bit mask. */ |
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#define | TWI_SLAVE_APIF_bp 6 /* Address/Stop Interrupt Flag bit position. */ |
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#define | TWI_SLAVE_CLKHOLD_bm 0x20 /* Clock Hold bit mask. */ |
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#define | TWI_SLAVE_CLKHOLD_bp 5 /* Clock Hold bit position. */ |
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#define | TWI_SLAVE_RXACK_bm 0x10 /* Received Acknowledge bit mask. */ |
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#define | TWI_SLAVE_RXACK_bp 4 /* Received Acknowledge bit position. */ |
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#define | TWI_SLAVE_COLL_bm 0x08 /* Collision bit mask. */ |
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#define | TWI_SLAVE_COLL_bp 3 /* Collision bit position. */ |
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#define | TWI_SLAVE_BUSERR_bm 0x04 /* Bus Error bit mask. */ |
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#define | TWI_SLAVE_BUSERR_bp 2 /* Bus Error bit position. */ |
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#define | TWI_SLAVE_DIR_bm 0x02 /* Read/Write Direction bit mask. */ |
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#define | TWI_SLAVE_DIR_bp 1 /* Read/Write Direction bit position. */ |
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#define | TWI_SLAVE_AP_bm 0x01 /* Slave Address or Stop bit mask. */ |
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#define | TWI_SLAVE_AP_bp 0 /* Slave Address or Stop bit position. */ |
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#define | TWI_SLAVE_ADDRMASK_gm 0xFE /* Address Mask group mask. */ |
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#define | TWI_SLAVE_ADDRMASK_gp 1 /* Address Mask group position. */ |
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#define | TWI_SLAVE_ADDRMASK0_bm (1<<1) /* Address Mask bit 0 mask. */ |
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#define | TWI_SLAVE_ADDRMASK0_bp 1 /* Address Mask bit 0 position. */ |
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#define | TWI_SLAVE_ADDRMASK1_bm (1<<2) /* Address Mask bit 1 mask. */ |
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#define | TWI_SLAVE_ADDRMASK1_bp 2 /* Address Mask bit 1 position. */ |
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#define | TWI_SLAVE_ADDRMASK2_bm (1<<3) /* Address Mask bit 2 mask. */ |
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#define | TWI_SLAVE_ADDRMASK2_bp 3 /* Address Mask bit 2 position. */ |
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#define | TWI_SLAVE_ADDRMASK3_bm (1<<4) /* Address Mask bit 3 mask. */ |
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#define | TWI_SLAVE_ADDRMASK3_bp 4 /* Address Mask bit 3 position. */ |
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#define | TWI_SLAVE_ADDRMASK4_bm (1<<5) /* Address Mask bit 4 mask. */ |
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#define | TWI_SLAVE_ADDRMASK4_bp 5 /* Address Mask bit 4 position. */ |
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#define | TWI_SLAVE_ADDRMASK5_bm (1<<6) /* Address Mask bit 5 mask. */ |
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#define | TWI_SLAVE_ADDRMASK5_bp 6 /* Address Mask bit 5 position. */ |
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#define | TWI_SLAVE_ADDRMASK6_bm (1<<7) /* Address Mask bit 6 mask. */ |
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#define | TWI_SLAVE_ADDRMASK6_bp 7 /* Address Mask bit 6 position. */ |
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#define | TWI_SLAVE_ADDREN_bm 0x01 /* Address Enable bit mask. */ |
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#define | TWI_SLAVE_ADDREN_bp 0 /* Address Enable bit position. */ |
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#define | TWI_SDAHOLD_bm 0x02 /* SDA Hold Time Enable bit mask. */ |
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#define | TWI_SDAHOLD_bp 1 /* SDA Hold Time Enable bit position. */ |
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#define | TWI_EDIEN_bm 0x01 /* External Driver Interface Enable bit mask. */ |
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#define | TWI_EDIEN_bp 0 /* External Driver Interface Enable bit position. */ |
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#define | PORTCFG_VP1MAP_gm 0xF0 /* Virtual Port 1 Mapping group mask. */ |
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#define | PORTCFG_VP1MAP_gp 4 /* Virtual Port 1 Mapping group position. */ |
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#define | PORTCFG_VP1MAP0_bm (1<<4) /* Virtual Port 1 Mapping bit 0 mask. */ |
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#define | PORTCFG_VP1MAP0_bp 4 /* Virtual Port 1 Mapping bit 0 position. */ |
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#define | PORTCFG_VP1MAP1_bm (1<<5) /* Virtual Port 1 Mapping bit 1 mask. */ |
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#define | PORTCFG_VP1MAP1_bp 5 /* Virtual Port 1 Mapping bit 1 position. */ |
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#define | PORTCFG_VP1MAP2_bm (1<<6) /* Virtual Port 1 Mapping bit 2 mask. */ |
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#define | PORTCFG_VP1MAP2_bp 6 /* Virtual Port 1 Mapping bit 2 position. */ |
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#define | PORTCFG_VP1MAP3_bm (1<<7) /* Virtual Port 1 Mapping bit 3 mask. */ |
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#define | PORTCFG_VP1MAP3_bp 7 /* Virtual Port 1 Mapping bit 3 position. */ |
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#define | PORTCFG_VP0MAP_gm 0x0F /* Virtual Port 0 Mapping group mask. */ |
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#define | PORTCFG_VP0MAP_gp 0 /* Virtual Port 0 Mapping group position. */ |
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#define | PORTCFG_VP0MAP0_bm (1<<0) /* Virtual Port 0 Mapping bit 0 mask. */ |
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#define | PORTCFG_VP0MAP0_bp 0 /* Virtual Port 0 Mapping bit 0 position. */ |
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#define | PORTCFG_VP0MAP1_bm (1<<1) /* Virtual Port 0 Mapping bit 1 mask. */ |
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#define | PORTCFG_VP0MAP1_bp 1 /* Virtual Port 0 Mapping bit 1 position. */ |
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#define | PORTCFG_VP0MAP2_bm (1<<2) /* Virtual Port 0 Mapping bit 2 mask. */ |
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#define | PORTCFG_VP0MAP2_bp 2 /* Virtual Port 0 Mapping bit 2 position. */ |
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#define | PORTCFG_VP0MAP3_bm (1<<3) /* Virtual Port 0 Mapping bit 3 mask. */ |
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#define | PORTCFG_VP0MAP3_bp 3 /* Virtual Port 0 Mapping bit 3 position. */ |
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#define | PORTCFG_VP3MAP_gm 0xF0 /* Virtual Port 3 Mapping group mask. */ |
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#define | PORTCFG_VP3MAP_gp 4 /* Virtual Port 3 Mapping group position. */ |
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#define | PORTCFG_VP3MAP0_bm (1<<4) /* Virtual Port 3 Mapping bit 0 mask. */ |
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#define | PORTCFG_VP3MAP0_bp 4 /* Virtual Port 3 Mapping bit 0 position. */ |
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#define | PORTCFG_VP3MAP1_bm (1<<5) /* Virtual Port 3 Mapping bit 1 mask. */ |
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#define | PORTCFG_VP3MAP1_bp 5 /* Virtual Port 3 Mapping bit 1 position. */ |
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#define | PORTCFG_VP3MAP2_bm (1<<6) /* Virtual Port 3 Mapping bit 2 mask. */ |
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#define | PORTCFG_VP3MAP2_bp 6 /* Virtual Port 3 Mapping bit 2 position. */ |
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#define | PORTCFG_VP3MAP3_bm (1<<7) /* Virtual Port 3 Mapping bit 3 mask. */ |
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#define | PORTCFG_VP3MAP3_bp 7 /* Virtual Port 3 Mapping bit 3 position. */ |
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#define | PORTCFG_VP2MAP_gm 0x0F /* Virtual Port 2 Mapping group mask. */ |
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#define | PORTCFG_VP2MAP_gp 0 /* Virtual Port 2 Mapping group position. */ |
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#define | PORTCFG_VP2MAP0_bm (1<<0) /* Virtual Port 2 Mapping bit 0 mask. */ |
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#define | PORTCFG_VP2MAP0_bp 0 /* Virtual Port 2 Mapping bit 0 position. */ |
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#define | PORTCFG_VP2MAP1_bm (1<<1) /* Virtual Port 2 Mapping bit 1 mask. */ |
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#define | PORTCFG_VP2MAP1_bp 1 /* Virtual Port 2 Mapping bit 1 position. */ |
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#define | PORTCFG_VP2MAP2_bm (1<<2) /* Virtual Port 2 Mapping bit 2 mask. */ |
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#define | PORTCFG_VP2MAP2_bp 2 /* Virtual Port 2 Mapping bit 2 position. */ |
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#define | PORTCFG_VP2MAP3_bm (1<<3) /* Virtual Port 2 Mapping bit 3 mask. */ |
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#define | PORTCFG_VP2MAP3_bp 3 /* Virtual Port 2 Mapping bit 3 position. */ |
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#define | PORTCFG_CLKOUT_gm 0x03 /* Clock Output Port group mask. */ |
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#define | PORTCFG_CLKOUT_gp 0 /* Clock Output Port group position. */ |
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#define | PORTCFG_CLKOUT0_bm (1<<0) /* Clock Output Port bit 0 mask. */ |
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#define | PORTCFG_CLKOUT0_bp 0 /* Clock Output Port bit 0 position. */ |
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#define | PORTCFG_CLKOUT1_bm (1<<1) /* Clock Output Port bit 1 mask. */ |
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#define | PORTCFG_CLKOUT1_bp 1 /* Clock Output Port bit 1 position. */ |
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#define | PORTCFG_EVOUT_gm 0x30 /* Event Output Port group mask. */ |
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#define | PORTCFG_EVOUT_gp 4 /* Event Output Port group position. */ |
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#define | PORTCFG_EVOUT0_bm (1<<4) /* Event Output Port bit 0 mask. */ |
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#define | PORTCFG_EVOUT0_bp 4 /* Event Output Port bit 0 position. */ |
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#define | PORTCFG_EVOUT1_bm (1<<5) /* Event Output Port bit 1 mask. */ |
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#define | PORTCFG_EVOUT1_bp 5 /* Event Output Port bit 1 position. */ |
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#define | VPORT_INT1IF_bm 0x02 /* Port Interrupt 1 Flag bit mask. */ |
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#define | VPORT_INT1IF_bp 1 /* Port Interrupt 1 Flag bit position. */ |
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#define | VPORT_INT0IF_bm 0x01 /* Port Interrupt 0 Flag bit mask. */ |
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#define | VPORT_INT0IF_bp 0 /* Port Interrupt 0 Flag bit position. */ |
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#define | PORT_INT1LVL_gm 0x0C /* Port Interrupt 1 Level group mask. */ |
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#define | PORT_INT1LVL_gp 2 /* Port Interrupt 1 Level group position. */ |
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#define | PORT_INT1LVL0_bm (1<<2) /* Port Interrupt 1 Level bit 0 mask. */ |
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#define | PORT_INT1LVL0_bp 2 /* Port Interrupt 1 Level bit 0 position. */ |
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#define | PORT_INT1LVL1_bm (1<<3) /* Port Interrupt 1 Level bit 1 mask. */ |
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#define | PORT_INT1LVL1_bp 3 /* Port Interrupt 1 Level bit 1 position. */ |
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#define | PORT_INT0LVL_gm 0x03 /* Port Interrupt 0 Level group mask. */ |
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#define | PORT_INT0LVL_gp 0 /* Port Interrupt 0 Level group position. */ |
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#define | PORT_INT0LVL0_bm (1<<0) /* Port Interrupt 0 Level bit 0 mask. */ |
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#define | PORT_INT0LVL0_bp 0 /* Port Interrupt 0 Level bit 0 position. */ |
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#define | PORT_INT0LVL1_bm (1<<1) /* Port Interrupt 0 Level bit 1 mask. */ |
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#define | PORT_INT0LVL1_bp 1 /* Port Interrupt 0 Level bit 1 position. */ |
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#define | PORT_INT1IF_bm 0x02 /* Port Interrupt 1 Flag bit mask. */ |
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#define | PORT_INT1IF_bp 1 /* Port Interrupt 1 Flag bit position. */ |
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#define | PORT_INT0IF_bm 0x01 /* Port Interrupt 0 Flag bit mask. */ |
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#define | PORT_INT0IF_bp 0 /* Port Interrupt 0 Flag bit position. */ |
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#define | PORT_SRLEN_bm 0x80 /* Slew Rate Enable bit mask. */ |
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#define | PORT_SRLEN_bp 7 /* Slew Rate Enable bit position. */ |
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#define | PORT_INVEN_bm 0x40 /* Inverted I/O Enable bit mask. */ |
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#define | PORT_INVEN_bp 6 /* Inverted I/O Enable bit position. */ |
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#define | PORT_OPC_gm 0x38 /* Output/Pull Configuration group mask. */ |
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#define | PORT_OPC_gp 3 /* Output/Pull Configuration group position. */ |
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#define | PORT_OPC0_bm (1<<3) /* Output/Pull Configuration bit 0 mask. */ |
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#define | PORT_OPC0_bp 3 /* Output/Pull Configuration bit 0 position. */ |
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#define | PORT_OPC1_bm (1<<4) /* Output/Pull Configuration bit 1 mask. */ |
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#define | PORT_OPC1_bp 4 /* Output/Pull Configuration bit 1 position. */ |
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#define | PORT_OPC2_bm (1<<5) /* Output/Pull Configuration bit 2 mask. */ |
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#define | PORT_OPC2_bp 5 /* Output/Pull Configuration bit 2 position. */ |
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#define | PORT_ISC_gm 0x07 /* Input/Sense Configuration group mask. */ |
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#define | PORT_ISC_gp 0 /* Input/Sense Configuration group position. */ |
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#define | PORT_ISC0_bm (1<<0) /* Input/Sense Configuration bit 0 mask. */ |
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#define | PORT_ISC0_bp 0 /* Input/Sense Configuration bit 0 position. */ |
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#define | PORT_ISC1_bm (1<<1) /* Input/Sense Configuration bit 1 mask. */ |
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#define | PORT_ISC1_bp 1 /* Input/Sense Configuration bit 1 position. */ |
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#define | PORT_ISC2_bm (1<<2) /* Input/Sense Configuration bit 2 mask. */ |
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#define | PORT_ISC2_bp 2 /* Input/Sense Configuration bit 2 position. */ |
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#define | TC0_CLKSEL_gm 0x0F /* Clock Selection group mask. */ |
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#define | TC0_CLKSEL_gp 0 /* Clock Selection group position. */ |
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#define | TC0_CLKSEL0_bm (1<<0) /* Clock Selection bit 0 mask. */ |
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#define | TC0_CLKSEL0_bp 0 /* Clock Selection bit 0 position. */ |
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#define | TC0_CLKSEL1_bm (1<<1) /* Clock Selection bit 1 mask. */ |
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#define | TC0_CLKSEL1_bp 1 /* Clock Selection bit 1 position. */ |
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#define | TC0_CLKSEL2_bm (1<<2) /* Clock Selection bit 2 mask. */ |
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#define | TC0_CLKSEL2_bp 2 /* Clock Selection bit 2 position. */ |
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#define | TC0_CLKSEL3_bm (1<<3) /* Clock Selection bit 3 mask. */ |
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#define | TC0_CLKSEL3_bp 3 /* Clock Selection bit 3 position. */ |
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#define | TC0_CCDEN_bm 0x80 /* Compare or Capture D Enable bit mask. */ |
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#define | TC0_CCDEN_bp 7 /* Compare or Capture D Enable bit position. */ |
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#define | TC0_CCCEN_bm 0x40 /* Compare or Capture C Enable bit mask. */ |
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#define | TC0_CCCEN_bp 6 /* Compare or Capture C Enable bit position. */ |
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#define | TC0_CCBEN_bm 0x20 /* Compare or Capture B Enable bit mask. */ |
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#define | TC0_CCBEN_bp 5 /* Compare or Capture B Enable bit position. */ |
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#define | TC0_CCAEN_bm 0x10 /* Compare or Capture A Enable bit mask. */ |
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#define | TC0_CCAEN_bp 4 /* Compare or Capture A Enable bit position. */ |
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#define | TC0_WGMODE_gm 0x07 /* Waveform generation mode group mask. */ |
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#define | TC0_WGMODE_gp 0 /* Waveform generation mode group position. */ |
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#define | TC0_WGMODE0_bm (1<<0) /* Waveform generation mode bit 0 mask. */ |
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#define | TC0_WGMODE0_bp 0 /* Waveform generation mode bit 0 position. */ |
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#define | TC0_WGMODE1_bm (1<<1) /* Waveform generation mode bit 1 mask. */ |
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#define | TC0_WGMODE1_bp 1 /* Waveform generation mode bit 1 position. */ |
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#define | TC0_WGMODE2_bm (1<<2) /* Waveform generation mode bit 2 mask. */ |
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#define | TC0_WGMODE2_bp 2 /* Waveform generation mode bit 2 position. */ |
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#define | TC0_CMPD_bm 0x08 /* Compare D Output Value bit mask. */ |
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#define | TC0_CMPD_bp 3 /* Compare D Output Value bit position. */ |
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#define | TC0_CMPC_bm 0x04 /* Compare C Output Value bit mask. */ |
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#define | TC0_CMPC_bp 2 /* Compare C Output Value bit position. */ |
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#define | TC0_CMPB_bm 0x02 /* Compare B Output Value bit mask. */ |
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#define | TC0_CMPB_bp 1 /* Compare B Output Value bit position. */ |
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#define | TC0_CMPA_bm 0x01 /* Compare A Output Value bit mask. */ |
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#define | TC0_CMPA_bp 0 /* Compare A Output Value bit position. */ |
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#define | TC0_EVACT_gm 0xE0 /* Event Action group mask. */ |
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#define | TC0_EVACT_gp 5 /* Event Action group position. */ |
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#define | TC0_EVACT0_bm (1<<5) /* Event Action bit 0 mask. */ |
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#define | TC0_EVACT0_bp 5 /* Event Action bit 0 position. */ |
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#define | TC0_EVACT1_bm (1<<6) /* Event Action bit 1 mask. */ |
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#define | TC0_EVACT1_bp 6 /* Event Action bit 1 position. */ |
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#define | TC0_EVACT2_bm (1<<7) /* Event Action bit 2 mask. */ |
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#define | TC0_EVACT2_bp 7 /* Event Action bit 2 position. */ |
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#define | TC0_EVDLY_bm 0x10 /* Event Delay bit mask. */ |
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#define | TC0_EVDLY_bp 4 /* Event Delay bit position. */ |
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#define | TC0_EVSEL_gm 0x0F /* Event Source Select group mask. */ |
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#define | TC0_EVSEL_gp 0 /* Event Source Select group position. */ |
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#define | TC0_EVSEL0_bm (1<<0) /* Event Source Select bit 0 mask. */ |
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#define | TC0_EVSEL0_bp 0 /* Event Source Select bit 0 position. */ |
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#define | TC0_EVSEL1_bm (1<<1) /* Event Source Select bit 1 mask. */ |
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#define | TC0_EVSEL1_bp 1 /* Event Source Select bit 1 position. */ |
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#define | TC0_EVSEL2_bm (1<<2) /* Event Source Select bit 2 mask. */ |
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#define | TC0_EVSEL2_bp 2 /* Event Source Select bit 2 position. */ |
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#define | TC0_EVSEL3_bm (1<<3) /* Event Source Select bit 3 mask. */ |
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#define | TC0_EVSEL3_bp 3 /* Event Source Select bit 3 position. */ |
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#define | TC0_DTHM_bm 0x02 /* Dead Time Hold Mode bit mask. */ |
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#define | TC0_DTHM_bp 1 /* Dead Time Hold Mode bit position. */ |
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#define | TC0_BYTEM_bm 0x01 /* Byte Mode bit mask. */ |
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#define | TC0_BYTEM_bp 0 /* Byte Mode bit position. */ |
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#define | TC0_ERRINTLVL_gm 0x0C /* Error Interrupt Level group mask. */ |
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#define | TC0_ERRINTLVL_gp 2 /* Error Interrupt Level group position. */ |
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#define | TC0_ERRINTLVL0_bm (1<<2) /* Error Interrupt Level bit 0 mask. */ |
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#define | TC0_ERRINTLVL0_bp 2 /* Error Interrupt Level bit 0 position. */ |
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#define | TC0_ERRINTLVL1_bm (1<<3) /* Error Interrupt Level bit 1 mask. */ |
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#define | TC0_ERRINTLVL1_bp 3 /* Error Interrupt Level bit 1 position. */ |
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#define | TC0_OVFINTLVL_gm 0x03 /* Overflow interrupt level group mask. */ |
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#define | TC0_OVFINTLVL_gp 0 /* Overflow interrupt level group position. */ |
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#define | TC0_OVFINTLVL0_bm (1<<0) /* Overflow interrupt level bit 0 mask. */ |
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#define | TC0_OVFINTLVL0_bp 0 /* Overflow interrupt level bit 0 position. */ |
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#define | TC0_OVFINTLVL1_bm (1<<1) /* Overflow interrupt level bit 1 mask. */ |
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#define | TC0_OVFINTLVL1_bp 1 /* Overflow interrupt level bit 1 position. */ |
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#define | TC0_CCDINTLVL_gm 0xC0 /* Compare or Capture D Interrupt Level group mask. */ |
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#define | TC0_CCDINTLVL_gp 6 /* Compare or Capture D Interrupt Level group position. */ |
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#define | TC0_CCDINTLVL0_bm (1<<6) /* Compare or Capture D Interrupt Level bit 0 mask. */ |
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#define | TC0_CCDINTLVL0_bp 6 /* Compare or Capture D Interrupt Level bit 0 position. */ |
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#define | TC0_CCDINTLVL1_bm (1<<7) /* Compare or Capture D Interrupt Level bit 1 mask. */ |
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#define | TC0_CCDINTLVL1_bp 7 /* Compare or Capture D Interrupt Level bit 1 position. */ |
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#define | TC0_CCCINTLVL_gm 0x30 /* Compare or Capture C Interrupt Level group mask. */ |
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#define | TC0_CCCINTLVL_gp 4 /* Compare or Capture C Interrupt Level group position. */ |
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#define | TC0_CCCINTLVL0_bm (1<<4) /* Compare or Capture C Interrupt Level bit 0 mask. */ |
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#define | TC0_CCCINTLVL0_bp 4 /* Compare or Capture C Interrupt Level bit 0 position. */ |
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#define | TC0_CCCINTLVL1_bm (1<<5) /* Compare or Capture C Interrupt Level bit 1 mask. */ |
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#define | TC0_CCCINTLVL1_bp 5 /* Compare or Capture C Interrupt Level bit 1 position. */ |
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#define | TC0_CCBINTLVL_gm 0x0C /* Compare or Capture B Interrupt Level group mask. */ |
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#define | TC0_CCBINTLVL_gp 2 /* Compare or Capture B Interrupt Level group position. */ |
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#define | TC0_CCBINTLVL0_bm (1<<2) /* Compare or Capture B Interrupt Level bit 0 mask. */ |
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#define | TC0_CCBINTLVL0_bp 2 /* Compare or Capture B Interrupt Level bit 0 position. */ |
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#define | TC0_CCBINTLVL1_bm (1<<3) /* Compare or Capture B Interrupt Level bit 1 mask. */ |
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#define | TC0_CCBINTLVL1_bp 3 /* Compare or Capture B Interrupt Level bit 1 position. */ |
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#define | TC0_CCAINTLVL_gm 0x03 /* Compare or Capture A Interrupt Level group mask. */ |
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#define | TC0_CCAINTLVL_gp 0 /* Compare or Capture A Interrupt Level group position. */ |
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#define | TC0_CCAINTLVL0_bm (1<<0) /* Compare or Capture A Interrupt Level bit 0 mask. */ |
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#define | TC0_CCAINTLVL0_bp 0 /* Compare or Capture A Interrupt Level bit 0 position. */ |
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#define | TC0_CCAINTLVL1_bm (1<<1) /* Compare or Capture A Interrupt Level bit 1 mask. */ |
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#define | TC0_CCAINTLVL1_bp 1 /* Compare or Capture A Interrupt Level bit 1 position. */ |
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#define | TC0_CMD_gm 0x0C /* Command group mask. */ |
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#define | TC0_CMD_gp 2 /* Command group position. */ |
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#define | TC0_CMD0_bm (1<<2) /* Command bit 0 mask. */ |
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#define | TC0_CMD0_bp 2 /* Command bit 0 position. */ |
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#define | TC0_CMD1_bm (1<<3) /* Command bit 1 mask. */ |
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#define | TC0_CMD1_bp 3 /* Command bit 1 position. */ |
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#define | TC0_LUPD_bm 0x02 /* Lock Update bit mask. */ |
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#define | TC0_LUPD_bp 1 /* Lock Update bit position. */ |
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#define | TC0_DIR_bm 0x01 /* Direction bit mask. */ |
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#define | TC0_DIR_bp 0 /* Direction bit position. */ |
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#define | TC0_CCDBV_bm 0x10 /* Compare or Capture D Buffer Valid bit mask. */ |
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#define | TC0_CCDBV_bp 4 /* Compare or Capture D Buffer Valid bit position. */ |
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#define | TC0_CCCBV_bm 0x08 /* Compare or Capture C Buffer Valid bit mask. */ |
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#define | TC0_CCCBV_bp 3 /* Compare or Capture C Buffer Valid bit position. */ |
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#define | TC0_CCBBV_bm 0x04 /* Compare or Capture B Buffer Valid bit mask. */ |
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#define | TC0_CCBBV_bp 2 /* Compare or Capture B Buffer Valid bit position. */ |
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#define | TC0_CCABV_bm 0x02 /* Compare or Capture A Buffer Valid bit mask. */ |
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#define | TC0_CCABV_bp 1 /* Compare or Capture A Buffer Valid bit position. */ |
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#define | TC0_PERBV_bm 0x01 /* Period Buffer Valid bit mask. */ |
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#define | TC0_PERBV_bp 0 /* Period Buffer Valid bit position. */ |
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#define | TC0_CCDIF_bm 0x80 /* Compare or Capture D Interrupt Flag bit mask. */ |
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#define | TC0_CCDIF_bp 7 /* Compare or Capture D Interrupt Flag bit position. */ |
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#define | TC0_CCCIF_bm 0x40 /* Compare or Capture C Interrupt Flag bit mask. */ |
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#define | TC0_CCCIF_bp 6 /* Compare or Capture C Interrupt Flag bit position. */ |
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#define | TC0_CCBIF_bm 0x20 /* Compare or Capture B Interrupt Flag bit mask. */ |
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#define | TC0_CCBIF_bp 5 /* Compare or Capture B Interrupt Flag bit position. */ |
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#define | TC0_CCAIF_bm 0x10 /* Compare or Capture A Interrupt Flag bit mask. */ |
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#define | TC0_CCAIF_bp 4 /* Compare or Capture A Interrupt Flag bit position. */ |
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#define | TC0_ERRIF_bm 0x02 /* Error Interrupt Flag bit mask. */ |
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#define | TC0_ERRIF_bp 1 /* Error Interrupt Flag bit position. */ |
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#define | TC0_OVFIF_bm 0x01 /* Overflow Interrupt Flag bit mask. */ |
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#define | TC0_OVFIF_bp 0 /* Overflow Interrupt Flag bit position. */ |
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#define | TC1_CLKSEL_gm 0x0F /* Clock Selection group mask. */ |
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#define | TC1_CLKSEL_gp 0 /* Clock Selection group position. */ |
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#define | TC1_CLKSEL0_bm (1<<0) /* Clock Selection bit 0 mask. */ |
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#define | TC1_CLKSEL0_bp 0 /* Clock Selection bit 0 position. */ |
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#define | TC1_CLKSEL1_bm (1<<1) /* Clock Selection bit 1 mask. */ |
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#define | TC1_CLKSEL1_bp 1 /* Clock Selection bit 1 position. */ |
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#define | TC1_CLKSEL2_bm (1<<2) /* Clock Selection bit 2 mask. */ |
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#define | TC1_CLKSEL2_bp 2 /* Clock Selection bit 2 position. */ |
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#define | TC1_CLKSEL3_bm (1<<3) /* Clock Selection bit 3 mask. */ |
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#define | TC1_CLKSEL3_bp 3 /* Clock Selection bit 3 position. */ |
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#define | TC1_CCBEN_bm 0x20 /* Compare or Capture B Enable bit mask. */ |
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#define | TC1_CCBEN_bp 5 /* Compare or Capture B Enable bit position. */ |
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#define | TC1_CCAEN_bm 0x10 /* Compare or Capture A Enable bit mask. */ |
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#define | TC1_CCAEN_bp 4 /* Compare or Capture A Enable bit position. */ |
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#define | TC1_WGMODE_gm 0x07 /* Waveform generation mode group mask. */ |
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#define | TC1_WGMODE_gp 0 /* Waveform generation mode group position. */ |
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#define | TC1_WGMODE0_bm (1<<0) /* Waveform generation mode bit 0 mask. */ |
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#define | TC1_WGMODE0_bp 0 /* Waveform generation mode bit 0 position. */ |
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#define | TC1_WGMODE1_bm (1<<1) /* Waveform generation mode bit 1 mask. */ |
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#define | TC1_WGMODE1_bp 1 /* Waveform generation mode bit 1 position. */ |
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#define | TC1_WGMODE2_bm (1<<2) /* Waveform generation mode bit 2 mask. */ |
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#define | TC1_WGMODE2_bp 2 /* Waveform generation mode bit 2 position. */ |
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#define | TC1_CMPB_bm 0x02 /* Compare B Output Value bit mask. */ |
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#define | TC1_CMPB_bp 1 /* Compare B Output Value bit position. */ |
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#define | TC1_CMPA_bm 0x01 /* Compare A Output Value bit mask. */ |
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#define | TC1_CMPA_bp 0 /* Compare A Output Value bit position. */ |
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#define | TC1_EVACT_gm 0xE0 /* Event Action group mask. */ |
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#define | TC1_EVACT_gp 5 /* Event Action group position. */ |
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#define | TC1_EVACT0_bm (1<<5) /* Event Action bit 0 mask. */ |
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#define | TC1_EVACT0_bp 5 /* Event Action bit 0 position. */ |
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#define | TC1_EVACT1_bm (1<<6) /* Event Action bit 1 mask. */ |
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#define | TC1_EVACT1_bp 6 /* Event Action bit 1 position. */ |
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#define | TC1_EVACT2_bm (1<<7) /* Event Action bit 2 mask. */ |
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#define | TC1_EVACT2_bp 7 /* Event Action bit 2 position. */ |
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#define | TC1_EVDLY_bm 0x10 /* Event Delay bit mask. */ |
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#define | TC1_EVDLY_bp 4 /* Event Delay bit position. */ |
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#define | TC1_EVSEL_gm 0x0F /* Event Source Select group mask. */ |
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#define | TC1_EVSEL_gp 0 /* Event Source Select group position. */ |
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#define | TC1_EVSEL0_bm (1<<0) /* Event Source Select bit 0 mask. */ |
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#define | TC1_EVSEL0_bp 0 /* Event Source Select bit 0 position. */ |
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#define | TC1_EVSEL1_bm (1<<1) /* Event Source Select bit 1 mask. */ |
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#define | TC1_EVSEL1_bp 1 /* Event Source Select bit 1 position. */ |
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#define | TC1_EVSEL2_bm (1<<2) /* Event Source Select bit 2 mask. */ |
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#define | TC1_EVSEL2_bp 2 /* Event Source Select bit 2 position. */ |
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#define | TC1_EVSEL3_bm (1<<3) /* Event Source Select bit 3 mask. */ |
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#define | TC1_EVSEL3_bp 3 /* Event Source Select bit 3 position. */ |
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#define | TC1_DTHM_bm 0x02 /* Dead Time Hold Mode bit mask. */ |
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#define | TC1_DTHM_bp 1 /* Dead Time Hold Mode bit position. */ |
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#define | TC1_BYTEM_bm 0x01 /* Byte Mode bit mask. */ |
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#define | TC1_BYTEM_bp 0 /* Byte Mode bit position. */ |
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#define | TC1_ERRINTLVL_gm 0x0C /* Error Interrupt Level group mask. */ |
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#define | TC1_ERRINTLVL_gp 2 /* Error Interrupt Level group position. */ |
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#define | TC1_ERRINTLVL0_bm (1<<2) /* Error Interrupt Level bit 0 mask. */ |
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#define | TC1_ERRINTLVL0_bp 2 /* Error Interrupt Level bit 0 position. */ |
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#define | TC1_ERRINTLVL1_bm (1<<3) /* Error Interrupt Level bit 1 mask. */ |
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#define | TC1_ERRINTLVL1_bp 3 /* Error Interrupt Level bit 1 position. */ |
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#define | TC1_OVFINTLVL_gm 0x03 /* Overflow interrupt level group mask. */ |
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#define | TC1_OVFINTLVL_gp 0 /* Overflow interrupt level group position. */ |
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#define | TC1_OVFINTLVL0_bm (1<<0) /* Overflow interrupt level bit 0 mask. */ |
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#define | TC1_OVFINTLVL0_bp 0 /* Overflow interrupt level bit 0 position. */ |
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#define | TC1_OVFINTLVL1_bm (1<<1) /* Overflow interrupt level bit 1 mask. */ |
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#define | TC1_OVFINTLVL1_bp 1 /* Overflow interrupt level bit 1 position. */ |
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#define | TC1_CCBINTLVL_gm 0x0C /* Compare or Capture B Interrupt Level group mask. */ |
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#define | TC1_CCBINTLVL_gp 2 /* Compare or Capture B Interrupt Level group position. */ |
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#define | TC1_CCBINTLVL0_bm (1<<2) /* Compare or Capture B Interrupt Level bit 0 mask. */ |
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#define | TC1_CCBINTLVL0_bp 2 /* Compare or Capture B Interrupt Level bit 0 position. */ |
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#define | TC1_CCBINTLVL1_bm (1<<3) /* Compare or Capture B Interrupt Level bit 1 mask. */ |
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#define | TC1_CCBINTLVL1_bp 3 /* Compare or Capture B Interrupt Level bit 1 position. */ |
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#define | TC1_CCAINTLVL_gm 0x03 /* Compare or Capture A Interrupt Level group mask. */ |
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#define | TC1_CCAINTLVL_gp 0 /* Compare or Capture A Interrupt Level group position. */ |
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#define | TC1_CCAINTLVL0_bm (1<<0) /* Compare or Capture A Interrupt Level bit 0 mask. */ |
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#define | TC1_CCAINTLVL0_bp 0 /* Compare or Capture A Interrupt Level bit 0 position. */ |
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#define | TC1_CCAINTLVL1_bm (1<<1) /* Compare or Capture A Interrupt Level bit 1 mask. */ |
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#define | TC1_CCAINTLVL1_bp 1 /* Compare or Capture A Interrupt Level bit 1 position. */ |
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#define | TC1_CMD_gm 0x0C /* Command group mask. */ |
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#define | TC1_CMD_gp 2 /* Command group position. */ |
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#define | TC1_CMD0_bm (1<<2) /* Command bit 0 mask. */ |
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#define | TC1_CMD0_bp 2 /* Command bit 0 position. */ |
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#define | TC1_CMD1_bm (1<<3) /* Command bit 1 mask. */ |
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#define | TC1_CMD1_bp 3 /* Command bit 1 position. */ |
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#define | TC1_LUPD_bm 0x02 /* Lock Update bit mask. */ |
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#define | TC1_LUPD_bp 1 /* Lock Update bit position. */ |
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#define | TC1_DIR_bm 0x01 /* Direction bit mask. */ |
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#define | TC1_DIR_bp 0 /* Direction bit position. */ |
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#define | TC1_CCBBV_bm 0x04 /* Compare or Capture B Buffer Valid bit mask. */ |
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#define | TC1_CCBBV_bp 2 /* Compare or Capture B Buffer Valid bit position. */ |
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#define | TC1_CCABV_bm 0x02 /* Compare or Capture A Buffer Valid bit mask. */ |
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#define | TC1_CCABV_bp 1 /* Compare or Capture A Buffer Valid bit position. */ |
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#define | TC1_PERBV_bm 0x01 /* Period Buffer Valid bit mask. */ |
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#define | TC1_PERBV_bp 0 /* Period Buffer Valid bit position. */ |
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#define | TC1_CCBIF_bm 0x20 /* Compare or Capture B Interrupt Flag bit mask. */ |
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#define | TC1_CCBIF_bp 5 /* Compare or Capture B Interrupt Flag bit position. */ |
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#define | TC1_CCAIF_bm 0x10 /* Compare or Capture A Interrupt Flag bit mask. */ |
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#define | TC1_CCAIF_bp 4 /* Compare or Capture A Interrupt Flag bit position. */ |
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#define | TC1_ERRIF_bm 0x02 /* Error Interrupt Flag bit mask. */ |
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#define | TC1_ERRIF_bp 1 /* Error Interrupt Flag bit position. */ |
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#define | TC1_OVFIF_bm 0x01 /* Overflow Interrupt Flag bit mask. */ |
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#define | TC1_OVFIF_bp 0 /* Overflow Interrupt Flag bit position. */ |
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#define | AWEX_PGM_bm 0x20 /* Pattern Generation Mode bit mask. */ |
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#define | AWEX_PGM_bp 5 /* Pattern Generation Mode bit position. */ |
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#define | AWEX_CWCM_bm 0x10 /* Common Waveform Channel Mode bit mask. */ |
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#define | AWEX_CWCM_bp 4 /* Common Waveform Channel Mode bit position. */ |
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#define | AWEX_DTICCDEN_bm 0x08 /* Dead Time Insertion Compare Channel D Enable bit mask. */ |
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#define | AWEX_DTICCDEN_bp 3 /* Dead Time Insertion Compare Channel D Enable bit position. */ |
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#define | AWEX_DTICCCEN_bm 0x04 /* Dead Time Insertion Compare Channel C Enable bit mask. */ |
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#define | AWEX_DTICCCEN_bp 2 /* Dead Time Insertion Compare Channel C Enable bit position. */ |
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#define | AWEX_DTICCBEN_bm 0x02 /* Dead Time Insertion Compare Channel B Enable bit mask. */ |
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#define | AWEX_DTICCBEN_bp 1 /* Dead Time Insertion Compare Channel B Enable bit position. */ |
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#define | AWEX_DTICCAEN_bm 0x01 /* Dead Time Insertion Compare Channel A Enable bit mask. */ |
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#define | AWEX_DTICCAEN_bp 0 /* Dead Time Insertion Compare Channel A Enable bit position. */ |
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#define | AWEX_FDDBD_bm 0x10 /* Fault Detect on Disable Break Disable bit mask. */ |
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#define | AWEX_FDDBD_bp 4 /* Fault Detect on Disable Break Disable bit position. */ |
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#define | AWEX_FDMODE_bm 0x04 /* Fault Detect Mode bit mask. */ |
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#define | AWEX_FDMODE_bp 2 /* Fault Detect Mode bit position. */ |
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#define | AWEX_FDACT_gm 0x03 /* Fault Detect Action group mask. */ |
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#define | AWEX_FDACT_gp 0 /* Fault Detect Action group position. */ |
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#define | AWEX_FDACT0_bm (1<<0) /* Fault Detect Action bit 0 mask. */ |
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#define | AWEX_FDACT0_bp 0 /* Fault Detect Action bit 0 position. */ |
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#define | AWEX_FDACT1_bm (1<<1) /* Fault Detect Action bit 1 mask. */ |
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#define | AWEX_FDACT1_bp 1 /* Fault Detect Action bit 1 position. */ |
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#define | AWEX_FDF_bm 0x04 /* Fault Detect Flag bit mask. */ |
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#define | AWEX_FDF_bp 2 /* Fault Detect Flag bit position. */ |
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#define | AWEX_DTHSBUFV_bm 0x02 /* Dead Time High Side Buffer Valid bit mask. */ |
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#define | AWEX_DTHSBUFV_bp 1 /* Dead Time High Side Buffer Valid bit position. */ |
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#define | AWEX_DTLSBUFV_bm 0x01 /* Dead Time Low Side Buffer Valid bit mask. */ |
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#define | AWEX_DTLSBUFV_bp 0 /* Dead Time Low Side Buffer Valid bit position. */ |
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#define | HIRES_HREN_gm 0x03 /* High Resolution Enable group mask. */ |
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#define | HIRES_HREN_gp 0 /* High Resolution Enable group position. */ |
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#define | HIRES_HREN0_bm (1<<0) /* High Resolution Enable bit 0 mask. */ |
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#define | HIRES_HREN0_bp 0 /* High Resolution Enable bit 0 position. */ |
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#define | HIRES_HREN1_bm (1<<1) /* High Resolution Enable bit 1 mask. */ |
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#define | HIRES_HREN1_bp 1 /* High Resolution Enable bit 1 position. */ |
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#define | USART_RXCIF_bm 0x80 /* Receive Interrupt Flag bit mask. */ |
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#define | USART_RXCIF_bp 7 /* Receive Interrupt Flag bit position. */ |
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#define | USART_TXCIF_bm 0x40 /* Transmit Interrupt Flag bit mask. */ |
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#define | USART_TXCIF_bp 6 /* Transmit Interrupt Flag bit position. */ |
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#define | USART_DREIF_bm 0x20 /* Data Register Empty Flag bit mask. */ |
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#define | USART_DREIF_bp 5 /* Data Register Empty Flag bit position. */ |
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#define | USART_FERR_bm 0x10 /* Frame Error bit mask. */ |
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#define | USART_FERR_bp 4 /* Frame Error bit position. */ |
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#define | USART_BUFOVF_bm 0x08 /* Buffer Overflow bit mask. */ |
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#define | USART_BUFOVF_bp 3 /* Buffer Overflow bit position. */ |
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#define | USART_PERR_bm 0x04 /* Parity Error bit mask. */ |
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#define | USART_PERR_bp 2 /* Parity Error bit position. */ |
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#define | USART_RXB8_bm 0x01 /* Receive Bit 8 bit mask. */ |
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#define | USART_RXB8_bp 0 /* Receive Bit 8 bit position. */ |
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#define | USART_RXCINTLVL_gm 0x30 /* Receive Interrupt Level group mask. */ |
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#define | USART_RXCINTLVL_gp 4 /* Receive Interrupt Level group position. */ |
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#define | USART_RXCINTLVL0_bm (1<<4) /* Receive Interrupt Level bit 0 mask. */ |
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#define | USART_RXCINTLVL0_bp 4 /* Receive Interrupt Level bit 0 position. */ |
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#define | USART_RXCINTLVL1_bm (1<<5) /* Receive Interrupt Level bit 1 mask. */ |
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#define | USART_RXCINTLVL1_bp 5 /* Receive Interrupt Level bit 1 position. */ |
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#define | USART_TXCINTLVL_gm 0x0C /* Transmit Interrupt Level group mask. */ |
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#define | USART_TXCINTLVL_gp 2 /* Transmit Interrupt Level group position. */ |
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#define | USART_TXCINTLVL0_bm (1<<2) /* Transmit Interrupt Level bit 0 mask. */ |
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#define | USART_TXCINTLVL0_bp 2 /* Transmit Interrupt Level bit 0 position. */ |
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#define | USART_TXCINTLVL1_bm (1<<3) /* Transmit Interrupt Level bit 1 mask. */ |
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#define | USART_TXCINTLVL1_bp 3 /* Transmit Interrupt Level bit 1 position. */ |
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#define | USART_DREINTLVL_gm 0x03 /* Data Register Empty Interrupt Level group mask. */ |
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#define | USART_DREINTLVL_gp 0 /* Data Register Empty Interrupt Level group position. */ |
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#define | USART_DREINTLVL0_bm (1<<0) /* Data Register Empty Interrupt Level bit 0 mask. */ |
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#define | USART_DREINTLVL0_bp 0 /* Data Register Empty Interrupt Level bit 0 position. */ |
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#define | USART_DREINTLVL1_bm (1<<1) /* Data Register Empty Interrupt Level bit 1 mask. */ |
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#define | USART_DREINTLVL1_bp 1 /* Data Register Empty Interrupt Level bit 1 position. */ |
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#define | USART_RXEN_bm 0x10 /* Receiver Enable bit mask. */ |
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#define | USART_RXEN_bp 4 /* Receiver Enable bit position. */ |
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#define | USART_TXEN_bm 0x08 /* Transmitter Enable bit mask. */ |
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#define | USART_TXEN_bp 3 /* Transmitter Enable bit position. */ |
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#define | USART_CLK2X_bm 0x04 /* Double transmission speed bit mask. */ |
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#define | USART_CLK2X_bp 2 /* Double transmission speed bit position. */ |
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#define | USART_MPCM_bm 0x02 /* Multi-processor Communication Mode bit mask. */ |
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#define | USART_MPCM_bp 1 /* Multi-processor Communication Mode bit position. */ |
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#define | USART_TXB8_bm 0x01 /* Transmit bit 8 bit mask. */ |
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#define | USART_TXB8_bp 0 /* Transmit bit 8 bit position. */ |
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#define | USART_CMODE_gm 0xC0 /* Communication Mode group mask. */ |
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#define | USART_CMODE_gp 6 /* Communication Mode group position. */ |
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#define | USART_CMODE0_bm (1<<6) /* Communication Mode bit 0 mask. */ |
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#define | USART_CMODE0_bp 6 /* Communication Mode bit 0 position. */ |
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#define | USART_CMODE1_bm (1<<7) /* Communication Mode bit 1 mask. */ |
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#define | USART_CMODE1_bp 7 /* Communication Mode bit 1 position. */ |
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#define | USART_PMODE_gm 0x30 /* Parity Mode group mask. */ |
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#define | USART_PMODE_gp 4 /* Parity Mode group position. */ |
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#define | USART_PMODE0_bm (1<<4) /* Parity Mode bit 0 mask. */ |
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#define | USART_PMODE0_bp 4 /* Parity Mode bit 0 position. */ |
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#define | USART_PMODE1_bm (1<<5) /* Parity Mode bit 1 mask. */ |
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#define | USART_PMODE1_bp 5 /* Parity Mode bit 1 position. */ |
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#define | USART_SBMODE_bm 0x08 /* Stop Bit Mode bit mask. */ |
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#define | USART_SBMODE_bp 3 /* Stop Bit Mode bit position. */ |
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#define | USART_CHSIZE_gm 0x07 /* Character Size group mask. */ |
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#define | USART_CHSIZE_gp 0 /* Character Size group position. */ |
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#define | USART_CHSIZE0_bm (1<<0) /* Character Size bit 0 mask. */ |
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#define | USART_CHSIZE0_bp 0 /* Character Size bit 0 position. */ |
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#define | USART_CHSIZE1_bm (1<<1) /* Character Size bit 1 mask. */ |
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#define | USART_CHSIZE1_bp 1 /* Character Size bit 1 position. */ |
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#define | USART_CHSIZE2_bm (1<<2) /* Character Size bit 2 mask. */ |
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#define | USART_CHSIZE2_bp 2 /* Character Size bit 2 position. */ |
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#define | USART_BSEL_gm 0xFF /* Baud Rate Selection Bits [7:0] group mask. */ |
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#define | USART_BSEL_gp 0 /* Baud Rate Selection Bits [7:0] group position. */ |
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#define | USART_BSEL0_bm (1<<0) /* Baud Rate Selection Bits [7:0] bit 0 mask. */ |
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#define | USART_BSEL0_bp 0 /* Baud Rate Selection Bits [7:0] bit 0 position. */ |
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#define | USART_BSEL1_bm (1<<1) /* Baud Rate Selection Bits [7:0] bit 1 mask. */ |
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#define | USART_BSEL1_bp 1 /* Baud Rate Selection Bits [7:0] bit 1 position. */ |
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#define | USART_BSEL2_bm (1<<2) /* Baud Rate Selection Bits [7:0] bit 2 mask. */ |
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#define | USART_BSEL2_bp 2 /* Baud Rate Selection Bits [7:0] bit 2 position. */ |
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#define | USART_BSEL3_bm (1<<3) /* Baud Rate Selection Bits [7:0] bit 3 mask. */ |
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#define | USART_BSEL3_bp 3 /* Baud Rate Selection Bits [7:0] bit 3 position. */ |
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#define | USART_BSEL4_bm (1<<4) /* Baud Rate Selection Bits [7:0] bit 4 mask. */ |
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#define | USART_BSEL4_bp 4 /* Baud Rate Selection Bits [7:0] bit 4 position. */ |
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#define | USART_BSEL5_bm (1<<5) /* Baud Rate Selection Bits [7:0] bit 5 mask. */ |
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#define | USART_BSEL5_bp 5 /* Baud Rate Selection Bits [7:0] bit 5 position. */ |
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#define | USART_BSEL6_bm (1<<6) /* Baud Rate Selection Bits [7:0] bit 6 mask. */ |
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#define | USART_BSEL6_bp 6 /* Baud Rate Selection Bits [7:0] bit 6 position. */ |
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#define | USART_BSEL7_bm (1<<7) /* Baud Rate Selection Bits [7:0] bit 7 mask. */ |
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#define | USART_BSEL7_bp 7 /* Baud Rate Selection Bits [7:0] bit 7 position. */ |
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#define | USART_BSCALE_gm 0xF0 /* Baud Rate Scale group mask. */ |
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#define | USART_BSCALE_gp 4 /* Baud Rate Scale group position. */ |
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#define | USART_BSCALE0_bm (1<<4) /* Baud Rate Scale bit 0 mask. */ |
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#define | USART_BSCALE0_bp 4 /* Baud Rate Scale bit 0 position. */ |
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#define | USART_BSCALE1_bm (1<<5) /* Baud Rate Scale bit 1 mask. */ |
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#define | USART_BSCALE1_bp 5 /* Baud Rate Scale bit 1 position. */ |
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#define | USART_BSCALE2_bm (1<<6) /* Baud Rate Scale bit 2 mask. */ |
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#define | USART_BSCALE2_bp 6 /* Baud Rate Scale bit 2 position. */ |
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#define | USART_BSCALE3_bm (1<<7) /* Baud Rate Scale bit 3 mask. */ |
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#define | USART_BSCALE3_bp 7 /* Baud Rate Scale bit 3 position. */ |
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#define | SPI_CLK2X_bm 0x80 /* Enable Double Speed bit mask. */ |
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#define | SPI_CLK2X_bp 7 /* Enable Double Speed bit position. */ |
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#define | SPI_ENABLE_bm 0x40 /* Enable Module bit mask. */ |
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#define | SPI_ENABLE_bp 6 /* Enable Module bit position. */ |
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#define | SPI_DORD_bm 0x20 /* Data Order Setting bit mask. */ |
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#define | SPI_DORD_bp 5 /* Data Order Setting bit position. */ |
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#define | SPI_MASTER_bm 0x10 /* Master Operation Enable bit mask. */ |
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#define | SPI_MASTER_bp 4 /* Master Operation Enable bit position. */ |
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#define | SPI_MODE_gm 0x0C /* SPI Mode group mask. */ |
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#define | SPI_MODE_gp 2 /* SPI Mode group position. */ |
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#define | SPI_MODE0_bm (1<<2) /* SPI Mode bit 0 mask. */ |
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#define | SPI_MODE0_bp 2 /* SPI Mode bit 0 position. */ |
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#define | SPI_MODE1_bm (1<<3) /* SPI Mode bit 1 mask. */ |
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#define | SPI_MODE1_bp 3 /* SPI Mode bit 1 position. */ |
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#define | SPI_PRESCALER_gm 0x03 /* Prescaler group mask. */ |
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#define | SPI_PRESCALER_gp 0 /* Prescaler group position. */ |
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#define | SPI_PRESCALER0_bm (1<<0) /* Prescaler bit 0 mask. */ |
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#define | SPI_PRESCALER0_bp 0 /* Prescaler bit 0 position. */ |
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#define | SPI_PRESCALER1_bm (1<<1) /* Prescaler bit 1 mask. */ |
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#define | SPI_PRESCALER1_bp 1 /* Prescaler bit 1 position. */ |
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#define | SPI_INTLVL_gm 0x03 /* Interrupt level group mask. */ |
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#define | SPI_INTLVL_gp 0 /* Interrupt level group position. */ |
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#define | SPI_INTLVL0_bm (1<<0) /* Interrupt level bit 0 mask. */ |
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#define | SPI_INTLVL0_bp 0 /* Interrupt level bit 0 position. */ |
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#define | SPI_INTLVL1_bm (1<<1) /* Interrupt level bit 1 mask. */ |
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#define | SPI_INTLVL1_bp 1 /* Interrupt level bit 1 position. */ |
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#define | SPI_IF_bm 0x80 /* Interrupt Flag bit mask. */ |
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#define | SPI_IF_bp 7 /* Interrupt Flag bit position. */ |
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#define | SPI_WRCOL_bm 0x40 /* Write Collision bit mask. */ |
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#define | SPI_WRCOL_bp 6 /* Write Collision bit position. */ |
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#define | IRCOM_EVSEL_gm 0x0F /* Event Channel Select group mask. */ |
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#define | IRCOM_EVSEL_gp 0 /* Event Channel Select group position. */ |
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#define | IRCOM_EVSEL0_bm (1<<0) /* Event Channel Select bit 0 mask. */ |
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#define | IRCOM_EVSEL0_bp 0 /* Event Channel Select bit 0 position. */ |
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#define | IRCOM_EVSEL1_bm (1<<1) /* Event Channel Select bit 1 mask. */ |
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#define | IRCOM_EVSEL1_bp 1 /* Event Channel Select bit 1 position. */ |
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#define | IRCOM_EVSEL2_bm (1<<2) /* Event Channel Select bit 2 mask. */ |
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#define | IRCOM_EVSEL2_bp 2 /* Event Channel Select bit 2 position. */ |
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#define | IRCOM_EVSEL3_bm (1<<3) /* Event Channel Select bit 3 mask. */ |
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#define | IRCOM_EVSEL3_bp 3 /* Event Channel Select bit 3 position. */ |
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#define | AES_START_bm 0x80 /* Start/Run bit mask. */ |
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#define | AES_START_bp 7 /* Start/Run bit position. */ |
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#define | AES_AUTO_bm 0x40 /* Auto Start Trigger bit mask. */ |
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#define | AES_AUTO_bp 6 /* Auto Start Trigger bit position. */ |
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#define | AES_RESET_bm 0x20 /* AES Software Reset bit mask. */ |
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#define | AES_RESET_bp 5 /* AES Software Reset bit position. */ |
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#define | AES_DECRYPT_bm 0x10 /* Decryption / Direction bit mask. */ |
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#define | AES_DECRYPT_bp 4 /* Decryption / Direction bit position. */ |
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#define | AES_XOR_bm 0x04 /* State XOR Load Enable bit mask. */ |
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#define | AES_XOR_bp 2 /* State XOR Load Enable bit position. */ |
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#define | AES_ERROR_bm 0x80 /* AES Error bit mask. */ |
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#define | AES_ERROR_bp 7 /* AES Error bit position. */ |
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#define | AES_SRIF_bm 0x01 /* State Ready Interrupt Flag bit mask. */ |
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#define | AES_SRIF_bp 0 /* State Ready Interrupt Flag bit position. */ |
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#define | AES_INTLVL_gm 0x03 /* Interrupt level group mask. */ |
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#define | AES_INTLVL_gp 0 /* Interrupt level group position. */ |
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#define | AES_INTLVL0_bm (1<<0) /* Interrupt level bit 0 mask. */ |
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#define | AES_INTLVL0_bp 0 /* Interrupt level bit 0 position. */ |
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#define | AES_INTLVL1_bm (1<<1) /* Interrupt level bit 1 mask. */ |
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#define | AES_INTLVL1_bp 1 /* Interrupt level bit 1 position. */ |
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#define | PIN0_bm 0x01 |
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#define | PIN0_bp 0 |
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#define | PIN1_bm 0x02 |
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#define | PIN1_bp 1 |
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#define | PIN2_bm 0x04 |
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#define | PIN2_bp 2 |
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#define | PIN3_bm 0x08 |
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#define | PIN3_bp 3 |
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#define | PIN4_bm 0x10 |
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#define | PIN4_bp 4 |
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#define | PIN5_bm 0x20 |
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#define | PIN5_bp 5 |
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#define | PIN6_bm 0x40 |
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#define | PIN6_bp 6 |
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#define | PIN7_bm 0x80 |
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#define | PIN7_bp 7 |
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#define | OSC_XOSCF_vect_num 1 |
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#define | OSC_XOSCF_vect _VECTOR(1) /* External Oscillator Failure Interrupt (NMI) */ |
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#define | PORTC_INT0_vect_num 2 |
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#define | PORTC_INT0_vect _VECTOR(2) /* External Interrupt 0 */ |
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#define | PORTC_INT1_vect_num 3 |
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#define | PORTC_INT1_vect _VECTOR(3) /* External Interrupt 1 */ |
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#define | PORTR_INT0_vect_num 4 |
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#define | PORTR_INT0_vect _VECTOR(4) /* External Interrupt 0 */ |
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#define | PORTR_INT1_vect_num 5 |
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#define | PORTR_INT1_vect _VECTOR(5) /* External Interrupt 1 */ |
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#define | DMA_CH0_vect_num 6 |
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#define | DMA_CH0_vect _VECTOR(6) /* Channel 0 Interrupt */ |
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#define | DMA_CH1_vect_num 7 |
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#define | DMA_CH1_vect _VECTOR(7) /* Channel 1 Interrupt */ |
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#define | DMA_CH2_vect_num 8 |
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#define | DMA_CH2_vect _VECTOR(8) /* Channel 2 Interrupt */ |
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#define | DMA_CH3_vect_num 9 |
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#define | DMA_CH3_vect _VECTOR(9) /* Channel 3 Interrupt */ |
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#define | RTC_OVF_vect_num 10 |
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#define | RTC_OVF_vect _VECTOR(10) /* Overflow Interrupt */ |
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#define | RTC_COMP_vect_num 11 |
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#define | RTC_COMP_vect _VECTOR(11) /* Compare Interrupt */ |
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#define | TWIC_TWIS_vect_num 12 |
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#define | TWIC_TWIS_vect _VECTOR(12) /* TWI Slave Interrupt */ |
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#define | TWIC_TWIM_vect_num 13 |
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#define | TWIC_TWIM_vect _VECTOR(13) /* TWI Master Interrupt */ |
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#define | TCC0_OVF_vect_num 14 |
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#define | TCC0_OVF_vect _VECTOR(14) /* Overflow Interrupt */ |
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#define | TCC0_ERR_vect_num 15 |
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#define | TCC0_ERR_vect _VECTOR(15) /* Error Interrupt */ |
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#define | TCC0_CCA_vect_num 16 |
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#define | TCC0_CCA_vect _VECTOR(16) /* Compare or Capture A Interrupt */ |
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#define | TCC0_CCB_vect_num 17 |
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#define | TCC0_CCB_vect _VECTOR(17) /* Compare or Capture B Interrupt */ |
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#define | TCC0_CCC_vect_num 18 |
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#define | TCC0_CCC_vect _VECTOR(18) /* Compare or Capture C Interrupt */ |
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#define | TCC0_CCD_vect_num 19 |
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#define | TCC0_CCD_vect _VECTOR(19) /* Compare or Capture D Interrupt */ |
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#define | TCC1_OVF_vect_num 20 |
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#define | TCC1_OVF_vect _VECTOR(20) /* Overflow Interrupt */ |
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#define | TCC1_ERR_vect_num 21 |
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#define | TCC1_ERR_vect _VECTOR(21) /* Error Interrupt */ |
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#define | TCC1_CCA_vect_num 22 |
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#define | TCC1_CCA_vect _VECTOR(22) /* Compare or Capture A Interrupt */ |
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#define | TCC1_CCB_vect_num 23 |
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#define | TCC1_CCB_vect _VECTOR(23) /* Compare or Capture B Interrupt */ |
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#define | SPIC_INT_vect_num 24 |
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#define | SPIC_INT_vect _VECTOR(24) /* SPI Interrupt */ |
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#define | USARTC0_RXC_vect_num 25 |
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#define | USARTC0_RXC_vect _VECTOR(25) /* Reception Complete Interrupt */ |
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#define | USARTC0_DRE_vect_num 26 |
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#define | USARTC0_DRE_vect _VECTOR(26) /* Data Register Empty Interrupt */ |
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#define | USARTC0_TXC_vect_num 27 |
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#define | USARTC0_TXC_vect _VECTOR(27) /* Transmission Complete Interrupt */ |
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#define | USARTC1_RXC_vect_num 28 |
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#define | USARTC1_RXC_vect _VECTOR(28) /* Reception Complete Interrupt */ |
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#define | USARTC1_DRE_vect_num 29 |
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#define | USARTC1_DRE_vect _VECTOR(29) /* Data Register Empty Interrupt */ |
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#define | USARTC1_TXC_vect_num 30 |
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#define | USARTC1_TXC_vect _VECTOR(30) /* Transmission Complete Interrupt */ |
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#define | AES_INT_vect_num 31 |
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#define | AES_INT_vect _VECTOR(31) /* AES Interrupt */ |
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#define | NVM_EE_vect_num 32 |
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#define | NVM_EE_vect _VECTOR(32) /* EE Interrupt */ |
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#define | NVM_SPM_vect_num 33 |
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#define | NVM_SPM_vect _VECTOR(33) /* SPM Interrupt */ |
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#define | PORTB_INT0_vect_num 34 |
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#define | PORTB_INT0_vect _VECTOR(34) /* External Interrupt 0 */ |
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#define | PORTB_INT1_vect_num 35 |
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#define | PORTB_INT1_vect _VECTOR(35) /* External Interrupt 1 */ |
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#define | PORTE_INT0_vect_num 43 |
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#define | PORTE_INT0_vect _VECTOR(43) /* External Interrupt 0 */ |
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#define | PORTE_INT1_vect_num 44 |
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#define | PORTE_INT1_vect _VECTOR(44) /* External Interrupt 1 */ |
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#define | TWIE_TWIS_vect_num 45 |
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#define | TWIE_TWIS_vect _VECTOR(45) /* TWI Slave Interrupt */ |
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#define | TWIE_TWIM_vect_num 46 |
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#define | TWIE_TWIM_vect _VECTOR(46) /* TWI Master Interrupt */ |
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#define | TCE0_OVF_vect_num 47 |
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#define | TCE0_OVF_vect _VECTOR(47) /* Overflow Interrupt */ |
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#define | TCE0_ERR_vect_num 48 |
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#define | TCE0_ERR_vect _VECTOR(48) /* Error Interrupt */ |
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#define | TCE0_CCA_vect_num 49 |
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#define | TCE0_CCA_vect _VECTOR(49) /* Compare or Capture A Interrupt */ |
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#define | TCE0_CCB_vect_num 50 |
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#define | TCE0_CCB_vect _VECTOR(50) /* Compare or Capture B Interrupt */ |
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#define | TCE0_CCC_vect_num 51 |
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#define | TCE0_CCC_vect _VECTOR(51) /* Compare or Capture C Interrupt */ |
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#define | TCE0_CCD_vect_num 52 |
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#define | TCE0_CCD_vect _VECTOR(52) /* Compare or Capture D Interrupt */ |
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#define | TCE1_OVF_vect_num 53 |
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#define | TCE1_OVF_vect _VECTOR(53) /* Overflow Interrupt */ |
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#define | TCE1_ERR_vect_num 54 |
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#define | TCE1_ERR_vect _VECTOR(54) /* Error Interrupt */ |
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#define | TCE1_CCA_vect_num 55 |
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#define | TCE1_CCA_vect _VECTOR(55) /* Compare or Capture A Interrupt */ |
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#define | TCE1_CCB_vect_num 56 |
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#define | TCE1_CCB_vect _VECTOR(56) /* Compare or Capture B Interrupt */ |
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#define | USARTE0_RXC_vect_num 58 |
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#define | USARTE0_RXC_vect _VECTOR(58) /* Reception Complete Interrupt */ |
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#define | USARTE0_DRE_vect_num 59 |
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#define | USARTE0_DRE_vect _VECTOR(59) /* Data Register Empty Interrupt */ |
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#define | USARTE0_TXC_vect_num 60 |
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#define | USARTE0_TXC_vect _VECTOR(60) /* Transmission Complete Interrupt */ |
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#define | PORTD_INT0_vect_num 64 |
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#define | PORTD_INT0_vect _VECTOR(64) /* External Interrupt 0 */ |
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#define | PORTD_INT1_vect_num 65 |
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#define | PORTD_INT1_vect _VECTOR(65) /* External Interrupt 1 */ |
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#define | PORTA_INT0_vect_num 66 |
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#define | PORTA_INT0_vect _VECTOR(66) /* External Interrupt 0 */ |
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#define | PORTA_INT1_vect_num 67 |
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#define | PORTA_INT1_vect _VECTOR(67) /* External Interrupt 1 */ |
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#define | ACA_AC0_vect_num 68 |
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#define | ACA_AC0_vect _VECTOR(68) /* AC0 Interrupt */ |
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#define | ACA_AC1_vect_num 69 |
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#define | ACA_AC1_vect _VECTOR(69) /* AC1 Interrupt */ |
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#define | ACA_ACW_vect_num 70 |
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#define | ACA_ACW_vect _VECTOR(70) /* ACW Window Mode Interrupt */ |
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#define | ADCA_CH0_vect_num 71 |
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#define | ADCA_CH0_vect _VECTOR(71) /* Interrupt 0 */ |
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#define | ADCA_CH1_vect_num 72 |
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#define | ADCA_CH1_vect _VECTOR(72) /* Interrupt 1 */ |
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#define | ADCA_CH2_vect_num 73 |
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#define | ADCA_CH2_vect _VECTOR(73) /* Interrupt 2 */ |
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#define | ADCA_CH3_vect_num 74 |
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#define | ADCA_CH3_vect _VECTOR(74) /* Interrupt 3 */ |
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#define | TCD0_OVF_vect_num 77 |
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#define | TCD0_OVF_vect _VECTOR(77) /* Overflow Interrupt */ |
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#define | TCD0_ERR_vect_num 78 |
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#define | TCD0_ERR_vect _VECTOR(78) /* Error Interrupt */ |
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#define | TCD0_CCA_vect_num 79 |
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#define | TCD0_CCA_vect _VECTOR(79) /* Compare or Capture A Interrupt */ |
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#define | TCD0_CCB_vect_num 80 |
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#define | TCD0_CCB_vect _VECTOR(80) /* Compare or Capture B Interrupt */ |
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#define | TCD0_CCC_vect_num 81 |
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#define | TCD0_CCC_vect _VECTOR(81) /* Compare or Capture C Interrupt */ |
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#define | TCD0_CCD_vect_num 82 |
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#define | TCD0_CCD_vect _VECTOR(82) /* Compare or Capture D Interrupt */ |
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#define | TCD1_OVF_vect_num 83 |
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#define | TCD1_OVF_vect _VECTOR(83) /* Overflow Interrupt */ |
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#define | TCD1_ERR_vect_num 84 |
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#define | TCD1_ERR_vect _VECTOR(84) /* Error Interrupt */ |
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#define | TCD1_CCA_vect_num 85 |
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#define | TCD1_CCA_vect _VECTOR(85) /* Compare or Capture A Interrupt */ |
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#define | TCD1_CCB_vect_num 86 |
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#define | TCD1_CCB_vect _VECTOR(86) /* Compare or Capture B Interrupt */ |
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#define | SPID_INT_vect_num 87 |
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#define | SPID_INT_vect _VECTOR(87) /* SPI Interrupt */ |
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#define | USARTD0_RXC_vect_num 88 |
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#define | USARTD0_RXC_vect _VECTOR(88) /* Reception Complete Interrupt */ |
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#define | USARTD0_DRE_vect_num 89 |
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#define | USARTD0_DRE_vect _VECTOR(89) /* Data Register Empty Interrupt */ |
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#define | USARTD0_TXC_vect_num 90 |
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#define | USARTD0_TXC_vect _VECTOR(90) /* Transmission Complete Interrupt */ |
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#define | USARTD1_RXC_vect_num 91 |
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#define | USARTD1_RXC_vect _VECTOR(91) /* Reception Complete Interrupt */ |
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#define | USARTD1_DRE_vect_num 92 |
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#define | USARTD1_DRE_vect _VECTOR(92) /* Data Register Empty Interrupt */ |
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#define | USARTD1_TXC_vect_num 93 |
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#define | USARTD1_TXC_vect _VECTOR(93) /* Transmission Complete Interrupt */ |
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#define | _VECTOR_SIZE 4 /* Size of individual vector. */ |
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#define | _VECTORS_SIZE (94 * _VECTOR_SIZE) |
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#define | PROGMEM_START (0x0000) |
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#define | PROGMEM_SIZE (36864) |
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#define | PROGMEM_PAGE_SIZE (256) |
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#define | PROGMEM_END (PROGMEM_START + PROGMEM_SIZE - 1) |
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#define | APP_SECTION_START (0x0000) |
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#define | APP_SECTION_SIZE (32768) |
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#define | APP_SECTION_PAGE_SIZE (256) |
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#define | APP_SECTION_END (APP_SECTION_START + APP_SECTION_SIZE - 1) |
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#define | APPTABLE_SECTION_START (0x07000) |
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#define | APPTABLE_SECTION_SIZE (4096) |
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#define | APPTABLE_SECTION_PAGE_SIZE (256) |
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#define | APPTABLE_SECTION_END (APPTABLE_SECTION_START + APPTABLE_SECTION_SIZE - 1) |
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#define | BOOT_SECTION_START (0x8000) |
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#define | BOOT_SECTION_SIZE (4096) |
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#define | BOOT_SECTION_PAGE_SIZE (256) |
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#define | BOOT_SECTION_END (BOOT_SECTION_START + BOOT_SECTION_SIZE - 1) |
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#define | DATAMEM_START (0x0000) |
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#define | DATAMEM_SIZE (12288) |
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#define | DATAMEM_PAGE_SIZE (0) |
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#define | DATAMEM_END (DATAMEM_START + DATAMEM_SIZE - 1) |
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#define | IO_START (0x0000) |
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#define | IO_SIZE (4096) |
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#define | IO_PAGE_SIZE (0) |
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#define | IO_END (IO_START + IO_SIZE - 1) |
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#define | MAPPED_EEPROM_START (0x1000) |
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#define | MAPPED_EEPROM_SIZE (1024) |
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#define | MAPPED_EEPROM_PAGE_SIZE (0) |
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#define | MAPPED_EEPROM_END (MAPPED_EEPROM_START + MAPPED_EEPROM_SIZE - 1) |
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#define | INTERNAL_SRAM_START (0x2000) |
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#define | INTERNAL_SRAM_SIZE (4096) |
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#define | INTERNAL_SRAM_PAGE_SIZE (0) |
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#define | INTERNAL_SRAM_END (INTERNAL_SRAM_START + INTERNAL_SRAM_SIZE - 1) |
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#define | EEPROM_START (0x0000) |
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#define | EEPROM_SIZE (1024) |
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#define | EEPROM_PAGE_SIZE (32) |
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#define | EEPROM_END (EEPROM_START + EEPROM_SIZE - 1) |
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#define | FUSE_START (0x0000) |
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#define | FUSE_SIZE (6) |
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#define | FUSE_PAGE_SIZE (0) |
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#define | FUSE_END (FUSE_START + FUSE_SIZE - 1) |
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#define | LOCKBIT_START (0x0000) |
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#define | LOCKBIT_SIZE (1) |
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#define | LOCKBIT_PAGE_SIZE (0) |
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#define | LOCKBIT_END (LOCKBIT_START + LOCKBIT_SIZE - 1) |
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#define | SIGNATURES_START (0x0000) |
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#define | SIGNATURES_SIZE (3) |
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#define | SIGNATURES_PAGE_SIZE (0) |
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#define | SIGNATURES_END (SIGNATURES_START + SIGNATURES_SIZE - 1) |
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#define | USER_SIGNATURES_START (0x0000) |
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#define | USER_SIGNATURES_SIZE (256) |
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#define | USER_SIGNATURES_PAGE_SIZE (0) |
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#define | USER_SIGNATURES_END (USER_SIGNATURES_START + USER_SIGNATURES_SIZE - 1) |
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#define | PROD_SIGNATURES_START (0x0000) |
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#define | PROD_SIGNATURES_SIZE (52) |
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#define | PROD_SIGNATURES_PAGE_SIZE (0) |
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#define | PROD_SIGNATURES_END (PROD_SIGNATURES_START + PROD_SIGNATURES_SIZE - 1) |
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#define | FLASHEND PROGMEM_END |
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#define | SPM_PAGESIZE PROGMEM_PAGE_SIZE |
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#define | RAMSTART INTERNAL_SRAM_START |
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#define | RAMSIZE INTERNAL_SRAM_SIZE |
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#define | RAMEND INTERNAL_SRAM_END |
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#define | XRAMSTART EXTERNAL_SRAM_START |
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#define | XRAMSIZE EXTERNAL_SRAM_SIZE |
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#define | XRAMEND INTERNAL_SRAM_END |
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#define | E2END EEPROM_END |
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#define | E2PAGESIZE EEPROM_PAGE_SIZE |
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#define | FUSE_MEMORY_SIZE 6 |
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#define | FUSE_USERID0 (unsigned char)~_BV(0) /* User ID Bit 0 */ |
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#define | FUSE_USERID1 (unsigned char)~_BV(1) /* User ID Bit 1 */ |
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#define | FUSE_USERID2 (unsigned char)~_BV(2) /* User ID Bit 2 */ |
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#define | FUSE_USERID3 (unsigned char)~_BV(3) /* User ID Bit 3 */ |
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#define | FUSE_USERID4 (unsigned char)~_BV(4) /* User ID Bit 4 */ |
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#define | FUSE_USERID5 (unsigned char)~_BV(5) /* User ID Bit 5 */ |
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#define | FUSE_USERID6 (unsigned char)~_BV(6) /* User ID Bit 6 */ |
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#define | FUSE_USERID7 (unsigned char)~_BV(7) /* User ID Bit 7 */ |
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#define | FUSE0_DEFAULT (0xFF) |
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#define | FUSE_WDP0 (unsigned char)~_BV(0) /* Watchdog Timeout Period Bit 0 */ |
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#define | FUSE_WDP1 (unsigned char)~_BV(1) /* Watchdog Timeout Period Bit 1 */ |
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#define | FUSE_WDP2 (unsigned char)~_BV(2) /* Watchdog Timeout Period Bit 2 */ |
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#define | FUSE_WDP3 (unsigned char)~_BV(3) /* Watchdog Timeout Period Bit 3 */ |
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#define | FUSE_WDWP0 (unsigned char)~_BV(4) /* Watchdog Window Timeout Period Bit 0 */ |
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#define | FUSE_WDWP1 (unsigned char)~_BV(5) /* Watchdog Window Timeout Period Bit 1 */ |
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#define | FUSE_WDWP2 (unsigned char)~_BV(6) /* Watchdog Window Timeout Period Bit 2 */ |
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#define | FUSE_WDWP3 (unsigned char)~_BV(7) /* Watchdog Window Timeout Period Bit 3 */ |
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#define | FUSE1_DEFAULT (0xFF) |
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#define | FUSE_BODPD0 (unsigned char)~_BV(0) /* BOD Operation in Power-Down Mode Bit 0 */ |
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#define | FUSE_BODPD1 (unsigned char)~_BV(1) /* BOD Operation in Power-Down Mode Bit 1 */ |
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#define | FUSE_BOOTRST (unsigned char)~_BV(6) /* Boot Loader Section Reset Vector */ |
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#define | FUSE_DVSDON (unsigned char)~_BV(7) /* Spike Detector Enable */ |
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#define | FUSE2_DEFAULT (0xFF) |
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#define | FUSE_WDLOCK (unsigned char)~_BV(1) /* Watchdog Timer Lock */ |
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#define | FUSE_SUT0 (unsigned char)~_BV(2) /* Start-up Time Bit 0 */ |
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#define | FUSE_SUT1 (unsigned char)~_BV(3) /* Start-up Time Bit 1 */ |
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#define | FUSE4_DEFAULT (0xFF) |
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#define | FUSE_BODLVL0 (unsigned char)~_BV(0) /* Brown Out Detection Voltage Level Bit 0 */ |
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#define | FUSE_BODLVL1 (unsigned char)~_BV(1) /* Brown Out Detection Voltage Level Bit 1 */ |
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#define | FUSE_BODLVL2 (unsigned char)~_BV(2) /* Brown Out Detection Voltage Level Bit 2 */ |
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#define | FUSE_EESAVE (unsigned char)~_BV(3) /* Preserve EEPROM Through Chip Erase */ |
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#define | FUSE_BODACT0 (unsigned char)~_BV(4) /* BOD Operation in Active Mode Bit 0 */ |
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#define | FUSE_BODACT1 (unsigned char)~_BV(5) /* BOD Operation in Active Mode Bit 1 */ |
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#define | FUSE5_DEFAULT (0xFF) |
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#define | __LOCK_BITS_EXIST |
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#define | __BOOT_LOCK_APPLICATION_TABLE_BITS_EXIST |
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#define | __BOOT_LOCK_APPLICATION_BITS_EXIST |
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#define | __BOOT_LOCK_BOOT_BITS_EXIST |
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#define | SIGNATURE_0 0x1E |
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#define | SIGNATURE_1 0x95 |
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#define | SIGNATURE_2 0x41 |
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enum | CCP_enum {
CCP_SPM_gc = (0x9D<<0),
CCP_IOREG_gc = (0xD8<<0),
CCP_SPM_gc = (0x9D<<0),
CCP_IOREG_gc = (0xD8<<0),
CCP_SPM_gc = (0x9D<<0),
CCP_IOREG_gc = (0xD8<<0),
CCP_SPM_gc = (0x9D<<0),
CCP_IOREG_gc = (0xD8<<0),
CCP_SPM_gc = (0x9D<<0),
CCP_IOREG_gc = (0xD8<<0),
CCP_SPM_gc = (0x9D<<0),
CCP_IOREG_gc = (0xD8<<0),
CCP_SPM_gc = (0x9D<<0),
CCP_IOREG_gc = (0xD8<<0),
CCP_SPM_gc = (0x9D<<0),
CCP_IOREG_gc = (0xD8<<0),
CCP_SPM_gc = (0x9D<<0),
CCP_IOREG_gc = (0xD8<<0),
CCP_SPM_gc = (0x9D<<0),
CCP_IOREG_gc = (0xD8<<0),
CCP_SPM_gc = (0x9D<<0),
CCP_IOREG_gc = (0xD8<<0),
CCP_SPM_gc = (0x9D<<0),
CCP_IOREG_gc = (0xD8<<0),
CCP_SPM_gc = (0x9D<<0),
CCP_IOREG_gc = (0xD8<<0),
CCP_SPM_gc = (0x9D<<0),
CCP_IOREG_gc = (0xD8<<0),
CCP_SPM_gc = (0x9D<<0),
CCP_IOREG_gc = (0xD8<<0)
} |
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enum | CLK_SCLKSEL_enum {
CLK_SCLKSEL_RC2M_gc = (0x00<<0),
CLK_SCLKSEL_RC32M_gc = (0x01<<0),
CLK_SCLKSEL_RC32K_gc = (0x02<<0),
CLK_SCLKSEL_XOSC_gc = (0x03<<0),
CLK_SCLKSEL_PLL_gc = (0x04<<0),
CLK_SCLKSEL_RC2M_gc = (0x00<<0),
CLK_SCLKSEL_RC32M_gc = (0x01<<0),
CLK_SCLKSEL_RC32K_gc = (0x02<<0),
CLK_SCLKSEL_XOSC_gc = (0x03<<0),
CLK_SCLKSEL_PLL_gc = (0x04<<0),
CLK_SCLKSEL_RC2M_gc = (0x00<<0),
CLK_SCLKSEL_RC32M_gc = (0x01<<0),
CLK_SCLKSEL_RC32K_gc = (0x02<<0),
CLK_SCLKSEL_XOSC_gc = (0x03<<0),
CLK_SCLKSEL_PLL_gc = (0x04<<0),
CLK_SCLKSEL_RC2M_gc = (0x00<<0),
CLK_SCLKSEL_RC32M_gc = (0x01<<0),
CLK_SCLKSEL_RC32K_gc = (0x02<<0),
CLK_SCLKSEL_XOSC_gc = (0x03<<0),
CLK_SCLKSEL_PLL_gc = (0x04<<0),
CLK_SCLKSEL_RC2M_gc = (0x00<<0),
CLK_SCLKSEL_RC32M_gc = (0x01<<0),
CLK_SCLKSEL_RC32K_gc = (0x02<<0),
CLK_SCLKSEL_XOSC_gc = (0x03<<0),
CLK_SCLKSEL_PLL_gc = (0x04<<0),
CLK_SCLKSEL_RC2M_gc = (0x00<<0),
CLK_SCLKSEL_RC32M_gc = (0x01<<0),
CLK_SCLKSEL_RC32K_gc = (0x02<<0),
CLK_SCLKSEL_XOSC_gc = (0x03<<0),
CLK_SCLKSEL_PLL_gc = (0x04<<0),
CLK_SCLKSEL_RC2M_gc = (0x00<<0),
CLK_SCLKSEL_RC32M_gc = (0x01<<0),
CLK_SCLKSEL_RC32K_gc = (0x02<<0),
CLK_SCLKSEL_XOSC_gc = (0x03<<0),
CLK_SCLKSEL_PLL_gc = (0x04<<0),
CLK_SCLKSEL_RC2M_gc = (0x00<<0),
CLK_SCLKSEL_RC32M_gc = (0x01<<0),
CLK_SCLKSEL_RC32K_gc = (0x02<<0),
CLK_SCLKSEL_XOSC_gc = (0x03<<0),
CLK_SCLKSEL_PLL_gc = (0x04<<0),
CLK_SCLKSEL_RC2M_gc = (0x00<<0),
CLK_SCLKSEL_RC32M_gc = (0x01<<0),
CLK_SCLKSEL_RC32K_gc = (0x02<<0),
CLK_SCLKSEL_XOSC_gc = (0x03<<0),
CLK_SCLKSEL_PLL_gc = (0x04<<0),
CLK_SCLKSEL_RC2M_gc = (0x00<<0),
CLK_SCLKSEL_RC32M_gc = (0x01<<0),
CLK_SCLKSEL_RC32K_gc = (0x02<<0),
CLK_SCLKSEL_XOSC_gc = (0x03<<0),
CLK_SCLKSEL_PLL_gc = (0x04<<0),
CLK_SCLKSEL_RC2M_gc = (0x00<<0),
CLK_SCLKSEL_RC32M_gc = (0x01<<0),
CLK_SCLKSEL_RC32K_gc = (0x02<<0),
CLK_SCLKSEL_XOSC_gc = (0x03<<0),
CLK_SCLKSEL_PLL_gc = (0x04<<0),
CLK_SCLKSEL_RC2M_gc = (0x00<<0),
CLK_SCLKSEL_RC32M_gc = (0x01<<0),
CLK_SCLKSEL_RC32K_gc = (0x02<<0),
CLK_SCLKSEL_XOSC_gc = (0x03<<0),
CLK_SCLKSEL_PLL_gc = (0x04<<0),
CLK_SCLKSEL_RC2M_gc = (0x00<<0),
CLK_SCLKSEL_RC32M_gc = (0x01<<0),
CLK_SCLKSEL_RC32K_gc = (0x02<<0),
CLK_SCLKSEL_XOSC_gc = (0x03<<0),
CLK_SCLKSEL_PLL_gc = (0x04<<0),
CLK_SCLKSEL_RC2M_gc = (0x00<<0),
CLK_SCLKSEL_RC32M_gc = (0x01<<0),
CLK_SCLKSEL_RC32K_gc = (0x02<<0),
CLK_SCLKSEL_XOSC_gc = (0x03<<0),
CLK_SCLKSEL_PLL_gc = (0x04<<0),
CLK_SCLKSEL_RC2M_gc = (0x00<<0),
CLK_SCLKSEL_RC32M_gc = (0x01<<0),
CLK_SCLKSEL_RC32K_gc = (0x02<<0),
CLK_SCLKSEL_XOSC_gc = (0x03<<0),
CLK_SCLKSEL_PLL_gc = (0x04<<0)
} |
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enum | CLK_PSADIV_enum {
CLK_PSADIV_1_gc = (0x00<<2),
CLK_PSADIV_2_gc = (0x01<<2),
CLK_PSADIV_4_gc = (0x03<<2),
CLK_PSADIV_8_gc = (0x05<<2),
CLK_PSADIV_16_gc = (0x07<<2),
CLK_PSADIV_32_gc = (0x09<<2),
CLK_PSADIV_64_gc = (0x0B<<2),
CLK_PSADIV_128_gc = (0x0D<<2),
CLK_PSADIV_256_gc = (0x0F<<2),
CLK_PSADIV_512_gc = (0x11<<2),
CLK_PSADIV_1_gc = (0x00<<2),
CLK_PSADIV_2_gc = (0x01<<2),
CLK_PSADIV_4_gc = (0x03<<2),
CLK_PSADIV_8_gc = (0x05<<2),
CLK_PSADIV_16_gc = (0x07<<2),
CLK_PSADIV_32_gc = (0x09<<2),
CLK_PSADIV_64_gc = (0x0B<<2),
CLK_PSADIV_128_gc = (0x0D<<2),
CLK_PSADIV_256_gc = (0x0F<<2),
CLK_PSADIV_512_gc = (0x11<<2),
CLK_PSADIV_1_gc = (0x00<<2),
CLK_PSADIV_2_gc = (0x01<<2),
CLK_PSADIV_4_gc = (0x03<<2),
CLK_PSADIV_8_gc = (0x05<<2),
CLK_PSADIV_16_gc = (0x07<<2),
CLK_PSADIV_32_gc = (0x09<<2),
CLK_PSADIV_64_gc = (0x0B<<2),
CLK_PSADIV_128_gc = (0x0D<<2),
CLK_PSADIV_256_gc = (0x0F<<2),
CLK_PSADIV_512_gc = (0x11<<2),
CLK_PSADIV_1_gc = (0x00<<2),
CLK_PSADIV_2_gc = (0x01<<2),
CLK_PSADIV_4_gc = (0x03<<2),
CLK_PSADIV_8_gc = (0x05<<2),
CLK_PSADIV_16_gc = (0x07<<2),
CLK_PSADIV_32_gc = (0x09<<2),
CLK_PSADIV_64_gc = (0x0B<<2),
CLK_PSADIV_128_gc = (0x0D<<2),
CLK_PSADIV_256_gc = (0x0F<<2),
CLK_PSADIV_512_gc = (0x11<<2),
CLK_PSADIV_1_gc = (0x00<<2),
CLK_PSADIV_2_gc = (0x01<<2),
CLK_PSADIV_4_gc = (0x03<<2),
CLK_PSADIV_8_gc = (0x05<<2),
CLK_PSADIV_16_gc = (0x07<<2),
CLK_PSADIV_32_gc = (0x09<<2),
CLK_PSADIV_64_gc = (0x0B<<2),
CLK_PSADIV_128_gc = (0x0D<<2),
CLK_PSADIV_256_gc = (0x0F<<2),
CLK_PSADIV_512_gc = (0x11<<2),
CLK_PSADIV_1_gc = (0x00<<2),
CLK_PSADIV_2_gc = (0x01<<2),
CLK_PSADIV_4_gc = (0x03<<2),
CLK_PSADIV_8_gc = (0x05<<2),
CLK_PSADIV_16_gc = (0x07<<2),
CLK_PSADIV_32_gc = (0x09<<2),
CLK_PSADIV_64_gc = (0x0B<<2),
CLK_PSADIV_128_gc = (0x0D<<2),
CLK_PSADIV_256_gc = (0x0F<<2),
CLK_PSADIV_512_gc = (0x11<<2),
CLK_PSADIV_1_gc = (0x00<<2),
CLK_PSADIV_2_gc = (0x01<<2),
CLK_PSADIV_4_gc = (0x03<<2),
CLK_PSADIV_8_gc = (0x05<<2),
CLK_PSADIV_16_gc = (0x07<<2),
CLK_PSADIV_32_gc = (0x09<<2),
CLK_PSADIV_64_gc = (0x0B<<2),
CLK_PSADIV_128_gc = (0x0D<<2),
CLK_PSADIV_256_gc = (0x0F<<2),
CLK_PSADIV_512_gc = (0x11<<2),
CLK_PSADIV_1_gc = (0x00<<2),
CLK_PSADIV_2_gc = (0x01<<2),
CLK_PSADIV_4_gc = (0x03<<2),
CLK_PSADIV_8_gc = (0x05<<2),
CLK_PSADIV_16_gc = (0x07<<2),
CLK_PSADIV_32_gc = (0x09<<2),
CLK_PSADIV_64_gc = (0x0B<<2),
CLK_PSADIV_128_gc = (0x0D<<2),
CLK_PSADIV_256_gc = (0x0F<<2),
CLK_PSADIV_512_gc = (0x11<<2),
CLK_PSADIV_1_gc = (0x00<<2),
CLK_PSADIV_2_gc = (0x01<<2),
CLK_PSADIV_4_gc = (0x03<<2),
CLK_PSADIV_8_gc = (0x05<<2),
CLK_PSADIV_16_gc = (0x07<<2),
CLK_PSADIV_32_gc = (0x09<<2),
CLK_PSADIV_64_gc = (0x0B<<2),
CLK_PSADIV_128_gc = (0x0D<<2),
CLK_PSADIV_256_gc = (0x0F<<2),
CLK_PSADIV_512_gc = (0x11<<2),
CLK_PSADIV_1_gc = (0x00<<2),
CLK_PSADIV_2_gc = (0x01<<2),
CLK_PSADIV_4_gc = (0x03<<2),
CLK_PSADIV_8_gc = (0x05<<2),
CLK_PSADIV_16_gc = (0x07<<2),
CLK_PSADIV_32_gc = (0x09<<2),
CLK_PSADIV_64_gc = (0x0B<<2),
CLK_PSADIV_128_gc = (0x0D<<2),
CLK_PSADIV_256_gc = (0x0F<<2),
CLK_PSADIV_512_gc = (0x11<<2),
CLK_PSADIV_1_gc = (0x00<<2),
CLK_PSADIV_2_gc = (0x01<<2),
CLK_PSADIV_4_gc = (0x03<<2),
CLK_PSADIV_8_gc = (0x05<<2),
CLK_PSADIV_16_gc = (0x07<<2),
CLK_PSADIV_32_gc = (0x09<<2),
CLK_PSADIV_64_gc = (0x0B<<2),
CLK_PSADIV_128_gc = (0x0D<<2),
CLK_PSADIV_256_gc = (0x0F<<2),
CLK_PSADIV_512_gc = (0x11<<2),
CLK_PSADIV_1_gc = (0x00<<2),
CLK_PSADIV_2_gc = (0x01<<2),
CLK_PSADIV_4_gc = (0x03<<2),
CLK_PSADIV_8_gc = (0x05<<2),
CLK_PSADIV_16_gc = (0x07<<2),
CLK_PSADIV_32_gc = (0x09<<2),
CLK_PSADIV_64_gc = (0x0B<<2),
CLK_PSADIV_128_gc = (0x0D<<2),
CLK_PSADIV_256_gc = (0x0F<<2),
CLK_PSADIV_512_gc = (0x11<<2),
CLK_PSADIV_1_gc = (0x00<<2),
CLK_PSADIV_2_gc = (0x01<<2),
CLK_PSADIV_4_gc = (0x03<<2),
CLK_PSADIV_8_gc = (0x05<<2),
CLK_PSADIV_16_gc = (0x07<<2),
CLK_PSADIV_32_gc = (0x09<<2),
CLK_PSADIV_64_gc = (0x0B<<2),
CLK_PSADIV_128_gc = (0x0D<<2),
CLK_PSADIV_256_gc = (0x0F<<2),
CLK_PSADIV_512_gc = (0x11<<2),
CLK_PSADIV_1_gc = (0x00<<2),
CLK_PSADIV_2_gc = (0x01<<2),
CLK_PSADIV_4_gc = (0x03<<2),
CLK_PSADIV_8_gc = (0x05<<2),
CLK_PSADIV_16_gc = (0x07<<2),
CLK_PSADIV_32_gc = (0x09<<2),
CLK_PSADIV_64_gc = (0x0B<<2),
CLK_PSADIV_128_gc = (0x0D<<2),
CLK_PSADIV_256_gc = (0x0F<<2),
CLK_PSADIV_512_gc = (0x11<<2),
CLK_PSADIV_1_gc = (0x00<<2),
CLK_PSADIV_2_gc = (0x01<<2),
CLK_PSADIV_4_gc = (0x03<<2),
CLK_PSADIV_8_gc = (0x05<<2),
CLK_PSADIV_16_gc = (0x07<<2),
CLK_PSADIV_32_gc = (0x09<<2),
CLK_PSADIV_64_gc = (0x0B<<2),
CLK_PSADIV_128_gc = (0x0D<<2),
CLK_PSADIV_256_gc = (0x0F<<2),
CLK_PSADIV_512_gc = (0x11<<2)
} |
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enum | CLK_PSBCDIV_enum {
CLK_PSBCDIV_1_1_gc = (0x00<<0),
CLK_PSBCDIV_1_2_gc = (0x01<<0),
CLK_PSBCDIV_4_1_gc = (0x02<<0),
CLK_PSBCDIV_2_2_gc = (0x03<<0),
CLK_PSBCDIV_1_1_gc = (0x00<<0),
CLK_PSBCDIV_1_2_gc = (0x01<<0),
CLK_PSBCDIV_4_1_gc = (0x02<<0),
CLK_PSBCDIV_2_2_gc = (0x03<<0),
CLK_PSBCDIV_1_1_gc = (0x00<<0),
CLK_PSBCDIV_1_2_gc = (0x01<<0),
CLK_PSBCDIV_4_1_gc = (0x02<<0),
CLK_PSBCDIV_2_2_gc = (0x03<<0),
CLK_PSBCDIV_1_1_gc = (0x00<<0),
CLK_PSBCDIV_1_2_gc = (0x01<<0),
CLK_PSBCDIV_4_1_gc = (0x02<<0),
CLK_PSBCDIV_2_2_gc = (0x03<<0),
CLK_PSBCDIV_1_1_gc = (0x00<<0),
CLK_PSBCDIV_1_2_gc = (0x01<<0),
CLK_PSBCDIV_4_1_gc = (0x02<<0),
CLK_PSBCDIV_2_2_gc = (0x03<<0),
CLK_PSBCDIV_1_1_gc = (0x00<<0),
CLK_PSBCDIV_1_2_gc = (0x01<<0),
CLK_PSBCDIV_4_1_gc = (0x02<<0),
CLK_PSBCDIV_2_2_gc = (0x03<<0),
CLK_PSBCDIV_1_1_gc = (0x00<<0),
CLK_PSBCDIV_1_2_gc = (0x01<<0),
CLK_PSBCDIV_4_1_gc = (0x02<<0),
CLK_PSBCDIV_2_2_gc = (0x03<<0),
CLK_PSBCDIV_1_1_gc = (0x00<<0),
CLK_PSBCDIV_1_2_gc = (0x01<<0),
CLK_PSBCDIV_4_1_gc = (0x02<<0),
CLK_PSBCDIV_2_2_gc = (0x03<<0),
CLK_PSBCDIV_1_1_gc = (0x00<<0),
CLK_PSBCDIV_1_2_gc = (0x01<<0),
CLK_PSBCDIV_4_1_gc = (0x02<<0),
CLK_PSBCDIV_2_2_gc = (0x03<<0),
CLK_PSBCDIV_1_1_gc = (0x00<<0),
CLK_PSBCDIV_1_2_gc = (0x01<<0),
CLK_PSBCDIV_4_1_gc = (0x02<<0),
CLK_PSBCDIV_2_2_gc = (0x03<<0),
CLK_PSBCDIV_1_1_gc = (0x00<<0),
CLK_PSBCDIV_1_2_gc = (0x01<<0),
CLK_PSBCDIV_4_1_gc = (0x02<<0),
CLK_PSBCDIV_2_2_gc = (0x03<<0),
CLK_PSBCDIV_1_1_gc = (0x00<<0),
CLK_PSBCDIV_1_2_gc = (0x01<<0),
CLK_PSBCDIV_4_1_gc = (0x02<<0),
CLK_PSBCDIV_2_2_gc = (0x03<<0),
CLK_PSBCDIV_1_1_gc = (0x00<<0),
CLK_PSBCDIV_1_2_gc = (0x01<<0),
CLK_PSBCDIV_4_1_gc = (0x02<<0),
CLK_PSBCDIV_2_2_gc = (0x03<<0),
CLK_PSBCDIV_1_1_gc = (0x00<<0),
CLK_PSBCDIV_1_2_gc = (0x01<<0),
CLK_PSBCDIV_4_1_gc = (0x02<<0),
CLK_PSBCDIV_2_2_gc = (0x03<<0),
CLK_PSBCDIV_1_1_gc = (0x00<<0),
CLK_PSBCDIV_1_2_gc = (0x01<<0),
CLK_PSBCDIV_4_1_gc = (0x02<<0),
CLK_PSBCDIV_2_2_gc = (0x03<<0)
} |
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enum | CLK_RTCSRC_enum {
CLK_RTCSRC_ULP_gc = (0x00<<1),
CLK_RTCSRC_TOSC_gc = (0x01<<1),
CLK_RTCSRC_RCOSC_gc = (0x02<<1),
CLK_RTCSRC_TOSC32_gc = (0x05<<1),
CLK_RTCSRC_ULP_gc = (0x00<<1),
CLK_RTCSRC_TOSC_gc = (0x01<<1),
CLK_RTCSRC_RCOSC_gc = (0x02<<1),
CLK_RTCSRC_TOSC32_gc = (0x05<<1),
CLK_RTCSRC_ULP_gc = (0x00<<1),
CLK_RTCSRC_TOSC_gc = (0x01<<1),
CLK_RTCSRC_RCOSC_gc = (0x02<<1),
CLK_RTCSRC_TOSC32_gc = (0x05<<1),
CLK_RTCSRC_ULP_gc = (0x00<<1),
CLK_RTCSRC_TOSC_gc = (0x01<<1),
CLK_RTCSRC_RCOSC_gc = (0x02<<1),
CLK_RTCSRC_TOSC32_gc = (0x05<<1),
CLK_RTCSRC_ULP_gc = (0x00<<1),
CLK_RTCSRC_TOSC_gc = (0x01<<1),
CLK_RTCSRC_RCOSC_gc = (0x02<<1),
CLK_RTCSRC_TOSC32_gc = (0x05<<1),
CLK_RTCSRC_ULP_gc = (0x00<<1),
CLK_RTCSRC_TOSC_gc = (0x01<<1),
CLK_RTCSRC_RCOSC_gc = (0x02<<1),
CLK_RTCSRC_TOSC32_gc = (0x05<<1),
CLK_RTCSRC_ULP_gc = (0x00<<1),
CLK_RTCSRC_TOSC_gc = (0x01<<1),
CLK_RTCSRC_RCOSC_gc = (0x02<<1),
CLK_RTCSRC_TOSC32_gc = (0x05<<1),
CLK_RTCSRC_ULP_gc = (0x00<<1),
CLK_RTCSRC_TOSC_gc = (0x01<<1),
CLK_RTCSRC_RCOSC_gc = (0x02<<1),
CLK_RTCSRC_TOSC32_gc = (0x05<<1),
CLK_RTCSRC_ULP_gc = (0x00<<1),
CLK_RTCSRC_TOSC_gc = (0x01<<1),
CLK_RTCSRC_RCOSC_gc = (0x02<<1),
CLK_RTCSRC_TOSC32_gc = (0x05<<1),
CLK_RTCSRC_ULP_gc = (0x00<<1),
CLK_RTCSRC_TOSC_gc = (0x01<<1),
CLK_RTCSRC_RCOSC_gc = (0x02<<1),
CLK_RTCSRC_TOSC32_gc = (0x05<<1),
CLK_RTCSRC_ULP_gc = (0x00<<1),
CLK_RTCSRC_TOSC_gc = (0x01<<1),
CLK_RTCSRC_RCOSC_gc = (0x02<<1),
CLK_RTCSRC_TOSC32_gc = (0x05<<1),
CLK_RTCSRC_ULP_gc = (0x00<<1),
CLK_RTCSRC_TOSC_gc = (0x01<<1),
CLK_RTCSRC_RCOSC_gc = (0x02<<1),
CLK_RTCSRC_TOSC32_gc = (0x05<<1),
CLK_RTCSRC_ULP_gc = (0x00<<1),
CLK_RTCSRC_TOSC_gc = (0x01<<1),
CLK_RTCSRC_RCOSC_gc = (0x02<<1),
CLK_RTCSRC_TOSC32_gc = (0x05<<1),
CLK_RTCSRC_ULP_gc = (0x00<<1),
CLK_RTCSRC_TOSC_gc = (0x01<<1),
CLK_RTCSRC_RCOSC_gc = (0x02<<1),
CLK_RTCSRC_TOSC32_gc = (0x05<<1),
CLK_RTCSRC_ULP_gc = (0x00<<1),
CLK_RTCSRC_TOSC_gc = (0x01<<1),
CLK_RTCSRC_RCOSC_gc = (0x02<<1),
CLK_RTCSRC_TOSC32_gc = (0x05<<1)
} |
|
enum | SLEEP_SMODE_enum {
SLEEP_SMODE_IDLE_gc = (0x00<<1),
SLEEP_SMODE_PDOWN_gc = (0x02<<1),
SLEEP_SMODE_PSAVE_gc = (0x03<<1),
SLEEP_SMODE_STDBY_gc = (0x06<<1),
SLEEP_SMODE_ESTDBY_gc = (0x07<<1),
SLEEP_SMODE_IDLE_gc = (0x00<<1),
SLEEP_SMODE_PDOWN_gc = (0x02<<1),
SLEEP_SMODE_PSAVE_gc = (0x03<<1),
SLEEP_SMODE_STDBY_gc = (0x06<<1),
SLEEP_SMODE_ESTDBY_gc = (0x07<<1),
SLEEP_SMODE_IDLE_gc = (0x00<<1),
SLEEP_SMODE_PDOWN_gc = (0x02<<1),
SLEEP_SMODE_PSAVE_gc = (0x03<<1),
SLEEP_SMODE_STDBY_gc = (0x06<<1),
SLEEP_SMODE_ESTDBY_gc = (0x07<<1),
SLEEP_SMODE_IDLE_gc = (0x00<<1),
SLEEP_SMODE_PDOWN_gc = (0x02<<1),
SLEEP_SMODE_PSAVE_gc = (0x03<<1),
SLEEP_SMODE_STDBY_gc = (0x06<<1),
SLEEP_SMODE_ESTDBY_gc = (0x07<<1),
SLEEP_SMODE_IDLE_gc = (0x00<<1),
SLEEP_SMODE_PDOWN_gc = (0x02<<1),
SLEEP_SMODE_PSAVE_gc = (0x03<<1),
SLEEP_SMODE_STDBY_gc = (0x06<<1),
SLEEP_SMODE_ESTDBY_gc = (0x07<<1),
SLEEP_SMODE_IDLE_gc = (0x00<<1),
SLEEP_SMODE_PDOWN_gc = (0x02<<1),
SLEEP_SMODE_PSAVE_gc = (0x03<<1),
SLEEP_SMODE_STDBY_gc = (0x06<<1),
SLEEP_SMODE_ESTDBY_gc = (0x07<<1),
SLEEP_SMODE_IDLE_gc = (0x00<<1),
SLEEP_SMODE_PDOWN_gc = (0x02<<1),
SLEEP_SMODE_PSAVE_gc = (0x03<<1),
SLEEP_SMODE_STDBY_gc = (0x06<<1),
SLEEP_SMODE_ESTDBY_gc = (0x07<<1),
SLEEP_SMODE_IDLE_gc = (0x00<<1),
SLEEP_SMODE_PDOWN_gc = (0x02<<1),
SLEEP_SMODE_PSAVE_gc = (0x03<<1),
SLEEP_SMODE_STDBY_gc = (0x06<<1),
SLEEP_SMODE_ESTDBY_gc = (0x07<<1),
SLEEP_SMODE_IDLE_gc = (0x00<<1),
SLEEP_SMODE_PDOWN_gc = (0x02<<1),
SLEEP_SMODE_PSAVE_gc = (0x03<<1),
SLEEP_SMODE_STDBY_gc = (0x06<<1),
SLEEP_SMODE_ESTDBY_gc = (0x07<<1),
SLEEP_SMODE_IDLE_gc = (0x00<<1),
SLEEP_SMODE_PDOWN_gc = (0x02<<1),
SLEEP_SMODE_PSAVE_gc = (0x03<<1),
SLEEP_SMODE_STDBY_gc = (0x06<<1),
SLEEP_SMODE_ESTDBY_gc = (0x07<<1),
SLEEP_SMODE_IDLE_gc = (0x00<<1),
SLEEP_SMODE_PDOWN_gc = (0x02<<1),
SLEEP_SMODE_PSAVE_gc = (0x03<<1),
SLEEP_SMODE_STDBY_gc = (0x06<<1),
SLEEP_SMODE_ESTDBY_gc = (0x07<<1),
SLEEP_SMODE_IDLE_gc = (0x00<<1),
SLEEP_SMODE_PDOWN_gc = (0x02<<1),
SLEEP_SMODE_PSAVE_gc = (0x03<<1),
SLEEP_SMODE_STDBY_gc = (0x06<<1),
SLEEP_SMODE_ESTDBY_gc = (0x07<<1),
SLEEP_SMODE_IDLE_gc = (0x00<<1),
SLEEP_SMODE_PDOWN_gc = (0x02<<1),
SLEEP_SMODE_PSAVE_gc = (0x03<<1),
SLEEP_SMODE_STDBY_gc = (0x06<<1),
SLEEP_SMODE_ESTDBY_gc = (0x07<<1),
SLEEP_SMODE_IDLE_gc = (0x00<<1),
SLEEP_SMODE_PDOWN_gc = (0x02<<1),
SLEEP_SMODE_PSAVE_gc = (0x03<<1),
SLEEP_SMODE_STDBY_gc = (0x06<<1),
SLEEP_SMODE_ESTDBY_gc = (0x07<<1),
SLEEP_SMODE_IDLE_gc = (0x00<<1),
SLEEP_SMODE_PDOWN_gc = (0x02<<1),
SLEEP_SMODE_PSAVE_gc = (0x03<<1),
SLEEP_SMODE_STDBY_gc = (0x06<<1),
SLEEP_SMODE_ESTDBY_gc = (0x07<<1)
} |
|
enum | OSC_FRQRANGE_enum {
OSC_FRQRANGE_04TO2_gc = (0x00<<6),
OSC_FRQRANGE_2TO9_gc = (0x01<<6),
OSC_FRQRANGE_9TO12_gc = (0x02<<6),
OSC_FRQRANGE_12TO16_gc = (0x03<<6),
OSC_FRQRANGE_04TO2_gc = (0x00<<6),
OSC_FRQRANGE_2TO9_gc = (0x01<<6),
OSC_FRQRANGE_9TO12_gc = (0x02<<6),
OSC_FRQRANGE_12TO16_gc = (0x03<<6),
OSC_FRQRANGE_04TO2_gc = (0x00<<6),
OSC_FRQRANGE_2TO9_gc = (0x01<<6),
OSC_FRQRANGE_9TO12_gc = (0x02<<6),
OSC_FRQRANGE_12TO16_gc = (0x03<<6),
OSC_FRQRANGE_04TO2_gc = (0x00<<6),
OSC_FRQRANGE_2TO9_gc = (0x01<<6),
OSC_FRQRANGE_9TO12_gc = (0x02<<6),
OSC_FRQRANGE_12TO16_gc = (0x03<<6),
OSC_FRQRANGE_04TO2_gc = (0x00<<6),
OSC_FRQRANGE_2TO9_gc = (0x01<<6),
OSC_FRQRANGE_9TO12_gc = (0x02<<6),
OSC_FRQRANGE_12TO16_gc = (0x03<<6),
OSC_FRQRANGE_04TO2_gc = (0x00<<6),
OSC_FRQRANGE_2TO9_gc = (0x01<<6),
OSC_FRQRANGE_9TO12_gc = (0x02<<6),
OSC_FRQRANGE_12TO16_gc = (0x03<<6),
OSC_FRQRANGE_04TO2_gc = (0x00<<6),
OSC_FRQRANGE_2TO9_gc = (0x01<<6),
OSC_FRQRANGE_9TO12_gc = (0x02<<6),
OSC_FRQRANGE_12TO16_gc = (0x03<<6),
OSC_FRQRANGE_04TO2_gc = (0x00<<6),
OSC_FRQRANGE_2TO9_gc = (0x01<<6),
OSC_FRQRANGE_9TO12_gc = (0x02<<6),
OSC_FRQRANGE_12TO16_gc = (0x03<<6),
OSC_FRQRANGE_04TO2_gc = (0x00<<6),
OSC_FRQRANGE_2TO9_gc = (0x01<<6),
OSC_FRQRANGE_9TO12_gc = (0x02<<6),
OSC_FRQRANGE_12TO16_gc = (0x03<<6),
OSC_FRQRANGE_04TO2_gc = (0x00<<6),
OSC_FRQRANGE_2TO9_gc = (0x01<<6),
OSC_FRQRANGE_9TO12_gc = (0x02<<6),
OSC_FRQRANGE_12TO16_gc = (0x03<<6),
OSC_FRQRANGE_04TO2_gc = (0x00<<6),
OSC_FRQRANGE_2TO9_gc = (0x01<<6),
OSC_FRQRANGE_9TO12_gc = (0x02<<6),
OSC_FRQRANGE_12TO16_gc = (0x03<<6),
OSC_FRQRANGE_04TO2_gc = (0x00<<6),
OSC_FRQRANGE_2TO9_gc = (0x01<<6),
OSC_FRQRANGE_9TO12_gc = (0x02<<6),
OSC_FRQRANGE_12TO16_gc = (0x03<<6),
OSC_FRQRANGE_04TO2_gc = (0x00<<6),
OSC_FRQRANGE_2TO9_gc = (0x01<<6),
OSC_FRQRANGE_9TO12_gc = (0x02<<6),
OSC_FRQRANGE_12TO16_gc = (0x03<<6),
OSC_FRQRANGE_04TO2_gc = (0x00<<6),
OSC_FRQRANGE_2TO9_gc = (0x01<<6),
OSC_FRQRANGE_9TO12_gc = (0x02<<6),
OSC_FRQRANGE_12TO16_gc = (0x03<<6),
OSC_FRQRANGE_04TO2_gc = (0x00<<6),
OSC_FRQRANGE_2TO9_gc = (0x01<<6),
OSC_FRQRANGE_9TO12_gc = (0x02<<6),
OSC_FRQRANGE_12TO16_gc = (0x03<<6)
} |
|
enum | OSC_XOSCSEL_enum {
OSC_XOSCSEL_EXTCLK_gc = (0x00<<0),
OSC_XOSCSEL_32KHz_gc = (0x02<<0),
OSC_XOSCSEL_XTAL_256CLK_gc = (0x03<<0),
OSC_XOSCSEL_XTAL_1KCLK_gc = (0x07<<0),
OSC_XOSCSEL_XTAL_16KCLK_gc = (0x0B<<0),
OSC_XOSCSEL_EXTCLK_gc = (0x00<<0),
OSC_XOSCSEL_32KHz_gc = (0x02<<0),
OSC_XOSCSEL_XTAL_256CLK_gc = (0x03<<0),
OSC_XOSCSEL_XTAL_1KCLK_gc = (0x07<<0),
OSC_XOSCSEL_XTAL_16KCLK_gc = (0x0B<<0),
OSC_XOSCSEL_EXTCLK_gc = (0x00<<0),
OSC_XOSCSEL_32KHz_gc = (0x02<<0),
OSC_XOSCSEL_XTAL_256CLK_gc = (0x03<<0),
OSC_XOSCSEL_XTAL_1KCLK_gc = (0x07<<0),
OSC_XOSCSEL_XTAL_16KCLK_gc = (0x0B<<0),
OSC_XOSCSEL_EXTCLK_gc = (0x00<<0),
OSC_XOSCSEL_32KHz_gc = (0x02<<0),
OSC_XOSCSEL_XTAL_256CLK_gc = (0x03<<0),
OSC_XOSCSEL_XTAL_1KCLK_gc = (0x07<<0),
OSC_XOSCSEL_XTAL_16KCLK_gc = (0x0B<<0),
OSC_XOSCSEL_EXTCLK_gc = (0x00<<0),
OSC_XOSCSEL_32KHz_gc = (0x02<<0),
OSC_XOSCSEL_XTAL_256CLK_gc = (0x03<<0),
OSC_XOSCSEL_XTAL_1KCLK_gc = (0x07<<0),
OSC_XOSCSEL_XTAL_16KCLK_gc = (0x0B<<0),
OSC_XOSCSEL_EXTCLK_gc = (0x00<<0),
OSC_XOSCSEL_32KHz_gc = (0x02<<0),
OSC_XOSCSEL_XTAL_256CLK_gc = (0x03<<0),
OSC_XOSCSEL_XTAL_1KCLK_gc = (0x07<<0),
OSC_XOSCSEL_XTAL_16KCLK_gc = (0x0B<<0),
OSC_XOSCSEL_EXTCLK_gc = (0x00<<0),
OSC_XOSCSEL_32KHz_gc = (0x02<<0),
OSC_XOSCSEL_XTAL_256CLK_gc = (0x03<<0),
OSC_XOSCSEL_XTAL_1KCLK_gc = (0x07<<0),
OSC_XOSCSEL_XTAL_16KCLK_gc = (0x0B<<0),
OSC_XOSCSEL_EXTCLK_gc = (0x00<<0),
OSC_XOSCSEL_32KHz_gc = (0x02<<0),
OSC_XOSCSEL_XTAL_256CLK_gc = (0x03<<0),
OSC_XOSCSEL_XTAL_1KCLK_gc = (0x07<<0),
OSC_XOSCSEL_XTAL_16KCLK_gc = (0x0B<<0),
OSC_XOSCSEL_EXTCLK_gc = (0x00<<0),
OSC_XOSCSEL_32KHz_gc = (0x02<<0),
OSC_XOSCSEL_XTAL_256CLK_gc = (0x03<<0),
OSC_XOSCSEL_XTAL_1KCLK_gc = (0x07<<0),
OSC_XOSCSEL_XTAL_16KCLK_gc = (0x0B<<0),
OSC_XOSCSEL_EXTCLK_gc = (0x00<<0),
OSC_XOSCSEL_32KHz_gc = (0x02<<0),
OSC_XOSCSEL_XTAL_256CLK_gc = (0x03<<0),
OSC_XOSCSEL_XTAL_1KCLK_gc = (0x07<<0),
OSC_XOSCSEL_XTAL_16KCLK_gc = (0x0B<<0),
OSC_XOSCSEL_EXTCLK_gc = (0x00<<0),
OSC_XOSCSEL_32KHz_gc = (0x02<<0),
OSC_XOSCSEL_XTAL_256CLK_gc = (0x03<<0),
OSC_XOSCSEL_XTAL_1KCLK_gc = (0x07<<0),
OSC_XOSCSEL_XTAL_16KCLK_gc = (0x0B<<0),
OSC_XOSCSEL_EXTCLK_gc = (0x00<<0),
OSC_XOSCSEL_32KHz_gc = (0x02<<0),
OSC_XOSCSEL_XTAL_256CLK_gc = (0x03<<0),
OSC_XOSCSEL_XTAL_1KCLK_gc = (0x07<<0),
OSC_XOSCSEL_XTAL_16KCLK_gc = (0x0B<<0),
OSC_XOSCSEL_EXTCLK_gc = (0x00<<0),
OSC_XOSCSEL_32KHz_gc = (0x02<<0),
OSC_XOSCSEL_XTAL_256CLK_gc = (0x03<<0),
OSC_XOSCSEL_XTAL_1KCLK_gc = (0x07<<0),
OSC_XOSCSEL_XTAL_16KCLK_gc = (0x0B<<0),
OSC_XOSCSEL_EXTCLK_gc = (0x00<<0),
OSC_XOSCSEL_32KHz_gc = (0x02<<0),
OSC_XOSCSEL_XTAL_256CLK_gc = (0x03<<0),
OSC_XOSCSEL_XTAL_1KCLK_gc = (0x07<<0),
OSC_XOSCSEL_XTAL_16KCLK_gc = (0x0B<<0),
OSC_XOSCSEL_EXTCLK_gc = (0x00<<0),
OSC_XOSCSEL_32KHz_gc = (0x02<<0),
OSC_XOSCSEL_XTAL_256CLK_gc = (0x03<<0),
OSC_XOSCSEL_XTAL_1KCLK_gc = (0x07<<0),
OSC_XOSCSEL_XTAL_16KCLK_gc = (0x0B<<0)
} |
|
enum | OSC_PLLSRC_enum {
OSC_PLLSRC_RC2M_gc = (0x00<<6),
OSC_PLLSRC_RC32M_gc = (0x02<<6),
OSC_PLLSRC_XOSC_gc = (0x03<<6),
OSC_PLLSRC_RC2M_gc = (0x00<<6),
OSC_PLLSRC_RC32M_gc = (0x02<<6),
OSC_PLLSRC_XOSC_gc = (0x03<<6),
OSC_PLLSRC_RC2M_gc = (0x00<<6),
OSC_PLLSRC_RC32M_gc = (0x02<<6),
OSC_PLLSRC_XOSC_gc = (0x03<<6),
OSC_PLLSRC_RC2M_gc = (0x00<<6),
OSC_PLLSRC_RC32M_gc = (0x02<<6),
OSC_PLLSRC_XOSC_gc = (0x03<<6),
OSC_PLLSRC_RC2M_gc = (0x00<<6),
OSC_PLLSRC_RC32M_gc = (0x02<<6),
OSC_PLLSRC_XOSC_gc = (0x03<<6),
OSC_PLLSRC_RC2M_gc = (0x00<<6),
OSC_PLLSRC_RC32M_gc = (0x02<<6),
OSC_PLLSRC_XOSC_gc = (0x03<<6),
OSC_PLLSRC_RC2M_gc = (0x00<<6),
OSC_PLLSRC_RC32M_gc = (0x02<<6),
OSC_PLLSRC_XOSC_gc = (0x03<<6),
OSC_PLLSRC_RC2M_gc = (0x00<<6),
OSC_PLLSRC_RC32M_gc = (0x02<<6),
OSC_PLLSRC_XOSC_gc = (0x03<<6),
OSC_PLLSRC_RC2M_gc = (0x00<<6),
OSC_PLLSRC_RC32M_gc = (0x02<<6),
OSC_PLLSRC_XOSC_gc = (0x03<<6),
OSC_PLLSRC_RC2M_gc = (0x00<<6),
OSC_PLLSRC_RC32M_gc = (0x02<<6),
OSC_PLLSRC_XOSC_gc = (0x03<<6),
OSC_PLLSRC_RC2M_gc = (0x00<<6),
OSC_PLLSRC_RC32M_gc = (0x02<<6),
OSC_PLLSRC_XOSC_gc = (0x03<<6),
OSC_PLLSRC_RC2M_gc = (0x00<<6),
OSC_PLLSRC_RC32M_gc = (0x02<<6),
OSC_PLLSRC_XOSC_gc = (0x03<<6),
OSC_PLLSRC_RC2M_gc = (0x00<<6),
OSC_PLLSRC_RC32M_gc = (0x02<<6),
OSC_PLLSRC_XOSC_gc = (0x03<<6),
OSC_PLLSRC_RC2M_gc = (0x00<<6),
OSC_PLLSRC_RC32M_gc = (0x02<<6),
OSC_PLLSRC_XOSC_gc = (0x03<<6),
OSC_PLLSRC_RC2M_gc = (0x00<<6),
OSC_PLLSRC_RC32M_gc = (0x02<<6),
OSC_PLLSRC_XOSC_gc = (0x03<<6)
} |
|
enum | WDT_PER_enum {
WDT_PER_8CLK_gc = (0x00<<2),
WDT_PER_16CLK_gc = (0x01<<2),
WDT_PER_32CLK_gc = (0x02<<2),
WDT_PER_64CLK_gc = (0x03<<2),
WDT_PER_128CLK_gc = (0x04<<2),
WDT_PER_256CLK_gc = (0x05<<2),
WDT_PER_512CLK_gc = (0x06<<2),
WDT_PER_1KCLK_gc = (0x07<<2),
WDT_PER_2KCLK_gc = (0x08<<2),
WDT_PER_4KCLK_gc = (0x09<<2),
WDT_PER_8KCLK_gc = (0x0A<<2),
WDT_PER_8CLK_gc = (0x00<<2),
WDT_PER_16CLK_gc = (0x01<<2),
WDT_PER_32CLK_gc = (0x02<<2),
WDT_PER_64CLK_gc = (0x03<<2),
WDT_PER_128CLK_gc = (0x04<<2),
WDT_PER_256CLK_gc = (0x05<<2),
WDT_PER_512CLK_gc = (0x06<<2),
WDT_PER_1KCLK_gc = (0x07<<2),
WDT_PER_2KCLK_gc = (0x08<<2),
WDT_PER_4KCLK_gc = (0x09<<2),
WDT_PER_8KCLK_gc = (0x0A<<2),
WDT_PER_8CLK_gc = (0x00<<2),
WDT_PER_16CLK_gc = (0x01<<2),
WDT_PER_32CLK_gc = (0x02<<2),
WDT_PER_64CLK_gc = (0x03<<2),
WDT_PER_125CLK_gc = (0x04<<2),
WDT_PER_250CLK_gc = (0x05<<2),
WDT_PER_500CLK_gc = (0x06<<2),
WDT_PER_1KCLK_gc = (0x07<<2),
WDT_PER_2KCLK_gc = (0x08<<2),
WDT_PER_4KCLK_gc = (0x09<<2),
WDT_PER_8KCLK_gc = (0x0A<<2),
WDT_PER_8CLK_gc = (0x00<<2),
WDT_PER_16CLK_gc = (0x01<<2),
WDT_PER_32CLK_gc = (0x02<<2),
WDT_PER_64CLK_gc = (0x03<<2),
WDT_PER_128CLK_gc = (0x04<<2),
WDT_PER_256CLK_gc = (0x05<<2),
WDT_PER_512CLK_gc = (0x06<<2),
WDT_PER_1KCLK_gc = (0x07<<2),
WDT_PER_2KCLK_gc = (0x08<<2),
WDT_PER_4KCLK_gc = (0x09<<2),
WDT_PER_8KCLK_gc = (0x0A<<2),
WDT_PER_8CLK_gc = (0x00<<2),
WDT_PER_16CLK_gc = (0x01<<2),
WDT_PER_32CLK_gc = (0x02<<2),
WDT_PER_64CLK_gc = (0x03<<2),
WDT_PER_128CLK_gc = (0x04<<2),
WDT_PER_256CLK_gc = (0x05<<2),
WDT_PER_512CLK_gc = (0x06<<2),
WDT_PER_1KCLK_gc = (0x07<<2),
WDT_PER_2KCLK_gc = (0x08<<2),
WDT_PER_4KCLK_gc = (0x09<<2),
WDT_PER_8KCLK_gc = (0x0A<<2),
WDT_PER_8CLK_gc = (0x00<<2),
WDT_PER_16CLK_gc = (0x01<<2),
WDT_PER_32CLK_gc = (0x02<<2),
WDT_PER_64CLK_gc = (0x03<<2),
WDT_PER_128CLK_gc = (0x04<<2),
WDT_PER_256CLK_gc = (0x05<<2),
WDT_PER_512CLK_gc = (0x06<<2),
WDT_PER_1KCLK_gc = (0x07<<2),
WDT_PER_2KCLK_gc = (0x08<<2),
WDT_PER_4KCLK_gc = (0x09<<2),
WDT_PER_8KCLK_gc = (0x0A<<2),
WDT_PER_8CLK_gc = (0x00<<2),
WDT_PER_16CLK_gc = (0x01<<2),
WDT_PER_32CLK_gc = (0x02<<2),
WDT_PER_64CLK_gc = (0x03<<2),
WDT_PER_125CLK_gc = (0x04<<2),
WDT_PER_250CLK_gc = (0x05<<2),
WDT_PER_500CLK_gc = (0x06<<2),
WDT_PER_1KCLK_gc = (0x07<<2),
WDT_PER_2KCLK_gc = (0x08<<2),
WDT_PER_4KCLK_gc = (0x09<<2),
WDT_PER_8KCLK_gc = (0x0A<<2),
WDT_PER_8CLK_gc = (0x00<<2),
WDT_PER_16CLK_gc = (0x01<<2),
WDT_PER_32CLK_gc = (0x02<<2),
WDT_PER_64CLK_gc = (0x03<<2),
WDT_PER_128CLK_gc = (0x04<<2),
WDT_PER_256CLK_gc = (0x05<<2),
WDT_PER_512CLK_gc = (0x06<<2),
WDT_PER_1KCLK_gc = (0x07<<2),
WDT_PER_2KCLK_gc = (0x08<<2),
WDT_PER_4KCLK_gc = (0x09<<2),
WDT_PER_8KCLK_gc = (0x0A<<2),
WDT_PER_8CLK_gc = (0x00<<2),
WDT_PER_16CLK_gc = (0x01<<2),
WDT_PER_32CLK_gc = (0x02<<2),
WDT_PER_64CLK_gc = (0x03<<2),
WDT_PER_128CLK_gc = (0x04<<2),
WDT_PER_256CLK_gc = (0x05<<2),
WDT_PER_512CLK_gc = (0x06<<2),
WDT_PER_1KCLK_gc = (0x07<<2),
WDT_PER_2KCLK_gc = (0x08<<2),
WDT_PER_4KCLK_gc = (0x09<<2),
WDT_PER_8KCLK_gc = (0x0A<<2),
WDT_PER_8CLK_gc = (0x00<<2),
WDT_PER_16CLK_gc = (0x01<<2),
WDT_PER_32CLK_gc = (0x02<<2),
WDT_PER_64CLK_gc = (0x03<<2),
WDT_PER_125CLK_gc = (0x04<<2),
WDT_PER_250CLK_gc = (0x05<<2),
WDT_PER_500CLK_gc = (0x06<<2),
WDT_PER_1KCLK_gc = (0x07<<2),
WDT_PER_2KCLK_gc = (0x08<<2),
WDT_PER_4KCLK_gc = (0x09<<2),
WDT_PER_8KCLK_gc = (0x0A<<2),
WDT_PER_8CLK_gc = (0x00<<2),
WDT_PER_16CLK_gc = (0x01<<2),
WDT_PER_32CLK_gc = (0x02<<2),
WDT_PER_64CLK_gc = (0x03<<2),
WDT_PER_128CLK_gc = (0x04<<2),
WDT_PER_256CLK_gc = (0x05<<2),
WDT_PER_512CLK_gc = (0x06<<2),
WDT_PER_1KCLK_gc = (0x07<<2),
WDT_PER_2KCLK_gc = (0x08<<2),
WDT_PER_4KCLK_gc = (0x09<<2),
WDT_PER_8KCLK_gc = (0x0A<<2),
WDT_PER_8CLK_gc = (0x00<<2),
WDT_PER_16CLK_gc = (0x01<<2),
WDT_PER_32CLK_gc = (0x02<<2),
WDT_PER_64CLK_gc = (0x03<<2),
WDT_PER_128CLK_gc = (0x04<<2),
WDT_PER_256CLK_gc = (0x05<<2),
WDT_PER_512CLK_gc = (0x06<<2),
WDT_PER_1KCLK_gc = (0x07<<2),
WDT_PER_2KCLK_gc = (0x08<<2),
WDT_PER_4KCLK_gc = (0x09<<2),
WDT_PER_8KCLK_gc = (0x0A<<2),
WDT_PER_8CLK_gc = (0x00<<2),
WDT_PER_16CLK_gc = (0x01<<2),
WDT_PER_32CLK_gc = (0x02<<2),
WDT_PER_64CLK_gc = (0x03<<2),
WDT_PER_128CLK_gc = (0x04<<2),
WDT_PER_256CLK_gc = (0x05<<2),
WDT_PER_512CLK_gc = (0x06<<2),
WDT_PER_1KCLK_gc = (0x07<<2),
WDT_PER_2KCLK_gc = (0x08<<2),
WDT_PER_4KCLK_gc = (0x09<<2),
WDT_PER_8KCLK_gc = (0x0A<<2),
WDT_PER_8CLK_gc = (0x00<<2),
WDT_PER_16CLK_gc = (0x01<<2),
WDT_PER_32CLK_gc = (0x02<<2),
WDT_PER_64CLK_gc = (0x03<<2),
WDT_PER_128CLK_gc = (0x04<<2),
WDT_PER_256CLK_gc = (0x05<<2),
WDT_PER_512CLK_gc = (0x06<<2),
WDT_PER_1KCLK_gc = (0x07<<2),
WDT_PER_2KCLK_gc = (0x08<<2),
WDT_PER_4KCLK_gc = (0x09<<2),
WDT_PER_8KCLK_gc = (0x0A<<2),
WDT_PER_8CLK_gc = (0x00<<2),
WDT_PER_16CLK_gc = (0x01<<2),
WDT_PER_32CLK_gc = (0x02<<2),
WDT_PER_64CLK_gc = (0x03<<2),
WDT_PER_125CLK_gc = (0x04<<2),
WDT_PER_250CLK_gc = (0x05<<2),
WDT_PER_500CLK_gc = (0x06<<2),
WDT_PER_1KCLK_gc = (0x07<<2),
WDT_PER_2KCLK_gc = (0x08<<2),
WDT_PER_4KCLK_gc = (0x09<<2),
WDT_PER_8KCLK_gc = (0x0A<<2)
} |
|
enum | WDT_WPER_enum {
WDT_WPER_8CLK_gc = (0x00<<2),
WDT_WPER_16CLK_gc = (0x01<<2),
WDT_WPER_32CLK_gc = (0x02<<2),
WDT_WPER_64CLK_gc = (0x03<<2),
WDT_WPER_128CLK_gc = (0x04<<2),
WDT_WPER_256CLK_gc = (0x05<<2),
WDT_WPER_512CLK_gc = (0x06<<2),
WDT_WPER_1KCLK_gc = (0x07<<2),
WDT_WPER_2KCLK_gc = (0x08<<2),
WDT_WPER_4KCLK_gc = (0x09<<2),
WDT_WPER_8KCLK_gc = (0x0A<<2),
WDT_WPER_8CLK_gc = (0x00<<2),
WDT_WPER_16CLK_gc = (0x01<<2),
WDT_WPER_32CLK_gc = (0x02<<2),
WDT_WPER_64CLK_gc = (0x03<<2),
WDT_WPER_128CLK_gc = (0x04<<2),
WDT_WPER_256CLK_gc = (0x05<<2),
WDT_WPER_512CLK_gc = (0x06<<2),
WDT_WPER_1KCLK_gc = (0x07<<2),
WDT_WPER_2KCLK_gc = (0x08<<2),
WDT_WPER_4KCLK_gc = (0x09<<2),
WDT_WPER_8KCLK_gc = (0x0A<<2),
WDT_WPER_8CLK_gc = (0x00<<2),
WDT_WPER_16CLK_gc = (0x01<<2),
WDT_WPER_32CLK_gc = (0x02<<2),
WDT_WPER_64CLK_gc = (0x03<<2),
WDT_WPER_125CLK_gc = (0x04<<2),
WDT_WPER_250CLK_gc = (0x05<<2),
WDT_WPER_500CLK_gc = (0x06<<2),
WDT_WPER_1KCLK_gc = (0x07<<2),
WDT_WPER_2KCLK_gc = (0x08<<2),
WDT_WPER_4KCLK_gc = (0x09<<2),
WDT_WPER_8KCLK_gc = (0x0A<<2),
WDT_WPER_8CLK_gc = (0x00<<2),
WDT_WPER_16CLK_gc = (0x01<<2),
WDT_WPER_32CLK_gc = (0x02<<2),
WDT_WPER_64CLK_gc = (0x03<<2),
WDT_WPER_128CLK_gc = (0x04<<2),
WDT_WPER_256CLK_gc = (0x05<<2),
WDT_WPER_512CLK_gc = (0x06<<2),
WDT_WPER_1KCLK_gc = (0x07<<2),
WDT_WPER_2KCLK_gc = (0x08<<2),
WDT_WPER_4KCLK_gc = (0x09<<2),
WDT_WPER_8KCLK_gc = (0x0A<<2),
WDT_WPER_8CLK_gc = (0x00<<2),
WDT_WPER_16CLK_gc = (0x01<<2),
WDT_WPER_32CLK_gc = (0x02<<2),
WDT_WPER_64CLK_gc = (0x03<<2),
WDT_WPER_128CLK_gc = (0x04<<2),
WDT_WPER_256CLK_gc = (0x05<<2),
WDT_WPER_512CLK_gc = (0x06<<2),
WDT_WPER_1KCLK_gc = (0x07<<2),
WDT_WPER_2KCLK_gc = (0x08<<2),
WDT_WPER_4KCLK_gc = (0x09<<2),
WDT_WPER_8KCLK_gc = (0x0A<<2),
WDT_WPER_8CLK_gc = (0x00<<2),
WDT_WPER_16CLK_gc = (0x01<<2),
WDT_WPER_32CLK_gc = (0x02<<2),
WDT_WPER_64CLK_gc = (0x03<<2),
WDT_WPER_128CLK_gc = (0x04<<2),
WDT_WPER_256CLK_gc = (0x05<<2),
WDT_WPER_512CLK_gc = (0x06<<2),
WDT_WPER_1KCLK_gc = (0x07<<2),
WDT_WPER_2KCLK_gc = (0x08<<2),
WDT_WPER_4KCLK_gc = (0x09<<2),
WDT_WPER_8KCLK_gc = (0x0A<<2),
WDT_WPER_8CLK_gc = (0x00<<2),
WDT_WPER_16CLK_gc = (0x01<<2),
WDT_WPER_32CLK_gc = (0x02<<2),
WDT_WPER_64CLK_gc = (0x03<<2),
WDT_WPER_125CLK_gc = (0x04<<2),
WDT_WPER_250CLK_gc = (0x05<<2),
WDT_WPER_500CLK_gc = (0x06<<2),
WDT_WPER_1KCLK_gc = (0x07<<2),
WDT_WPER_2KCLK_gc = (0x08<<2),
WDT_WPER_4KCLK_gc = (0x09<<2),
WDT_WPER_8KCLK_gc = (0x0A<<2),
WDT_WPER_8CLK_gc = (0x00<<2),
WDT_WPER_16CLK_gc = (0x01<<2),
WDT_WPER_32CLK_gc = (0x02<<2),
WDT_WPER_64CLK_gc = (0x03<<2),
WDT_WPER_128CLK_gc = (0x04<<2),
WDT_WPER_256CLK_gc = (0x05<<2),
WDT_WPER_512CLK_gc = (0x06<<2),
WDT_WPER_1KCLK_gc = (0x07<<2),
WDT_WPER_2KCLK_gc = (0x08<<2),
WDT_WPER_4KCLK_gc = (0x09<<2),
WDT_WPER_8KCLK_gc = (0x0A<<2),
WDT_WPER_8CLK_gc = (0x00<<2),
WDT_WPER_16CLK_gc = (0x01<<2),
WDT_WPER_32CLK_gc = (0x02<<2),
WDT_WPER_64CLK_gc = (0x03<<2),
WDT_WPER_128CLK_gc = (0x04<<2),
WDT_WPER_256CLK_gc = (0x05<<2),
WDT_WPER_512CLK_gc = (0x06<<2),
WDT_WPER_1KCLK_gc = (0x07<<2),
WDT_WPER_2KCLK_gc = (0x08<<2),
WDT_WPER_4KCLK_gc = (0x09<<2),
WDT_WPER_8KCLK_gc = (0x0A<<2),
WDT_WPER_8CLK_gc = (0x00<<2),
WDT_WPER_16CLK_gc = (0x01<<2),
WDT_WPER_32CLK_gc = (0x02<<2),
WDT_WPER_64CLK_gc = (0x03<<2),
WDT_WPER_125CLK_gc = (0x04<<2),
WDT_WPER_250CLK_gc = (0x05<<2),
WDT_WPER_500CLK_gc = (0x06<<2),
WDT_WPER_1KCLK_gc = (0x07<<2),
WDT_WPER_2KCLK_gc = (0x08<<2),
WDT_WPER_4KCLK_gc = (0x09<<2),
WDT_WPER_8KCLK_gc = (0x0A<<2),
WDT_WPER_8CLK_gc = (0x00<<2),
WDT_WPER_16CLK_gc = (0x01<<2),
WDT_WPER_32CLK_gc = (0x02<<2),
WDT_WPER_64CLK_gc = (0x03<<2),
WDT_WPER_128CLK_gc = (0x04<<2),
WDT_WPER_256CLK_gc = (0x05<<2),
WDT_WPER_512CLK_gc = (0x06<<2),
WDT_WPER_1KCLK_gc = (0x07<<2),
WDT_WPER_2KCLK_gc = (0x08<<2),
WDT_WPER_4KCLK_gc = (0x09<<2),
WDT_WPER_8KCLK_gc = (0x0A<<2),
WDT_WPER_8CLK_gc = (0x00<<2),
WDT_WPER_16CLK_gc = (0x01<<2),
WDT_WPER_32CLK_gc = (0x02<<2),
WDT_WPER_64CLK_gc = (0x03<<2),
WDT_WPER_128CLK_gc = (0x04<<2),
WDT_WPER_256CLK_gc = (0x05<<2),
WDT_WPER_512CLK_gc = (0x06<<2),
WDT_WPER_1KCLK_gc = (0x07<<2),
WDT_WPER_2KCLK_gc = (0x08<<2),
WDT_WPER_4KCLK_gc = (0x09<<2),
WDT_WPER_8KCLK_gc = (0x0A<<2),
WDT_WPER_8CLK_gc = (0x00<<2),
WDT_WPER_16CLK_gc = (0x01<<2),
WDT_WPER_32CLK_gc = (0x02<<2),
WDT_WPER_64CLK_gc = (0x03<<2),
WDT_WPER_128CLK_gc = (0x04<<2),
WDT_WPER_256CLK_gc = (0x05<<2),
WDT_WPER_512CLK_gc = (0x06<<2),
WDT_WPER_1KCLK_gc = (0x07<<2),
WDT_WPER_2KCLK_gc = (0x08<<2),
WDT_WPER_4KCLK_gc = (0x09<<2),
WDT_WPER_8KCLK_gc = (0x0A<<2),
WDT_WPER_8CLK_gc = (0x00<<2),
WDT_WPER_16CLK_gc = (0x01<<2),
WDT_WPER_32CLK_gc = (0x02<<2),
WDT_WPER_64CLK_gc = (0x03<<2),
WDT_WPER_128CLK_gc = (0x04<<2),
WDT_WPER_256CLK_gc = (0x05<<2),
WDT_WPER_512CLK_gc = (0x06<<2),
WDT_WPER_1KCLK_gc = (0x07<<2),
WDT_WPER_2KCLK_gc = (0x08<<2),
WDT_WPER_4KCLK_gc = (0x09<<2),
WDT_WPER_8KCLK_gc = (0x0A<<2),
WDT_WPER_8CLK_gc = (0x00<<2),
WDT_WPER_16CLK_gc = (0x01<<2),
WDT_WPER_32CLK_gc = (0x02<<2),
WDT_WPER_64CLK_gc = (0x03<<2),
WDT_WPER_125CLK_gc = (0x04<<2),
WDT_WPER_250CLK_gc = (0x05<<2),
WDT_WPER_500CLK_gc = (0x06<<2),
WDT_WPER_1KCLK_gc = (0x07<<2),
WDT_WPER_2KCLK_gc = (0x08<<2),
WDT_WPER_4KCLK_gc = (0x09<<2),
WDT_WPER_8KCLK_gc = (0x0A<<2)
} |
|
enum | DMA_CH_BURSTLEN_enum {
DMA_CH_BURSTLEN_1BYTE_gc = (0x00<<0),
DMA_CH_BURSTLEN_2BYTE_gc = (0x01<<0),
DMA_CH_BURSTLEN_4BYTE_gc = (0x02<<0),
DMA_CH_BURSTLEN_8BYTE_gc = (0x03<<0),
DMA_CH_BURSTLEN_1BYTE_gc = (0x00<<0),
DMA_CH_BURSTLEN_2BYTE_gc = (0x01<<0),
DMA_CH_BURSTLEN_4BYTE_gc = (0x02<<0),
DMA_CH_BURSTLEN_8BYTE_gc = (0x03<<0),
DMA_CH_BURSTLEN_1BYTE_gc = (0x00<<0),
DMA_CH_BURSTLEN_2BYTE_gc = (0x01<<0),
DMA_CH_BURSTLEN_4BYTE_gc = (0x02<<0),
DMA_CH_BURSTLEN_8BYTE_gc = (0x03<<0),
DMA_CH_BURSTLEN_1BYTE_gc = (0x00<<0),
DMA_CH_BURSTLEN_2BYTE_gc = (0x01<<0),
DMA_CH_BURSTLEN_4BYTE_gc = (0x02<<0),
DMA_CH_BURSTLEN_8BYTE_gc = (0x03<<0),
DMA_CH_BURSTLEN_1BYTE_gc = (0x00<<0),
DMA_CH_BURSTLEN_2BYTE_gc = (0x01<<0),
DMA_CH_BURSTLEN_4BYTE_gc = (0x02<<0),
DMA_CH_BURSTLEN_8BYTE_gc = (0x03<<0),
DMA_CH_BURSTLEN_1BYTE_gc = (0x00<<0),
DMA_CH_BURSTLEN_2BYTE_gc = (0x01<<0),
DMA_CH_BURSTLEN_4BYTE_gc = (0x02<<0),
DMA_CH_BURSTLEN_8BYTE_gc = (0x03<<0),
DMA_CH_BURSTLEN_1BYTE_gc = (0x00<<0),
DMA_CH_BURSTLEN_2BYTE_gc = (0x01<<0),
DMA_CH_BURSTLEN_4BYTE_gc = (0x02<<0),
DMA_CH_BURSTLEN_8BYTE_gc = (0x03<<0),
DMA_CH_BURSTLEN_1BYTE_gc = (0x00<<0),
DMA_CH_BURSTLEN_2BYTE_gc = (0x01<<0),
DMA_CH_BURSTLEN_4BYTE_gc = (0x02<<0),
DMA_CH_BURSTLEN_8BYTE_gc = (0x03<<0),
DMA_CH_BURSTLEN_1BYTE_gc = (0x00<<0),
DMA_CH_BURSTLEN_2BYTE_gc = (0x01<<0),
DMA_CH_BURSTLEN_4BYTE_gc = (0x02<<0),
DMA_CH_BURSTLEN_8BYTE_gc = (0x03<<0)
} |
|
enum | DMA_CH_SRCRELOAD_enum {
DMA_CH_SRCRELOAD_NONE_gc = (0x00<<6),
DMA_CH_SRCRELOAD_BLOCK_gc = (0x01<<6),
DMA_CH_SRCRELOAD_BURST_gc = (0x02<<6),
DMA_CH_SRCRELOAD_TRANSACTION_gc = (0x03<<6),
DMA_CH_SRCRELOAD_NONE_gc = (0x00<<6),
DMA_CH_SRCRELOAD_BLOCK_gc = (0x01<<6),
DMA_CH_SRCRELOAD_BURST_gc = (0x02<<6),
DMA_CH_SRCRELOAD_TRANSACTION_gc = (0x03<<6),
DMA_CH_SRCRELOAD_NONE_gc = (0x00<<6),
DMA_CH_SRCRELOAD_BLOCK_gc = (0x01<<6),
DMA_CH_SRCRELOAD_BURST_gc = (0x02<<6),
DMA_CH_SRCRELOAD_TRANSACTION_gc = (0x03<<6),
DMA_CH_SRCRELOAD_NONE_gc = (0x00<<6),
DMA_CH_SRCRELOAD_BLOCK_gc = (0x01<<6),
DMA_CH_SRCRELOAD_BURST_gc = (0x02<<6),
DMA_CH_SRCRELOAD_TRANSACTION_gc = (0x03<<6),
DMA_CH_SRCRELOAD_NONE_gc = (0x00<<6),
DMA_CH_SRCRELOAD_BLOCK_gc = (0x01<<6),
DMA_CH_SRCRELOAD_BURST_gc = (0x02<<6),
DMA_CH_SRCRELOAD_TRANSACTION_gc = (0x03<<6),
DMA_CH_SRCRELOAD_NONE_gc = (0x00<<6),
DMA_CH_SRCRELOAD_BLOCK_gc = (0x01<<6),
DMA_CH_SRCRELOAD_BURST_gc = (0x02<<6),
DMA_CH_SRCRELOAD_TRANSACTION_gc = (0x03<<6),
DMA_CH_SRCRELOAD_NONE_gc = (0x00<<6),
DMA_CH_SRCRELOAD_BLOCK_gc = (0x01<<6),
DMA_CH_SRCRELOAD_BURST_gc = (0x02<<6),
DMA_CH_SRCRELOAD_TRANSACTION_gc = (0x03<<6),
DMA_CH_SRCRELOAD_NONE_gc = (0x00<<6),
DMA_CH_SRCRELOAD_BLOCK_gc = (0x01<<6),
DMA_CH_SRCRELOAD_BURST_gc = (0x02<<6),
DMA_CH_SRCRELOAD_TRANSACTION_gc = (0x03<<6),
DMA_CH_SRCRELOAD_NONE_gc = (0x00<<6),
DMA_CH_SRCRELOAD_BLOCK_gc = (0x01<<6),
DMA_CH_SRCRELOAD_BURST_gc = (0x02<<6),
DMA_CH_SRCRELOAD_TRANSACTION_gc = (0x03<<6)
} |
|
enum | DMA_CH_SRCDIR_enum {
DMA_CH_SRCDIR_FIXED_gc = (0x00<<4),
DMA_CH_SRCDIR_INC_gc = (0x01<<4),
DMA_CH_SRCDIR_DEC_gc = (0x02<<4),
DMA_CH_SRCDIR_FIXED_gc = (0x00<<4),
DMA_CH_SRCDIR_INC_gc = (0x01<<4),
DMA_CH_SRCDIR_DEC_gc = (0x02<<4),
DMA_CH_SRCDIR_FIXED_gc = (0x00<<4),
DMA_CH_SRCDIR_INC_gc = (0x01<<4),
DMA_CH_SRCDIR_DEC_gc = (0x02<<4),
DMA_CH_SRCDIR_FIXED_gc = (0x00<<4),
DMA_CH_SRCDIR_INC_gc = (0x01<<4),
DMA_CH_SRCDIR_DEC_gc = (0x02<<4),
DMA_CH_SRCDIR_FIXED_gc = (0x00<<4),
DMA_CH_SRCDIR_INC_gc = (0x01<<4),
DMA_CH_SRCDIR_DEC_gc = (0x02<<4),
DMA_CH_SRCDIR_FIXED_gc = (0x00<<4),
DMA_CH_SRCDIR_INC_gc = (0x01<<4),
DMA_CH_SRCDIR_DEC_gc = (0x02<<4),
DMA_CH_SRCDIR_FIXED_gc = (0x00<<4),
DMA_CH_SRCDIR_INC_gc = (0x01<<4),
DMA_CH_SRCDIR_DEC_gc = (0x02<<4),
DMA_CH_SRCDIR_FIXED_gc = (0x00<<4),
DMA_CH_SRCDIR_INC_gc = (0x01<<4),
DMA_CH_SRCDIR_DEC_gc = (0x02<<4),
DMA_CH_SRCDIR_FIXED_gc = (0x00<<4),
DMA_CH_SRCDIR_INC_gc = (0x01<<4),
DMA_CH_SRCDIR_DEC_gc = (0x02<<4)
} |
|
enum | DMA_CH_DESTRELOAD_enum {
DMA_CH_DESTRELOAD_NONE_gc = (0x00<<2),
DMA_CH_DESTRELOAD_BLOCK_gc = (0x01<<2),
DMA_CH_DESTRELOAD_BURST_gc = (0x02<<2),
DMA_CH_DESTRELOAD_TRANSACTION_gc = (0x03<<2),
DMA_CH_DESTRELOAD_NONE_gc = (0x00<<2),
DMA_CH_DESTRELOAD_BLOCK_gc = (0x01<<2),
DMA_CH_DESTRELOAD_BURST_gc = (0x02<<2),
DMA_CH_DESTRELOAD_TRANSACTION_gc = (0x03<<2),
DMA_CH_DESTRELOAD_NONE_gc = (0x00<<2),
DMA_CH_DESTRELOAD_BLOCK_gc = (0x01<<2),
DMA_CH_DESTRELOAD_BURST_gc = (0x02<<2),
DMA_CH_DESTRELOAD_TRANSACTION_gc = (0x03<<2),
DMA_CH_DESTRELOAD_NONE_gc = (0x00<<2),
DMA_CH_DESTRELOAD_BLOCK_gc = (0x01<<2),
DMA_CH_DESTRELOAD_BURST_gc = (0x02<<2),
DMA_CH_DESTRELOAD_TRANSACTION_gc = (0x03<<2),
DMA_CH_DESTRELOAD_NONE_gc = (0x00<<2),
DMA_CH_DESTRELOAD_BLOCK_gc = (0x01<<2),
DMA_CH_DESTRELOAD_BURST_gc = (0x02<<2),
DMA_CH_DESTRELOAD_TRANSACTION_gc = (0x03<<2),
DMA_CH_DESTRELOAD_NONE_gc = (0x00<<2),
DMA_CH_DESTRELOAD_BLOCK_gc = (0x01<<2),
DMA_CH_DESTRELOAD_BURST_gc = (0x02<<2),
DMA_CH_DESTRELOAD_TRANSACTION_gc = (0x03<<2),
DMA_CH_DESTRELOAD_NONE_gc = (0x00<<2),
DMA_CH_DESTRELOAD_BLOCK_gc = (0x01<<2),
DMA_CH_DESTRELOAD_BURST_gc = (0x02<<2),
DMA_CH_DESTRELOAD_TRANSACTION_gc = (0x03<<2),
DMA_CH_DESTRELOAD_NONE_gc = (0x00<<2),
DMA_CH_DESTRELOAD_BLOCK_gc = (0x01<<2),
DMA_CH_DESTRELOAD_BURST_gc = (0x02<<2),
DMA_CH_DESTRELOAD_TRANSACTION_gc = (0x03<<2),
DMA_CH_DESTRELOAD_NONE_gc = (0x00<<2),
DMA_CH_DESTRELOAD_BLOCK_gc = (0x01<<2),
DMA_CH_DESTRELOAD_BURST_gc = (0x02<<2),
DMA_CH_DESTRELOAD_TRANSACTION_gc = (0x03<<2)
} |
|
enum | DMA_CH_DESTDIR_enum {
DMA_CH_DESTDIR_FIXED_gc = (0x00<<0),
DMA_CH_DESTDIR_INC_gc = (0x01<<0),
DMA_CH_DESTDIR_DEC_gc = (0x02<<0),
DMA_CH_DESTDIR_FIXED_gc = (0x00<<0),
DMA_CH_DESTDIR_INC_gc = (0x01<<0),
DMA_CH_DESTDIR_DEC_gc = (0x02<<0),
DMA_CH_DESTDIR_FIXED_gc = (0x00<<0),
DMA_CH_DESTDIR_INC_gc = (0x01<<0),
DMA_CH_DESTDIR_DEC_gc = (0x02<<0),
DMA_CH_DESTDIR_FIXED_gc = (0x00<<0),
DMA_CH_DESTDIR_INC_gc = (0x01<<0),
DMA_CH_DESTDIR_DEC_gc = (0x02<<0),
DMA_CH_DESTDIR_FIXED_gc = (0x00<<0),
DMA_CH_DESTDIR_INC_gc = (0x01<<0),
DMA_CH_DESTDIR_DEC_gc = (0x02<<0),
DMA_CH_DESTDIR_FIXED_gc = (0x00<<0),
DMA_CH_DESTDIR_INC_gc = (0x01<<0),
DMA_CH_DESTDIR_DEC_gc = (0x02<<0),
DMA_CH_DESTDIR_FIXED_gc = (0x00<<0),
DMA_CH_DESTDIR_INC_gc = (0x01<<0),
DMA_CH_DESTDIR_DEC_gc = (0x02<<0),
DMA_CH_DESTDIR_FIXED_gc = (0x00<<0),
DMA_CH_DESTDIR_INC_gc = (0x01<<0),
DMA_CH_DESTDIR_DEC_gc = (0x02<<0),
DMA_CH_DESTDIR_FIXED_gc = (0x00<<0),
DMA_CH_DESTDIR_INC_gc = (0x01<<0),
DMA_CH_DESTDIR_DEC_gc = (0x02<<0)
} |
|
enum | DMA_CH_TRIGSRC_enum {
DMA_CH_TRIGSRC_OFF_gc = (0x00<<0),
DMA_CH_TRIGSRC_EVSYS_CH0_gc = (0x01<<0),
DMA_CH_TRIGSRC_EVSYS_CH1_gc = (0x02<<0),
DMA_CH_TRIGSRC_EVSYS_CH2_gc = (0x03<<0),
DMA_CH_TRIGSRC_ADCA_CH0_gc = (0x10<<0),
DMA_CH_TRIGSRC_ADCA_CH1_gc = (0x11<<0),
DMA_CH_TRIGSRC_ADCA_CH2_gc = (0x12<<0),
DMA_CH_TRIGSRC_ADCA_CH3_gc = (0x13<<0),
DMA_CH_TRIGSRC_ADCA_CH4_gc = (0x14<<0),
DMA_CH_TRIGSRC_DACA_CH0_gc = (0x15<<0),
DMA_CH_TRIGSRC_DACA_CH1_gc = (0x16<<0),
DMA_CH_TRIGSRC_ADCB_CH0_gc = (0x20<<0),
DMA_CH_TRIGSRC_ADCB_CH1_gc = (0x21<<0),
DMA_CH_TRIGSRC_ADCB_CH2_gc = (0x22<<0),
DMA_CH_TRIGSRC_ADCB_CH3_gc = (0x23<<0),
DMA_CH_TRIGSRC_ADCB_CH4_gc = (0x24<<0),
DMA_CH_TRIGSRC_DACB_CH0_gc = (0x25<<0),
DMA_CH_TRIGSRC_DACB_CH1_gc = (0x26<<0),
DMA_CH_TRIGSRC_TCC0_OVF_gc = (0x40<<0),
DMA_CH_TRIGSRC_TCC0_ERR_gc = (0x41<<0),
DMA_CH_TRIGSRC_TCC0_CCA_gc = (0x42<<0),
DMA_CH_TRIGSRC_TCC0_CCB_gc = (0x43<<0),
DMA_CH_TRIGSRC_TCC0_CCC_gc = (0x44<<0),
DMA_CH_TRIGSRC_TCC0_CCD_gc = (0x45<<0),
DMA_CH_TRIGSRC_TCC1_OVF_gc = (0x46<<0),
DMA_CH_TRIGSRC_TCC1_ERR_gc = (0x47<<0),
DMA_CH_TRIGSRC_TCC1_CCA_gc = (0x48<<0),
DMA_CH_TRIGSRC_TCC1_CCB_gc = (0x49<<0),
DMA_CH_TRIGSRC_SPIC_gc = (0x4A<<0),
DMA_CH_TRIGSRC_USARTC0_RXC_gc = (0x4B<<0),
DMA_CH_TRIGSRC_USARTC0_DRE_gc = (0x4C<<0),
DMA_CH_TRIGSRC_USARTC1_RXC_gc = (0x4E<<0),
DMA_CH_TRIGSRC_USARTC1_DRE_gc = (0x4F<<0),
DMA_CH_TRIGSRC_TCD0_OVF_gc = (0x60<<0),
DMA_CH_TRIGSRC_TCD0_ERR_gc = (0x61<<0),
DMA_CH_TRIGSRC_TCD0_CCA_gc = (0x62<<0),
DMA_CH_TRIGSRC_TCD0_CCB_gc = (0x63<<0),
DMA_CH_TRIGSRC_TCD0_CCC_gc = (0x64<<0),
DMA_CH_TRIGSRC_TCD0_CCD_gc = (0x65<<0),
DMA_CH_TRIGSRC_TCD1_OVF_gc = (0x66<<0),
DMA_CH_TRIGSRC_TCD1_ERR_gc = (0x67<<0),
DMA_CH_TRIGSRC_TCD1_CCA_gc = (0x68<<0),
DMA_CH_TRIGSRC_TCD1_CCB_gc = (0x69<<0),
DMA_CH_TRIGSRC_SPID_gc = (0x6A<<0),
DMA_CH_TRIGSRC_USARTD0_RXC_gc = (0x6B<<0),
DMA_CH_TRIGSRC_USARTD0_DRE_gc = (0x6C<<0),
DMA_CH_TRIGSRC_USARTD1_RXC_gc = (0x6E<<0),
DMA_CH_TRIGSRC_USARTD1_DRE_gc = (0x6F<<0),
DMA_CH_TRIGSRC_TCE0_OVF_gc = (0x80<<0),
DMA_CH_TRIGSRC_TCE0_ERR_gc = (0x81<<0),
DMA_CH_TRIGSRC_TCE0_CCA_gc = (0x82<<0),
DMA_CH_TRIGSRC_TCE0_CCB_gc = (0x83<<0),
DMA_CH_TRIGSRC_TCE0_CCC_gc = (0x84<<0),
DMA_CH_TRIGSRC_TCE0_CCD_gc = (0x85<<0),
DMA_CH_TRIGSRC_TCE1_OVF_gc = (0x86<<0),
DMA_CH_TRIGSRC_TCE1_ERR_gc = (0x87<<0),
DMA_CH_TRIGSRC_TCE1_CCA_gc = (0x88<<0),
DMA_CH_TRIGSRC_TCE1_CCB_gc = (0x89<<0),
DMA_CH_TRIGSRC_SPIE_gc = (0x8A<<0),
DMA_CH_TRIGSRC_USARTE0_RXC_gc = (0x8B<<0),
DMA_CH_TRIGSRC_USARTE0_DRE_gc = (0x8C<<0),
DMA_CH_TRIGSRC_USARTE1_RXC_gc = (0x8E<<0),
DMA_CH_TRIGSRC_USARTE1_DRE_gc = (0x8F<<0),
DMA_CH_TRIGSRC_TCF0_OVF_gc = (0xA0<<0),
DMA_CH_TRIGSRC_TCF0_ERR_gc = (0xA1<<0),
DMA_CH_TRIGSRC_TCF0_CCA_gc = (0xA2<<0),
DMA_CH_TRIGSRC_TCF0_CCB_gc = (0xA3<<0),
DMA_CH_TRIGSRC_TCF0_CCC_gc = (0xA4<<0),
DMA_CH_TRIGSRC_TCF0_CCD_gc = (0xA5<<0),
DMA_CH_TRIGSRC_TCF1_OVF_gc = (0xA6<<0),
DMA_CH_TRIGSRC_TCF1_ERR_gc = (0xA7<<0),
DMA_CH_TRIGSRC_TCF1_CCA_gc = (0xA8<<0),
DMA_CH_TRIGSRC_TCF1_CCB_gc = (0xA9<<0),
DMA_CH_TRIGSRC_SPIF_gc = (0xAA<<0),
DMA_CH_TRIGSRC_USARTF0_RXC_gc = (0xAB<<0),
DMA_CH_TRIGSRC_USARTF0_DRE_gc = (0xAC<<0),
DMA_CH_TRIGSRC_USARTF1_RXC_gc = (0xAE<<0),
DMA_CH_TRIGSRC_USARTF1_DRE_gc = (0xAF<<0),
DMA_CH_TRIGSRC_OFF_gc = (0x00<<0),
DMA_CH_TRIGSRC_EVSYS_CH0_gc = (0x01<<0),
DMA_CH_TRIGSRC_EVSYS_CH1_gc = (0x02<<0),
DMA_CH_TRIGSRC_EVSYS_CH2_gc = (0x03<<0),
DMA_CH_TRIGSRC_ADCA_CH0_gc = (0x10<<0),
DMA_CH_TRIGSRC_ADCA_CH1_gc = (0x11<<0),
DMA_CH_TRIGSRC_ADCA_CH2_gc = (0x12<<0),
DMA_CH_TRIGSRC_ADCA_CH3_gc = (0x13<<0),
DMA_CH_TRIGSRC_ADCA_CH4_gc = (0x14<<0),
DMA_CH_TRIGSRC_DACA_CH0_gc = (0x15<<0),
DMA_CH_TRIGSRC_DACA_CH1_gc = (0x16<<0),
DMA_CH_TRIGSRC_ADCB_CH0_gc = (0x20<<0),
DMA_CH_TRIGSRC_ADCB_CH1_gc = (0x21<<0),
DMA_CH_TRIGSRC_ADCB_CH2_gc = (0x22<<0),
DMA_CH_TRIGSRC_ADCB_CH3_gc = (0x23<<0),
DMA_CH_TRIGSRC_ADCB_CH4_gc = (0x24<<0),
DMA_CH_TRIGSRC_DACB_CH0_gc = (0x25<<0),
DMA_CH_TRIGSRC_DACB_CH1_gc = (0x26<<0),
DMA_CH_TRIGSRC_TCC0_OVF_gc = (0x40<<0),
DMA_CH_TRIGSRC_TCC0_ERR_gc = (0x41<<0),
DMA_CH_TRIGSRC_TCC0_CCA_gc = (0x42<<0),
DMA_CH_TRIGSRC_TCC0_CCB_gc = (0x43<<0),
DMA_CH_TRIGSRC_TCC0_CCC_gc = (0x44<<0),
DMA_CH_TRIGSRC_TCC0_CCD_gc = (0x45<<0),
DMA_CH_TRIGSRC_TCC1_OVF_gc = (0x46<<0),
DMA_CH_TRIGSRC_TCC1_ERR_gc = (0x47<<0),
DMA_CH_TRIGSRC_TCC1_CCA_gc = (0x48<<0),
DMA_CH_TRIGSRC_TCC1_CCB_gc = (0x49<<0),
DMA_CH_TRIGSRC_SPIC_gc = (0x4A<<0),
DMA_CH_TRIGSRC_USARTC0_RXC_gc = (0x4B<<0),
DMA_CH_TRIGSRC_USARTC0_DRE_gc = (0x4C<<0),
DMA_CH_TRIGSRC_USARTC1_RXC_gc = (0x4E<<0),
DMA_CH_TRIGSRC_USARTC1_DRE_gc = (0x4F<<0),
DMA_CH_TRIGSRC_TCD0_OVF_gc = (0x60<<0),
DMA_CH_TRIGSRC_TCD0_ERR_gc = (0x61<<0),
DMA_CH_TRIGSRC_TCD0_CCA_gc = (0x62<<0),
DMA_CH_TRIGSRC_TCD0_CCB_gc = (0x63<<0),
DMA_CH_TRIGSRC_TCD0_CCC_gc = (0x64<<0),
DMA_CH_TRIGSRC_TCD0_CCD_gc = (0x65<<0),
DMA_CH_TRIGSRC_TCD1_OVF_gc = (0x66<<0),
DMA_CH_TRIGSRC_TCD1_ERR_gc = (0x67<<0),
DMA_CH_TRIGSRC_TCD1_CCA_gc = (0x68<<0),
DMA_CH_TRIGSRC_TCD1_CCB_gc = (0x69<<0),
DMA_CH_TRIGSRC_SPID_gc = (0x6A<<0),
DMA_CH_TRIGSRC_USARTD0_RXC_gc = (0x6B<<0),
DMA_CH_TRIGSRC_USARTD0_DRE_gc = (0x6C<<0),
DMA_CH_TRIGSRC_USARTD1_RXC_gc = (0x6E<<0),
DMA_CH_TRIGSRC_USARTD1_DRE_gc = (0x6F<<0),
DMA_CH_TRIGSRC_TCE0_OVF_gc = (0x80<<0),
DMA_CH_TRIGSRC_TCE0_ERR_gc = (0x81<<0),
DMA_CH_TRIGSRC_TCE0_CCA_gc = (0x82<<0),
DMA_CH_TRIGSRC_TCE0_CCB_gc = (0x83<<0),
DMA_CH_TRIGSRC_TCE0_CCC_gc = (0x84<<0),
DMA_CH_TRIGSRC_TCE0_CCD_gc = (0x85<<0),
DMA_CH_TRIGSRC_TCE1_OVF_gc = (0x86<<0),
DMA_CH_TRIGSRC_TCE1_ERR_gc = (0x87<<0),
DMA_CH_TRIGSRC_TCE1_CCA_gc = (0x88<<0),
DMA_CH_TRIGSRC_TCE1_CCB_gc = (0x89<<0),
DMA_CH_TRIGSRC_SPIE_gc = (0x8A<<0),
DMA_CH_TRIGSRC_USARTE0_RXC_gc = (0x8B<<0),
DMA_CH_TRIGSRC_USARTE0_DRE_gc = (0x8C<<0),
DMA_CH_TRIGSRC_USARTE1_RXC_gc = (0x8E<<0),
DMA_CH_TRIGSRC_USARTE1_DRE_gc = (0x8F<<0),
DMA_CH_TRIGSRC_TCF0_OVF_gc = (0xA0<<0),
DMA_CH_TRIGSRC_TCF0_ERR_gc = (0xA1<<0),
DMA_CH_TRIGSRC_TCF0_CCA_gc = (0xA2<<0),
DMA_CH_TRIGSRC_TCF0_CCB_gc = (0xA3<<0),
DMA_CH_TRIGSRC_TCF0_CCC_gc = (0xA4<<0),
DMA_CH_TRIGSRC_TCF0_CCD_gc = (0xA5<<0),
DMA_CH_TRIGSRC_TCF1_OVF_gc = (0xA6<<0),
DMA_CH_TRIGSRC_TCF1_ERR_gc = (0xA7<<0),
DMA_CH_TRIGSRC_TCF1_CCA_gc = (0xA8<<0),
DMA_CH_TRIGSRC_TCF1_CCB_gc = (0xA9<<0),
DMA_CH_TRIGSRC_SPIF_gc = (0xAA<<0),
DMA_CH_TRIGSRC_USARTF0_RXC_gc = (0xAB<<0),
DMA_CH_TRIGSRC_USARTF0_DRE_gc = (0xAC<<0),
DMA_CH_TRIGSRC_USARTF1_RXC_gc = (0xAE<<0),
DMA_CH_TRIGSRC_USARTF1_DRE_gc = (0xAF<<0),
DMA_CH_TRIGSRC_OFF_gc = (0x00<<0),
DMA_CH_TRIGSRC_EVSYS_CH0_gc = (0x01<<0),
DMA_CH_TRIGSRC_EVSYS_CH1_gc = (0x02<<0),
DMA_CH_TRIGSRC_EVSYS_CH2_gc = (0x03<<0),
DMA_CH_TRIGSRC_ADCA_CH0_gc = (0x10<<0),
DMA_CH_TRIGSRC_ADCA_CH1_gc = (0x11<<0),
DMA_CH_TRIGSRC_ADCA_CH2_gc = (0x12<<0),
DMA_CH_TRIGSRC_ADCA_CH3_gc = (0x13<<0),
DMA_CH_TRIGSRC_ADCA_CH4_gc = (0x14<<0),
DMA_CH_TRIGSRC_DACA_CH0_gc = (0x15<<0),
DMA_CH_TRIGSRC_DACA_CH1_gc = (0x16<<0),
DMA_CH_TRIGSRC_ADCB_CH0_gc = (0x20<<0),
DMA_CH_TRIGSRC_ADCB_CH1_gc = (0x21<<0),
DMA_CH_TRIGSRC_ADCB_CH2_gc = (0x22<<0),
DMA_CH_TRIGSRC_ADCB_CH3_gc = (0x23<<0),
DMA_CH_TRIGSRC_ADCB_CH4_gc = (0x24<<0),
DMA_CH_TRIGSRC_DACB_CH0_gc = (0x25<<0),
DMA_CH_TRIGSRC_DACB_CH1_gc = (0x26<<0),
DMA_CH_TRIGSRC_TCC0_OVF_gc = (0x40<<0),
DMA_CH_TRIGSRC_TCC0_ERR_gc = (0x41<<0),
DMA_CH_TRIGSRC_TCC0_CCA_gc = (0x42<<0),
DMA_CH_TRIGSRC_TCC0_CCB_gc = (0x43<<0),
DMA_CH_TRIGSRC_TCC0_CCC_gc = (0x44<<0),
DMA_CH_TRIGSRC_TCC0_CCD_gc = (0x45<<0),
DMA_CH_TRIGSRC_TCC1_OVF_gc = (0x46<<0),
DMA_CH_TRIGSRC_TCC1_ERR_gc = (0x47<<0),
DMA_CH_TRIGSRC_TCC1_CCA_gc = (0x48<<0),
DMA_CH_TRIGSRC_TCC1_CCB_gc = (0x49<<0),
DMA_CH_TRIGSRC_SPIC_gc = (0x4A<<0),
DMA_CH_TRIGSRC_USARTC0_RXC_gc = (0x4B<<0),
DMA_CH_TRIGSRC_USARTC0_DRE_gc = (0x4C<<0),
DMA_CH_TRIGSRC_USARTC1_RXC_gc = (0x4E<<0),
DMA_CH_TRIGSRC_USARTC1_DRE_gc = (0x4F<<0),
DMA_CH_TRIGSRC_TCD0_OVF_gc = (0x60<<0),
DMA_CH_TRIGSRC_TCD0_ERR_gc = (0x61<<0),
DMA_CH_TRIGSRC_TCD0_CCA_gc = (0x62<<0),
DMA_CH_TRIGSRC_TCD0_CCB_gc = (0x63<<0),
DMA_CH_TRIGSRC_TCD0_CCC_gc = (0x64<<0),
DMA_CH_TRIGSRC_TCD0_CCD_gc = (0x65<<0),
DMA_CH_TRIGSRC_TCD1_OVF_gc = (0x66<<0),
DMA_CH_TRIGSRC_TCD1_ERR_gc = (0x67<<0),
DMA_CH_TRIGSRC_TCD1_CCA_gc = (0x68<<0),
DMA_CH_TRIGSRC_TCD1_CCB_gc = (0x69<<0),
DMA_CH_TRIGSRC_SPID_gc = (0x6A<<0),
DMA_CH_TRIGSRC_USARTD0_RXC_gc = (0x6B<<0),
DMA_CH_TRIGSRC_USARTD0_DRE_gc = (0x6C<<0),
DMA_CH_TRIGSRC_USARTD1_RXC_gc = (0x6E<<0),
DMA_CH_TRIGSRC_USARTD1_DRE_gc = (0x6F<<0),
DMA_CH_TRIGSRC_TCE0_OVF_gc = (0x80<<0),
DMA_CH_TRIGSRC_TCE0_ERR_gc = (0x81<<0),
DMA_CH_TRIGSRC_TCE0_CCA_gc = (0x82<<0),
DMA_CH_TRIGSRC_TCE0_CCB_gc = (0x83<<0),
DMA_CH_TRIGSRC_TCE0_CCC_gc = (0x84<<0),
DMA_CH_TRIGSRC_TCE0_CCD_gc = (0x85<<0),
DMA_CH_TRIGSRC_TCE1_OVF_gc = (0x86<<0),
DMA_CH_TRIGSRC_TCE1_ERR_gc = (0x87<<0),
DMA_CH_TRIGSRC_TCE1_CCA_gc = (0x88<<0),
DMA_CH_TRIGSRC_TCE1_CCB_gc = (0x89<<0),
DMA_CH_TRIGSRC_SPIE_gc = (0x8A<<0),
DMA_CH_TRIGSRC_USARTE0_RXC_gc = (0x8B<<0),
DMA_CH_TRIGSRC_USARTE0_DRE_gc = (0x8C<<0),
DMA_CH_TRIGSRC_USARTE1_RXC_gc = (0x8E<<0),
DMA_CH_TRIGSRC_USARTE1_DRE_gc = (0x8F<<0),
DMA_CH_TRIGSRC_TCF0_OVF_gc = (0xA0<<0),
DMA_CH_TRIGSRC_TCF0_ERR_gc = (0xA1<<0),
DMA_CH_TRIGSRC_TCF0_CCA_gc = (0xA2<<0),
DMA_CH_TRIGSRC_TCF0_CCB_gc = (0xA3<<0),
DMA_CH_TRIGSRC_TCF0_CCC_gc = (0xA4<<0),
DMA_CH_TRIGSRC_TCF0_CCD_gc = (0xA5<<0),
DMA_CH_TRIGSRC_TCF1_OVF_gc = (0xA6<<0),
DMA_CH_TRIGSRC_TCF1_ERR_gc = (0xA7<<0),
DMA_CH_TRIGSRC_TCF1_CCA_gc = (0xA8<<0),
DMA_CH_TRIGSRC_TCF1_CCB_gc = (0xA9<<0),
DMA_CH_TRIGSRC_SPIF_gc = (0xAA<<0),
DMA_CH_TRIGSRC_USARTF0_RXC_gc = (0xAB<<0),
DMA_CH_TRIGSRC_USARTF0_DRE_gc = (0xAC<<0),
DMA_CH_TRIGSRC_USARTF1_RXC_gc = (0xAE<<0),
DMA_CH_TRIGSRC_USARTF1_DRE_gc = (0xAF<<0),
DMA_CH_TRIGSRC_OFF_gc = (0x00<<0),
DMA_CH_TRIGSRC_EVSYS_CH0_gc = (0x01<<0),
DMA_CH_TRIGSRC_EVSYS_CH1_gc = (0x02<<0),
DMA_CH_TRIGSRC_EVSYS_CH2_gc = (0x03<<0),
DMA_CH_TRIGSRC_ADCA_CH0_gc = (0x10<<0),
DMA_CH_TRIGSRC_ADCA_CH1_gc = (0x11<<0),
DMA_CH_TRIGSRC_ADCA_CH2_gc = (0x12<<0),
DMA_CH_TRIGSRC_ADCA_CH3_gc = (0x13<<0),
DMA_CH_TRIGSRC_ADCA_CH4_gc = (0x14<<0),
DMA_CH_TRIGSRC_DACA_CH0_gc = (0x15<<0),
DMA_CH_TRIGSRC_DACA_CH1_gc = (0x16<<0),
DMA_CH_TRIGSRC_ADCB_CH0_gc = (0x20<<0),
DMA_CH_TRIGSRC_ADCB_CH1_gc = (0x21<<0),
DMA_CH_TRIGSRC_ADCB_CH2_gc = (0x22<<0),
DMA_CH_TRIGSRC_ADCB_CH3_gc = (0x23<<0),
DMA_CH_TRIGSRC_ADCB_CH4_gc = (0x24<<0),
DMA_CH_TRIGSRC_DACB_CH0_gc = (0x25<<0),
DMA_CH_TRIGSRC_DACB_CH1_gc = (0x26<<0),
DMA_CH_TRIGSRC_TCC0_OVF_gc = (0x40<<0),
DMA_CH_TRIGSRC_TCC0_ERR_gc = (0x41<<0),
DMA_CH_TRIGSRC_TCC0_CCA_gc = (0x42<<0),
DMA_CH_TRIGSRC_TCC0_CCB_gc = (0x43<<0),
DMA_CH_TRIGSRC_TCC0_CCC_gc = (0x44<<0),
DMA_CH_TRIGSRC_TCC0_CCD_gc = (0x45<<0),
DMA_CH_TRIGSRC_TCC1_OVF_gc = (0x46<<0),
DMA_CH_TRIGSRC_TCC1_ERR_gc = (0x47<<0),
DMA_CH_TRIGSRC_TCC1_CCA_gc = (0x48<<0),
DMA_CH_TRIGSRC_TCC1_CCB_gc = (0x49<<0),
DMA_CH_TRIGSRC_SPIC_gc = (0x4A<<0),
DMA_CH_TRIGSRC_USARTC0_RXC_gc = (0x4B<<0),
DMA_CH_TRIGSRC_USARTC0_DRE_gc = (0x4C<<0),
DMA_CH_TRIGSRC_USARTC1_RXC_gc = (0x4E<<0),
DMA_CH_TRIGSRC_USARTC1_DRE_gc = (0x4F<<0),
DMA_CH_TRIGSRC_TCD0_OVF_gc = (0x60<<0),
DMA_CH_TRIGSRC_TCD0_ERR_gc = (0x61<<0),
DMA_CH_TRIGSRC_TCD0_CCA_gc = (0x62<<0),
DMA_CH_TRIGSRC_TCD0_CCB_gc = (0x63<<0),
DMA_CH_TRIGSRC_TCD0_CCC_gc = (0x64<<0),
DMA_CH_TRIGSRC_TCD0_CCD_gc = (0x65<<0),
DMA_CH_TRIGSRC_TCD1_OVF_gc = (0x66<<0),
DMA_CH_TRIGSRC_TCD1_ERR_gc = (0x67<<0),
DMA_CH_TRIGSRC_TCD1_CCA_gc = (0x68<<0),
DMA_CH_TRIGSRC_TCD1_CCB_gc = (0x69<<0),
DMA_CH_TRIGSRC_SPID_gc = (0x6A<<0),
DMA_CH_TRIGSRC_USARTD0_RXC_gc = (0x6B<<0),
DMA_CH_TRIGSRC_USARTD0_DRE_gc = (0x6C<<0),
DMA_CH_TRIGSRC_USARTD1_RXC_gc = (0x6E<<0),
DMA_CH_TRIGSRC_USARTD1_DRE_gc = (0x6F<<0),
DMA_CH_TRIGSRC_TCE0_OVF_gc = (0x80<<0),
DMA_CH_TRIGSRC_TCE0_ERR_gc = (0x81<<0),
DMA_CH_TRIGSRC_TCE0_CCA_gc = (0x82<<0),
DMA_CH_TRIGSRC_TCE0_CCB_gc = (0x83<<0),
DMA_CH_TRIGSRC_TCE0_CCC_gc = (0x84<<0),
DMA_CH_TRIGSRC_TCE0_CCD_gc = (0x85<<0),
DMA_CH_TRIGSRC_TCE1_OVF_gc = (0x86<<0),
DMA_CH_TRIGSRC_TCE1_ERR_gc = (0x87<<0),
DMA_CH_TRIGSRC_TCE1_CCA_gc = (0x88<<0),
DMA_CH_TRIGSRC_TCE1_CCB_gc = (0x89<<0),
DMA_CH_TRIGSRC_SPIE_gc = (0x8A<<0),
DMA_CH_TRIGSRC_USARTE0_RXC_gc = (0x8B<<0),
DMA_CH_TRIGSRC_USARTE0_DRE_gc = (0x8C<<0),
DMA_CH_TRIGSRC_USARTE1_RXC_gc = (0x8E<<0),
DMA_CH_TRIGSRC_USARTE1_DRE_gc = (0x8F<<0),
DMA_CH_TRIGSRC_TCF0_OVF_gc = (0xA0<<0),
DMA_CH_TRIGSRC_TCF0_ERR_gc = (0xA1<<0),
DMA_CH_TRIGSRC_TCF0_CCA_gc = (0xA2<<0),
DMA_CH_TRIGSRC_TCF0_CCB_gc = (0xA3<<0),
DMA_CH_TRIGSRC_TCF0_CCC_gc = (0xA4<<0),
DMA_CH_TRIGSRC_TCF0_CCD_gc = (0xA5<<0),
DMA_CH_TRIGSRC_TCF1_OVF_gc = (0xA6<<0),
DMA_CH_TRIGSRC_TCF1_ERR_gc = (0xA7<<0),
DMA_CH_TRIGSRC_TCF1_CCA_gc = (0xA8<<0),
DMA_CH_TRIGSRC_TCF1_CCB_gc = (0xA9<<0),
DMA_CH_TRIGSRC_SPIF_gc = (0xAA<<0),
DMA_CH_TRIGSRC_USARTF0_RXC_gc = (0xAB<<0),
DMA_CH_TRIGSRC_USARTF0_DRE_gc = (0xAC<<0),
DMA_CH_TRIGSRC_USARTF1_RXC_gc = (0xAE<<0),
DMA_CH_TRIGSRC_USARTF1_DRE_gc = (0xAF<<0),
DMA_CH_TRIGSRC_OFF_gc = (0x00<<0),
DMA_CH_TRIGSRC_EVSYS_CH0_gc = (0x01<<0),
DMA_CH_TRIGSRC_EVSYS_CH1_gc = (0x02<<0),
DMA_CH_TRIGSRC_EVSYS_CH2_gc = (0x03<<0),
DMA_CH_TRIGSRC_ADCA_CH0_gc = (0x10<<0),
DMA_CH_TRIGSRC_ADCA_CH1_gc = (0x11<<0),
DMA_CH_TRIGSRC_ADCA_CH2_gc = (0x12<<0),
DMA_CH_TRIGSRC_ADCA_CH3_gc = (0x13<<0),
DMA_CH_TRIGSRC_ADCA_CH4_gc = (0x14<<0),
DMA_CH_TRIGSRC_DACA_CH0_gc = (0x15<<0),
DMA_CH_TRIGSRC_DACA_CH1_gc = (0x16<<0),
DMA_CH_TRIGSRC_ADCB_CH0_gc = (0x20<<0),
DMA_CH_TRIGSRC_ADCB_CH1_gc = (0x21<<0),
DMA_CH_TRIGSRC_ADCB_CH2_gc = (0x22<<0),
DMA_CH_TRIGSRC_ADCB_CH3_gc = (0x23<<0),
DMA_CH_TRIGSRC_ADCB_CH4_gc = (0x24<<0),
DMA_CH_TRIGSRC_DACB_CH0_gc = (0x25<<0),
DMA_CH_TRIGSRC_DACB_CH1_gc = (0x26<<0),
DMA_CH_TRIGSRC_TCC0_OVF_gc = (0x40<<0),
DMA_CH_TRIGSRC_TCC0_ERR_gc = (0x41<<0),
DMA_CH_TRIGSRC_TCC0_CCA_gc = (0x42<<0),
DMA_CH_TRIGSRC_TCC0_CCB_gc = (0x43<<0),
DMA_CH_TRIGSRC_TCC0_CCC_gc = (0x44<<0),
DMA_CH_TRIGSRC_TCC0_CCD_gc = (0x45<<0),
DMA_CH_TRIGSRC_TCC1_OVF_gc = (0x46<<0),
DMA_CH_TRIGSRC_TCC1_ERR_gc = (0x47<<0),
DMA_CH_TRIGSRC_TCC1_CCA_gc = (0x48<<0),
DMA_CH_TRIGSRC_TCC1_CCB_gc = (0x49<<0),
DMA_CH_TRIGSRC_SPIC_gc = (0x4A<<0),
DMA_CH_TRIGSRC_USARTC0_RXC_gc = (0x4B<<0),
DMA_CH_TRIGSRC_USARTC0_DRE_gc = (0x4C<<0),
DMA_CH_TRIGSRC_USARTC1_RXC_gc = (0x4E<<0),
DMA_CH_TRIGSRC_USARTC1_DRE_gc = (0x4F<<0),
DMA_CH_TRIGSRC_TCD0_OVF_gc = (0x60<<0),
DMA_CH_TRIGSRC_TCD0_ERR_gc = (0x61<<0),
DMA_CH_TRIGSRC_TCD0_CCA_gc = (0x62<<0),
DMA_CH_TRIGSRC_TCD0_CCB_gc = (0x63<<0),
DMA_CH_TRIGSRC_TCD0_CCC_gc = (0x64<<0),
DMA_CH_TRIGSRC_TCD0_CCD_gc = (0x65<<0),
DMA_CH_TRIGSRC_TCD1_OVF_gc = (0x66<<0),
DMA_CH_TRIGSRC_TCD1_ERR_gc = (0x67<<0),
DMA_CH_TRIGSRC_TCD1_CCA_gc = (0x68<<0),
DMA_CH_TRIGSRC_TCD1_CCB_gc = (0x69<<0),
DMA_CH_TRIGSRC_SPID_gc = (0x6A<<0),
DMA_CH_TRIGSRC_USARTD0_RXC_gc = (0x6B<<0),
DMA_CH_TRIGSRC_USARTD0_DRE_gc = (0x6C<<0),
DMA_CH_TRIGSRC_USARTD1_RXC_gc = (0x6E<<0),
DMA_CH_TRIGSRC_USARTD1_DRE_gc = (0x6F<<0),
DMA_CH_TRIGSRC_TCE0_OVF_gc = (0x80<<0),
DMA_CH_TRIGSRC_TCE0_ERR_gc = (0x81<<0),
DMA_CH_TRIGSRC_TCE0_CCA_gc = (0x82<<0),
DMA_CH_TRIGSRC_TCE0_CCB_gc = (0x83<<0),
DMA_CH_TRIGSRC_TCE0_CCC_gc = (0x84<<0),
DMA_CH_TRIGSRC_TCE0_CCD_gc = (0x85<<0),
DMA_CH_TRIGSRC_TCE1_OVF_gc = (0x86<<0),
DMA_CH_TRIGSRC_TCE1_ERR_gc = (0x87<<0),
DMA_CH_TRIGSRC_TCE1_CCA_gc = (0x88<<0),
DMA_CH_TRIGSRC_TCE1_CCB_gc = (0x89<<0),
DMA_CH_TRIGSRC_SPIE_gc = (0x8A<<0),
DMA_CH_TRIGSRC_USARTE0_RXC_gc = (0x8B<<0),
DMA_CH_TRIGSRC_USARTE0_DRE_gc = (0x8C<<0),
DMA_CH_TRIGSRC_USARTE1_RXC_gc = (0x8E<<0),
DMA_CH_TRIGSRC_USARTE1_DRE_gc = (0x8F<<0),
DMA_CH_TRIGSRC_TCF0_OVF_gc = (0xA0<<0),
DMA_CH_TRIGSRC_TCF0_ERR_gc = (0xA1<<0),
DMA_CH_TRIGSRC_TCF0_CCA_gc = (0xA2<<0),
DMA_CH_TRIGSRC_TCF0_CCB_gc = (0xA3<<0),
DMA_CH_TRIGSRC_TCF0_CCC_gc = (0xA4<<0),
DMA_CH_TRIGSRC_TCF0_CCD_gc = (0xA5<<0),
DMA_CH_TRIGSRC_TCF1_OVF_gc = (0xA6<<0),
DMA_CH_TRIGSRC_TCF1_ERR_gc = (0xA7<<0),
DMA_CH_TRIGSRC_TCF1_CCA_gc = (0xA8<<0),
DMA_CH_TRIGSRC_TCF1_CCB_gc = (0xA9<<0),
DMA_CH_TRIGSRC_SPIF_gc = (0xAA<<0),
DMA_CH_TRIGSRC_USARTF0_RXC_gc = (0xAB<<0),
DMA_CH_TRIGSRC_USARTF0_DRE_gc = (0xAC<<0),
DMA_CH_TRIGSRC_USARTF1_RXC_gc = (0xAE<<0),
DMA_CH_TRIGSRC_USARTF1_DRE_gc = (0xAF<<0),
DMA_CH_TRIGSRC_OFF_gc = (0x00<<0),
DMA_CH_TRIGSRC_EVSYS_CH0_gc = (0x01<<0),
DMA_CH_TRIGSRC_EVSYS_CH1_gc = (0x02<<0),
DMA_CH_TRIGSRC_EVSYS_CH2_gc = (0x03<<0),
DMA_CH_TRIGSRC_ADCA_CH0_gc = (0x10<<0),
DMA_CH_TRIGSRC_ADCA_CH1_gc = (0x11<<0),
DMA_CH_TRIGSRC_ADCA_CH2_gc = (0x12<<0),
DMA_CH_TRIGSRC_ADCA_CH3_gc = (0x13<<0),
DMA_CH_TRIGSRC_ADCA_CH4_gc = (0x14<<0),
DMA_CH_TRIGSRC_DACA_CH0_gc = (0x15<<0),
DMA_CH_TRIGSRC_DACA_CH1_gc = (0x16<<0),
DMA_CH_TRIGSRC_ADCB_CH0_gc = (0x20<<0),
DMA_CH_TRIGSRC_ADCB_CH1_gc = (0x21<<0),
DMA_CH_TRIGSRC_ADCB_CH2_gc = (0x22<<0),
DMA_CH_TRIGSRC_ADCB_CH3_gc = (0x23<<0),
DMA_CH_TRIGSRC_ADCB_CH4_gc = (0x24<<0),
DMA_CH_TRIGSRC_DACB_CH0_gc = (0x25<<0),
DMA_CH_TRIGSRC_DACB_CH1_gc = (0x26<<0),
DMA_CH_TRIGSRC_TCC0_OVF_gc = (0x40<<0),
DMA_CH_TRIGSRC_TCC0_ERR_gc = (0x41<<0),
DMA_CH_TRIGSRC_TCC0_CCA_gc = (0x42<<0),
DMA_CH_TRIGSRC_TCC0_CCB_gc = (0x43<<0),
DMA_CH_TRIGSRC_TCC0_CCC_gc = (0x44<<0),
DMA_CH_TRIGSRC_TCC0_CCD_gc = (0x45<<0),
DMA_CH_TRIGSRC_TCC1_OVF_gc = (0x46<<0),
DMA_CH_TRIGSRC_TCC1_ERR_gc = (0x47<<0),
DMA_CH_TRIGSRC_TCC1_CCA_gc = (0x48<<0),
DMA_CH_TRIGSRC_TCC1_CCB_gc = (0x49<<0),
DMA_CH_TRIGSRC_SPIC_gc = (0x4A<<0),
DMA_CH_TRIGSRC_USARTC0_RXC_gc = (0x4B<<0),
DMA_CH_TRIGSRC_USARTC0_DRE_gc = (0x4C<<0),
DMA_CH_TRIGSRC_USARTC1_RXC_gc = (0x4E<<0),
DMA_CH_TRIGSRC_USARTC1_DRE_gc = (0x4F<<0),
DMA_CH_TRIGSRC_TCD0_OVF_gc = (0x60<<0),
DMA_CH_TRIGSRC_TCD0_ERR_gc = (0x61<<0),
DMA_CH_TRIGSRC_TCD0_CCA_gc = (0x62<<0),
DMA_CH_TRIGSRC_TCD0_CCB_gc = (0x63<<0),
DMA_CH_TRIGSRC_TCD0_CCC_gc = (0x64<<0),
DMA_CH_TRIGSRC_TCD0_CCD_gc = (0x65<<0),
DMA_CH_TRIGSRC_TCD1_OVF_gc = (0x66<<0),
DMA_CH_TRIGSRC_TCD1_ERR_gc = (0x67<<0),
DMA_CH_TRIGSRC_TCD1_CCA_gc = (0x68<<0),
DMA_CH_TRIGSRC_TCD1_CCB_gc = (0x69<<0),
DMA_CH_TRIGSRC_SPID_gc = (0x6A<<0),
DMA_CH_TRIGSRC_USARTD0_RXC_gc = (0x6B<<0),
DMA_CH_TRIGSRC_USARTD0_DRE_gc = (0x6C<<0),
DMA_CH_TRIGSRC_USARTD1_RXC_gc = (0x6E<<0),
DMA_CH_TRIGSRC_USARTD1_DRE_gc = (0x6F<<0),
DMA_CH_TRIGSRC_TCE0_OVF_gc = (0x80<<0),
DMA_CH_TRIGSRC_TCE0_ERR_gc = (0x81<<0),
DMA_CH_TRIGSRC_TCE0_CCA_gc = (0x82<<0),
DMA_CH_TRIGSRC_TCE0_CCB_gc = (0x83<<0),
DMA_CH_TRIGSRC_TCE0_CCC_gc = (0x84<<0),
DMA_CH_TRIGSRC_TCE0_CCD_gc = (0x85<<0),
DMA_CH_TRIGSRC_TCE1_OVF_gc = (0x86<<0),
DMA_CH_TRIGSRC_TCE1_ERR_gc = (0x87<<0),
DMA_CH_TRIGSRC_TCE1_CCA_gc = (0x88<<0),
DMA_CH_TRIGSRC_TCE1_CCB_gc = (0x89<<0),
DMA_CH_TRIGSRC_SPIE_gc = (0x8A<<0),
DMA_CH_TRIGSRC_USARTE0_RXC_gc = (0x8B<<0),
DMA_CH_TRIGSRC_USARTE0_DRE_gc = (0x8C<<0),
DMA_CH_TRIGSRC_USARTE1_RXC_gc = (0x8E<<0),
DMA_CH_TRIGSRC_USARTE1_DRE_gc = (0x8F<<0),
DMA_CH_TRIGSRC_TCF0_OVF_gc = (0xA0<<0),
DMA_CH_TRIGSRC_TCF0_ERR_gc = (0xA1<<0),
DMA_CH_TRIGSRC_TCF0_CCA_gc = (0xA2<<0),
DMA_CH_TRIGSRC_TCF0_CCB_gc = (0xA3<<0),
DMA_CH_TRIGSRC_TCF0_CCC_gc = (0xA4<<0),
DMA_CH_TRIGSRC_TCF0_CCD_gc = (0xA5<<0),
DMA_CH_TRIGSRC_TCF1_OVF_gc = (0xA6<<0),
DMA_CH_TRIGSRC_TCF1_ERR_gc = (0xA7<<0),
DMA_CH_TRIGSRC_TCF1_CCA_gc = (0xA8<<0),
DMA_CH_TRIGSRC_TCF1_CCB_gc = (0xA9<<0),
DMA_CH_TRIGSRC_SPIF_gc = (0xAA<<0),
DMA_CH_TRIGSRC_USARTF0_RXC_gc = (0xAB<<0),
DMA_CH_TRIGSRC_USARTF0_DRE_gc = (0xAC<<0),
DMA_CH_TRIGSRC_USARTF1_RXC_gc = (0xAE<<0),
DMA_CH_TRIGSRC_USARTF1_DRE_gc = (0xAF<<0),
DMA_CH_TRIGSRC_OFF_gc = (0x00<<0),
DMA_CH_TRIGSRC_EVSYS_CH0_gc = (0x01<<0),
DMA_CH_TRIGSRC_EVSYS_CH1_gc = (0x02<<0),
DMA_CH_TRIGSRC_EVSYS_CH2_gc = (0x03<<0),
DMA_CH_TRIGSRC_ADCA_CH0_gc = (0x10<<0),
DMA_CH_TRIGSRC_ADCA_CH1_gc = (0x11<<0),
DMA_CH_TRIGSRC_ADCA_CH2_gc = (0x12<<0),
DMA_CH_TRIGSRC_ADCA_CH3_gc = (0x13<<0),
DMA_CH_TRIGSRC_ADCA_CH4_gc = (0x14<<0),
DMA_CH_TRIGSRC_DACA_CH0_gc = (0x15<<0),
DMA_CH_TRIGSRC_DACA_CH1_gc = (0x16<<0),
DMA_CH_TRIGSRC_ADCB_CH0_gc = (0x20<<0),
DMA_CH_TRIGSRC_ADCB_CH1_gc = (0x21<<0),
DMA_CH_TRIGSRC_ADCB_CH2_gc = (0x22<<0),
DMA_CH_TRIGSRC_ADCB_CH3_gc = (0x23<<0),
DMA_CH_TRIGSRC_ADCB_CH4_gc = (0x24<<0),
DMA_CH_TRIGSRC_DACB_CH0_gc = (0x25<<0),
DMA_CH_TRIGSRC_DACB_CH1_gc = (0x26<<0),
DMA_CH_TRIGSRC_TCC0_OVF_gc = (0x40<<0),
DMA_CH_TRIGSRC_TCC0_ERR_gc = (0x41<<0),
DMA_CH_TRIGSRC_TCC0_CCA_gc = (0x42<<0),
DMA_CH_TRIGSRC_TCC0_CCB_gc = (0x43<<0),
DMA_CH_TRIGSRC_TCC0_CCC_gc = (0x44<<0),
DMA_CH_TRIGSRC_TCC0_CCD_gc = (0x45<<0),
DMA_CH_TRIGSRC_TCC1_OVF_gc = (0x46<<0),
DMA_CH_TRIGSRC_TCC1_ERR_gc = (0x47<<0),
DMA_CH_TRIGSRC_TCC1_CCA_gc = (0x48<<0),
DMA_CH_TRIGSRC_TCC1_CCB_gc = (0x49<<0),
DMA_CH_TRIGSRC_SPIC_gc = (0x4A<<0),
DMA_CH_TRIGSRC_USARTC0_RXC_gc = (0x4B<<0),
DMA_CH_TRIGSRC_USARTC0_DRE_gc = (0x4C<<0),
DMA_CH_TRIGSRC_USARTC1_RXC_gc = (0x4E<<0),
DMA_CH_TRIGSRC_USARTC1_DRE_gc = (0x4F<<0),
DMA_CH_TRIGSRC_TCD0_OVF_gc = (0x60<<0),
DMA_CH_TRIGSRC_TCD0_ERR_gc = (0x61<<0),
DMA_CH_TRIGSRC_TCD0_CCA_gc = (0x62<<0),
DMA_CH_TRIGSRC_TCD0_CCB_gc = (0x63<<0),
DMA_CH_TRIGSRC_TCD0_CCC_gc = (0x64<<0),
DMA_CH_TRIGSRC_TCD0_CCD_gc = (0x65<<0),
DMA_CH_TRIGSRC_TCD1_OVF_gc = (0x66<<0),
DMA_CH_TRIGSRC_TCD1_ERR_gc = (0x67<<0),
DMA_CH_TRIGSRC_TCD1_CCA_gc = (0x68<<0),
DMA_CH_TRIGSRC_TCD1_CCB_gc = (0x69<<0),
DMA_CH_TRIGSRC_SPID_gc = (0x6A<<0),
DMA_CH_TRIGSRC_USARTD0_RXC_gc = (0x6B<<0),
DMA_CH_TRIGSRC_USARTD0_DRE_gc = (0x6C<<0),
DMA_CH_TRIGSRC_USARTD1_RXC_gc = (0x6E<<0),
DMA_CH_TRIGSRC_USARTD1_DRE_gc = (0x6F<<0),
DMA_CH_TRIGSRC_TCE0_OVF_gc = (0x80<<0),
DMA_CH_TRIGSRC_TCE0_ERR_gc = (0x81<<0),
DMA_CH_TRIGSRC_TCE0_CCA_gc = (0x82<<0),
DMA_CH_TRIGSRC_TCE0_CCB_gc = (0x83<<0),
DMA_CH_TRIGSRC_TCE0_CCC_gc = (0x84<<0),
DMA_CH_TRIGSRC_TCE0_CCD_gc = (0x85<<0),
DMA_CH_TRIGSRC_TCE1_OVF_gc = (0x86<<0),
DMA_CH_TRIGSRC_TCE1_ERR_gc = (0x87<<0),
DMA_CH_TRIGSRC_TCE1_CCA_gc = (0x88<<0),
DMA_CH_TRIGSRC_TCE1_CCB_gc = (0x89<<0),
DMA_CH_TRIGSRC_SPIE_gc = (0x8A<<0),
DMA_CH_TRIGSRC_USARTE0_RXC_gc = (0x8B<<0),
DMA_CH_TRIGSRC_USARTE0_DRE_gc = (0x8C<<0),
DMA_CH_TRIGSRC_USARTE1_RXC_gc = (0x8E<<0),
DMA_CH_TRIGSRC_USARTE1_DRE_gc = (0x8F<<0),
DMA_CH_TRIGSRC_TCF0_OVF_gc = (0xA0<<0),
DMA_CH_TRIGSRC_TCF0_ERR_gc = (0xA1<<0),
DMA_CH_TRIGSRC_TCF0_CCA_gc = (0xA2<<0),
DMA_CH_TRIGSRC_TCF0_CCB_gc = (0xA3<<0),
DMA_CH_TRIGSRC_TCF0_CCC_gc = (0xA4<<0),
DMA_CH_TRIGSRC_TCF0_CCD_gc = (0xA5<<0),
DMA_CH_TRIGSRC_TCF1_OVF_gc = (0xA6<<0),
DMA_CH_TRIGSRC_TCF1_ERR_gc = (0xA7<<0),
DMA_CH_TRIGSRC_TCF1_CCA_gc = (0xA8<<0),
DMA_CH_TRIGSRC_TCF1_CCB_gc = (0xA9<<0),
DMA_CH_TRIGSRC_SPIF_gc = (0xAA<<0),
DMA_CH_TRIGSRC_USARTF0_RXC_gc = (0xAB<<0),
DMA_CH_TRIGSRC_USARTF0_DRE_gc = (0xAC<<0),
DMA_CH_TRIGSRC_USARTF1_RXC_gc = (0xAE<<0),
DMA_CH_TRIGSRC_USARTF1_DRE_gc = (0xAF<<0),
DMA_CH_TRIGSRC_OFF_gc = (0x00<<0),
DMA_CH_TRIGSRC_EVSYS_CH0_gc = (0x01<<0),
DMA_CH_TRIGSRC_EVSYS_CH1_gc = (0x02<<0),
DMA_CH_TRIGSRC_EVSYS_CH2_gc = (0x03<<0),
DMA_CH_TRIGSRC_ADCA_CH0_gc = (0x10<<0),
DMA_CH_TRIGSRC_ADCA_CH1_gc = (0x11<<0),
DMA_CH_TRIGSRC_ADCA_CH2_gc = (0x12<<0),
DMA_CH_TRIGSRC_ADCA_CH3_gc = (0x13<<0),
DMA_CH_TRIGSRC_ADCA_CH4_gc = (0x14<<0),
DMA_CH_TRIGSRC_DACA_CH0_gc = (0x15<<0),
DMA_CH_TRIGSRC_DACA_CH1_gc = (0x16<<0),
DMA_CH_TRIGSRC_ADCB_CH0_gc = (0x20<<0),
DMA_CH_TRIGSRC_ADCB_CH1_gc = (0x21<<0),
DMA_CH_TRIGSRC_ADCB_CH2_gc = (0x22<<0),
DMA_CH_TRIGSRC_ADCB_CH3_gc = (0x23<<0),
DMA_CH_TRIGSRC_ADCB_CH4_gc = (0x24<<0),
DMA_CH_TRIGSRC_DACB_CH0_gc = (0x25<<0),
DMA_CH_TRIGSRC_DACB_CH1_gc = (0x26<<0),
DMA_CH_TRIGSRC_TCC0_OVF_gc = (0x40<<0),
DMA_CH_TRIGSRC_TCC0_ERR_gc = (0x41<<0),
DMA_CH_TRIGSRC_TCC0_CCA_gc = (0x42<<0),
DMA_CH_TRIGSRC_TCC0_CCB_gc = (0x43<<0),
DMA_CH_TRIGSRC_TCC0_CCC_gc = (0x44<<0),
DMA_CH_TRIGSRC_TCC0_CCD_gc = (0x45<<0),
DMA_CH_TRIGSRC_TCC1_OVF_gc = (0x46<<0),
DMA_CH_TRIGSRC_TCC1_ERR_gc = (0x47<<0),
DMA_CH_TRIGSRC_TCC1_CCA_gc = (0x48<<0),
DMA_CH_TRIGSRC_TCC1_CCB_gc = (0x49<<0),
DMA_CH_TRIGSRC_SPIC_gc = (0x4A<<0),
DMA_CH_TRIGSRC_USARTC0_RXC_gc = (0x4B<<0),
DMA_CH_TRIGSRC_USARTC0_DRE_gc = (0x4C<<0),
DMA_CH_TRIGSRC_USARTC1_RXC_gc = (0x4E<<0),
DMA_CH_TRIGSRC_USARTC1_DRE_gc = (0x4F<<0),
DMA_CH_TRIGSRC_TCD0_OVF_gc = (0x60<<0),
DMA_CH_TRIGSRC_TCD0_ERR_gc = (0x61<<0),
DMA_CH_TRIGSRC_TCD0_CCA_gc = (0x62<<0),
DMA_CH_TRIGSRC_TCD0_CCB_gc = (0x63<<0),
DMA_CH_TRIGSRC_TCD0_CCC_gc = (0x64<<0),
DMA_CH_TRIGSRC_TCD0_CCD_gc = (0x65<<0),
DMA_CH_TRIGSRC_TCD1_OVF_gc = (0x66<<0),
DMA_CH_TRIGSRC_TCD1_ERR_gc = (0x67<<0),
DMA_CH_TRIGSRC_TCD1_CCA_gc = (0x68<<0),
DMA_CH_TRIGSRC_TCD1_CCB_gc = (0x69<<0),
DMA_CH_TRIGSRC_SPID_gc = (0x6A<<0),
DMA_CH_TRIGSRC_USARTD0_RXC_gc = (0x6B<<0),
DMA_CH_TRIGSRC_USARTD0_DRE_gc = (0x6C<<0),
DMA_CH_TRIGSRC_USARTD1_RXC_gc = (0x6E<<0),
DMA_CH_TRIGSRC_USARTD1_DRE_gc = (0x6F<<0),
DMA_CH_TRIGSRC_TCE0_OVF_gc = (0x80<<0),
DMA_CH_TRIGSRC_TCE0_ERR_gc = (0x81<<0),
DMA_CH_TRIGSRC_TCE0_CCA_gc = (0x82<<0),
DMA_CH_TRIGSRC_TCE0_CCB_gc = (0x83<<0),
DMA_CH_TRIGSRC_TCE0_CCC_gc = (0x84<<0),
DMA_CH_TRIGSRC_TCE0_CCD_gc = (0x85<<0),
DMA_CH_TRIGSRC_TCE1_OVF_gc = (0x86<<0),
DMA_CH_TRIGSRC_TCE1_ERR_gc = (0x87<<0),
DMA_CH_TRIGSRC_TCE1_CCA_gc = (0x88<<0),
DMA_CH_TRIGSRC_TCE1_CCB_gc = (0x89<<0),
DMA_CH_TRIGSRC_SPIE_gc = (0x8A<<0),
DMA_CH_TRIGSRC_USARTE0_RXC_gc = (0x8B<<0),
DMA_CH_TRIGSRC_USARTE0_DRE_gc = (0x8C<<0),
DMA_CH_TRIGSRC_USARTE1_RXC_gc = (0x8E<<0),
DMA_CH_TRIGSRC_USARTE1_DRE_gc = (0x8F<<0),
DMA_CH_TRIGSRC_TCF0_OVF_gc = (0xA0<<0),
DMA_CH_TRIGSRC_TCF0_ERR_gc = (0xA1<<0),
DMA_CH_TRIGSRC_TCF0_CCA_gc = (0xA2<<0),
DMA_CH_TRIGSRC_TCF0_CCB_gc = (0xA3<<0),
DMA_CH_TRIGSRC_TCF0_CCC_gc = (0xA4<<0),
DMA_CH_TRIGSRC_TCF0_CCD_gc = (0xA5<<0),
DMA_CH_TRIGSRC_TCF1_OVF_gc = (0xA6<<0),
DMA_CH_TRIGSRC_TCF1_ERR_gc = (0xA7<<0),
DMA_CH_TRIGSRC_TCF1_CCA_gc = (0xA8<<0),
DMA_CH_TRIGSRC_TCF1_CCB_gc = (0xA9<<0),
DMA_CH_TRIGSRC_SPIF_gc = (0xAA<<0),
DMA_CH_TRIGSRC_USARTF0_RXC_gc = (0xAB<<0),
DMA_CH_TRIGSRC_USARTF0_DRE_gc = (0xAC<<0),
DMA_CH_TRIGSRC_USARTF1_RXC_gc = (0xAE<<0),
DMA_CH_TRIGSRC_USARTF1_DRE_gc = (0xAF<<0),
DMA_CH_TRIGSRC_OFF_gc = (0x00<<0),
DMA_CH_TRIGSRC_EVSYS_CH0_gc = (0x01<<0),
DMA_CH_TRIGSRC_EVSYS_CH1_gc = (0x02<<0),
DMA_CH_TRIGSRC_EVSYS_CH2_gc = (0x03<<0),
DMA_CH_TRIGSRC_ADCA_CH0_gc = (0x10<<0),
DMA_CH_TRIGSRC_ADCA_CH1_gc = (0x11<<0),
DMA_CH_TRIGSRC_ADCA_CH2_gc = (0x12<<0),
DMA_CH_TRIGSRC_ADCA_CH3_gc = (0x13<<0),
DMA_CH_TRIGSRC_ADCA_CH4_gc = (0x14<<0),
DMA_CH_TRIGSRC_DACA_CH0_gc = (0x15<<0),
DMA_CH_TRIGSRC_DACA_CH1_gc = (0x16<<0),
DMA_CH_TRIGSRC_ADCB_CH0_gc = (0x20<<0),
DMA_CH_TRIGSRC_ADCB_CH1_gc = (0x21<<0),
DMA_CH_TRIGSRC_ADCB_CH2_gc = (0x22<<0),
DMA_CH_TRIGSRC_ADCB_CH3_gc = (0x23<<0),
DMA_CH_TRIGSRC_ADCB_CH4_gc = (0x24<<0),
DMA_CH_TRIGSRC_DACB_CH0_gc = (0x25<<0),
DMA_CH_TRIGSRC_DACB_CH1_gc = (0x26<<0),
DMA_CH_TRIGSRC_TCC0_OVF_gc = (0x40<<0),
DMA_CH_TRIGSRC_TCC0_ERR_gc = (0x41<<0),
DMA_CH_TRIGSRC_TCC0_CCA_gc = (0x42<<0),
DMA_CH_TRIGSRC_TCC0_CCB_gc = (0x43<<0),
DMA_CH_TRIGSRC_TCC0_CCC_gc = (0x44<<0),
DMA_CH_TRIGSRC_TCC0_CCD_gc = (0x45<<0),
DMA_CH_TRIGSRC_TCC1_OVF_gc = (0x46<<0),
DMA_CH_TRIGSRC_TCC1_ERR_gc = (0x47<<0),
DMA_CH_TRIGSRC_TCC1_CCA_gc = (0x48<<0),
DMA_CH_TRIGSRC_TCC1_CCB_gc = (0x49<<0),
DMA_CH_TRIGSRC_SPIC_gc = (0x4A<<0),
DMA_CH_TRIGSRC_USARTC0_RXC_gc = (0x4B<<0),
DMA_CH_TRIGSRC_USARTC0_DRE_gc = (0x4C<<0),
DMA_CH_TRIGSRC_USARTC1_RXC_gc = (0x4E<<0),
DMA_CH_TRIGSRC_USARTC1_DRE_gc = (0x4F<<0),
DMA_CH_TRIGSRC_TCD0_OVF_gc = (0x60<<0),
DMA_CH_TRIGSRC_TCD0_ERR_gc = (0x61<<0),
DMA_CH_TRIGSRC_TCD0_CCA_gc = (0x62<<0),
DMA_CH_TRIGSRC_TCD0_CCB_gc = (0x63<<0),
DMA_CH_TRIGSRC_TCD0_CCC_gc = (0x64<<0),
DMA_CH_TRIGSRC_TCD0_CCD_gc = (0x65<<0),
DMA_CH_TRIGSRC_TCD1_OVF_gc = (0x66<<0),
DMA_CH_TRIGSRC_TCD1_ERR_gc = (0x67<<0),
DMA_CH_TRIGSRC_TCD1_CCA_gc = (0x68<<0),
DMA_CH_TRIGSRC_TCD1_CCB_gc = (0x69<<0),
DMA_CH_TRIGSRC_SPID_gc = (0x6A<<0),
DMA_CH_TRIGSRC_USARTD0_RXC_gc = (0x6B<<0),
DMA_CH_TRIGSRC_USARTD0_DRE_gc = (0x6C<<0),
DMA_CH_TRIGSRC_USARTD1_RXC_gc = (0x6E<<0),
DMA_CH_TRIGSRC_USARTD1_DRE_gc = (0x6F<<0),
DMA_CH_TRIGSRC_TCE0_OVF_gc = (0x80<<0),
DMA_CH_TRIGSRC_TCE0_ERR_gc = (0x81<<0),
DMA_CH_TRIGSRC_TCE0_CCA_gc = (0x82<<0),
DMA_CH_TRIGSRC_TCE0_CCB_gc = (0x83<<0),
DMA_CH_TRIGSRC_TCE0_CCC_gc = (0x84<<0),
DMA_CH_TRIGSRC_TCE0_CCD_gc = (0x85<<0),
DMA_CH_TRIGSRC_TCE1_OVF_gc = (0x86<<0),
DMA_CH_TRIGSRC_TCE1_ERR_gc = (0x87<<0),
DMA_CH_TRIGSRC_TCE1_CCA_gc = (0x88<<0),
DMA_CH_TRIGSRC_TCE1_CCB_gc = (0x89<<0),
DMA_CH_TRIGSRC_SPIE_gc = (0x8A<<0),
DMA_CH_TRIGSRC_USARTE0_RXC_gc = (0x8B<<0),
DMA_CH_TRIGSRC_USARTE0_DRE_gc = (0x8C<<0),
DMA_CH_TRIGSRC_USARTE1_RXC_gc = (0x8E<<0),
DMA_CH_TRIGSRC_USARTE1_DRE_gc = (0x8F<<0),
DMA_CH_TRIGSRC_TCF0_OVF_gc = (0xA0<<0),
DMA_CH_TRIGSRC_TCF0_ERR_gc = (0xA1<<0),
DMA_CH_TRIGSRC_TCF0_CCA_gc = (0xA2<<0),
DMA_CH_TRIGSRC_TCF0_CCB_gc = (0xA3<<0),
DMA_CH_TRIGSRC_TCF0_CCC_gc = (0xA4<<0),
DMA_CH_TRIGSRC_TCF0_CCD_gc = (0xA5<<0),
DMA_CH_TRIGSRC_TCF1_OVF_gc = (0xA6<<0),
DMA_CH_TRIGSRC_TCF1_ERR_gc = (0xA7<<0),
DMA_CH_TRIGSRC_TCF1_CCA_gc = (0xA8<<0),
DMA_CH_TRIGSRC_TCF1_CCB_gc = (0xA9<<0),
DMA_CH_TRIGSRC_SPIF_gc = (0xAA<<0),
DMA_CH_TRIGSRC_USARTF0_RXC_gc = (0xAB<<0),
DMA_CH_TRIGSRC_USARTF0_DRE_gc = (0xAC<<0),
DMA_CH_TRIGSRC_USARTF1_RXC_gc = (0xAE<<0),
DMA_CH_TRIGSRC_USARTF1_DRE_gc = (0xAF<<0)
} |
|
enum | DMA_DBUFMODE_enum {
DMA_DBUFMODE_DISABLED_gc = (0x00<<2),
DMA_DBUFMODE_CH01_gc = (0x01<<2),
DMA_DBUFMODE_CH23_gc = (0x02<<2),
DMA_DBUFMODE_CH01CH23_gc = (0x03<<2),
DMA_DBUFMODE_DISABLED_gc = (0x00<<2),
DMA_DBUFMODE_CH01_gc = (0x01<<2),
DMA_DBUFMODE_CH23_gc = (0x02<<2),
DMA_DBUFMODE_CH01CH23_gc = (0x03<<2),
DMA_DBUFMODE_DISABLED_gc = (0x00<<2),
DMA_DBUFMODE_CH01_gc = (0x01<<2),
DMA_DBUFMODE_CH23_gc = (0x02<<2),
DMA_DBUFMODE_CH01CH23_gc = (0x03<<2),
DMA_DBUFMODE_DISABLED_gc = (0x00<<2),
DMA_DBUFMODE_CH01_gc = (0x01<<2),
DMA_DBUFMODE_CH23_gc = (0x02<<2),
DMA_DBUFMODE_CH01CH23_gc = (0x03<<2),
DMA_DBUFMODE_DISABLED_gc = (0x00<<2),
DMA_DBUFMODE_CH01_gc = (0x01<<2),
DMA_DBUFMODE_CH23_gc = (0x02<<2),
DMA_DBUFMODE_CH01CH23_gc = (0x03<<2),
DMA_DBUFMODE_DISABLED_gc = (0x00<<2),
DMA_DBUFMODE_CH01_gc = (0x01<<2),
DMA_DBUFMODE_CH23_gc = (0x02<<2),
DMA_DBUFMODE_CH01CH23_gc = (0x03<<2),
DMA_DBUFMODE_DISABLED_gc = (0x00<<2),
DMA_DBUFMODE_CH01_gc = (0x01<<2),
DMA_DBUFMODE_CH23_gc = (0x02<<2),
DMA_DBUFMODE_CH01CH23_gc = (0x03<<2),
DMA_DBUFMODE_DISABLED_gc = (0x00<<2),
DMA_DBUFMODE_CH01_gc = (0x01<<2),
DMA_DBUFMODE_CH23_gc = (0x02<<2),
DMA_DBUFMODE_CH01CH23_gc = (0x03<<2),
DMA_DBUFMODE_DISABLED_gc = (0x00<<2),
DMA_DBUFMODE_CH01_gc = (0x01<<2),
DMA_DBUFMODE_CH23_gc = (0x02<<2),
DMA_DBUFMODE_CH01CH23_gc = (0x03<<2)
} |
|
enum | DMA_PRIMODE_enum {
DMA_PRIMODE_RR0123_gc = (0x00<<0),
DMA_PRIMODE_CH0RR123_gc = (0x01<<0),
DMA_PRIMODE_CH01RR23_gc = (0x02<<0),
DMA_PRIMODE_CH0123_gc = (0x03<<0),
DMA_PRIMODE_RR0123_gc = (0x00<<0),
DMA_PRIMODE_CH0RR123_gc = (0x01<<0),
DMA_PRIMODE_CH01RR23_gc = (0x02<<0),
DMA_PRIMODE_CH0123_gc = (0x03<<0),
DMA_PRIMODE_RR0123_gc = (0x00<<0),
DMA_PRIMODE_CH0RR123_gc = (0x01<<0),
DMA_PRIMODE_CH01RR23_gc = (0x02<<0),
DMA_PRIMODE_CH0123_gc = (0x03<<0),
DMA_PRIMODE_RR0123_gc = (0x00<<0),
DMA_PRIMODE_CH0RR123_gc = (0x01<<0),
DMA_PRIMODE_CH01RR23_gc = (0x02<<0),
DMA_PRIMODE_CH0123_gc = (0x03<<0),
DMA_PRIMODE_RR0123_gc = (0x00<<0),
DMA_PRIMODE_CH0RR123_gc = (0x01<<0),
DMA_PRIMODE_CH01RR23_gc = (0x02<<0),
DMA_PRIMODE_CH0123_gc = (0x03<<0),
DMA_PRIMODE_RR0123_gc = (0x00<<0),
DMA_PRIMODE_CH0RR123_gc = (0x01<<0),
DMA_PRIMODE_CH01RR23_gc = (0x02<<0),
DMA_PRIMODE_CH0123_gc = (0x03<<0),
DMA_PRIMODE_RR0123_gc = (0x00<<0),
DMA_PRIMODE_CH0RR123_gc = (0x01<<0),
DMA_PRIMODE_CH01RR23_gc = (0x02<<0),
DMA_PRIMODE_CH0123_gc = (0x03<<0),
DMA_PRIMODE_RR0123_gc = (0x00<<0),
DMA_PRIMODE_CH0RR123_gc = (0x01<<0),
DMA_PRIMODE_CH01RR23_gc = (0x02<<0),
DMA_PRIMODE_CH0123_gc = (0x03<<0),
DMA_PRIMODE_RR0123_gc = (0x00<<0),
DMA_PRIMODE_CH0RR123_gc = (0x01<<0),
DMA_PRIMODE_CH01RR23_gc = (0x02<<0),
DMA_PRIMODE_CH0123_gc = (0x03<<0)
} |
|
enum | DMA_CH_ERRINTLVL_enum {
DMA_CH_ERRINTLVL_OFF_gc = (0x00<<2),
DMA_CH_ERRINTLVL_LO_gc = (0x01<<2),
DMA_CH_ERRINTLVL_MED_gc = (0x02<<2),
DMA_CH_ERRINTLVL_HI_gc = (0x03<<2),
DMA_CH_ERRINTLVL_OFF_gc = (0x00<<2),
DMA_CH_ERRINTLVL_LO_gc = (0x01<<2),
DMA_CH_ERRINTLVL_MED_gc = (0x02<<2),
DMA_CH_ERRINTLVL_HI_gc = (0x03<<2),
DMA_CH_ERRINTLVL_OFF_gc = (0x00<<2),
DMA_CH_ERRINTLVL_LO_gc = (0x01<<2),
DMA_CH_ERRINTLVL_MED_gc = (0x02<<2),
DMA_CH_ERRINTLVL_HI_gc = (0x03<<2),
DMA_CH_ERRINTLVL_OFF_gc = (0x00<<2),
DMA_CH_ERRINTLVL_LO_gc = (0x01<<2),
DMA_CH_ERRINTLVL_MED_gc = (0x02<<2),
DMA_CH_ERRINTLVL_HI_gc = (0x03<<2),
DMA_CH_ERRINTLVL_OFF_gc = (0x00<<2),
DMA_CH_ERRINTLVL_LO_gc = (0x01<<2),
DMA_CH_ERRINTLVL_MED_gc = (0x02<<2),
DMA_CH_ERRINTLVL_HI_gc = (0x03<<2),
DMA_CH_ERRINTLVL_OFF_gc = (0x00<<2),
DMA_CH_ERRINTLVL_LO_gc = (0x01<<2),
DMA_CH_ERRINTLVL_MED_gc = (0x02<<2),
DMA_CH_ERRINTLVL_HI_gc = (0x03<<2),
DMA_CH_ERRINTLVL_OFF_gc = (0x00<<2),
DMA_CH_ERRINTLVL_LO_gc = (0x01<<2),
DMA_CH_ERRINTLVL_MED_gc = (0x02<<2),
DMA_CH_ERRINTLVL_HI_gc = (0x03<<2),
DMA_CH_ERRINTLVL_OFF_gc = (0x00<<2),
DMA_CH_ERRINTLVL_LO_gc = (0x01<<2),
DMA_CH_ERRINTLVL_MED_gc = (0x02<<2),
DMA_CH_ERRINTLVL_HI_gc = (0x03<<2),
DMA_CH_ERRINTLVL_OFF_gc = (0x00<<2),
DMA_CH_ERRINTLVL_LO_gc = (0x01<<2),
DMA_CH_ERRINTLVL_MED_gc = (0x02<<2),
DMA_CH_ERRINTLVL_HI_gc = (0x03<<2)
} |
|
enum | DMA_CH_TRNINTLVL_enum {
DMA_CH_TRNINTLVL_OFF_gc = (0x00<<0),
DMA_CH_TRNINTLVL_LO_gc = (0x01<<0),
DMA_CH_TRNINTLVL_MED_gc = (0x02<<0),
DMA_CH_TRNINTLVL_HI_gc = (0x03<<0),
DMA_CH_TRNINTLVL_OFF_gc = (0x00<<0),
DMA_CH_TRNINTLVL_LO_gc = (0x01<<0),
DMA_CH_TRNINTLVL_MED_gc = (0x02<<0),
DMA_CH_TRNINTLVL_HI_gc = (0x03<<0),
DMA_CH_TRNINTLVL_OFF_gc = (0x00<<0),
DMA_CH_TRNINTLVL_LO_gc = (0x01<<0),
DMA_CH_TRNINTLVL_MED_gc = (0x02<<0),
DMA_CH_TRNINTLVL_HI_gc = (0x03<<0),
DMA_CH_TRNINTLVL_OFF_gc = (0x00<<0),
DMA_CH_TRNINTLVL_LO_gc = (0x01<<0),
DMA_CH_TRNINTLVL_MED_gc = (0x02<<0),
DMA_CH_TRNINTLVL_HI_gc = (0x03<<0),
DMA_CH_TRNINTLVL_OFF_gc = (0x00<<0),
DMA_CH_TRNINTLVL_LO_gc = (0x01<<0),
DMA_CH_TRNINTLVL_MED_gc = (0x02<<0),
DMA_CH_TRNINTLVL_HI_gc = (0x03<<0),
DMA_CH_TRNINTLVL_OFF_gc = (0x00<<0),
DMA_CH_TRNINTLVL_LO_gc = (0x01<<0),
DMA_CH_TRNINTLVL_MED_gc = (0x02<<0),
DMA_CH_TRNINTLVL_HI_gc = (0x03<<0),
DMA_CH_TRNINTLVL_OFF_gc = (0x00<<0),
DMA_CH_TRNINTLVL_LO_gc = (0x01<<0),
DMA_CH_TRNINTLVL_MED_gc = (0x02<<0),
DMA_CH_TRNINTLVL_HI_gc = (0x03<<0),
DMA_CH_TRNINTLVL_OFF_gc = (0x00<<0),
DMA_CH_TRNINTLVL_LO_gc = (0x01<<0),
DMA_CH_TRNINTLVL_MED_gc = (0x02<<0),
DMA_CH_TRNINTLVL_HI_gc = (0x03<<0),
DMA_CH_TRNINTLVL_OFF_gc = (0x00<<0),
DMA_CH_TRNINTLVL_LO_gc = (0x01<<0),
DMA_CH_TRNINTLVL_MED_gc = (0x02<<0),
DMA_CH_TRNINTLVL_HI_gc = (0x03<<0)
} |
|
enum | EVSYS_QDIRM_enum {
EVSYS_QDIRM_00_gc = (0x00<<5),
EVSYS_QDIRM_01_gc = (0x01<<5),
EVSYS_QDIRM_10_gc = (0x02<<5),
EVSYS_QDIRM_11_gc = (0x03<<5),
EVSYS_QDIRM_00_gc = (0x00<<5),
EVSYS_QDIRM_01_gc = (0x01<<5),
EVSYS_QDIRM_10_gc = (0x02<<5),
EVSYS_QDIRM_11_gc = (0x03<<5),
EVSYS_QDIRM_00_gc = (0x00<<5),
EVSYS_QDIRM_01_gc = (0x01<<5),
EVSYS_QDIRM_10_gc = (0x02<<5),
EVSYS_QDIRM_11_gc = (0x03<<5),
EVSYS_QDIRM_00_gc = (0x00<<5),
EVSYS_QDIRM_01_gc = (0x01<<5),
EVSYS_QDIRM_10_gc = (0x02<<5),
EVSYS_QDIRM_11_gc = (0x03<<5),
EVSYS_QDIRM_00_gc = (0x00<<5),
EVSYS_QDIRM_01_gc = (0x01<<5),
EVSYS_QDIRM_10_gc = (0x02<<5),
EVSYS_QDIRM_11_gc = (0x03<<5),
EVSYS_QDIRM_00_gc = (0x00<<5),
EVSYS_QDIRM_01_gc = (0x01<<5),
EVSYS_QDIRM_10_gc = (0x02<<5),
EVSYS_QDIRM_11_gc = (0x03<<5),
EVSYS_QDIRM_00_gc = (0x00<<5),
EVSYS_QDIRM_01_gc = (0x01<<5),
EVSYS_QDIRM_10_gc = (0x02<<5),
EVSYS_QDIRM_11_gc = (0x03<<5),
EVSYS_QDIRM_00_gc = (0x00<<5),
EVSYS_QDIRM_01_gc = (0x01<<5),
EVSYS_QDIRM_10_gc = (0x02<<5),
EVSYS_QDIRM_11_gc = (0x03<<5),
EVSYS_QDIRM_00_gc = (0x00<<5),
EVSYS_QDIRM_01_gc = (0x01<<5),
EVSYS_QDIRM_10_gc = (0x02<<5),
EVSYS_QDIRM_11_gc = (0x03<<5),
EVSYS_QDIRM_00_gc = (0x00<<5),
EVSYS_QDIRM_01_gc = (0x01<<5),
EVSYS_QDIRM_10_gc = (0x02<<5),
EVSYS_QDIRM_11_gc = (0x03<<5),
EVSYS_QDIRM_00_gc = (0x00<<5),
EVSYS_QDIRM_01_gc = (0x01<<5),
EVSYS_QDIRM_10_gc = (0x02<<5),
EVSYS_QDIRM_11_gc = (0x03<<5),
EVSYS_QDIRM_00_gc = (0x00<<5),
EVSYS_QDIRM_01_gc = (0x01<<5),
EVSYS_QDIRM_10_gc = (0x02<<5),
EVSYS_QDIRM_11_gc = (0x03<<5),
EVSYS_QDIRM_00_gc = (0x00<<5),
EVSYS_QDIRM_01_gc = (0x01<<5),
EVSYS_QDIRM_10_gc = (0x02<<5),
EVSYS_QDIRM_11_gc = (0x03<<5),
EVSYS_QDIRM_00_gc = (0x00<<5),
EVSYS_QDIRM_01_gc = (0x01<<5),
EVSYS_QDIRM_10_gc = (0x02<<5),
EVSYS_QDIRM_11_gc = (0x03<<5),
EVSYS_QDIRM_00_gc = (0x00<<5),
EVSYS_QDIRM_01_gc = (0x01<<5),
EVSYS_QDIRM_10_gc = (0x02<<5),
EVSYS_QDIRM_11_gc = (0x03<<5)
} |
|
enum | EVSYS_DIGFILT_enum {
EVSYS_DIGFILT_1SAMPLE_gc = (0x00<<0),
EVSYS_DIGFILT_2SAMPLES_gc = (0x01<<0),
EVSYS_DIGFILT_3SAMPLES_gc = (0x02<<0),
EVSYS_DIGFILT_4SAMPLES_gc = (0x03<<0),
EVSYS_DIGFILT_5SAMPLES_gc = (0x04<<0),
EVSYS_DIGFILT_6SAMPLES_gc = (0x05<<0),
EVSYS_DIGFILT_7SAMPLES_gc = (0x06<<0),
EVSYS_DIGFILT_8SAMPLES_gc = (0x07<<0),
EVSYS_DIGFILT_1SAMPLE_gc = (0x00<<0),
EVSYS_DIGFILT_2SAMPLES_gc = (0x01<<0),
EVSYS_DIGFILT_3SAMPLES_gc = (0x02<<0),
EVSYS_DIGFILT_4SAMPLES_gc = (0x03<<0),
EVSYS_DIGFILT_5SAMPLES_gc = (0x04<<0),
EVSYS_DIGFILT_6SAMPLES_gc = (0x05<<0),
EVSYS_DIGFILT_7SAMPLES_gc = (0x06<<0),
EVSYS_DIGFILT_8SAMPLES_gc = (0x07<<0),
EVSYS_DIGFILT_1SAMPLE_gc = (0x00<<0),
EVSYS_DIGFILT_2SAMPLES_gc = (0x01<<0),
EVSYS_DIGFILT_3SAMPLES_gc = (0x02<<0),
EVSYS_DIGFILT_4SAMPLES_gc = (0x03<<0),
EVSYS_DIGFILT_5SAMPLES_gc = (0x04<<0),
EVSYS_DIGFILT_6SAMPLES_gc = (0x05<<0),
EVSYS_DIGFILT_7SAMPLES_gc = (0x06<<0),
EVSYS_DIGFILT_8SAMPLES_gc = (0x07<<0),
EVSYS_DIGFILT_1SAMPLE_gc = (0x00<<0),
EVSYS_DIGFILT_2SAMPLES_gc = (0x01<<0),
EVSYS_DIGFILT_3SAMPLES_gc = (0x02<<0),
EVSYS_DIGFILT_4SAMPLES_gc = (0x03<<0),
EVSYS_DIGFILT_5SAMPLES_gc = (0x04<<0),
EVSYS_DIGFILT_6SAMPLES_gc = (0x05<<0),
EVSYS_DIGFILT_7SAMPLES_gc = (0x06<<0),
EVSYS_DIGFILT_8SAMPLES_gc = (0x07<<0),
EVSYS_DIGFILT_1SAMPLE_gc = (0x00<<0),
EVSYS_DIGFILT_2SAMPLES_gc = (0x01<<0),
EVSYS_DIGFILT_3SAMPLES_gc = (0x02<<0),
EVSYS_DIGFILT_4SAMPLES_gc = (0x03<<0),
EVSYS_DIGFILT_5SAMPLES_gc = (0x04<<0),
EVSYS_DIGFILT_6SAMPLES_gc = (0x05<<0),
EVSYS_DIGFILT_7SAMPLES_gc = (0x06<<0),
EVSYS_DIGFILT_8SAMPLES_gc = (0x07<<0),
EVSYS_DIGFILT_1SAMPLE_gc = (0x00<<0),
EVSYS_DIGFILT_2SAMPLES_gc = (0x01<<0),
EVSYS_DIGFILT_3SAMPLES_gc = (0x02<<0),
EVSYS_DIGFILT_4SAMPLES_gc = (0x03<<0),
EVSYS_DIGFILT_5SAMPLES_gc = (0x04<<0),
EVSYS_DIGFILT_6SAMPLES_gc = (0x05<<0),
EVSYS_DIGFILT_7SAMPLES_gc = (0x06<<0),
EVSYS_DIGFILT_8SAMPLES_gc = (0x07<<0),
EVSYS_DIGFILT_1SAMPLE_gc = (0x00<<0),
EVSYS_DIGFILT_2SAMPLES_gc = (0x01<<0),
EVSYS_DIGFILT_3SAMPLES_gc = (0x02<<0),
EVSYS_DIGFILT_4SAMPLES_gc = (0x03<<0),
EVSYS_DIGFILT_5SAMPLES_gc = (0x04<<0),
EVSYS_DIGFILT_6SAMPLES_gc = (0x05<<0),
EVSYS_DIGFILT_7SAMPLES_gc = (0x06<<0),
EVSYS_DIGFILT_8SAMPLES_gc = (0x07<<0),
EVSYS_DIGFILT_1SAMPLE_gc = (0x00<<0),
EVSYS_DIGFILT_2SAMPLES_gc = (0x01<<0),
EVSYS_DIGFILT_3SAMPLES_gc = (0x02<<0),
EVSYS_DIGFILT_4SAMPLES_gc = (0x03<<0),
EVSYS_DIGFILT_5SAMPLES_gc = (0x04<<0),
EVSYS_DIGFILT_6SAMPLES_gc = (0x05<<0),
EVSYS_DIGFILT_7SAMPLES_gc = (0x06<<0),
EVSYS_DIGFILT_8SAMPLES_gc = (0x07<<0),
EVSYS_DIGFILT_1SAMPLE_gc = (0x00<<0),
EVSYS_DIGFILT_2SAMPLES_gc = (0x01<<0),
EVSYS_DIGFILT_3SAMPLES_gc = (0x02<<0),
EVSYS_DIGFILT_4SAMPLES_gc = (0x03<<0),
EVSYS_DIGFILT_5SAMPLES_gc = (0x04<<0),
EVSYS_DIGFILT_6SAMPLES_gc = (0x05<<0),
EVSYS_DIGFILT_7SAMPLES_gc = (0x06<<0),
EVSYS_DIGFILT_8SAMPLES_gc = (0x07<<0),
EVSYS_DIGFILT_1SAMPLE_gc = (0x00<<0),
EVSYS_DIGFILT_2SAMPLES_gc = (0x01<<0),
EVSYS_DIGFILT_3SAMPLES_gc = (0x02<<0),
EVSYS_DIGFILT_4SAMPLES_gc = (0x03<<0),
EVSYS_DIGFILT_5SAMPLES_gc = (0x04<<0),
EVSYS_DIGFILT_6SAMPLES_gc = (0x05<<0),
EVSYS_DIGFILT_7SAMPLES_gc = (0x06<<0),
EVSYS_DIGFILT_8SAMPLES_gc = (0x07<<0),
EVSYS_DIGFILT_1SAMPLE_gc = (0x00<<0),
EVSYS_DIGFILT_2SAMPLES_gc = (0x01<<0),
EVSYS_DIGFILT_3SAMPLES_gc = (0x02<<0),
EVSYS_DIGFILT_4SAMPLES_gc = (0x03<<0),
EVSYS_DIGFILT_5SAMPLES_gc = (0x04<<0),
EVSYS_DIGFILT_6SAMPLES_gc = (0x05<<0),
EVSYS_DIGFILT_7SAMPLES_gc = (0x06<<0),
EVSYS_DIGFILT_8SAMPLES_gc = (0x07<<0),
EVSYS_DIGFILT_1SAMPLE_gc = (0x00<<0),
EVSYS_DIGFILT_2SAMPLES_gc = (0x01<<0),
EVSYS_DIGFILT_3SAMPLES_gc = (0x02<<0),
EVSYS_DIGFILT_4SAMPLES_gc = (0x03<<0),
EVSYS_DIGFILT_5SAMPLES_gc = (0x04<<0),
EVSYS_DIGFILT_6SAMPLES_gc = (0x05<<0),
EVSYS_DIGFILT_7SAMPLES_gc = (0x06<<0),
EVSYS_DIGFILT_8SAMPLES_gc = (0x07<<0),
EVSYS_DIGFILT_1SAMPLE_gc = (0x00<<0),
EVSYS_DIGFILT_2SAMPLES_gc = (0x01<<0),
EVSYS_DIGFILT_3SAMPLES_gc = (0x02<<0),
EVSYS_DIGFILT_4SAMPLES_gc = (0x03<<0),
EVSYS_DIGFILT_5SAMPLES_gc = (0x04<<0),
EVSYS_DIGFILT_6SAMPLES_gc = (0x05<<0),
EVSYS_DIGFILT_7SAMPLES_gc = (0x06<<0),
EVSYS_DIGFILT_8SAMPLES_gc = (0x07<<0),
EVSYS_DIGFILT_1SAMPLE_gc = (0x00<<0),
EVSYS_DIGFILT_2SAMPLES_gc = (0x01<<0),
EVSYS_DIGFILT_3SAMPLES_gc = (0x02<<0),
EVSYS_DIGFILT_4SAMPLES_gc = (0x03<<0),
EVSYS_DIGFILT_5SAMPLES_gc = (0x04<<0),
EVSYS_DIGFILT_6SAMPLES_gc = (0x05<<0),
EVSYS_DIGFILT_7SAMPLES_gc = (0x06<<0),
EVSYS_DIGFILT_8SAMPLES_gc = (0x07<<0),
EVSYS_DIGFILT_1SAMPLE_gc = (0x00<<0),
EVSYS_DIGFILT_2SAMPLES_gc = (0x01<<0),
EVSYS_DIGFILT_3SAMPLES_gc = (0x02<<0),
EVSYS_DIGFILT_4SAMPLES_gc = (0x03<<0),
EVSYS_DIGFILT_5SAMPLES_gc = (0x04<<0),
EVSYS_DIGFILT_6SAMPLES_gc = (0x05<<0),
EVSYS_DIGFILT_7SAMPLES_gc = (0x06<<0),
EVSYS_DIGFILT_8SAMPLES_gc = (0x07<<0)
} |
|
enum | EVSYS_CHMUX_enum {
EVSYS_CHMUX_OFF_gc = (0x00<<0),
EVSYS_CHMUX_RTC_OVF_gc = (0x08<<0),
EVSYS_CHMUX_RTC_CMP_gc = (0x09<<0),
EVSYS_CHMUX_ACA_CH0_gc = (0x10<<0),
EVSYS_CHMUX_ACA_CH1_gc = (0x11<<0),
EVSYS_CHMUX_ACA_WIN_gc = (0x12<<0),
EVSYS_CHMUX_ACB_CH0_gc = (0x13<<0),
EVSYS_CHMUX_ACB_CH1_gc = (0x14<<0),
EVSYS_CHMUX_ACB_WIN_gc = (0x15<<0),
EVSYS_CHMUX_ADCA_CH0_gc = (0x20<<0),
EVSYS_CHMUX_ADCA_CH1_gc = (0x21<<0),
EVSYS_CHMUX_ADCA_CH2_gc = (0x22<<0),
EVSYS_CHMUX_ADCA_CH3_gc = (0x23<<0),
EVSYS_CHMUX_ADCB_CH0_gc = (0x24<<0),
EVSYS_CHMUX_ADCB_CH1_gc = (0x25<<0),
EVSYS_CHMUX_ADCB_CH2_gc = (0x26<<0),
EVSYS_CHMUX_ADCB_CH3_gc = (0x27<<0),
EVSYS_CHMUX_PORTA_PIN0_gc = (0x50<<0),
EVSYS_CHMUX_PORTA_PIN1_gc = (0x51<<0),
EVSYS_CHMUX_PORTA_PIN2_gc = (0x52<<0),
EVSYS_CHMUX_PORTA_PIN3_gc = (0x53<<0),
EVSYS_CHMUX_PORTA_PIN4_gc = (0x54<<0),
EVSYS_CHMUX_PORTA_PIN5_gc = (0x55<<0),
EVSYS_CHMUX_PORTA_PIN6_gc = (0x56<<0),
EVSYS_CHMUX_PORTA_PIN7_gc = (0x57<<0),
EVSYS_CHMUX_PORTB_PIN0_gc = (0x58<<0),
EVSYS_CHMUX_PORTB_PIN1_gc = (0x59<<0),
EVSYS_CHMUX_PORTB_PIN2_gc = (0x5A<<0),
EVSYS_CHMUX_PORTB_PIN3_gc = (0x5B<<0),
EVSYS_CHMUX_PORTB_PIN4_gc = (0x5C<<0),
EVSYS_CHMUX_PORTB_PIN5_gc = (0x5D<<0),
EVSYS_CHMUX_PORTB_PIN6_gc = (0x5E<<0),
EVSYS_CHMUX_PORTB_PIN7_gc = (0x5F<<0),
EVSYS_CHMUX_PORTC_PIN0_gc = (0x60<<0),
EVSYS_CHMUX_PORTC_PIN1_gc = (0x61<<0),
EVSYS_CHMUX_PORTC_PIN2_gc = (0x62<<0),
EVSYS_CHMUX_PORTC_PIN3_gc = (0x63<<0),
EVSYS_CHMUX_PORTC_PIN4_gc = (0x64<<0),
EVSYS_CHMUX_PORTC_PIN5_gc = (0x65<<0),
EVSYS_CHMUX_PORTC_PIN6_gc = (0x66<<0),
EVSYS_CHMUX_PORTC_PIN7_gc = (0x67<<0),
EVSYS_CHMUX_PORTD_PIN0_gc = (0x68<<0),
EVSYS_CHMUX_PORTD_PIN1_gc = (0x69<<0),
EVSYS_CHMUX_PORTD_PIN2_gc = (0x6A<<0),
EVSYS_CHMUX_PORTD_PIN3_gc = (0x6B<<0),
EVSYS_CHMUX_PORTD_PIN4_gc = (0x6C<<0),
EVSYS_CHMUX_PORTD_PIN5_gc = (0x6D<<0),
EVSYS_CHMUX_PORTD_PIN6_gc = (0x6E<<0),
EVSYS_CHMUX_PORTD_PIN7_gc = (0x6F<<0),
EVSYS_CHMUX_PORTE_PIN0_gc = (0x70<<0),
EVSYS_CHMUX_PORTE_PIN1_gc = (0x71<<0),
EVSYS_CHMUX_PORTE_PIN2_gc = (0x72<<0),
EVSYS_CHMUX_PORTE_PIN3_gc = (0x73<<0),
EVSYS_CHMUX_PORTE_PIN4_gc = (0x74<<0),
EVSYS_CHMUX_PORTE_PIN5_gc = (0x75<<0),
EVSYS_CHMUX_PORTE_PIN6_gc = (0x76<<0),
EVSYS_CHMUX_PORTE_PIN7_gc = (0x77<<0),
EVSYS_CHMUX_PORTF_PIN0_gc = (0x78<<0),
EVSYS_CHMUX_PORTF_PIN1_gc = (0x79<<0),
EVSYS_CHMUX_PORTF_PIN2_gc = (0x7A<<0),
EVSYS_CHMUX_PORTF_PIN3_gc = (0x7B<<0),
EVSYS_CHMUX_PORTF_PIN4_gc = (0x7C<<0),
EVSYS_CHMUX_PORTF_PIN5_gc = (0x7D<<0),
EVSYS_CHMUX_PORTF_PIN6_gc = (0x7E<<0),
EVSYS_CHMUX_PORTF_PIN7_gc = (0x7F<<0),
EVSYS_CHMUX_PRESCALER_1_gc = (0x80<<0),
EVSYS_CHMUX_PRESCALER_2_gc = (0x81<<0),
EVSYS_CHMUX_PRESCALER_4_gc = (0x82<<0),
EVSYS_CHMUX_PRESCALER_8_gc = (0x83<<0),
EVSYS_CHMUX_PRESCALER_16_gc = (0x84<<0),
EVSYS_CHMUX_PRESCALER_32_gc = (0x85<<0),
EVSYS_CHMUX_PRESCALER_64_gc = (0x86<<0),
EVSYS_CHMUX_PRESCALER_128_gc = (0x87<<0),
EVSYS_CHMUX_PRESCALER_256_gc = (0x88<<0),
EVSYS_CHMUX_PRESCALER_512_gc = (0x89<<0),
EVSYS_CHMUX_PRESCALER_1024_gc = (0x8A<<0),
EVSYS_CHMUX_PRESCALER_2048_gc = (0x8B<<0),
EVSYS_CHMUX_PRESCALER_4096_gc = (0x8C<<0),
EVSYS_CHMUX_PRESCALER_8192_gc = (0x8D<<0),
EVSYS_CHMUX_PRESCALER_16384_gc = (0x8E<<0),
EVSYS_CHMUX_PRESCALER_32768_gc = (0x8F<<0),
EVSYS_CHMUX_TCC0_OVF_gc = (0xC0<<0),
EVSYS_CHMUX_TCC0_ERR_gc = (0xC1<<0),
EVSYS_CHMUX_TCC0_CCA_gc = (0xC4<<0),
EVSYS_CHMUX_TCC0_CCB_gc = (0xC5<<0),
EVSYS_CHMUX_TCC0_CCC_gc = (0xC6<<0),
EVSYS_CHMUX_TCC0_CCD_gc = (0xC7<<0),
EVSYS_CHMUX_TCC1_OVF_gc = (0xC8<<0),
EVSYS_CHMUX_TCC1_ERR_gc = (0xC9<<0),
EVSYS_CHMUX_TCC1_CCA_gc = (0xCC<<0),
EVSYS_CHMUX_TCC1_CCB_gc = (0xCD<<0),
EVSYS_CHMUX_TCD0_OVF_gc = (0xD0<<0),
EVSYS_CHMUX_TCD0_ERR_gc = (0xD1<<0),
EVSYS_CHMUX_TCD0_CCA_gc = (0xD4<<0),
EVSYS_CHMUX_TCD0_CCB_gc = (0xD5<<0),
EVSYS_CHMUX_TCD0_CCC_gc = (0xD6<<0),
EVSYS_CHMUX_TCD0_CCD_gc = (0xD7<<0),
EVSYS_CHMUX_TCD1_OVF_gc = (0xD8<<0),
EVSYS_CHMUX_TCD1_ERR_gc = (0xD9<<0),
EVSYS_CHMUX_TCD1_CCA_gc = (0xDC<<0),
EVSYS_CHMUX_TCD1_CCB_gc = (0xDD<<0),
EVSYS_CHMUX_TCE0_OVF_gc = (0xE0<<0),
EVSYS_CHMUX_TCE0_ERR_gc = (0xE1<<0),
EVSYS_CHMUX_TCE0_CCA_gc = (0xE4<<0),
EVSYS_CHMUX_TCE0_CCB_gc = (0xE5<<0),
EVSYS_CHMUX_TCE0_CCC_gc = (0xE6<<0),
EVSYS_CHMUX_TCE0_CCD_gc = (0xE7<<0),
EVSYS_CHMUX_TCE1_OVF_gc = (0xE8<<0),
EVSYS_CHMUX_TCE1_ERR_gc = (0xE9<<0),
EVSYS_CHMUX_TCE1_CCA_gc = (0xEC<<0),
EVSYS_CHMUX_TCE1_CCB_gc = (0xED<<0),
EVSYS_CHMUX_TCF0_OVF_gc = (0xF0<<0),
EVSYS_CHMUX_TCF0_ERR_gc = (0xF1<<0),
EVSYS_CHMUX_TCF0_CCA_gc = (0xF4<<0),
EVSYS_CHMUX_TCF0_CCB_gc = (0xF5<<0),
EVSYS_CHMUX_TCF0_CCC_gc = (0xF6<<0),
EVSYS_CHMUX_TCF0_CCD_gc = (0xF7<<0),
EVSYS_CHMUX_TCF1_OVF_gc = (0xF8<<0),
EVSYS_CHMUX_TCF1_ERR_gc = (0xF9<<0),
EVSYS_CHMUX_TCF1_CCA_gc = (0xFC<<0),
EVSYS_CHMUX_TCF1_CCB_gc = (0xFD<<0),
EVSYS_CHMUX_OFF_gc = (0x00<<0),
EVSYS_CHMUX_RTC_OVF_gc = (0x08<<0),
EVSYS_CHMUX_RTC_CMP_gc = (0x09<<0),
EVSYS_CHMUX_ACA_CH0_gc = (0x10<<0),
EVSYS_CHMUX_ACA_CH1_gc = (0x11<<0),
EVSYS_CHMUX_ACA_WIN_gc = (0x12<<0),
EVSYS_CHMUX_ACB_CH0_gc = (0x13<<0),
EVSYS_CHMUX_ACB_CH1_gc = (0x14<<0),
EVSYS_CHMUX_ACB_WIN_gc = (0x15<<0),
EVSYS_CHMUX_ADCA_CH0_gc = (0x20<<0),
EVSYS_CHMUX_ADCA_CH1_gc = (0x21<<0),
EVSYS_CHMUX_ADCA_CH2_gc = (0x22<<0),
EVSYS_CHMUX_ADCA_CH3_gc = (0x23<<0),
EVSYS_CHMUX_ADCB_CH0_gc = (0x24<<0),
EVSYS_CHMUX_ADCB_CH1_gc = (0x25<<0),
EVSYS_CHMUX_ADCB_CH2_gc = (0x26<<0),
EVSYS_CHMUX_ADCB_CH3_gc = (0x27<<0),
EVSYS_CHMUX_PORTA_PIN0_gc = (0x50<<0),
EVSYS_CHMUX_PORTA_PIN1_gc = (0x51<<0),
EVSYS_CHMUX_PORTA_PIN2_gc = (0x52<<0),
EVSYS_CHMUX_PORTA_PIN3_gc = (0x53<<0),
EVSYS_CHMUX_PORTA_PIN4_gc = (0x54<<0),
EVSYS_CHMUX_PORTA_PIN5_gc = (0x55<<0),
EVSYS_CHMUX_PORTA_PIN6_gc = (0x56<<0),
EVSYS_CHMUX_PORTA_PIN7_gc = (0x57<<0),
EVSYS_CHMUX_PORTB_PIN0_gc = (0x58<<0),
EVSYS_CHMUX_PORTB_PIN1_gc = (0x59<<0),
EVSYS_CHMUX_PORTB_PIN2_gc = (0x5A<<0),
EVSYS_CHMUX_PORTB_PIN3_gc = (0x5B<<0),
EVSYS_CHMUX_PORTB_PIN4_gc = (0x5C<<0),
EVSYS_CHMUX_PORTB_PIN5_gc = (0x5D<<0),
EVSYS_CHMUX_PORTB_PIN6_gc = (0x5E<<0),
EVSYS_CHMUX_PORTB_PIN7_gc = (0x5F<<0),
EVSYS_CHMUX_PORTC_PIN0_gc = (0x60<<0),
EVSYS_CHMUX_PORTC_PIN1_gc = (0x61<<0),
EVSYS_CHMUX_PORTC_PIN2_gc = (0x62<<0),
EVSYS_CHMUX_PORTC_PIN3_gc = (0x63<<0),
EVSYS_CHMUX_PORTC_PIN4_gc = (0x64<<0),
EVSYS_CHMUX_PORTC_PIN5_gc = (0x65<<0),
EVSYS_CHMUX_PORTC_PIN6_gc = (0x66<<0),
EVSYS_CHMUX_PORTC_PIN7_gc = (0x67<<0),
EVSYS_CHMUX_PORTD_PIN0_gc = (0x68<<0),
EVSYS_CHMUX_PORTD_PIN1_gc = (0x69<<0),
EVSYS_CHMUX_PORTD_PIN2_gc = (0x6A<<0),
EVSYS_CHMUX_PORTD_PIN3_gc = (0x6B<<0),
EVSYS_CHMUX_PORTD_PIN4_gc = (0x6C<<0),
EVSYS_CHMUX_PORTD_PIN5_gc = (0x6D<<0),
EVSYS_CHMUX_PORTD_PIN6_gc = (0x6E<<0),
EVSYS_CHMUX_PORTD_PIN7_gc = (0x6F<<0),
EVSYS_CHMUX_PORTE_PIN0_gc = (0x70<<0),
EVSYS_CHMUX_PORTE_PIN1_gc = (0x71<<0),
EVSYS_CHMUX_PORTE_PIN2_gc = (0x72<<0),
EVSYS_CHMUX_PORTE_PIN3_gc = (0x73<<0),
EVSYS_CHMUX_PORTE_PIN4_gc = (0x74<<0),
EVSYS_CHMUX_PORTE_PIN5_gc = (0x75<<0),
EVSYS_CHMUX_PORTE_PIN6_gc = (0x76<<0),
EVSYS_CHMUX_PORTE_PIN7_gc = (0x77<<0),
EVSYS_CHMUX_PORTF_PIN0_gc = (0x78<<0),
EVSYS_CHMUX_PORTF_PIN1_gc = (0x79<<0),
EVSYS_CHMUX_PORTF_PIN2_gc = (0x7A<<0),
EVSYS_CHMUX_PORTF_PIN3_gc = (0x7B<<0),
EVSYS_CHMUX_PORTF_PIN4_gc = (0x7C<<0),
EVSYS_CHMUX_PORTF_PIN5_gc = (0x7D<<0),
EVSYS_CHMUX_PORTF_PIN6_gc = (0x7E<<0),
EVSYS_CHMUX_PORTF_PIN7_gc = (0x7F<<0),
EVSYS_CHMUX_PRESCALER_1_gc = (0x80<<0),
EVSYS_CHMUX_PRESCALER_2_gc = (0x81<<0),
EVSYS_CHMUX_PRESCALER_4_gc = (0x82<<0),
EVSYS_CHMUX_PRESCALER_8_gc = (0x83<<0),
EVSYS_CHMUX_PRESCALER_16_gc = (0x84<<0),
EVSYS_CHMUX_PRESCALER_32_gc = (0x85<<0),
EVSYS_CHMUX_PRESCALER_64_gc = (0x86<<0),
EVSYS_CHMUX_PRESCALER_128_gc = (0x87<<0),
EVSYS_CHMUX_PRESCALER_256_gc = (0x88<<0),
EVSYS_CHMUX_PRESCALER_512_gc = (0x89<<0),
EVSYS_CHMUX_PRESCALER_1024_gc = (0x8A<<0),
EVSYS_CHMUX_PRESCALER_2048_gc = (0x8B<<0),
EVSYS_CHMUX_PRESCALER_4096_gc = (0x8C<<0),
EVSYS_CHMUX_PRESCALER_8192_gc = (0x8D<<0),
EVSYS_CHMUX_PRESCALER_16384_gc = (0x8E<<0),
EVSYS_CHMUX_PRESCALER_32768_gc = (0x8F<<0),
EVSYS_CHMUX_TCC0_OVF_gc = (0xC0<<0),
EVSYS_CHMUX_TCC0_ERR_gc = (0xC1<<0),
EVSYS_CHMUX_TCC0_CCA_gc = (0xC4<<0),
EVSYS_CHMUX_TCC0_CCB_gc = (0xC5<<0),
EVSYS_CHMUX_TCC0_CCC_gc = (0xC6<<0),
EVSYS_CHMUX_TCC0_CCD_gc = (0xC7<<0),
EVSYS_CHMUX_TCC1_OVF_gc = (0xC8<<0),
EVSYS_CHMUX_TCC1_ERR_gc = (0xC9<<0),
EVSYS_CHMUX_TCC1_CCA_gc = (0xCC<<0),
EVSYS_CHMUX_TCC1_CCB_gc = (0xCD<<0),
EVSYS_CHMUX_TCD0_OVF_gc = (0xD0<<0),
EVSYS_CHMUX_TCD0_ERR_gc = (0xD1<<0),
EVSYS_CHMUX_TCD0_CCA_gc = (0xD4<<0),
EVSYS_CHMUX_TCD0_CCB_gc = (0xD5<<0),
EVSYS_CHMUX_TCD0_CCC_gc = (0xD6<<0),
EVSYS_CHMUX_TCD0_CCD_gc = (0xD7<<0),
EVSYS_CHMUX_TCD1_OVF_gc = (0xD8<<0),
EVSYS_CHMUX_TCD1_ERR_gc = (0xD9<<0),
EVSYS_CHMUX_TCD1_CCA_gc = (0xDC<<0),
EVSYS_CHMUX_TCD1_CCB_gc = (0xDD<<0),
EVSYS_CHMUX_TCE0_OVF_gc = (0xE0<<0),
EVSYS_CHMUX_TCE0_ERR_gc = (0xE1<<0),
EVSYS_CHMUX_TCE0_CCA_gc = (0xE4<<0),
EVSYS_CHMUX_TCE0_CCB_gc = (0xE5<<0),
EVSYS_CHMUX_TCE0_CCC_gc = (0xE6<<0),
EVSYS_CHMUX_TCE0_CCD_gc = (0xE7<<0),
EVSYS_CHMUX_TCE1_OVF_gc = (0xE8<<0),
EVSYS_CHMUX_TCE1_ERR_gc = (0xE9<<0),
EVSYS_CHMUX_TCE1_CCA_gc = (0xEC<<0),
EVSYS_CHMUX_TCE1_CCB_gc = (0xED<<0),
EVSYS_CHMUX_TCF0_OVF_gc = (0xF0<<0),
EVSYS_CHMUX_TCF0_ERR_gc = (0xF1<<0),
EVSYS_CHMUX_TCF0_CCA_gc = (0xF4<<0),
EVSYS_CHMUX_TCF0_CCB_gc = (0xF5<<0),
EVSYS_CHMUX_TCF0_CCC_gc = (0xF6<<0),
EVSYS_CHMUX_TCF0_CCD_gc = (0xF7<<0),
EVSYS_CHMUX_TCF1_OVF_gc = (0xF8<<0),
EVSYS_CHMUX_TCF1_ERR_gc = (0xF9<<0),
EVSYS_CHMUX_TCF1_CCA_gc = (0xFC<<0),
EVSYS_CHMUX_TCF1_CCB_gc = (0xFD<<0),
EVSYS_CHMUX_OFF_gc = (0x00<<0),
EVSYS_CHMUX_RTC_OVF_gc = (0x08<<0),
EVSYS_CHMUX_RTC_CMP_gc = (0x09<<0),
EVSYS_CHMUX_ACA_CH0_gc = (0x10<<0),
EVSYS_CHMUX_ACA_CH1_gc = (0x11<<0),
EVSYS_CHMUX_ACA_WIN_gc = (0x12<<0),
EVSYS_CHMUX_ADCA_CH0_gc = (0x20<<0),
EVSYS_CHMUX_PORTA_PIN0_gc = (0x50<<0),
EVSYS_CHMUX_PORTA_PIN1_gc = (0x51<<0),
EVSYS_CHMUX_PORTA_PIN2_gc = (0x52<<0),
EVSYS_CHMUX_PORTA_PIN3_gc = (0x53<<0),
EVSYS_CHMUX_PORTA_PIN4_gc = (0x54<<0),
EVSYS_CHMUX_PORTA_PIN5_gc = (0x55<<0),
EVSYS_CHMUX_PORTA_PIN6_gc = (0x56<<0),
EVSYS_CHMUX_PORTA_PIN7_gc = (0x57<<0),
EVSYS_CHMUX_PORTB_PIN0_gc = (0x58<<0),
EVSYS_CHMUX_PORTB_PIN1_gc = (0x59<<0),
EVSYS_CHMUX_PORTB_PIN2_gc = (0x5A<<0),
EVSYS_CHMUX_PORTB_PIN3_gc = (0x5B<<0),
EVSYS_CHMUX_PORTB_PIN4_gc = (0x5C<<0),
EVSYS_CHMUX_PORTB_PIN5_gc = (0x5D<<0),
EVSYS_CHMUX_PORTB_PIN6_gc = (0x5E<<0),
EVSYS_CHMUX_PORTB_PIN7_gc = (0x5F<<0),
EVSYS_CHMUX_PORTC_PIN0_gc = (0x60<<0),
EVSYS_CHMUX_PORTC_PIN1_gc = (0x61<<0),
EVSYS_CHMUX_PORTC_PIN2_gc = (0x62<<0),
EVSYS_CHMUX_PORTC_PIN3_gc = (0x63<<0),
EVSYS_CHMUX_PORTC_PIN4_gc = (0x64<<0),
EVSYS_CHMUX_PORTC_PIN5_gc = (0x65<<0),
EVSYS_CHMUX_PORTC_PIN6_gc = (0x66<<0),
EVSYS_CHMUX_PORTC_PIN7_gc = (0x67<<0),
EVSYS_CHMUX_PORTD_PIN0_gc = (0x68<<0),
EVSYS_CHMUX_PORTD_PIN1_gc = (0x69<<0),
EVSYS_CHMUX_PORTD_PIN2_gc = (0x6A<<0),
EVSYS_CHMUX_PORTD_PIN3_gc = (0x6B<<0),
EVSYS_CHMUX_PORTD_PIN4_gc = (0x6C<<0),
EVSYS_CHMUX_PORTD_PIN5_gc = (0x6D<<0),
EVSYS_CHMUX_PORTD_PIN6_gc = (0x6E<<0),
EVSYS_CHMUX_PORTD_PIN7_gc = (0x6F<<0),
EVSYS_CHMUX_PORTE_PIN0_gc = (0x70<<0),
EVSYS_CHMUX_PORTE_PIN1_gc = (0x71<<0),
EVSYS_CHMUX_PORTE_PIN2_gc = (0x72<<0),
EVSYS_CHMUX_PORTE_PIN3_gc = (0x73<<0),
EVSYS_CHMUX_PORTE_PIN4_gc = (0x74<<0),
EVSYS_CHMUX_PORTE_PIN5_gc = (0x75<<0),
EVSYS_CHMUX_PORTE_PIN6_gc = (0x76<<0),
EVSYS_CHMUX_PORTE_PIN7_gc = (0x77<<0),
EVSYS_CHMUX_PORTF_PIN0_gc = (0x78<<0),
EVSYS_CHMUX_PORTF_PIN1_gc = (0x79<<0),
EVSYS_CHMUX_PORTF_PIN2_gc = (0x7A<<0),
EVSYS_CHMUX_PORTF_PIN3_gc = (0x7B<<0),
EVSYS_CHMUX_PORTF_PIN4_gc = (0x7C<<0),
EVSYS_CHMUX_PORTF_PIN5_gc = (0x7D<<0),
EVSYS_CHMUX_PORTF_PIN6_gc = (0x7E<<0),
EVSYS_CHMUX_PORTF_PIN7_gc = (0x7F<<0),
EVSYS_CHMUX_PRESCALER_1_gc = (0x80<<0),
EVSYS_CHMUX_PRESCALER_2_gc = (0x81<<0),
EVSYS_CHMUX_PRESCALER_4_gc = (0x82<<0),
EVSYS_CHMUX_PRESCALER_8_gc = (0x83<<0),
EVSYS_CHMUX_PRESCALER_16_gc = (0x84<<0),
EVSYS_CHMUX_PRESCALER_32_gc = (0x85<<0),
EVSYS_CHMUX_PRESCALER_64_gc = (0x86<<0),
EVSYS_CHMUX_PRESCALER_128_gc = (0x87<<0),
EVSYS_CHMUX_PRESCALER_256_gc = (0x88<<0),
EVSYS_CHMUX_PRESCALER_512_gc = (0x89<<0),
EVSYS_CHMUX_PRESCALER_1024_gc = (0x8A<<0),
EVSYS_CHMUX_PRESCALER_2048_gc = (0x8B<<0),
EVSYS_CHMUX_PRESCALER_4096_gc = (0x8C<<0),
EVSYS_CHMUX_PRESCALER_8192_gc = (0x8D<<0),
EVSYS_CHMUX_PRESCALER_16384_gc = (0x8E<<0),
EVSYS_CHMUX_PRESCALER_32768_gc = (0x8F<<0),
EVSYS_CHMUX_TCC0_OVF_gc = (0xC0<<0),
EVSYS_CHMUX_TCC0_ERR_gc = (0xC1<<0),
EVSYS_CHMUX_TCC0_CCA_gc = (0xC4<<0),
EVSYS_CHMUX_TCC0_CCB_gc = (0xC5<<0),
EVSYS_CHMUX_TCC0_CCC_gc = (0xC6<<0),
EVSYS_CHMUX_TCC0_CCD_gc = (0xC7<<0),
EVSYS_CHMUX_TCC1_OVF_gc = (0xC8<<0),
EVSYS_CHMUX_TCC1_ERR_gc = (0xC9<<0),
EVSYS_CHMUX_TCC1_CCA_gc = (0xCC<<0),
EVSYS_CHMUX_TCC1_CCB_gc = (0xCD<<0),
EVSYS_CHMUX_TCD0_OVF_gc = (0xD0<<0),
EVSYS_CHMUX_TCD0_ERR_gc = (0xD1<<0),
EVSYS_CHMUX_TCD0_CCA_gc = (0xD4<<0),
EVSYS_CHMUX_TCD0_CCB_gc = (0xD5<<0),
EVSYS_CHMUX_TCD0_CCC_gc = (0xD6<<0),
EVSYS_CHMUX_TCD0_CCD_gc = (0xD7<<0),
EVSYS_CHMUX_TCD1_OVF_gc = (0xD8<<0),
EVSYS_CHMUX_TCD1_ERR_gc = (0xD9<<0),
EVSYS_CHMUX_TCD1_CCA_gc = (0xDC<<0),
EVSYS_CHMUX_TCD1_CCB_gc = (0xDD<<0),
EVSYS_CHMUX_TCE0_OVF_gc = (0xE0<<0),
EVSYS_CHMUX_TCE0_ERR_gc = (0xE1<<0),
EVSYS_CHMUX_TCE0_CCA_gc = (0xE4<<0),
EVSYS_CHMUX_TCE0_CCB_gc = (0xE5<<0),
EVSYS_CHMUX_TCE0_CCC_gc = (0xE6<<0),
EVSYS_CHMUX_TCE0_CCD_gc = (0xE7<<0),
EVSYS_CHMUX_TCE1_OVF_gc = (0xE8<<0),
EVSYS_CHMUX_TCE1_ERR_gc = (0xE9<<0),
EVSYS_CHMUX_TCE1_CCA_gc = (0xEC<<0),
EVSYS_CHMUX_TCE1_CCB_gc = (0xED<<0),
EVSYS_CHMUX_TCF0_OVF_gc = (0xF0<<0),
EVSYS_CHMUX_TCF0_ERR_gc = (0xF1<<0),
EVSYS_CHMUX_TCF0_CCA_gc = (0xF4<<0),
EVSYS_CHMUX_TCF0_CCB_gc = (0xF5<<0),
EVSYS_CHMUX_TCF0_CCC_gc = (0xF6<<0),
EVSYS_CHMUX_TCF0_CCD_gc = (0xF7<<0),
EVSYS_CHMUX_TCF1_OVF_gc = (0xF8<<0),
EVSYS_CHMUX_TCF1_ERR_gc = (0xF9<<0),
EVSYS_CHMUX_TCF1_CCA_gc = (0xFC<<0),
EVSYS_CHMUX_TCF1_CCB_gc = (0xFD<<0),
EVSYS_CHMUX_OFF_gc = (0x00<<0),
EVSYS_CHMUX_RTC_OVF_gc = (0x08<<0),
EVSYS_CHMUX_RTC_CMP_gc = (0x09<<0),
EVSYS_CHMUX_ACA_CH0_gc = (0x10<<0),
EVSYS_CHMUX_ACA_CH1_gc = (0x11<<0),
EVSYS_CHMUX_ACA_WIN_gc = (0x12<<0),
EVSYS_CHMUX_ACB_CH0_gc = (0x13<<0),
EVSYS_CHMUX_ACB_CH1_gc = (0x14<<0),
EVSYS_CHMUX_ACB_WIN_gc = (0x15<<0),
EVSYS_CHMUX_ADCA_CH0_gc = (0x20<<0),
EVSYS_CHMUX_ADCA_CH1_gc = (0x21<<0),
EVSYS_CHMUX_ADCA_CH2_gc = (0x22<<0),
EVSYS_CHMUX_ADCA_CH3_gc = (0x23<<0),
EVSYS_CHMUX_ADCB_CH0_gc = (0x24<<0),
EVSYS_CHMUX_ADCB_CH1_gc = (0x25<<0),
EVSYS_CHMUX_ADCB_CH2_gc = (0x26<<0),
EVSYS_CHMUX_ADCB_CH3_gc = (0x27<<0),
EVSYS_CHMUX_PORTA_PIN0_gc = (0x50<<0),
EVSYS_CHMUX_PORTA_PIN1_gc = (0x51<<0),
EVSYS_CHMUX_PORTA_PIN2_gc = (0x52<<0),
EVSYS_CHMUX_PORTA_PIN3_gc = (0x53<<0),
EVSYS_CHMUX_PORTA_PIN4_gc = (0x54<<0),
EVSYS_CHMUX_PORTA_PIN5_gc = (0x55<<0),
EVSYS_CHMUX_PORTA_PIN6_gc = (0x56<<0),
EVSYS_CHMUX_PORTA_PIN7_gc = (0x57<<0),
EVSYS_CHMUX_PORTB_PIN0_gc = (0x58<<0),
EVSYS_CHMUX_PORTB_PIN1_gc = (0x59<<0),
EVSYS_CHMUX_PORTB_PIN2_gc = (0x5A<<0),
EVSYS_CHMUX_PORTB_PIN3_gc = (0x5B<<0),
EVSYS_CHMUX_PORTB_PIN4_gc = (0x5C<<0),
EVSYS_CHMUX_PORTB_PIN5_gc = (0x5D<<0),
EVSYS_CHMUX_PORTB_PIN6_gc = (0x5E<<0),
EVSYS_CHMUX_PORTB_PIN7_gc = (0x5F<<0),
EVSYS_CHMUX_PORTC_PIN0_gc = (0x60<<0),
EVSYS_CHMUX_PORTC_PIN1_gc = (0x61<<0),
EVSYS_CHMUX_PORTC_PIN2_gc = (0x62<<0),
EVSYS_CHMUX_PORTC_PIN3_gc = (0x63<<0),
EVSYS_CHMUX_PORTC_PIN4_gc = (0x64<<0),
EVSYS_CHMUX_PORTC_PIN5_gc = (0x65<<0),
EVSYS_CHMUX_PORTC_PIN6_gc = (0x66<<0),
EVSYS_CHMUX_PORTC_PIN7_gc = (0x67<<0),
EVSYS_CHMUX_PORTD_PIN0_gc = (0x68<<0),
EVSYS_CHMUX_PORTD_PIN1_gc = (0x69<<0),
EVSYS_CHMUX_PORTD_PIN2_gc = (0x6A<<0),
EVSYS_CHMUX_PORTD_PIN3_gc = (0x6B<<0),
EVSYS_CHMUX_PORTD_PIN4_gc = (0x6C<<0),
EVSYS_CHMUX_PORTD_PIN5_gc = (0x6D<<0),
EVSYS_CHMUX_PORTD_PIN6_gc = (0x6E<<0),
EVSYS_CHMUX_PORTD_PIN7_gc = (0x6F<<0),
EVSYS_CHMUX_PORTE_PIN0_gc = (0x70<<0),
EVSYS_CHMUX_PORTE_PIN1_gc = (0x71<<0),
EVSYS_CHMUX_PORTE_PIN2_gc = (0x72<<0),
EVSYS_CHMUX_PORTE_PIN3_gc = (0x73<<0),
EVSYS_CHMUX_PORTE_PIN4_gc = (0x74<<0),
EVSYS_CHMUX_PORTE_PIN5_gc = (0x75<<0),
EVSYS_CHMUX_PORTE_PIN6_gc = (0x76<<0),
EVSYS_CHMUX_PORTE_PIN7_gc = (0x77<<0),
EVSYS_CHMUX_PORTF_PIN0_gc = (0x78<<0),
EVSYS_CHMUX_PORTF_PIN1_gc = (0x79<<0),
EVSYS_CHMUX_PORTF_PIN2_gc = (0x7A<<0),
EVSYS_CHMUX_PORTF_PIN3_gc = (0x7B<<0),
EVSYS_CHMUX_PORTF_PIN4_gc = (0x7C<<0),
EVSYS_CHMUX_PORTF_PIN5_gc = (0x7D<<0),
EVSYS_CHMUX_PORTF_PIN6_gc = (0x7E<<0),
EVSYS_CHMUX_PORTF_PIN7_gc = (0x7F<<0),
EVSYS_CHMUX_PRESCALER_1_gc = (0x80<<0),
EVSYS_CHMUX_PRESCALER_2_gc = (0x81<<0),
EVSYS_CHMUX_PRESCALER_4_gc = (0x82<<0),
EVSYS_CHMUX_PRESCALER_8_gc = (0x83<<0),
EVSYS_CHMUX_PRESCALER_16_gc = (0x84<<0),
EVSYS_CHMUX_PRESCALER_32_gc = (0x85<<0),
EVSYS_CHMUX_PRESCALER_64_gc = (0x86<<0),
EVSYS_CHMUX_PRESCALER_128_gc = (0x87<<0),
EVSYS_CHMUX_PRESCALER_256_gc = (0x88<<0),
EVSYS_CHMUX_PRESCALER_512_gc = (0x89<<0),
EVSYS_CHMUX_PRESCALER_1024_gc = (0x8A<<0),
EVSYS_CHMUX_PRESCALER_2048_gc = (0x8B<<0),
EVSYS_CHMUX_PRESCALER_4096_gc = (0x8C<<0),
EVSYS_CHMUX_PRESCALER_8192_gc = (0x8D<<0),
EVSYS_CHMUX_PRESCALER_16384_gc = (0x8E<<0),
EVSYS_CHMUX_PRESCALER_32768_gc = (0x8F<<0),
EVSYS_CHMUX_TCC0_OVF_gc = (0xC0<<0),
EVSYS_CHMUX_TCC0_ERR_gc = (0xC1<<0),
EVSYS_CHMUX_TCC0_CCA_gc = (0xC4<<0),
EVSYS_CHMUX_TCC0_CCB_gc = (0xC5<<0),
EVSYS_CHMUX_TCC0_CCC_gc = (0xC6<<0),
EVSYS_CHMUX_TCC0_CCD_gc = (0xC7<<0),
EVSYS_CHMUX_TCC1_OVF_gc = (0xC8<<0),
EVSYS_CHMUX_TCC1_ERR_gc = (0xC9<<0),
EVSYS_CHMUX_TCC1_CCA_gc = (0xCC<<0),
EVSYS_CHMUX_TCC1_CCB_gc = (0xCD<<0),
EVSYS_CHMUX_TCD0_OVF_gc = (0xD0<<0),
EVSYS_CHMUX_TCD0_ERR_gc = (0xD1<<0),
EVSYS_CHMUX_TCD0_CCA_gc = (0xD4<<0),
EVSYS_CHMUX_TCD0_CCB_gc = (0xD5<<0),
EVSYS_CHMUX_TCD0_CCC_gc = (0xD6<<0),
EVSYS_CHMUX_TCD0_CCD_gc = (0xD7<<0),
EVSYS_CHMUX_TCD1_OVF_gc = (0xD8<<0),
EVSYS_CHMUX_TCD1_ERR_gc = (0xD9<<0),
EVSYS_CHMUX_TCD1_CCA_gc = (0xDC<<0),
EVSYS_CHMUX_TCD1_CCB_gc = (0xDD<<0),
EVSYS_CHMUX_TCE0_OVF_gc = (0xE0<<0),
EVSYS_CHMUX_TCE0_ERR_gc = (0xE1<<0),
EVSYS_CHMUX_TCE0_CCA_gc = (0xE4<<0),
EVSYS_CHMUX_TCE0_CCB_gc = (0xE5<<0),
EVSYS_CHMUX_TCE0_CCC_gc = (0xE6<<0),
EVSYS_CHMUX_TCE0_CCD_gc = (0xE7<<0),
EVSYS_CHMUX_TCE1_OVF_gc = (0xE8<<0),
EVSYS_CHMUX_TCE1_ERR_gc = (0xE9<<0),
EVSYS_CHMUX_TCE1_CCA_gc = (0xEC<<0),
EVSYS_CHMUX_TCE1_CCB_gc = (0xED<<0),
EVSYS_CHMUX_TCF0_OVF_gc = (0xF0<<0),
EVSYS_CHMUX_TCF0_ERR_gc = (0xF1<<0),
EVSYS_CHMUX_TCF0_CCA_gc = (0xF4<<0),
EVSYS_CHMUX_TCF0_CCB_gc = (0xF5<<0),
EVSYS_CHMUX_TCF0_CCC_gc = (0xF6<<0),
EVSYS_CHMUX_TCF0_CCD_gc = (0xF7<<0),
EVSYS_CHMUX_TCF1_OVF_gc = (0xF8<<0),
EVSYS_CHMUX_TCF1_ERR_gc = (0xF9<<0),
EVSYS_CHMUX_TCF1_CCA_gc = (0xFC<<0),
EVSYS_CHMUX_TCF1_CCB_gc = (0xFD<<0),
EVSYS_CHMUX_OFF_gc = (0x00<<0),
EVSYS_CHMUX_RTC_OVF_gc = (0x08<<0),
EVSYS_CHMUX_RTC_CMP_gc = (0x09<<0),
EVSYS_CHMUX_ACA_CH0_gc = (0x10<<0),
EVSYS_CHMUX_ACA_CH1_gc = (0x11<<0),
EVSYS_CHMUX_ACA_WIN_gc = (0x12<<0),
EVSYS_CHMUX_ADCA_CH0_gc = (0x20<<0),
EVSYS_CHMUX_PORTA_PIN0_gc = (0x50<<0),
EVSYS_CHMUX_PORTA_PIN1_gc = (0x51<<0),
EVSYS_CHMUX_PORTA_PIN2_gc = (0x52<<0),
EVSYS_CHMUX_PORTA_PIN3_gc = (0x53<<0),
EVSYS_CHMUX_PORTA_PIN4_gc = (0x54<<0),
EVSYS_CHMUX_PORTA_PIN5_gc = (0x55<<0),
EVSYS_CHMUX_PORTA_PIN6_gc = (0x56<<0),
EVSYS_CHMUX_PORTA_PIN7_gc = (0x57<<0),
EVSYS_CHMUX_PORTB_PIN0_gc = (0x58<<0),
EVSYS_CHMUX_PORTB_PIN1_gc = (0x59<<0),
EVSYS_CHMUX_PORTB_PIN2_gc = (0x5A<<0),
EVSYS_CHMUX_PORTB_PIN3_gc = (0x5B<<0),
EVSYS_CHMUX_PORTB_PIN4_gc = (0x5C<<0),
EVSYS_CHMUX_PORTB_PIN5_gc = (0x5D<<0),
EVSYS_CHMUX_PORTB_PIN6_gc = (0x5E<<0),
EVSYS_CHMUX_PORTB_PIN7_gc = (0x5F<<0),
EVSYS_CHMUX_PORTC_PIN0_gc = (0x60<<0),
EVSYS_CHMUX_PORTC_PIN1_gc = (0x61<<0),
EVSYS_CHMUX_PORTC_PIN2_gc = (0x62<<0),
EVSYS_CHMUX_PORTC_PIN3_gc = (0x63<<0),
EVSYS_CHMUX_PORTC_PIN4_gc = (0x64<<0),
EVSYS_CHMUX_PORTC_PIN5_gc = (0x65<<0),
EVSYS_CHMUX_PORTC_PIN6_gc = (0x66<<0),
EVSYS_CHMUX_PORTC_PIN7_gc = (0x67<<0),
EVSYS_CHMUX_PORTD_PIN0_gc = (0x68<<0),
EVSYS_CHMUX_PORTD_PIN1_gc = (0x69<<0),
EVSYS_CHMUX_PORTD_PIN2_gc = (0x6A<<0),
EVSYS_CHMUX_PORTD_PIN3_gc = (0x6B<<0),
EVSYS_CHMUX_PORTD_PIN4_gc = (0x6C<<0),
EVSYS_CHMUX_PORTD_PIN5_gc = (0x6D<<0),
EVSYS_CHMUX_PORTD_PIN6_gc = (0x6E<<0),
EVSYS_CHMUX_PORTD_PIN7_gc = (0x6F<<0),
EVSYS_CHMUX_PORTE_PIN0_gc = (0x70<<0),
EVSYS_CHMUX_PORTE_PIN1_gc = (0x71<<0),
EVSYS_CHMUX_PORTE_PIN2_gc = (0x72<<0),
EVSYS_CHMUX_PORTE_PIN3_gc = (0x73<<0),
EVSYS_CHMUX_PORTE_PIN4_gc = (0x74<<0),
EVSYS_CHMUX_PORTE_PIN5_gc = (0x75<<0),
EVSYS_CHMUX_PORTE_PIN6_gc = (0x76<<0),
EVSYS_CHMUX_PORTE_PIN7_gc = (0x77<<0),
EVSYS_CHMUX_PORTF_PIN0_gc = (0x78<<0),
EVSYS_CHMUX_PORTF_PIN1_gc = (0x79<<0),
EVSYS_CHMUX_PORTF_PIN2_gc = (0x7A<<0),
EVSYS_CHMUX_PORTF_PIN3_gc = (0x7B<<0),
EVSYS_CHMUX_PORTF_PIN4_gc = (0x7C<<0),
EVSYS_CHMUX_PORTF_PIN5_gc = (0x7D<<0),
EVSYS_CHMUX_PORTF_PIN6_gc = (0x7E<<0),
EVSYS_CHMUX_PORTF_PIN7_gc = (0x7F<<0),
EVSYS_CHMUX_PRESCALER_1_gc = (0x80<<0),
EVSYS_CHMUX_PRESCALER_2_gc = (0x81<<0),
EVSYS_CHMUX_PRESCALER_4_gc = (0x82<<0),
EVSYS_CHMUX_PRESCALER_8_gc = (0x83<<0),
EVSYS_CHMUX_PRESCALER_16_gc = (0x84<<0),
EVSYS_CHMUX_PRESCALER_32_gc = (0x85<<0),
EVSYS_CHMUX_PRESCALER_64_gc = (0x86<<0),
EVSYS_CHMUX_PRESCALER_128_gc = (0x87<<0),
EVSYS_CHMUX_PRESCALER_256_gc = (0x88<<0),
EVSYS_CHMUX_PRESCALER_512_gc = (0x89<<0),
EVSYS_CHMUX_PRESCALER_1024_gc = (0x8A<<0),
EVSYS_CHMUX_PRESCALER_2048_gc = (0x8B<<0),
EVSYS_CHMUX_PRESCALER_4096_gc = (0x8C<<0),
EVSYS_CHMUX_PRESCALER_8192_gc = (0x8D<<0),
EVSYS_CHMUX_PRESCALER_16384_gc = (0x8E<<0),
EVSYS_CHMUX_PRESCALER_32768_gc = (0x8F<<0),
EVSYS_CHMUX_TCC0_OVF_gc = (0xC0<<0),
EVSYS_CHMUX_TCC0_ERR_gc = (0xC1<<0),
EVSYS_CHMUX_TCC0_CCA_gc = (0xC4<<0),
EVSYS_CHMUX_TCC0_CCB_gc = (0xC5<<0),
EVSYS_CHMUX_TCC0_CCC_gc = (0xC6<<0),
EVSYS_CHMUX_TCC0_CCD_gc = (0xC7<<0),
EVSYS_CHMUX_TCC1_OVF_gc = (0xC8<<0),
EVSYS_CHMUX_TCC1_ERR_gc = (0xC9<<0),
EVSYS_CHMUX_TCC1_CCA_gc = (0xCC<<0),
EVSYS_CHMUX_TCC1_CCB_gc = (0xCD<<0),
EVSYS_CHMUX_TCD0_OVF_gc = (0xD0<<0),
EVSYS_CHMUX_TCD0_ERR_gc = (0xD1<<0),
EVSYS_CHMUX_TCD0_CCA_gc = (0xD4<<0),
EVSYS_CHMUX_TCD0_CCB_gc = (0xD5<<0),
EVSYS_CHMUX_TCD0_CCC_gc = (0xD6<<0),
EVSYS_CHMUX_TCD0_CCD_gc = (0xD7<<0),
EVSYS_CHMUX_TCD1_OVF_gc = (0xD8<<0),
EVSYS_CHMUX_TCD1_ERR_gc = (0xD9<<0),
EVSYS_CHMUX_TCD1_CCA_gc = (0xDC<<0),
EVSYS_CHMUX_TCD1_CCB_gc = (0xDD<<0),
EVSYS_CHMUX_TCE0_OVF_gc = (0xE0<<0),
EVSYS_CHMUX_TCE0_ERR_gc = (0xE1<<0),
EVSYS_CHMUX_TCE0_CCA_gc = (0xE4<<0),
EVSYS_CHMUX_TCE0_CCB_gc = (0xE5<<0),
EVSYS_CHMUX_TCE0_CCC_gc = (0xE6<<0),
EVSYS_CHMUX_TCE0_CCD_gc = (0xE7<<0),
EVSYS_CHMUX_TCE1_OVF_gc = (0xE8<<0),
EVSYS_CHMUX_TCE1_ERR_gc = (0xE9<<0),
EVSYS_CHMUX_TCE1_CCA_gc = (0xEC<<0),
EVSYS_CHMUX_TCE1_CCB_gc = (0xED<<0),
EVSYS_CHMUX_TCF0_OVF_gc = (0xF0<<0),
EVSYS_CHMUX_TCF0_ERR_gc = (0xF1<<0),
EVSYS_CHMUX_TCF0_CCA_gc = (0xF4<<0),
EVSYS_CHMUX_TCF0_CCB_gc = (0xF5<<0),
EVSYS_CHMUX_TCF0_CCC_gc = (0xF6<<0),
EVSYS_CHMUX_TCF0_CCD_gc = (0xF7<<0),
EVSYS_CHMUX_TCF1_OVF_gc = (0xF8<<0),
EVSYS_CHMUX_TCF1_ERR_gc = (0xF9<<0),
EVSYS_CHMUX_TCF1_CCA_gc = (0xFC<<0),
EVSYS_CHMUX_TCF1_CCB_gc = (0xFD<<0),
EVSYS_CHMUX_OFF_gc = (0x00<<0),
EVSYS_CHMUX_RTC_OVF_gc = (0x08<<0),
EVSYS_CHMUX_RTC_CMP_gc = (0x09<<0),
EVSYS_CHMUX_ACA_CH0_gc = (0x10<<0),
EVSYS_CHMUX_ACA_CH1_gc = (0x11<<0),
EVSYS_CHMUX_ACA_WIN_gc = (0x12<<0),
EVSYS_CHMUX_ACB_CH0_gc = (0x13<<0),
EVSYS_CHMUX_ACB_CH1_gc = (0x14<<0),
EVSYS_CHMUX_ACB_WIN_gc = (0x15<<0),
EVSYS_CHMUX_ADCA_CH0_gc = (0x20<<0),
EVSYS_CHMUX_ADCA_CH1_gc = (0x21<<0),
EVSYS_CHMUX_ADCA_CH2_gc = (0x22<<0),
EVSYS_CHMUX_ADCA_CH3_gc = (0x23<<0),
EVSYS_CHMUX_ADCB_CH0_gc = (0x24<<0),
EVSYS_CHMUX_ADCB_CH1_gc = (0x25<<0),
EVSYS_CHMUX_ADCB_CH2_gc = (0x26<<0),
EVSYS_CHMUX_ADCB_CH3_gc = (0x27<<0),
EVSYS_CHMUX_PORTA_PIN0_gc = (0x50<<0),
EVSYS_CHMUX_PORTA_PIN1_gc = (0x51<<0),
EVSYS_CHMUX_PORTA_PIN2_gc = (0x52<<0),
EVSYS_CHMUX_PORTA_PIN3_gc = (0x53<<0),
EVSYS_CHMUX_PORTA_PIN4_gc = (0x54<<0),
EVSYS_CHMUX_PORTA_PIN5_gc = (0x55<<0),
EVSYS_CHMUX_PORTA_PIN6_gc = (0x56<<0),
EVSYS_CHMUX_PORTA_PIN7_gc = (0x57<<0),
EVSYS_CHMUX_PORTB_PIN0_gc = (0x58<<0),
EVSYS_CHMUX_PORTB_PIN1_gc = (0x59<<0),
EVSYS_CHMUX_PORTB_PIN2_gc = (0x5A<<0),
EVSYS_CHMUX_PORTB_PIN3_gc = (0x5B<<0),
EVSYS_CHMUX_PORTB_PIN4_gc = (0x5C<<0),
EVSYS_CHMUX_PORTB_PIN5_gc = (0x5D<<0),
EVSYS_CHMUX_PORTB_PIN6_gc = (0x5E<<0),
EVSYS_CHMUX_PORTB_PIN7_gc = (0x5F<<0),
EVSYS_CHMUX_PORTC_PIN0_gc = (0x60<<0),
EVSYS_CHMUX_PORTC_PIN1_gc = (0x61<<0),
EVSYS_CHMUX_PORTC_PIN2_gc = (0x62<<0),
EVSYS_CHMUX_PORTC_PIN3_gc = (0x63<<0),
EVSYS_CHMUX_PORTC_PIN4_gc = (0x64<<0),
EVSYS_CHMUX_PORTC_PIN5_gc = (0x65<<0),
EVSYS_CHMUX_PORTC_PIN6_gc = (0x66<<0),
EVSYS_CHMUX_PORTC_PIN7_gc = (0x67<<0),
EVSYS_CHMUX_PORTD_PIN0_gc = (0x68<<0),
EVSYS_CHMUX_PORTD_PIN1_gc = (0x69<<0),
EVSYS_CHMUX_PORTD_PIN2_gc = (0x6A<<0),
EVSYS_CHMUX_PORTD_PIN3_gc = (0x6B<<0),
EVSYS_CHMUX_PORTD_PIN4_gc = (0x6C<<0),
EVSYS_CHMUX_PORTD_PIN5_gc = (0x6D<<0),
EVSYS_CHMUX_PORTD_PIN6_gc = (0x6E<<0),
EVSYS_CHMUX_PORTD_PIN7_gc = (0x6F<<0),
EVSYS_CHMUX_PORTE_PIN0_gc = (0x70<<0),
EVSYS_CHMUX_PORTE_PIN1_gc = (0x71<<0),
EVSYS_CHMUX_PORTE_PIN2_gc = (0x72<<0),
EVSYS_CHMUX_PORTE_PIN3_gc = (0x73<<0),
EVSYS_CHMUX_PORTE_PIN4_gc = (0x74<<0),
EVSYS_CHMUX_PORTE_PIN5_gc = (0x75<<0),
EVSYS_CHMUX_PORTE_PIN6_gc = (0x76<<0),
EVSYS_CHMUX_PORTE_PIN7_gc = (0x77<<0),
EVSYS_CHMUX_PORTF_PIN0_gc = (0x78<<0),
EVSYS_CHMUX_PORTF_PIN1_gc = (0x79<<0),
EVSYS_CHMUX_PORTF_PIN2_gc = (0x7A<<0),
EVSYS_CHMUX_PORTF_PIN3_gc = (0x7B<<0),
EVSYS_CHMUX_PORTF_PIN4_gc = (0x7C<<0),
EVSYS_CHMUX_PORTF_PIN5_gc = (0x7D<<0),
EVSYS_CHMUX_PORTF_PIN6_gc = (0x7E<<0),
EVSYS_CHMUX_PORTF_PIN7_gc = (0x7F<<0),
EVSYS_CHMUX_PRESCALER_1_gc = (0x80<<0),
EVSYS_CHMUX_PRESCALER_2_gc = (0x81<<0),
EVSYS_CHMUX_PRESCALER_4_gc = (0x82<<0),
EVSYS_CHMUX_PRESCALER_8_gc = (0x83<<0),
EVSYS_CHMUX_PRESCALER_16_gc = (0x84<<0),
EVSYS_CHMUX_PRESCALER_32_gc = (0x85<<0),
EVSYS_CHMUX_PRESCALER_64_gc = (0x86<<0),
EVSYS_CHMUX_PRESCALER_128_gc = (0x87<<0),
EVSYS_CHMUX_PRESCALER_256_gc = (0x88<<0),
EVSYS_CHMUX_PRESCALER_512_gc = (0x89<<0),
EVSYS_CHMUX_PRESCALER_1024_gc = (0x8A<<0),
EVSYS_CHMUX_PRESCALER_2048_gc = (0x8B<<0),
EVSYS_CHMUX_PRESCALER_4096_gc = (0x8C<<0),
EVSYS_CHMUX_PRESCALER_8192_gc = (0x8D<<0),
EVSYS_CHMUX_PRESCALER_16384_gc = (0x8E<<0),
EVSYS_CHMUX_PRESCALER_32768_gc = (0x8F<<0),
EVSYS_CHMUX_TCC0_OVF_gc = (0xC0<<0),
EVSYS_CHMUX_TCC0_ERR_gc = (0xC1<<0),
EVSYS_CHMUX_TCC0_CCA_gc = (0xC4<<0),
EVSYS_CHMUX_TCC0_CCB_gc = (0xC5<<0),
EVSYS_CHMUX_TCC0_CCC_gc = (0xC6<<0),
EVSYS_CHMUX_TCC0_CCD_gc = (0xC7<<0),
EVSYS_CHMUX_TCC1_OVF_gc = (0xC8<<0),
EVSYS_CHMUX_TCC1_ERR_gc = (0xC9<<0),
EVSYS_CHMUX_TCC1_CCA_gc = (0xCC<<0),
EVSYS_CHMUX_TCC1_CCB_gc = (0xCD<<0),
EVSYS_CHMUX_TCD0_OVF_gc = (0xD0<<0),
EVSYS_CHMUX_TCD0_ERR_gc = (0xD1<<0),
EVSYS_CHMUX_TCD0_CCA_gc = (0xD4<<0),
EVSYS_CHMUX_TCD0_CCB_gc = (0xD5<<0),
EVSYS_CHMUX_TCD0_CCC_gc = (0xD6<<0),
EVSYS_CHMUX_TCD0_CCD_gc = (0xD7<<0),
EVSYS_CHMUX_TCD1_OVF_gc = (0xD8<<0),
EVSYS_CHMUX_TCD1_ERR_gc = (0xD9<<0),
EVSYS_CHMUX_TCD1_CCA_gc = (0xDC<<0),
EVSYS_CHMUX_TCD1_CCB_gc = (0xDD<<0),
EVSYS_CHMUX_TCE0_OVF_gc = (0xE0<<0),
EVSYS_CHMUX_TCE0_ERR_gc = (0xE1<<0),
EVSYS_CHMUX_TCE0_CCA_gc = (0xE4<<0),
EVSYS_CHMUX_TCE0_CCB_gc = (0xE5<<0),
EVSYS_CHMUX_TCE0_CCC_gc = (0xE6<<0),
EVSYS_CHMUX_TCE0_CCD_gc = (0xE7<<0),
EVSYS_CHMUX_TCE1_OVF_gc = (0xE8<<0),
EVSYS_CHMUX_TCE1_ERR_gc = (0xE9<<0),
EVSYS_CHMUX_TCE1_CCA_gc = (0xEC<<0),
EVSYS_CHMUX_TCE1_CCB_gc = (0xED<<0),
EVSYS_CHMUX_TCF0_OVF_gc = (0xF0<<0),
EVSYS_CHMUX_TCF0_ERR_gc = (0xF1<<0),
EVSYS_CHMUX_TCF0_CCA_gc = (0xF4<<0),
EVSYS_CHMUX_TCF0_CCB_gc = (0xF5<<0),
EVSYS_CHMUX_TCF0_CCC_gc = (0xF6<<0),
EVSYS_CHMUX_TCF0_CCD_gc = (0xF7<<0),
EVSYS_CHMUX_TCF1_OVF_gc = (0xF8<<0),
EVSYS_CHMUX_TCF1_ERR_gc = (0xF9<<0),
EVSYS_CHMUX_TCF1_CCA_gc = (0xFC<<0),
EVSYS_CHMUX_TCF1_CCB_gc = (0xFD<<0),
EVSYS_CHMUX_OFF_gc = (0x00<<0),
EVSYS_CHMUX_RTC_OVF_gc = (0x08<<0),
EVSYS_CHMUX_RTC_CMP_gc = (0x09<<0),
EVSYS_CHMUX_ACA_CH0_gc = (0x10<<0),
EVSYS_CHMUX_ACA_CH1_gc = (0x11<<0),
EVSYS_CHMUX_ACA_WIN_gc = (0x12<<0),
EVSYS_CHMUX_ADCA_CH0_gc = (0x20<<0),
EVSYS_CHMUX_PORTA_PIN0_gc = (0x50<<0),
EVSYS_CHMUX_PORTA_PIN1_gc = (0x51<<0),
EVSYS_CHMUX_PORTA_PIN2_gc = (0x52<<0),
EVSYS_CHMUX_PORTA_PIN3_gc = (0x53<<0),
EVSYS_CHMUX_PORTA_PIN4_gc = (0x54<<0),
EVSYS_CHMUX_PORTA_PIN5_gc = (0x55<<0),
EVSYS_CHMUX_PORTA_PIN6_gc = (0x56<<0),
EVSYS_CHMUX_PORTA_PIN7_gc = (0x57<<0),
EVSYS_CHMUX_PORTB_PIN0_gc = (0x58<<0),
EVSYS_CHMUX_PORTB_PIN1_gc = (0x59<<0),
EVSYS_CHMUX_PORTB_PIN2_gc = (0x5A<<0),
EVSYS_CHMUX_PORTB_PIN3_gc = (0x5B<<0),
EVSYS_CHMUX_PORTB_PIN4_gc = (0x5C<<0),
EVSYS_CHMUX_PORTB_PIN5_gc = (0x5D<<0),
EVSYS_CHMUX_PORTB_PIN6_gc = (0x5E<<0),
EVSYS_CHMUX_PORTB_PIN7_gc = (0x5F<<0),
EVSYS_CHMUX_PORTC_PIN0_gc = (0x60<<0),
EVSYS_CHMUX_PORTC_PIN1_gc = (0x61<<0),
EVSYS_CHMUX_PORTC_PIN2_gc = (0x62<<0),
EVSYS_CHMUX_PORTC_PIN3_gc = (0x63<<0),
EVSYS_CHMUX_PORTC_PIN4_gc = (0x64<<0),
EVSYS_CHMUX_PORTC_PIN5_gc = (0x65<<0),
EVSYS_CHMUX_PORTC_PIN6_gc = (0x66<<0),
EVSYS_CHMUX_PORTC_PIN7_gc = (0x67<<0),
EVSYS_CHMUX_PORTD_PIN0_gc = (0x68<<0),
EVSYS_CHMUX_PORTD_PIN1_gc = (0x69<<0),
EVSYS_CHMUX_PORTD_PIN2_gc = (0x6A<<0),
EVSYS_CHMUX_PORTD_PIN3_gc = (0x6B<<0),
EVSYS_CHMUX_PORTD_PIN4_gc = (0x6C<<0),
EVSYS_CHMUX_PORTD_PIN5_gc = (0x6D<<0),
EVSYS_CHMUX_PORTD_PIN6_gc = (0x6E<<0),
EVSYS_CHMUX_PORTD_PIN7_gc = (0x6F<<0),
EVSYS_CHMUX_PORTE_PIN0_gc = (0x70<<0),
EVSYS_CHMUX_PORTE_PIN1_gc = (0x71<<0),
EVSYS_CHMUX_PORTE_PIN2_gc = (0x72<<0),
EVSYS_CHMUX_PORTE_PIN3_gc = (0x73<<0),
EVSYS_CHMUX_PORTE_PIN4_gc = (0x74<<0),
EVSYS_CHMUX_PORTE_PIN5_gc = (0x75<<0),
EVSYS_CHMUX_PORTE_PIN6_gc = (0x76<<0),
EVSYS_CHMUX_PORTE_PIN7_gc = (0x77<<0),
EVSYS_CHMUX_PORTF_PIN0_gc = (0x78<<0),
EVSYS_CHMUX_PORTF_PIN1_gc = (0x79<<0),
EVSYS_CHMUX_PORTF_PIN2_gc = (0x7A<<0),
EVSYS_CHMUX_PORTF_PIN3_gc = (0x7B<<0),
EVSYS_CHMUX_PORTF_PIN4_gc = (0x7C<<0),
EVSYS_CHMUX_PORTF_PIN5_gc = (0x7D<<0),
EVSYS_CHMUX_PORTF_PIN6_gc = (0x7E<<0),
EVSYS_CHMUX_PORTF_PIN7_gc = (0x7F<<0),
EVSYS_CHMUX_PRESCALER_1_gc = (0x80<<0),
EVSYS_CHMUX_PRESCALER_2_gc = (0x81<<0),
EVSYS_CHMUX_PRESCALER_4_gc = (0x82<<0),
EVSYS_CHMUX_PRESCALER_8_gc = (0x83<<0),
EVSYS_CHMUX_PRESCALER_16_gc = (0x84<<0),
EVSYS_CHMUX_PRESCALER_32_gc = (0x85<<0),
EVSYS_CHMUX_PRESCALER_64_gc = (0x86<<0),
EVSYS_CHMUX_PRESCALER_128_gc = (0x87<<0),
EVSYS_CHMUX_PRESCALER_256_gc = (0x88<<0),
EVSYS_CHMUX_PRESCALER_512_gc = (0x89<<0),
EVSYS_CHMUX_PRESCALER_1024_gc = (0x8A<<0),
EVSYS_CHMUX_PRESCALER_2048_gc = (0x8B<<0),
EVSYS_CHMUX_PRESCALER_4096_gc = (0x8C<<0),
EVSYS_CHMUX_PRESCALER_8192_gc = (0x8D<<0),
EVSYS_CHMUX_PRESCALER_16384_gc = (0x8E<<0),
EVSYS_CHMUX_PRESCALER_32768_gc = (0x8F<<0),
EVSYS_CHMUX_TCC0_OVF_gc = (0xC0<<0),
EVSYS_CHMUX_TCC0_ERR_gc = (0xC1<<0),
EVSYS_CHMUX_TCC0_CCA_gc = (0xC4<<0),
EVSYS_CHMUX_TCC0_CCB_gc = (0xC5<<0),
EVSYS_CHMUX_TCC0_CCC_gc = (0xC6<<0),
EVSYS_CHMUX_TCC0_CCD_gc = (0xC7<<0),
EVSYS_CHMUX_TCC1_OVF_gc = (0xC8<<0),
EVSYS_CHMUX_TCC1_ERR_gc = (0xC9<<0),
EVSYS_CHMUX_TCC1_CCA_gc = (0xCC<<0),
EVSYS_CHMUX_TCC1_CCB_gc = (0xCD<<0),
EVSYS_CHMUX_TCD0_OVF_gc = (0xD0<<0),
EVSYS_CHMUX_TCD0_ERR_gc = (0xD1<<0),
EVSYS_CHMUX_TCD0_CCA_gc = (0xD4<<0),
EVSYS_CHMUX_TCD0_CCB_gc = (0xD5<<0),
EVSYS_CHMUX_TCD0_CCC_gc = (0xD6<<0),
EVSYS_CHMUX_TCD0_CCD_gc = (0xD7<<0),
EVSYS_CHMUX_TCD1_OVF_gc = (0xD8<<0),
EVSYS_CHMUX_TCD1_ERR_gc = (0xD9<<0),
EVSYS_CHMUX_TCD1_CCA_gc = (0xDC<<0),
EVSYS_CHMUX_TCD1_CCB_gc = (0xDD<<0),
EVSYS_CHMUX_TCE0_OVF_gc = (0xE0<<0),
EVSYS_CHMUX_TCE0_ERR_gc = (0xE1<<0),
EVSYS_CHMUX_TCE0_CCA_gc = (0xE4<<0),
EVSYS_CHMUX_TCE0_CCB_gc = (0xE5<<0),
EVSYS_CHMUX_TCE0_CCC_gc = (0xE6<<0),
EVSYS_CHMUX_TCE0_CCD_gc = (0xE7<<0),
EVSYS_CHMUX_TCE1_OVF_gc = (0xE8<<0),
EVSYS_CHMUX_TCE1_ERR_gc = (0xE9<<0),
EVSYS_CHMUX_TCE1_CCA_gc = (0xEC<<0),
EVSYS_CHMUX_TCE1_CCB_gc = (0xED<<0),
EVSYS_CHMUX_TCF0_OVF_gc = (0xF0<<0),
EVSYS_CHMUX_TCF0_ERR_gc = (0xF1<<0),
EVSYS_CHMUX_TCF0_CCA_gc = (0xF4<<0),
EVSYS_CHMUX_TCF0_CCB_gc = (0xF5<<0),
EVSYS_CHMUX_TCF0_CCC_gc = (0xF6<<0),
EVSYS_CHMUX_TCF0_CCD_gc = (0xF7<<0),
EVSYS_CHMUX_TCF1_OVF_gc = (0xF8<<0),
EVSYS_CHMUX_TCF1_ERR_gc = (0xF9<<0),
EVSYS_CHMUX_TCF1_CCA_gc = (0xFC<<0),
EVSYS_CHMUX_TCF1_CCB_gc = (0xFD<<0),
EVSYS_CHMUX_OFF_gc = (0x00<<0),
EVSYS_CHMUX_RTC_OVF_gc = (0x08<<0),
EVSYS_CHMUX_RTC_CMP_gc = (0x09<<0),
EVSYS_CHMUX_ACA_CH0_gc = (0x10<<0),
EVSYS_CHMUX_ACA_CH1_gc = (0x11<<0),
EVSYS_CHMUX_ACA_WIN_gc = (0x12<<0),
EVSYS_CHMUX_ACB_CH0_gc = (0x13<<0),
EVSYS_CHMUX_ACB_CH1_gc = (0x14<<0),
EVSYS_CHMUX_ACB_WIN_gc = (0x15<<0),
EVSYS_CHMUX_ADCA_CH0_gc = (0x20<<0),
EVSYS_CHMUX_ADCA_CH1_gc = (0x21<<0),
EVSYS_CHMUX_ADCA_CH2_gc = (0x22<<0),
EVSYS_CHMUX_ADCA_CH3_gc = (0x23<<0),
EVSYS_CHMUX_ADCB_CH0_gc = (0x24<<0),
EVSYS_CHMUX_ADCB_CH1_gc = (0x25<<0),
EVSYS_CHMUX_ADCB_CH2_gc = (0x26<<0),
EVSYS_CHMUX_ADCB_CH3_gc = (0x27<<0),
EVSYS_CHMUX_PORTA_PIN0_gc = (0x50<<0),
EVSYS_CHMUX_PORTA_PIN1_gc = (0x51<<0),
EVSYS_CHMUX_PORTA_PIN2_gc = (0x52<<0),
EVSYS_CHMUX_PORTA_PIN3_gc = (0x53<<0),
EVSYS_CHMUX_PORTA_PIN4_gc = (0x54<<0),
EVSYS_CHMUX_PORTA_PIN5_gc = (0x55<<0),
EVSYS_CHMUX_PORTA_PIN6_gc = (0x56<<0),
EVSYS_CHMUX_PORTA_PIN7_gc = (0x57<<0),
EVSYS_CHMUX_PORTB_PIN0_gc = (0x58<<0),
EVSYS_CHMUX_PORTB_PIN1_gc = (0x59<<0),
EVSYS_CHMUX_PORTB_PIN2_gc = (0x5A<<0),
EVSYS_CHMUX_PORTB_PIN3_gc = (0x5B<<0),
EVSYS_CHMUX_PORTB_PIN4_gc = (0x5C<<0),
EVSYS_CHMUX_PORTB_PIN5_gc = (0x5D<<0),
EVSYS_CHMUX_PORTB_PIN6_gc = (0x5E<<0),
EVSYS_CHMUX_PORTB_PIN7_gc = (0x5F<<0),
EVSYS_CHMUX_PORTC_PIN0_gc = (0x60<<0),
EVSYS_CHMUX_PORTC_PIN1_gc = (0x61<<0),
EVSYS_CHMUX_PORTC_PIN2_gc = (0x62<<0),
EVSYS_CHMUX_PORTC_PIN3_gc = (0x63<<0),
EVSYS_CHMUX_PORTC_PIN4_gc = (0x64<<0),
EVSYS_CHMUX_PORTC_PIN5_gc = (0x65<<0),
EVSYS_CHMUX_PORTC_PIN6_gc = (0x66<<0),
EVSYS_CHMUX_PORTC_PIN7_gc = (0x67<<0),
EVSYS_CHMUX_PORTD_PIN0_gc = (0x68<<0),
EVSYS_CHMUX_PORTD_PIN1_gc = (0x69<<0),
EVSYS_CHMUX_PORTD_PIN2_gc = (0x6A<<0),
EVSYS_CHMUX_PORTD_PIN3_gc = (0x6B<<0),
EVSYS_CHMUX_PORTD_PIN4_gc = (0x6C<<0),
EVSYS_CHMUX_PORTD_PIN5_gc = (0x6D<<0),
EVSYS_CHMUX_PORTD_PIN6_gc = (0x6E<<0),
EVSYS_CHMUX_PORTD_PIN7_gc = (0x6F<<0),
EVSYS_CHMUX_PORTE_PIN0_gc = (0x70<<0),
EVSYS_CHMUX_PORTE_PIN1_gc = (0x71<<0),
EVSYS_CHMUX_PORTE_PIN2_gc = (0x72<<0),
EVSYS_CHMUX_PORTE_PIN3_gc = (0x73<<0),
EVSYS_CHMUX_PORTE_PIN4_gc = (0x74<<0),
EVSYS_CHMUX_PORTE_PIN5_gc = (0x75<<0),
EVSYS_CHMUX_PORTE_PIN6_gc = (0x76<<0),
EVSYS_CHMUX_PORTE_PIN7_gc = (0x77<<0),
EVSYS_CHMUX_PORTF_PIN0_gc = (0x78<<0),
EVSYS_CHMUX_PORTF_PIN1_gc = (0x79<<0),
EVSYS_CHMUX_PORTF_PIN2_gc = (0x7A<<0),
EVSYS_CHMUX_PORTF_PIN3_gc = (0x7B<<0),
EVSYS_CHMUX_PORTF_PIN4_gc = (0x7C<<0),
EVSYS_CHMUX_PORTF_PIN5_gc = (0x7D<<0),
EVSYS_CHMUX_PORTF_PIN6_gc = (0x7E<<0),
EVSYS_CHMUX_PORTF_PIN7_gc = (0x7F<<0),
EVSYS_CHMUX_PRESCALER_1_gc = (0x80<<0),
EVSYS_CHMUX_PRESCALER_2_gc = (0x81<<0),
EVSYS_CHMUX_PRESCALER_4_gc = (0x82<<0),
EVSYS_CHMUX_PRESCALER_8_gc = (0x83<<0),
EVSYS_CHMUX_PRESCALER_16_gc = (0x84<<0),
EVSYS_CHMUX_PRESCALER_32_gc = (0x85<<0),
EVSYS_CHMUX_PRESCALER_64_gc = (0x86<<0),
EVSYS_CHMUX_PRESCALER_128_gc = (0x87<<0),
EVSYS_CHMUX_PRESCALER_256_gc = (0x88<<0),
EVSYS_CHMUX_PRESCALER_512_gc = (0x89<<0),
EVSYS_CHMUX_PRESCALER_1024_gc = (0x8A<<0),
EVSYS_CHMUX_PRESCALER_2048_gc = (0x8B<<0),
EVSYS_CHMUX_PRESCALER_4096_gc = (0x8C<<0),
EVSYS_CHMUX_PRESCALER_8192_gc = (0x8D<<0),
EVSYS_CHMUX_PRESCALER_16384_gc = (0x8E<<0),
EVSYS_CHMUX_PRESCALER_32768_gc = (0x8F<<0),
EVSYS_CHMUX_TCC0_OVF_gc = (0xC0<<0),
EVSYS_CHMUX_TCC0_ERR_gc = (0xC1<<0),
EVSYS_CHMUX_TCC0_CCA_gc = (0xC4<<0),
EVSYS_CHMUX_TCC0_CCB_gc = (0xC5<<0),
EVSYS_CHMUX_TCC0_CCC_gc = (0xC6<<0),
EVSYS_CHMUX_TCC0_CCD_gc = (0xC7<<0),
EVSYS_CHMUX_TCC1_OVF_gc = (0xC8<<0),
EVSYS_CHMUX_TCC1_ERR_gc = (0xC9<<0),
EVSYS_CHMUX_TCC1_CCA_gc = (0xCC<<0),
EVSYS_CHMUX_TCC1_CCB_gc = (0xCD<<0),
EVSYS_CHMUX_TCD0_OVF_gc = (0xD0<<0),
EVSYS_CHMUX_TCD0_ERR_gc = (0xD1<<0),
EVSYS_CHMUX_TCD0_CCA_gc = (0xD4<<0),
EVSYS_CHMUX_TCD0_CCB_gc = (0xD5<<0),
EVSYS_CHMUX_TCD0_CCC_gc = (0xD6<<0),
EVSYS_CHMUX_TCD0_CCD_gc = (0xD7<<0),
EVSYS_CHMUX_TCD1_OVF_gc = (0xD8<<0),
EVSYS_CHMUX_TCD1_ERR_gc = (0xD9<<0),
EVSYS_CHMUX_TCD1_CCA_gc = (0xDC<<0),
EVSYS_CHMUX_TCD1_CCB_gc = (0xDD<<0),
EVSYS_CHMUX_TCE0_OVF_gc = (0xE0<<0),
EVSYS_CHMUX_TCE0_ERR_gc = (0xE1<<0),
EVSYS_CHMUX_TCE0_CCA_gc = (0xE4<<0),
EVSYS_CHMUX_TCE0_CCB_gc = (0xE5<<0),
EVSYS_CHMUX_TCE0_CCC_gc = (0xE6<<0),
EVSYS_CHMUX_TCE0_CCD_gc = (0xE7<<0),
EVSYS_CHMUX_TCE1_OVF_gc = (0xE8<<0),
EVSYS_CHMUX_TCE1_ERR_gc = (0xE9<<0),
EVSYS_CHMUX_TCE1_CCA_gc = (0xEC<<0),
EVSYS_CHMUX_TCE1_CCB_gc = (0xED<<0),
EVSYS_CHMUX_TCF0_OVF_gc = (0xF0<<0),
EVSYS_CHMUX_TCF0_ERR_gc = (0xF1<<0),
EVSYS_CHMUX_TCF0_CCA_gc = (0xF4<<0),
EVSYS_CHMUX_TCF0_CCB_gc = (0xF5<<0),
EVSYS_CHMUX_TCF0_CCC_gc = (0xF6<<0),
EVSYS_CHMUX_TCF0_CCD_gc = (0xF7<<0),
EVSYS_CHMUX_TCF1_OVF_gc = (0xF8<<0),
EVSYS_CHMUX_TCF1_ERR_gc = (0xF9<<0),
EVSYS_CHMUX_TCF1_CCA_gc = (0xFC<<0),
EVSYS_CHMUX_TCF1_CCB_gc = (0xFD<<0),
EVSYS_CHMUX_OFF_gc = (0x00<<0),
EVSYS_CHMUX_RTC_OVF_gc = (0x08<<0),
EVSYS_CHMUX_RTC_CMP_gc = (0x09<<0),
EVSYS_CHMUX_ACA_CH0_gc = (0x10<<0),
EVSYS_CHMUX_ACA_CH1_gc = (0x11<<0),
EVSYS_CHMUX_ACA_WIN_gc = (0x12<<0),
EVSYS_CHMUX_ACB_CH0_gc = (0x13<<0),
EVSYS_CHMUX_ACB_CH1_gc = (0x14<<0),
EVSYS_CHMUX_ACB_WIN_gc = (0x15<<0),
EVSYS_CHMUX_ADCA_CH0_gc = (0x20<<0),
EVSYS_CHMUX_ADCA_CH1_gc = (0x21<<0),
EVSYS_CHMUX_ADCA_CH2_gc = (0x22<<0),
EVSYS_CHMUX_ADCA_CH3_gc = (0x23<<0),
EVSYS_CHMUX_ADCB_CH0_gc = (0x24<<0),
EVSYS_CHMUX_ADCB_CH1_gc = (0x25<<0),
EVSYS_CHMUX_ADCB_CH2_gc = (0x26<<0),
EVSYS_CHMUX_ADCB_CH3_gc = (0x27<<0),
EVSYS_CHMUX_PORTA_PIN0_gc = (0x50<<0),
EVSYS_CHMUX_PORTA_PIN1_gc = (0x51<<0),
EVSYS_CHMUX_PORTA_PIN2_gc = (0x52<<0),
EVSYS_CHMUX_PORTA_PIN3_gc = (0x53<<0),
EVSYS_CHMUX_PORTA_PIN4_gc = (0x54<<0),
EVSYS_CHMUX_PORTA_PIN5_gc = (0x55<<0),
EVSYS_CHMUX_PORTA_PIN6_gc = (0x56<<0),
EVSYS_CHMUX_PORTA_PIN7_gc = (0x57<<0),
EVSYS_CHMUX_PORTB_PIN0_gc = (0x58<<0),
EVSYS_CHMUX_PORTB_PIN1_gc = (0x59<<0),
EVSYS_CHMUX_PORTB_PIN2_gc = (0x5A<<0),
EVSYS_CHMUX_PORTB_PIN3_gc = (0x5B<<0),
EVSYS_CHMUX_PORTB_PIN4_gc = (0x5C<<0),
EVSYS_CHMUX_PORTB_PIN5_gc = (0x5D<<0),
EVSYS_CHMUX_PORTB_PIN6_gc = (0x5E<<0),
EVSYS_CHMUX_PORTB_PIN7_gc = (0x5F<<0),
EVSYS_CHMUX_PORTC_PIN0_gc = (0x60<<0),
EVSYS_CHMUX_PORTC_PIN1_gc = (0x61<<0),
EVSYS_CHMUX_PORTC_PIN2_gc = (0x62<<0),
EVSYS_CHMUX_PORTC_PIN3_gc = (0x63<<0),
EVSYS_CHMUX_PORTC_PIN4_gc = (0x64<<0),
EVSYS_CHMUX_PORTC_PIN5_gc = (0x65<<0),
EVSYS_CHMUX_PORTC_PIN6_gc = (0x66<<0),
EVSYS_CHMUX_PORTC_PIN7_gc = (0x67<<0),
EVSYS_CHMUX_PORTD_PIN0_gc = (0x68<<0),
EVSYS_CHMUX_PORTD_PIN1_gc = (0x69<<0),
EVSYS_CHMUX_PORTD_PIN2_gc = (0x6A<<0),
EVSYS_CHMUX_PORTD_PIN3_gc = (0x6B<<0),
EVSYS_CHMUX_PORTD_PIN4_gc = (0x6C<<0),
EVSYS_CHMUX_PORTD_PIN5_gc = (0x6D<<0),
EVSYS_CHMUX_PORTD_PIN6_gc = (0x6E<<0),
EVSYS_CHMUX_PORTD_PIN7_gc = (0x6F<<0),
EVSYS_CHMUX_PORTE_PIN0_gc = (0x70<<0),
EVSYS_CHMUX_PORTE_PIN1_gc = (0x71<<0),
EVSYS_CHMUX_PORTE_PIN2_gc = (0x72<<0),
EVSYS_CHMUX_PORTE_PIN3_gc = (0x73<<0),
EVSYS_CHMUX_PORTE_PIN4_gc = (0x74<<0),
EVSYS_CHMUX_PORTE_PIN5_gc = (0x75<<0),
EVSYS_CHMUX_PORTE_PIN6_gc = (0x76<<0),
EVSYS_CHMUX_PORTE_PIN7_gc = (0x77<<0),
EVSYS_CHMUX_PORTF_PIN0_gc = (0x78<<0),
EVSYS_CHMUX_PORTF_PIN1_gc = (0x79<<0),
EVSYS_CHMUX_PORTF_PIN2_gc = (0x7A<<0),
EVSYS_CHMUX_PORTF_PIN3_gc = (0x7B<<0),
EVSYS_CHMUX_PORTF_PIN4_gc = (0x7C<<0),
EVSYS_CHMUX_PORTF_PIN5_gc = (0x7D<<0),
EVSYS_CHMUX_PORTF_PIN6_gc = (0x7E<<0),
EVSYS_CHMUX_PORTF_PIN7_gc = (0x7F<<0),
EVSYS_CHMUX_PRESCALER_1_gc = (0x80<<0),
EVSYS_CHMUX_PRESCALER_2_gc = (0x81<<0),
EVSYS_CHMUX_PRESCALER_4_gc = (0x82<<0),
EVSYS_CHMUX_PRESCALER_8_gc = (0x83<<0),
EVSYS_CHMUX_PRESCALER_16_gc = (0x84<<0),
EVSYS_CHMUX_PRESCALER_32_gc = (0x85<<0),
EVSYS_CHMUX_PRESCALER_64_gc = (0x86<<0),
EVSYS_CHMUX_PRESCALER_128_gc = (0x87<<0),
EVSYS_CHMUX_PRESCALER_256_gc = (0x88<<0),
EVSYS_CHMUX_PRESCALER_512_gc = (0x89<<0),
EVSYS_CHMUX_PRESCALER_1024_gc = (0x8A<<0),
EVSYS_CHMUX_PRESCALER_2048_gc = (0x8B<<0),
EVSYS_CHMUX_PRESCALER_4096_gc = (0x8C<<0),
EVSYS_CHMUX_PRESCALER_8192_gc = (0x8D<<0),
EVSYS_CHMUX_PRESCALER_16384_gc = (0x8E<<0),
EVSYS_CHMUX_PRESCALER_32768_gc = (0x8F<<0),
EVSYS_CHMUX_TCC0_OVF_gc = (0xC0<<0),
EVSYS_CHMUX_TCC0_ERR_gc = (0xC1<<0),
EVSYS_CHMUX_TCC0_CCA_gc = (0xC4<<0),
EVSYS_CHMUX_TCC0_CCB_gc = (0xC5<<0),
EVSYS_CHMUX_TCC0_CCC_gc = (0xC6<<0),
EVSYS_CHMUX_TCC0_CCD_gc = (0xC7<<0),
EVSYS_CHMUX_TCC1_OVF_gc = (0xC8<<0),
EVSYS_CHMUX_TCC1_ERR_gc = (0xC9<<0),
EVSYS_CHMUX_TCC1_CCA_gc = (0xCC<<0),
EVSYS_CHMUX_TCC1_CCB_gc = (0xCD<<0),
EVSYS_CHMUX_TCD0_OVF_gc = (0xD0<<0),
EVSYS_CHMUX_TCD0_ERR_gc = (0xD1<<0),
EVSYS_CHMUX_TCD0_CCA_gc = (0xD4<<0),
EVSYS_CHMUX_TCD0_CCB_gc = (0xD5<<0),
EVSYS_CHMUX_TCD0_CCC_gc = (0xD6<<0),
EVSYS_CHMUX_TCD0_CCD_gc = (0xD7<<0),
EVSYS_CHMUX_TCD1_OVF_gc = (0xD8<<0),
EVSYS_CHMUX_TCD1_ERR_gc = (0xD9<<0),
EVSYS_CHMUX_TCD1_CCA_gc = (0xDC<<0),
EVSYS_CHMUX_TCD1_CCB_gc = (0xDD<<0),
EVSYS_CHMUX_TCE0_OVF_gc = (0xE0<<0),
EVSYS_CHMUX_TCE0_ERR_gc = (0xE1<<0),
EVSYS_CHMUX_TCE0_CCA_gc = (0xE4<<0),
EVSYS_CHMUX_TCE0_CCB_gc = (0xE5<<0),
EVSYS_CHMUX_TCE0_CCC_gc = (0xE6<<0),
EVSYS_CHMUX_TCE0_CCD_gc = (0xE7<<0),
EVSYS_CHMUX_TCE1_OVF_gc = (0xE8<<0),
EVSYS_CHMUX_TCE1_ERR_gc = (0xE9<<0),
EVSYS_CHMUX_TCE1_CCA_gc = (0xEC<<0),
EVSYS_CHMUX_TCE1_CCB_gc = (0xED<<0),
EVSYS_CHMUX_TCF0_OVF_gc = (0xF0<<0),
EVSYS_CHMUX_TCF0_ERR_gc = (0xF1<<0),
EVSYS_CHMUX_TCF0_CCA_gc = (0xF4<<0),
EVSYS_CHMUX_TCF0_CCB_gc = (0xF5<<0),
EVSYS_CHMUX_TCF0_CCC_gc = (0xF6<<0),
EVSYS_CHMUX_TCF0_CCD_gc = (0xF7<<0),
EVSYS_CHMUX_TCF1_OVF_gc = (0xF8<<0),
EVSYS_CHMUX_TCF1_ERR_gc = (0xF9<<0),
EVSYS_CHMUX_TCF1_CCA_gc = (0xFC<<0),
EVSYS_CHMUX_TCF1_CCB_gc = (0xFD<<0),
EVSYS_CHMUX_OFF_gc = (0x00<<0),
EVSYS_CHMUX_RTC_OVF_gc = (0x08<<0),
EVSYS_CHMUX_RTC_CMP_gc = (0x09<<0),
EVSYS_CHMUX_ACA_CH0_gc = (0x10<<0),
EVSYS_CHMUX_ACA_CH1_gc = (0x11<<0),
EVSYS_CHMUX_ACA_WIN_gc = (0x12<<0),
EVSYS_CHMUX_ADCA_CH0_gc = (0x20<<0),
EVSYS_CHMUX_PORTA_PIN0_gc = (0x50<<0),
EVSYS_CHMUX_PORTA_PIN1_gc = (0x51<<0),
EVSYS_CHMUX_PORTA_PIN2_gc = (0x52<<0),
EVSYS_CHMUX_PORTA_PIN3_gc = (0x53<<0),
EVSYS_CHMUX_PORTA_PIN4_gc = (0x54<<0),
EVSYS_CHMUX_PORTA_PIN5_gc = (0x55<<0),
EVSYS_CHMUX_PORTA_PIN6_gc = (0x56<<0),
EVSYS_CHMUX_PORTA_PIN7_gc = (0x57<<0),
EVSYS_CHMUX_PORTB_PIN0_gc = (0x58<<0),
EVSYS_CHMUX_PORTB_PIN1_gc = (0x59<<0),
EVSYS_CHMUX_PORTB_PIN2_gc = (0x5A<<0),
EVSYS_CHMUX_PORTB_PIN3_gc = (0x5B<<0),
EVSYS_CHMUX_PORTB_PIN4_gc = (0x5C<<0),
EVSYS_CHMUX_PORTB_PIN5_gc = (0x5D<<0),
EVSYS_CHMUX_PORTB_PIN6_gc = (0x5E<<0),
EVSYS_CHMUX_PORTB_PIN7_gc = (0x5F<<0),
EVSYS_CHMUX_PORTC_PIN0_gc = (0x60<<0),
EVSYS_CHMUX_PORTC_PIN1_gc = (0x61<<0),
EVSYS_CHMUX_PORTC_PIN2_gc = (0x62<<0),
EVSYS_CHMUX_PORTC_PIN3_gc = (0x63<<0),
EVSYS_CHMUX_PORTC_PIN4_gc = (0x64<<0),
EVSYS_CHMUX_PORTC_PIN5_gc = (0x65<<0),
EVSYS_CHMUX_PORTC_PIN6_gc = (0x66<<0),
EVSYS_CHMUX_PORTC_PIN7_gc = (0x67<<0),
EVSYS_CHMUX_PORTD_PIN0_gc = (0x68<<0),
EVSYS_CHMUX_PORTD_PIN1_gc = (0x69<<0),
EVSYS_CHMUX_PORTD_PIN2_gc = (0x6A<<0),
EVSYS_CHMUX_PORTD_PIN3_gc = (0x6B<<0),
EVSYS_CHMUX_PORTD_PIN4_gc = (0x6C<<0),
EVSYS_CHMUX_PORTD_PIN5_gc = (0x6D<<0),
EVSYS_CHMUX_PORTD_PIN6_gc = (0x6E<<0),
EVSYS_CHMUX_PORTD_PIN7_gc = (0x6F<<0),
EVSYS_CHMUX_PORTE_PIN0_gc = (0x70<<0),
EVSYS_CHMUX_PORTE_PIN1_gc = (0x71<<0),
EVSYS_CHMUX_PORTE_PIN2_gc = (0x72<<0),
EVSYS_CHMUX_PORTE_PIN3_gc = (0x73<<0),
EVSYS_CHMUX_PORTE_PIN4_gc = (0x74<<0),
EVSYS_CHMUX_PORTE_PIN5_gc = (0x75<<0),
EVSYS_CHMUX_PORTE_PIN6_gc = (0x76<<0),
EVSYS_CHMUX_PORTE_PIN7_gc = (0x77<<0),
EVSYS_CHMUX_PORTF_PIN0_gc = (0x78<<0),
EVSYS_CHMUX_PORTF_PIN1_gc = (0x79<<0),
EVSYS_CHMUX_PORTF_PIN2_gc = (0x7A<<0),
EVSYS_CHMUX_PORTF_PIN3_gc = (0x7B<<0),
EVSYS_CHMUX_PORTF_PIN4_gc = (0x7C<<0),
EVSYS_CHMUX_PORTF_PIN5_gc = (0x7D<<0),
EVSYS_CHMUX_PORTF_PIN6_gc = (0x7E<<0),
EVSYS_CHMUX_PORTF_PIN7_gc = (0x7F<<0),
EVSYS_CHMUX_PRESCALER_1_gc = (0x80<<0),
EVSYS_CHMUX_PRESCALER_2_gc = (0x81<<0),
EVSYS_CHMUX_PRESCALER_4_gc = (0x82<<0),
EVSYS_CHMUX_PRESCALER_8_gc = (0x83<<0),
EVSYS_CHMUX_PRESCALER_16_gc = (0x84<<0),
EVSYS_CHMUX_PRESCALER_32_gc = (0x85<<0),
EVSYS_CHMUX_PRESCALER_64_gc = (0x86<<0),
EVSYS_CHMUX_PRESCALER_128_gc = (0x87<<0),
EVSYS_CHMUX_PRESCALER_256_gc = (0x88<<0),
EVSYS_CHMUX_PRESCALER_512_gc = (0x89<<0),
EVSYS_CHMUX_PRESCALER_1024_gc = (0x8A<<0),
EVSYS_CHMUX_PRESCALER_2048_gc = (0x8B<<0),
EVSYS_CHMUX_PRESCALER_4096_gc = (0x8C<<0),
EVSYS_CHMUX_PRESCALER_8192_gc = (0x8D<<0),
EVSYS_CHMUX_PRESCALER_16384_gc = (0x8E<<0),
EVSYS_CHMUX_PRESCALER_32768_gc = (0x8F<<0),
EVSYS_CHMUX_TCC0_OVF_gc = (0xC0<<0),
EVSYS_CHMUX_TCC0_ERR_gc = (0xC1<<0),
EVSYS_CHMUX_TCC0_CCA_gc = (0xC4<<0),
EVSYS_CHMUX_TCC0_CCB_gc = (0xC5<<0),
EVSYS_CHMUX_TCC0_CCC_gc = (0xC6<<0),
EVSYS_CHMUX_TCC0_CCD_gc = (0xC7<<0),
EVSYS_CHMUX_TCC1_OVF_gc = (0xC8<<0),
EVSYS_CHMUX_TCC1_ERR_gc = (0xC9<<0),
EVSYS_CHMUX_TCC1_CCA_gc = (0xCC<<0),
EVSYS_CHMUX_TCC1_CCB_gc = (0xCD<<0),
EVSYS_CHMUX_TCD0_OVF_gc = (0xD0<<0),
EVSYS_CHMUX_TCD0_ERR_gc = (0xD1<<0),
EVSYS_CHMUX_TCD0_CCA_gc = (0xD4<<0),
EVSYS_CHMUX_TCD0_CCB_gc = (0xD5<<0),
EVSYS_CHMUX_TCD0_CCC_gc = (0xD6<<0),
EVSYS_CHMUX_TCD0_CCD_gc = (0xD7<<0),
EVSYS_CHMUX_TCD1_OVF_gc = (0xD8<<0),
EVSYS_CHMUX_TCD1_ERR_gc = (0xD9<<0),
EVSYS_CHMUX_TCD1_CCA_gc = (0xDC<<0),
EVSYS_CHMUX_TCD1_CCB_gc = (0xDD<<0),
EVSYS_CHMUX_TCE0_OVF_gc = (0xE0<<0),
EVSYS_CHMUX_TCE0_ERR_gc = (0xE1<<0),
EVSYS_CHMUX_TCE0_CCA_gc = (0xE4<<0),
EVSYS_CHMUX_TCE0_CCB_gc = (0xE5<<0),
EVSYS_CHMUX_TCE0_CCC_gc = (0xE6<<0),
EVSYS_CHMUX_TCE0_CCD_gc = (0xE7<<0),
EVSYS_CHMUX_TCE1_OVF_gc = (0xE8<<0),
EVSYS_CHMUX_TCE1_ERR_gc = (0xE9<<0),
EVSYS_CHMUX_TCE1_CCA_gc = (0xEC<<0),
EVSYS_CHMUX_TCE1_CCB_gc = (0xED<<0),
EVSYS_CHMUX_TCF0_OVF_gc = (0xF0<<0),
EVSYS_CHMUX_TCF0_ERR_gc = (0xF1<<0),
EVSYS_CHMUX_TCF0_CCA_gc = (0xF4<<0),
EVSYS_CHMUX_TCF0_CCB_gc = (0xF5<<0),
EVSYS_CHMUX_TCF0_CCC_gc = (0xF6<<0),
EVSYS_CHMUX_TCF0_CCD_gc = (0xF7<<0),
EVSYS_CHMUX_TCF1_OVF_gc = (0xF8<<0),
EVSYS_CHMUX_TCF1_ERR_gc = (0xF9<<0),
EVSYS_CHMUX_TCF1_CCA_gc = (0xFC<<0),
EVSYS_CHMUX_TCF1_CCB_gc = (0xFD<<0),
EVSYS_CHMUX_OFF_gc = (0x00<<0),
EVSYS_CHMUX_RTC_OVF_gc = (0x08<<0),
EVSYS_CHMUX_RTC_CMP_gc = (0x09<<0),
EVSYS_CHMUX_ACA_CH0_gc = (0x10<<0),
EVSYS_CHMUX_ACA_CH1_gc = (0x11<<0),
EVSYS_CHMUX_ACA_WIN_gc = (0x12<<0),
EVSYS_CHMUX_ACB_CH0_gc = (0x13<<0),
EVSYS_CHMUX_ACB_CH1_gc = (0x14<<0),
EVSYS_CHMUX_ACB_WIN_gc = (0x15<<0),
EVSYS_CHMUX_ADCA_CH0_gc = (0x20<<0),
EVSYS_CHMUX_ADCA_CH1_gc = (0x21<<0),
EVSYS_CHMUX_ADCA_CH2_gc = (0x22<<0),
EVSYS_CHMUX_ADCA_CH3_gc = (0x23<<0),
EVSYS_CHMUX_ADCB_CH0_gc = (0x24<<0),
EVSYS_CHMUX_ADCB_CH1_gc = (0x25<<0),
EVSYS_CHMUX_ADCB_CH2_gc = (0x26<<0),
EVSYS_CHMUX_ADCB_CH3_gc = (0x27<<0),
EVSYS_CHMUX_PORTA_PIN0_gc = (0x50<<0),
EVSYS_CHMUX_PORTA_PIN1_gc = (0x51<<0),
EVSYS_CHMUX_PORTA_PIN2_gc = (0x52<<0),
EVSYS_CHMUX_PORTA_PIN3_gc = (0x53<<0),
EVSYS_CHMUX_PORTA_PIN4_gc = (0x54<<0),
EVSYS_CHMUX_PORTA_PIN5_gc = (0x55<<0),
EVSYS_CHMUX_PORTA_PIN6_gc = (0x56<<0),
EVSYS_CHMUX_PORTA_PIN7_gc = (0x57<<0),
EVSYS_CHMUX_PORTB_PIN0_gc = (0x58<<0),
EVSYS_CHMUX_PORTB_PIN1_gc = (0x59<<0),
EVSYS_CHMUX_PORTB_PIN2_gc = (0x5A<<0),
EVSYS_CHMUX_PORTB_PIN3_gc = (0x5B<<0),
EVSYS_CHMUX_PORTB_PIN4_gc = (0x5C<<0),
EVSYS_CHMUX_PORTB_PIN5_gc = (0x5D<<0),
EVSYS_CHMUX_PORTB_PIN6_gc = (0x5E<<0),
EVSYS_CHMUX_PORTB_PIN7_gc = (0x5F<<0),
EVSYS_CHMUX_PORTC_PIN0_gc = (0x60<<0),
EVSYS_CHMUX_PORTC_PIN1_gc = (0x61<<0),
EVSYS_CHMUX_PORTC_PIN2_gc = (0x62<<0),
EVSYS_CHMUX_PORTC_PIN3_gc = (0x63<<0),
EVSYS_CHMUX_PORTC_PIN4_gc = (0x64<<0),
EVSYS_CHMUX_PORTC_PIN5_gc = (0x65<<0),
EVSYS_CHMUX_PORTC_PIN6_gc = (0x66<<0),
EVSYS_CHMUX_PORTC_PIN7_gc = (0x67<<0),
EVSYS_CHMUX_PORTD_PIN0_gc = (0x68<<0),
EVSYS_CHMUX_PORTD_PIN1_gc = (0x69<<0),
EVSYS_CHMUX_PORTD_PIN2_gc = (0x6A<<0),
EVSYS_CHMUX_PORTD_PIN3_gc = (0x6B<<0),
EVSYS_CHMUX_PORTD_PIN4_gc = (0x6C<<0),
EVSYS_CHMUX_PORTD_PIN5_gc = (0x6D<<0),
EVSYS_CHMUX_PORTD_PIN6_gc = (0x6E<<0),
EVSYS_CHMUX_PORTD_PIN7_gc = (0x6F<<0),
EVSYS_CHMUX_PORTE_PIN0_gc = (0x70<<0),
EVSYS_CHMUX_PORTE_PIN1_gc = (0x71<<0),
EVSYS_CHMUX_PORTE_PIN2_gc = (0x72<<0),
EVSYS_CHMUX_PORTE_PIN3_gc = (0x73<<0),
EVSYS_CHMUX_PORTE_PIN4_gc = (0x74<<0),
EVSYS_CHMUX_PORTE_PIN5_gc = (0x75<<0),
EVSYS_CHMUX_PORTE_PIN6_gc = (0x76<<0),
EVSYS_CHMUX_PORTE_PIN7_gc = (0x77<<0),
EVSYS_CHMUX_PORTF_PIN0_gc = (0x78<<0),
EVSYS_CHMUX_PORTF_PIN1_gc = (0x79<<0),
EVSYS_CHMUX_PORTF_PIN2_gc = (0x7A<<0),
EVSYS_CHMUX_PORTF_PIN3_gc = (0x7B<<0),
EVSYS_CHMUX_PORTF_PIN4_gc = (0x7C<<0),
EVSYS_CHMUX_PORTF_PIN5_gc = (0x7D<<0),
EVSYS_CHMUX_PORTF_PIN6_gc = (0x7E<<0),
EVSYS_CHMUX_PORTF_PIN7_gc = (0x7F<<0),
EVSYS_CHMUX_PRESCALER_1_gc = (0x80<<0),
EVSYS_CHMUX_PRESCALER_2_gc = (0x81<<0),
EVSYS_CHMUX_PRESCALER_4_gc = (0x82<<0),
EVSYS_CHMUX_PRESCALER_8_gc = (0x83<<0),
EVSYS_CHMUX_PRESCALER_16_gc = (0x84<<0),
EVSYS_CHMUX_PRESCALER_32_gc = (0x85<<0),
EVSYS_CHMUX_PRESCALER_64_gc = (0x86<<0),
EVSYS_CHMUX_PRESCALER_128_gc = (0x87<<0),
EVSYS_CHMUX_PRESCALER_256_gc = (0x88<<0),
EVSYS_CHMUX_PRESCALER_512_gc = (0x89<<0),
EVSYS_CHMUX_PRESCALER_1024_gc = (0x8A<<0),
EVSYS_CHMUX_PRESCALER_2048_gc = (0x8B<<0),
EVSYS_CHMUX_PRESCALER_4096_gc = (0x8C<<0),
EVSYS_CHMUX_PRESCALER_8192_gc = (0x8D<<0),
EVSYS_CHMUX_PRESCALER_16384_gc = (0x8E<<0),
EVSYS_CHMUX_PRESCALER_32768_gc = (0x8F<<0),
EVSYS_CHMUX_TCC0_OVF_gc = (0xC0<<0),
EVSYS_CHMUX_TCC0_ERR_gc = (0xC1<<0),
EVSYS_CHMUX_TCC0_CCA_gc = (0xC4<<0),
EVSYS_CHMUX_TCC0_CCB_gc = (0xC5<<0),
EVSYS_CHMUX_TCC0_CCC_gc = (0xC6<<0),
EVSYS_CHMUX_TCC0_CCD_gc = (0xC7<<0),
EVSYS_CHMUX_TCC1_OVF_gc = (0xC8<<0),
EVSYS_CHMUX_TCC1_ERR_gc = (0xC9<<0),
EVSYS_CHMUX_TCC1_CCA_gc = (0xCC<<0),
EVSYS_CHMUX_TCC1_CCB_gc = (0xCD<<0),
EVSYS_CHMUX_TCD0_OVF_gc = (0xD0<<0),
EVSYS_CHMUX_TCD0_ERR_gc = (0xD1<<0),
EVSYS_CHMUX_TCD0_CCA_gc = (0xD4<<0),
EVSYS_CHMUX_TCD0_CCB_gc = (0xD5<<0),
EVSYS_CHMUX_TCD0_CCC_gc = (0xD6<<0),
EVSYS_CHMUX_TCD0_CCD_gc = (0xD7<<0),
EVSYS_CHMUX_TCD1_OVF_gc = (0xD8<<0),
EVSYS_CHMUX_TCD1_ERR_gc = (0xD9<<0),
EVSYS_CHMUX_TCD1_CCA_gc = (0xDC<<0),
EVSYS_CHMUX_TCD1_CCB_gc = (0xDD<<0),
EVSYS_CHMUX_TCE0_OVF_gc = (0xE0<<0),
EVSYS_CHMUX_TCE0_ERR_gc = (0xE1<<0),
EVSYS_CHMUX_TCE0_CCA_gc = (0xE4<<0),
EVSYS_CHMUX_TCE0_CCB_gc = (0xE5<<0),
EVSYS_CHMUX_TCE0_CCC_gc = (0xE6<<0),
EVSYS_CHMUX_TCE0_CCD_gc = (0xE7<<0),
EVSYS_CHMUX_TCE1_OVF_gc = (0xE8<<0),
EVSYS_CHMUX_TCE1_ERR_gc = (0xE9<<0),
EVSYS_CHMUX_TCE1_CCA_gc = (0xEC<<0),
EVSYS_CHMUX_TCE1_CCB_gc = (0xED<<0),
EVSYS_CHMUX_TCF0_OVF_gc = (0xF0<<0),
EVSYS_CHMUX_TCF0_ERR_gc = (0xF1<<0),
EVSYS_CHMUX_TCF0_CCA_gc = (0xF4<<0),
EVSYS_CHMUX_TCF0_CCB_gc = (0xF5<<0),
EVSYS_CHMUX_TCF0_CCC_gc = (0xF6<<0),
EVSYS_CHMUX_TCF0_CCD_gc = (0xF7<<0),
EVSYS_CHMUX_TCF1_OVF_gc = (0xF8<<0),
EVSYS_CHMUX_TCF1_ERR_gc = (0xF9<<0),
EVSYS_CHMUX_TCF1_CCA_gc = (0xFC<<0),
EVSYS_CHMUX_TCF1_CCB_gc = (0xFD<<0),
EVSYS_CHMUX_OFF_gc = (0x00<<0),
EVSYS_CHMUX_RTC_OVF_gc = (0x08<<0),
EVSYS_CHMUX_RTC_CMP_gc = (0x09<<0),
EVSYS_CHMUX_ACA_CH0_gc = (0x10<<0),
EVSYS_CHMUX_ACA_CH1_gc = (0x11<<0),
EVSYS_CHMUX_ACA_WIN_gc = (0x12<<0),
EVSYS_CHMUX_ADCA_CH0_gc = (0x20<<0),
EVSYS_CHMUX_PORTA_PIN0_gc = (0x50<<0),
EVSYS_CHMUX_PORTA_PIN1_gc = (0x51<<0),
EVSYS_CHMUX_PORTA_PIN2_gc = (0x52<<0),
EVSYS_CHMUX_PORTA_PIN3_gc = (0x53<<0),
EVSYS_CHMUX_PORTA_PIN4_gc = (0x54<<0),
EVSYS_CHMUX_PORTA_PIN5_gc = (0x55<<0),
EVSYS_CHMUX_PORTA_PIN6_gc = (0x56<<0),
EVSYS_CHMUX_PORTA_PIN7_gc = (0x57<<0),
EVSYS_CHMUX_PORTB_PIN0_gc = (0x58<<0),
EVSYS_CHMUX_PORTB_PIN1_gc = (0x59<<0),
EVSYS_CHMUX_PORTB_PIN2_gc = (0x5A<<0),
EVSYS_CHMUX_PORTB_PIN3_gc = (0x5B<<0),
EVSYS_CHMUX_PORTB_PIN4_gc = (0x5C<<0),
EVSYS_CHMUX_PORTB_PIN5_gc = (0x5D<<0),
EVSYS_CHMUX_PORTB_PIN6_gc = (0x5E<<0),
EVSYS_CHMUX_PORTB_PIN7_gc = (0x5F<<0),
EVSYS_CHMUX_PORTC_PIN0_gc = (0x60<<0),
EVSYS_CHMUX_PORTC_PIN1_gc = (0x61<<0),
EVSYS_CHMUX_PORTC_PIN2_gc = (0x62<<0),
EVSYS_CHMUX_PORTC_PIN3_gc = (0x63<<0),
EVSYS_CHMUX_PORTC_PIN4_gc = (0x64<<0),
EVSYS_CHMUX_PORTC_PIN5_gc = (0x65<<0),
EVSYS_CHMUX_PORTC_PIN6_gc = (0x66<<0),
EVSYS_CHMUX_PORTC_PIN7_gc = (0x67<<0),
EVSYS_CHMUX_PORTD_PIN0_gc = (0x68<<0),
EVSYS_CHMUX_PORTD_PIN1_gc = (0x69<<0),
EVSYS_CHMUX_PORTD_PIN2_gc = (0x6A<<0),
EVSYS_CHMUX_PORTD_PIN3_gc = (0x6B<<0),
EVSYS_CHMUX_PORTD_PIN4_gc = (0x6C<<0),
EVSYS_CHMUX_PORTD_PIN5_gc = (0x6D<<0),
EVSYS_CHMUX_PORTD_PIN6_gc = (0x6E<<0),
EVSYS_CHMUX_PORTD_PIN7_gc = (0x6F<<0),
EVSYS_CHMUX_PORTE_PIN0_gc = (0x70<<0),
EVSYS_CHMUX_PORTE_PIN1_gc = (0x71<<0),
EVSYS_CHMUX_PORTE_PIN2_gc = (0x72<<0),
EVSYS_CHMUX_PORTE_PIN3_gc = (0x73<<0),
EVSYS_CHMUX_PORTE_PIN4_gc = (0x74<<0),
EVSYS_CHMUX_PORTE_PIN5_gc = (0x75<<0),
EVSYS_CHMUX_PORTE_PIN6_gc = (0x76<<0),
EVSYS_CHMUX_PORTE_PIN7_gc = (0x77<<0),
EVSYS_CHMUX_PORTF_PIN0_gc = (0x78<<0),
EVSYS_CHMUX_PORTF_PIN1_gc = (0x79<<0),
EVSYS_CHMUX_PORTF_PIN2_gc = (0x7A<<0),
EVSYS_CHMUX_PORTF_PIN3_gc = (0x7B<<0),
EVSYS_CHMUX_PORTF_PIN4_gc = (0x7C<<0),
EVSYS_CHMUX_PORTF_PIN5_gc = (0x7D<<0),
EVSYS_CHMUX_PORTF_PIN6_gc = (0x7E<<0),
EVSYS_CHMUX_PORTF_PIN7_gc = (0x7F<<0),
EVSYS_CHMUX_PRESCALER_1_gc = (0x80<<0),
EVSYS_CHMUX_PRESCALER_2_gc = (0x81<<0),
EVSYS_CHMUX_PRESCALER_4_gc = (0x82<<0),
EVSYS_CHMUX_PRESCALER_8_gc = (0x83<<0),
EVSYS_CHMUX_PRESCALER_16_gc = (0x84<<0),
EVSYS_CHMUX_PRESCALER_32_gc = (0x85<<0),
EVSYS_CHMUX_PRESCALER_64_gc = (0x86<<0),
EVSYS_CHMUX_PRESCALER_128_gc = (0x87<<0),
EVSYS_CHMUX_PRESCALER_256_gc = (0x88<<0),
EVSYS_CHMUX_PRESCALER_512_gc = (0x89<<0),
EVSYS_CHMUX_PRESCALER_1024_gc = (0x8A<<0),
EVSYS_CHMUX_PRESCALER_2048_gc = (0x8B<<0),
EVSYS_CHMUX_PRESCALER_4096_gc = (0x8C<<0),
EVSYS_CHMUX_PRESCALER_8192_gc = (0x8D<<0),
EVSYS_CHMUX_PRESCALER_16384_gc = (0x8E<<0),
EVSYS_CHMUX_PRESCALER_32768_gc = (0x8F<<0),
EVSYS_CHMUX_TCC0_OVF_gc = (0xC0<<0),
EVSYS_CHMUX_TCC0_ERR_gc = (0xC1<<0),
EVSYS_CHMUX_TCC0_CCA_gc = (0xC4<<0),
EVSYS_CHMUX_TCC0_CCB_gc = (0xC5<<0),
EVSYS_CHMUX_TCC0_CCC_gc = (0xC6<<0),
EVSYS_CHMUX_TCC0_CCD_gc = (0xC7<<0),
EVSYS_CHMUX_TCC1_OVF_gc = (0xC8<<0),
EVSYS_CHMUX_TCC1_ERR_gc = (0xC9<<0),
EVSYS_CHMUX_TCC1_CCA_gc = (0xCC<<0),
EVSYS_CHMUX_TCC1_CCB_gc = (0xCD<<0),
EVSYS_CHMUX_TCD0_OVF_gc = (0xD0<<0),
EVSYS_CHMUX_TCD0_ERR_gc = (0xD1<<0),
EVSYS_CHMUX_TCD0_CCA_gc = (0xD4<<0),
EVSYS_CHMUX_TCD0_CCB_gc = (0xD5<<0),
EVSYS_CHMUX_TCD0_CCC_gc = (0xD6<<0),
EVSYS_CHMUX_TCD0_CCD_gc = (0xD7<<0),
EVSYS_CHMUX_TCD1_OVF_gc = (0xD8<<0),
EVSYS_CHMUX_TCD1_ERR_gc = (0xD9<<0),
EVSYS_CHMUX_TCD1_CCA_gc = (0xDC<<0),
EVSYS_CHMUX_TCD1_CCB_gc = (0xDD<<0),
EVSYS_CHMUX_TCE0_OVF_gc = (0xE0<<0),
EVSYS_CHMUX_TCE0_ERR_gc = (0xE1<<0),
EVSYS_CHMUX_TCE0_CCA_gc = (0xE4<<0),
EVSYS_CHMUX_TCE0_CCB_gc = (0xE5<<0),
EVSYS_CHMUX_TCE0_CCC_gc = (0xE6<<0),
EVSYS_CHMUX_TCE0_CCD_gc = (0xE7<<0),
EVSYS_CHMUX_TCE1_OVF_gc = (0xE8<<0),
EVSYS_CHMUX_TCE1_ERR_gc = (0xE9<<0),
EVSYS_CHMUX_TCE1_CCA_gc = (0xEC<<0),
EVSYS_CHMUX_TCE1_CCB_gc = (0xED<<0),
EVSYS_CHMUX_TCF0_OVF_gc = (0xF0<<0),
EVSYS_CHMUX_TCF0_ERR_gc = (0xF1<<0),
EVSYS_CHMUX_TCF0_CCA_gc = (0xF4<<0),
EVSYS_CHMUX_TCF0_CCB_gc = (0xF5<<0),
EVSYS_CHMUX_TCF0_CCC_gc = (0xF6<<0),
EVSYS_CHMUX_TCF0_CCD_gc = (0xF7<<0),
EVSYS_CHMUX_TCF1_OVF_gc = (0xF8<<0),
EVSYS_CHMUX_TCF1_ERR_gc = (0xF9<<0),
EVSYS_CHMUX_TCF1_CCA_gc = (0xFC<<0),
EVSYS_CHMUX_TCF1_CCB_gc = (0xFD<<0),
EVSYS_CHMUX_OFF_gc = (0x00<<0),
EVSYS_CHMUX_RTC_OVF_gc = (0x08<<0),
EVSYS_CHMUX_RTC_CMP_gc = (0x09<<0),
EVSYS_CHMUX_ACA_CH0_gc = (0x10<<0),
EVSYS_CHMUX_ACA_CH1_gc = (0x11<<0),
EVSYS_CHMUX_ACA_WIN_gc = (0x12<<0),
EVSYS_CHMUX_ACB_CH0_gc = (0x13<<0),
EVSYS_CHMUX_ACB_CH1_gc = (0x14<<0),
EVSYS_CHMUX_ACB_WIN_gc = (0x15<<0),
EVSYS_CHMUX_ADCA_CH0_gc = (0x20<<0),
EVSYS_CHMUX_ADCA_CH1_gc = (0x21<<0),
EVSYS_CHMUX_ADCA_CH2_gc = (0x22<<0),
EVSYS_CHMUX_ADCA_CH3_gc = (0x23<<0),
EVSYS_CHMUX_ADCB_CH0_gc = (0x24<<0),
EVSYS_CHMUX_ADCB_CH1_gc = (0x25<<0),
EVSYS_CHMUX_ADCB_CH2_gc = (0x26<<0),
EVSYS_CHMUX_ADCB_CH3_gc = (0x27<<0),
EVSYS_CHMUX_PORTA_PIN0_gc = (0x50<<0),
EVSYS_CHMUX_PORTA_PIN1_gc = (0x51<<0),
EVSYS_CHMUX_PORTA_PIN2_gc = (0x52<<0),
EVSYS_CHMUX_PORTA_PIN3_gc = (0x53<<0),
EVSYS_CHMUX_PORTA_PIN4_gc = (0x54<<0),
EVSYS_CHMUX_PORTA_PIN5_gc = (0x55<<0),
EVSYS_CHMUX_PORTA_PIN6_gc = (0x56<<0),
EVSYS_CHMUX_PORTA_PIN7_gc = (0x57<<0),
EVSYS_CHMUX_PORTB_PIN0_gc = (0x58<<0),
EVSYS_CHMUX_PORTB_PIN1_gc = (0x59<<0),
EVSYS_CHMUX_PORTB_PIN2_gc = (0x5A<<0),
EVSYS_CHMUX_PORTB_PIN3_gc = (0x5B<<0),
EVSYS_CHMUX_PORTB_PIN4_gc = (0x5C<<0),
EVSYS_CHMUX_PORTB_PIN5_gc = (0x5D<<0),
EVSYS_CHMUX_PORTB_PIN6_gc = (0x5E<<0),
EVSYS_CHMUX_PORTB_PIN7_gc = (0x5F<<0),
EVSYS_CHMUX_PORTC_PIN0_gc = (0x60<<0),
EVSYS_CHMUX_PORTC_PIN1_gc = (0x61<<0),
EVSYS_CHMUX_PORTC_PIN2_gc = (0x62<<0),
EVSYS_CHMUX_PORTC_PIN3_gc = (0x63<<0),
EVSYS_CHMUX_PORTC_PIN4_gc = (0x64<<0),
EVSYS_CHMUX_PORTC_PIN5_gc = (0x65<<0),
EVSYS_CHMUX_PORTC_PIN6_gc = (0x66<<0),
EVSYS_CHMUX_PORTC_PIN7_gc = (0x67<<0),
EVSYS_CHMUX_PORTD_PIN0_gc = (0x68<<0),
EVSYS_CHMUX_PORTD_PIN1_gc = (0x69<<0),
EVSYS_CHMUX_PORTD_PIN2_gc = (0x6A<<0),
EVSYS_CHMUX_PORTD_PIN3_gc = (0x6B<<0),
EVSYS_CHMUX_PORTD_PIN4_gc = (0x6C<<0),
EVSYS_CHMUX_PORTD_PIN5_gc = (0x6D<<0),
EVSYS_CHMUX_PORTD_PIN6_gc = (0x6E<<0),
EVSYS_CHMUX_PORTD_PIN7_gc = (0x6F<<0),
EVSYS_CHMUX_PORTE_PIN0_gc = (0x70<<0),
EVSYS_CHMUX_PORTE_PIN1_gc = (0x71<<0),
EVSYS_CHMUX_PORTE_PIN2_gc = (0x72<<0),
EVSYS_CHMUX_PORTE_PIN3_gc = (0x73<<0),
EVSYS_CHMUX_PORTE_PIN4_gc = (0x74<<0),
EVSYS_CHMUX_PORTE_PIN5_gc = (0x75<<0),
EVSYS_CHMUX_PORTE_PIN6_gc = (0x76<<0),
EVSYS_CHMUX_PORTE_PIN7_gc = (0x77<<0),
EVSYS_CHMUX_PORTF_PIN0_gc = (0x78<<0),
EVSYS_CHMUX_PORTF_PIN1_gc = (0x79<<0),
EVSYS_CHMUX_PORTF_PIN2_gc = (0x7A<<0),
EVSYS_CHMUX_PORTF_PIN3_gc = (0x7B<<0),
EVSYS_CHMUX_PORTF_PIN4_gc = (0x7C<<0),
EVSYS_CHMUX_PORTF_PIN5_gc = (0x7D<<0),
EVSYS_CHMUX_PORTF_PIN6_gc = (0x7E<<0),
EVSYS_CHMUX_PORTF_PIN7_gc = (0x7F<<0),
EVSYS_CHMUX_PRESCALER_1_gc = (0x80<<0),
EVSYS_CHMUX_PRESCALER_2_gc = (0x81<<0),
EVSYS_CHMUX_PRESCALER_4_gc = (0x82<<0),
EVSYS_CHMUX_PRESCALER_8_gc = (0x83<<0),
EVSYS_CHMUX_PRESCALER_16_gc = (0x84<<0),
EVSYS_CHMUX_PRESCALER_32_gc = (0x85<<0),
EVSYS_CHMUX_PRESCALER_64_gc = (0x86<<0),
EVSYS_CHMUX_PRESCALER_128_gc = (0x87<<0),
EVSYS_CHMUX_PRESCALER_256_gc = (0x88<<0),
EVSYS_CHMUX_PRESCALER_512_gc = (0x89<<0),
EVSYS_CHMUX_PRESCALER_1024_gc = (0x8A<<0),
EVSYS_CHMUX_PRESCALER_2048_gc = (0x8B<<0),
EVSYS_CHMUX_PRESCALER_4096_gc = (0x8C<<0),
EVSYS_CHMUX_PRESCALER_8192_gc = (0x8D<<0),
EVSYS_CHMUX_PRESCALER_16384_gc = (0x8E<<0),
EVSYS_CHMUX_PRESCALER_32768_gc = (0x8F<<0),
EVSYS_CHMUX_TCC0_OVF_gc = (0xC0<<0),
EVSYS_CHMUX_TCC0_ERR_gc = (0xC1<<0),
EVSYS_CHMUX_TCC0_CCA_gc = (0xC4<<0),
EVSYS_CHMUX_TCC0_CCB_gc = (0xC5<<0),
EVSYS_CHMUX_TCC0_CCC_gc = (0xC6<<0),
EVSYS_CHMUX_TCC0_CCD_gc = (0xC7<<0),
EVSYS_CHMUX_TCC1_OVF_gc = (0xC8<<0),
EVSYS_CHMUX_TCC1_ERR_gc = (0xC9<<0),
EVSYS_CHMUX_TCC1_CCA_gc = (0xCC<<0),
EVSYS_CHMUX_TCC1_CCB_gc = (0xCD<<0),
EVSYS_CHMUX_TCD0_OVF_gc = (0xD0<<0),
EVSYS_CHMUX_TCD0_ERR_gc = (0xD1<<0),
EVSYS_CHMUX_TCD0_CCA_gc = (0xD4<<0),
EVSYS_CHMUX_TCD0_CCB_gc = (0xD5<<0),
EVSYS_CHMUX_TCD0_CCC_gc = (0xD6<<0),
EVSYS_CHMUX_TCD0_CCD_gc = (0xD7<<0),
EVSYS_CHMUX_TCD1_OVF_gc = (0xD8<<0),
EVSYS_CHMUX_TCD1_ERR_gc = (0xD9<<0),
EVSYS_CHMUX_TCD1_CCA_gc = (0xDC<<0),
EVSYS_CHMUX_TCD1_CCB_gc = (0xDD<<0),
EVSYS_CHMUX_TCE0_OVF_gc = (0xE0<<0),
EVSYS_CHMUX_TCE0_ERR_gc = (0xE1<<0),
EVSYS_CHMUX_TCE0_CCA_gc = (0xE4<<0),
EVSYS_CHMUX_TCE0_CCB_gc = (0xE5<<0),
EVSYS_CHMUX_TCE0_CCC_gc = (0xE6<<0),
EVSYS_CHMUX_TCE0_CCD_gc = (0xE7<<0),
EVSYS_CHMUX_TCE1_OVF_gc = (0xE8<<0),
EVSYS_CHMUX_TCE1_ERR_gc = (0xE9<<0),
EVSYS_CHMUX_TCE1_CCA_gc = (0xEC<<0),
EVSYS_CHMUX_TCE1_CCB_gc = (0xED<<0),
EVSYS_CHMUX_TCF0_OVF_gc = (0xF0<<0),
EVSYS_CHMUX_TCF0_ERR_gc = (0xF1<<0),
EVSYS_CHMUX_TCF0_CCA_gc = (0xF4<<0),
EVSYS_CHMUX_TCF0_CCB_gc = (0xF5<<0),
EVSYS_CHMUX_TCF0_CCC_gc = (0xF6<<0),
EVSYS_CHMUX_TCF0_CCD_gc = (0xF7<<0),
EVSYS_CHMUX_TCF1_OVF_gc = (0xF8<<0),
EVSYS_CHMUX_TCF1_ERR_gc = (0xF9<<0),
EVSYS_CHMUX_TCF1_CCA_gc = (0xFC<<0),
EVSYS_CHMUX_TCF1_CCB_gc = (0xFD<<0),
EVSYS_CHMUX_OFF_gc = (0x00<<0),
EVSYS_CHMUX_RTC_OVF_gc = (0x08<<0),
EVSYS_CHMUX_RTC_CMP_gc = (0x09<<0),
EVSYS_CHMUX_ACA_CH0_gc = (0x10<<0),
EVSYS_CHMUX_ACA_CH1_gc = (0x11<<0),
EVSYS_CHMUX_ACA_WIN_gc = (0x12<<0),
EVSYS_CHMUX_ACB_CH0_gc = (0x13<<0),
EVSYS_CHMUX_ACB_CH1_gc = (0x14<<0),
EVSYS_CHMUX_ACB_WIN_gc = (0x15<<0),
EVSYS_CHMUX_ADCA_CH0_gc = (0x20<<0),
EVSYS_CHMUX_ADCA_CH1_gc = (0x21<<0),
EVSYS_CHMUX_ADCA_CH2_gc = (0x22<<0),
EVSYS_CHMUX_ADCA_CH3_gc = (0x23<<0),
EVSYS_CHMUX_ADCB_CH0_gc = (0x24<<0),
EVSYS_CHMUX_ADCB_CH1_gc = (0x25<<0),
EVSYS_CHMUX_ADCB_CH2_gc = (0x26<<0),
EVSYS_CHMUX_ADCB_CH3_gc = (0x27<<0),
EVSYS_CHMUX_PORTA_PIN0_gc = (0x50<<0),
EVSYS_CHMUX_PORTA_PIN1_gc = (0x51<<0),
EVSYS_CHMUX_PORTA_PIN2_gc = (0x52<<0),
EVSYS_CHMUX_PORTA_PIN3_gc = (0x53<<0),
EVSYS_CHMUX_PORTA_PIN4_gc = (0x54<<0),
EVSYS_CHMUX_PORTA_PIN5_gc = (0x55<<0),
EVSYS_CHMUX_PORTA_PIN6_gc = (0x56<<0),
EVSYS_CHMUX_PORTA_PIN7_gc = (0x57<<0),
EVSYS_CHMUX_PORTB_PIN0_gc = (0x58<<0),
EVSYS_CHMUX_PORTB_PIN1_gc = (0x59<<0),
EVSYS_CHMUX_PORTB_PIN2_gc = (0x5A<<0),
EVSYS_CHMUX_PORTB_PIN3_gc = (0x5B<<0),
EVSYS_CHMUX_PORTB_PIN4_gc = (0x5C<<0),
EVSYS_CHMUX_PORTB_PIN5_gc = (0x5D<<0),
EVSYS_CHMUX_PORTB_PIN6_gc = (0x5E<<0),
EVSYS_CHMUX_PORTB_PIN7_gc = (0x5F<<0),
EVSYS_CHMUX_PORTC_PIN0_gc = (0x60<<0),
EVSYS_CHMUX_PORTC_PIN1_gc = (0x61<<0),
EVSYS_CHMUX_PORTC_PIN2_gc = (0x62<<0),
EVSYS_CHMUX_PORTC_PIN3_gc = (0x63<<0),
EVSYS_CHMUX_PORTC_PIN4_gc = (0x64<<0),
EVSYS_CHMUX_PORTC_PIN5_gc = (0x65<<0),
EVSYS_CHMUX_PORTC_PIN6_gc = (0x66<<0),
EVSYS_CHMUX_PORTC_PIN7_gc = (0x67<<0),
EVSYS_CHMUX_PORTD_PIN0_gc = (0x68<<0),
EVSYS_CHMUX_PORTD_PIN1_gc = (0x69<<0),
EVSYS_CHMUX_PORTD_PIN2_gc = (0x6A<<0),
EVSYS_CHMUX_PORTD_PIN3_gc = (0x6B<<0),
EVSYS_CHMUX_PORTD_PIN4_gc = (0x6C<<0),
EVSYS_CHMUX_PORTD_PIN5_gc = (0x6D<<0),
EVSYS_CHMUX_PORTD_PIN6_gc = (0x6E<<0),
EVSYS_CHMUX_PORTD_PIN7_gc = (0x6F<<0),
EVSYS_CHMUX_PORTE_PIN0_gc = (0x70<<0),
EVSYS_CHMUX_PORTE_PIN1_gc = (0x71<<0),
EVSYS_CHMUX_PORTE_PIN2_gc = (0x72<<0),
EVSYS_CHMUX_PORTE_PIN3_gc = (0x73<<0),
EVSYS_CHMUX_PORTE_PIN4_gc = (0x74<<0),
EVSYS_CHMUX_PORTE_PIN5_gc = (0x75<<0),
EVSYS_CHMUX_PORTE_PIN6_gc = (0x76<<0),
EVSYS_CHMUX_PORTE_PIN7_gc = (0x77<<0),
EVSYS_CHMUX_PORTF_PIN0_gc = (0x78<<0),
EVSYS_CHMUX_PORTF_PIN1_gc = (0x79<<0),
EVSYS_CHMUX_PORTF_PIN2_gc = (0x7A<<0),
EVSYS_CHMUX_PORTF_PIN3_gc = (0x7B<<0),
EVSYS_CHMUX_PORTF_PIN4_gc = (0x7C<<0),
EVSYS_CHMUX_PORTF_PIN5_gc = (0x7D<<0),
EVSYS_CHMUX_PORTF_PIN6_gc = (0x7E<<0),
EVSYS_CHMUX_PORTF_PIN7_gc = (0x7F<<0),
EVSYS_CHMUX_PRESCALER_1_gc = (0x80<<0),
EVSYS_CHMUX_PRESCALER_2_gc = (0x81<<0),
EVSYS_CHMUX_PRESCALER_4_gc = (0x82<<0),
EVSYS_CHMUX_PRESCALER_8_gc = (0x83<<0),
EVSYS_CHMUX_PRESCALER_16_gc = (0x84<<0),
EVSYS_CHMUX_PRESCALER_32_gc = (0x85<<0),
EVSYS_CHMUX_PRESCALER_64_gc = (0x86<<0),
EVSYS_CHMUX_PRESCALER_128_gc = (0x87<<0),
EVSYS_CHMUX_PRESCALER_256_gc = (0x88<<0),
EVSYS_CHMUX_PRESCALER_512_gc = (0x89<<0),
EVSYS_CHMUX_PRESCALER_1024_gc = (0x8A<<0),
EVSYS_CHMUX_PRESCALER_2048_gc = (0x8B<<0),
EVSYS_CHMUX_PRESCALER_4096_gc = (0x8C<<0),
EVSYS_CHMUX_PRESCALER_8192_gc = (0x8D<<0),
EVSYS_CHMUX_PRESCALER_16384_gc = (0x8E<<0),
EVSYS_CHMUX_PRESCALER_32768_gc = (0x8F<<0),
EVSYS_CHMUX_TCC0_OVF_gc = (0xC0<<0),
EVSYS_CHMUX_TCC0_ERR_gc = (0xC1<<0),
EVSYS_CHMUX_TCC0_CCA_gc = (0xC4<<0),
EVSYS_CHMUX_TCC0_CCB_gc = (0xC5<<0),
EVSYS_CHMUX_TCC0_CCC_gc = (0xC6<<0),
EVSYS_CHMUX_TCC0_CCD_gc = (0xC7<<0),
EVSYS_CHMUX_TCC1_OVF_gc = (0xC8<<0),
EVSYS_CHMUX_TCC1_ERR_gc = (0xC9<<0),
EVSYS_CHMUX_TCC1_CCA_gc = (0xCC<<0),
EVSYS_CHMUX_TCC1_CCB_gc = (0xCD<<0),
EVSYS_CHMUX_TCD0_OVF_gc = (0xD0<<0),
EVSYS_CHMUX_TCD0_ERR_gc = (0xD1<<0),
EVSYS_CHMUX_TCD0_CCA_gc = (0xD4<<0),
EVSYS_CHMUX_TCD0_CCB_gc = (0xD5<<0),
EVSYS_CHMUX_TCD0_CCC_gc = (0xD6<<0),
EVSYS_CHMUX_TCD0_CCD_gc = (0xD7<<0),
EVSYS_CHMUX_TCD1_OVF_gc = (0xD8<<0),
EVSYS_CHMUX_TCD1_ERR_gc = (0xD9<<0),
EVSYS_CHMUX_TCD1_CCA_gc = (0xDC<<0),
EVSYS_CHMUX_TCD1_CCB_gc = (0xDD<<0),
EVSYS_CHMUX_TCE0_OVF_gc = (0xE0<<0),
EVSYS_CHMUX_TCE0_ERR_gc = (0xE1<<0),
EVSYS_CHMUX_TCE0_CCA_gc = (0xE4<<0),
EVSYS_CHMUX_TCE0_CCB_gc = (0xE5<<0),
EVSYS_CHMUX_TCE0_CCC_gc = (0xE6<<0),
EVSYS_CHMUX_TCE0_CCD_gc = (0xE7<<0),
EVSYS_CHMUX_TCE1_OVF_gc = (0xE8<<0),
EVSYS_CHMUX_TCE1_ERR_gc = (0xE9<<0),
EVSYS_CHMUX_TCE1_CCA_gc = (0xEC<<0),
EVSYS_CHMUX_TCE1_CCB_gc = (0xED<<0),
EVSYS_CHMUX_TCF0_OVF_gc = (0xF0<<0),
EVSYS_CHMUX_TCF0_ERR_gc = (0xF1<<0),
EVSYS_CHMUX_TCF0_CCA_gc = (0xF4<<0),
EVSYS_CHMUX_TCF0_CCB_gc = (0xF5<<0),
EVSYS_CHMUX_TCF0_CCC_gc = (0xF6<<0),
EVSYS_CHMUX_TCF0_CCD_gc = (0xF7<<0),
EVSYS_CHMUX_TCF1_OVF_gc = (0xF8<<0),
EVSYS_CHMUX_TCF1_ERR_gc = (0xF9<<0),
EVSYS_CHMUX_TCF1_CCA_gc = (0xFC<<0),
EVSYS_CHMUX_TCF1_CCB_gc = (0xFD<<0),
EVSYS_CHMUX_OFF_gc = (0x00<<0),
EVSYS_CHMUX_RTC_OVF_gc = (0x08<<0),
EVSYS_CHMUX_RTC_CMP_gc = (0x09<<0),
EVSYS_CHMUX_ACA_CH0_gc = (0x10<<0),
EVSYS_CHMUX_ACA_CH1_gc = (0x11<<0),
EVSYS_CHMUX_ACA_WIN_gc = (0x12<<0),
EVSYS_CHMUX_ADCA_CH0_gc = (0x20<<0),
EVSYS_CHMUX_PORTA_PIN0_gc = (0x50<<0),
EVSYS_CHMUX_PORTA_PIN1_gc = (0x51<<0),
EVSYS_CHMUX_PORTA_PIN2_gc = (0x52<<0),
EVSYS_CHMUX_PORTA_PIN3_gc = (0x53<<0),
EVSYS_CHMUX_PORTA_PIN4_gc = (0x54<<0),
EVSYS_CHMUX_PORTA_PIN5_gc = (0x55<<0),
EVSYS_CHMUX_PORTA_PIN6_gc = (0x56<<0),
EVSYS_CHMUX_PORTA_PIN7_gc = (0x57<<0),
EVSYS_CHMUX_PORTB_PIN0_gc = (0x58<<0),
EVSYS_CHMUX_PORTB_PIN1_gc = (0x59<<0),
EVSYS_CHMUX_PORTB_PIN2_gc = (0x5A<<0),
EVSYS_CHMUX_PORTB_PIN3_gc = (0x5B<<0),
EVSYS_CHMUX_PORTB_PIN4_gc = (0x5C<<0),
EVSYS_CHMUX_PORTB_PIN5_gc = (0x5D<<0),
EVSYS_CHMUX_PORTB_PIN6_gc = (0x5E<<0),
EVSYS_CHMUX_PORTB_PIN7_gc = (0x5F<<0),
EVSYS_CHMUX_PORTC_PIN0_gc = (0x60<<0),
EVSYS_CHMUX_PORTC_PIN1_gc = (0x61<<0),
EVSYS_CHMUX_PORTC_PIN2_gc = (0x62<<0),
EVSYS_CHMUX_PORTC_PIN3_gc = (0x63<<0),
EVSYS_CHMUX_PORTC_PIN4_gc = (0x64<<0),
EVSYS_CHMUX_PORTC_PIN5_gc = (0x65<<0),
EVSYS_CHMUX_PORTC_PIN6_gc = (0x66<<0),
EVSYS_CHMUX_PORTC_PIN7_gc = (0x67<<0),
EVSYS_CHMUX_PORTD_PIN0_gc = (0x68<<0),
EVSYS_CHMUX_PORTD_PIN1_gc = (0x69<<0),
EVSYS_CHMUX_PORTD_PIN2_gc = (0x6A<<0),
EVSYS_CHMUX_PORTD_PIN3_gc = (0x6B<<0),
EVSYS_CHMUX_PORTD_PIN4_gc = (0x6C<<0),
EVSYS_CHMUX_PORTD_PIN5_gc = (0x6D<<0),
EVSYS_CHMUX_PORTD_PIN6_gc = (0x6E<<0),
EVSYS_CHMUX_PORTD_PIN7_gc = (0x6F<<0),
EVSYS_CHMUX_PORTE_PIN0_gc = (0x70<<0),
EVSYS_CHMUX_PORTE_PIN1_gc = (0x71<<0),
EVSYS_CHMUX_PORTE_PIN2_gc = (0x72<<0),
EVSYS_CHMUX_PORTE_PIN3_gc = (0x73<<0),
EVSYS_CHMUX_PORTE_PIN4_gc = (0x74<<0),
EVSYS_CHMUX_PORTE_PIN5_gc = (0x75<<0),
EVSYS_CHMUX_PORTE_PIN6_gc = (0x76<<0),
EVSYS_CHMUX_PORTE_PIN7_gc = (0x77<<0),
EVSYS_CHMUX_PORTF_PIN0_gc = (0x78<<0),
EVSYS_CHMUX_PORTF_PIN1_gc = (0x79<<0),
EVSYS_CHMUX_PORTF_PIN2_gc = (0x7A<<0),
EVSYS_CHMUX_PORTF_PIN3_gc = (0x7B<<0),
EVSYS_CHMUX_PORTF_PIN4_gc = (0x7C<<0),
EVSYS_CHMUX_PORTF_PIN5_gc = (0x7D<<0),
EVSYS_CHMUX_PORTF_PIN6_gc = (0x7E<<0),
EVSYS_CHMUX_PORTF_PIN7_gc = (0x7F<<0),
EVSYS_CHMUX_PRESCALER_1_gc = (0x80<<0),
EVSYS_CHMUX_PRESCALER_2_gc = (0x81<<0),
EVSYS_CHMUX_PRESCALER_4_gc = (0x82<<0),
EVSYS_CHMUX_PRESCALER_8_gc = (0x83<<0),
EVSYS_CHMUX_PRESCALER_16_gc = (0x84<<0),
EVSYS_CHMUX_PRESCALER_32_gc = (0x85<<0),
EVSYS_CHMUX_PRESCALER_64_gc = (0x86<<0),
EVSYS_CHMUX_PRESCALER_128_gc = (0x87<<0),
EVSYS_CHMUX_PRESCALER_256_gc = (0x88<<0),
EVSYS_CHMUX_PRESCALER_512_gc = (0x89<<0),
EVSYS_CHMUX_PRESCALER_1024_gc = (0x8A<<0),
EVSYS_CHMUX_PRESCALER_2048_gc = (0x8B<<0),
EVSYS_CHMUX_PRESCALER_4096_gc = (0x8C<<0),
EVSYS_CHMUX_PRESCALER_8192_gc = (0x8D<<0),
EVSYS_CHMUX_PRESCALER_16384_gc = (0x8E<<0),
EVSYS_CHMUX_PRESCALER_32768_gc = (0x8F<<0),
EVSYS_CHMUX_TCC0_OVF_gc = (0xC0<<0),
EVSYS_CHMUX_TCC0_ERR_gc = (0xC1<<0),
EVSYS_CHMUX_TCC0_CCA_gc = (0xC4<<0),
EVSYS_CHMUX_TCC0_CCB_gc = (0xC5<<0),
EVSYS_CHMUX_TCC0_CCC_gc = (0xC6<<0),
EVSYS_CHMUX_TCC0_CCD_gc = (0xC7<<0),
EVSYS_CHMUX_TCC1_OVF_gc = (0xC8<<0),
EVSYS_CHMUX_TCC1_ERR_gc = (0xC9<<0),
EVSYS_CHMUX_TCC1_CCA_gc = (0xCC<<0),
EVSYS_CHMUX_TCC1_CCB_gc = (0xCD<<0),
EVSYS_CHMUX_TCD0_OVF_gc = (0xD0<<0),
EVSYS_CHMUX_TCD0_ERR_gc = (0xD1<<0),
EVSYS_CHMUX_TCD0_CCA_gc = (0xD4<<0),
EVSYS_CHMUX_TCD0_CCB_gc = (0xD5<<0),
EVSYS_CHMUX_TCD0_CCC_gc = (0xD6<<0),
EVSYS_CHMUX_TCD0_CCD_gc = (0xD7<<0),
EVSYS_CHMUX_TCD1_OVF_gc = (0xD8<<0),
EVSYS_CHMUX_TCD1_ERR_gc = (0xD9<<0),
EVSYS_CHMUX_TCD1_CCA_gc = (0xDC<<0),
EVSYS_CHMUX_TCD1_CCB_gc = (0xDD<<0),
EVSYS_CHMUX_TCE0_OVF_gc = (0xE0<<0),
EVSYS_CHMUX_TCE0_ERR_gc = (0xE1<<0),
EVSYS_CHMUX_TCE0_CCA_gc = (0xE4<<0),
EVSYS_CHMUX_TCE0_CCB_gc = (0xE5<<0),
EVSYS_CHMUX_TCE0_CCC_gc = (0xE6<<0),
EVSYS_CHMUX_TCE0_CCD_gc = (0xE7<<0),
EVSYS_CHMUX_TCE1_OVF_gc = (0xE8<<0),
EVSYS_CHMUX_TCE1_ERR_gc = (0xE9<<0),
EVSYS_CHMUX_TCE1_CCA_gc = (0xEC<<0),
EVSYS_CHMUX_TCE1_CCB_gc = (0xED<<0),
EVSYS_CHMUX_TCF0_OVF_gc = (0xF0<<0),
EVSYS_CHMUX_TCF0_ERR_gc = (0xF1<<0),
EVSYS_CHMUX_TCF0_CCA_gc = (0xF4<<0),
EVSYS_CHMUX_TCF0_CCB_gc = (0xF5<<0),
EVSYS_CHMUX_TCF0_CCC_gc = (0xF6<<0),
EVSYS_CHMUX_TCF0_CCD_gc = (0xF7<<0),
EVSYS_CHMUX_TCF1_OVF_gc = (0xF8<<0),
EVSYS_CHMUX_TCF1_ERR_gc = (0xF9<<0),
EVSYS_CHMUX_TCF1_CCA_gc = (0xFC<<0),
EVSYS_CHMUX_TCF1_CCB_gc = (0xFD<<0)
} |
|
enum | NVM_CMD_enum {
NVM_CMD_NO_OPERATION_gc = (0x00<<0),
NVM_CMD_READ_CALIB_ROW_gc = (0x02<<0),
NVM_CMD_READ_USER_SIG_ROW_gc = (0x01<<0),
NVM_CMD_READ_EEPROM_gc = (0x06<<0),
NVM_CMD_READ_FUSES_gc = (0x07<<0),
NVM_CMD_WRITE_LOCK_BITS_gc = (0x08<<0),
NVM_CMD_ERASE_USER_SIG_ROW_gc = (0x18<<0),
NVM_CMD_WRITE_USER_SIG_ROW_gc = (0x1A<<0),
NVM_CMD_ERASE_APP_gc = (0x20<<0),
NVM_CMD_ERASE_APP_PAGE_gc = (0x22<<0),
NVM_CMD_LOAD_FLASH_BUFFER_gc = (0x23<<0),
NVM_CMD_WRITE_APP_PAGE_gc = (0x24<<0),
NVM_CMD_ERASE_WRITE_APP_PAGE_gc = (0x25<<0),
NVM_CMD_ERASE_FLASH_BUFFER_gc = (0x26<<0),
NVM_CMD_ERASE_BOOT_PAGE_gc = (0x2A<<0),
NVM_CMD_WRITE_BOOT_PAGE_gc = (0x2C<<0),
NVM_CMD_ERASE_WRITE_BOOT_PAGE_gc = (0x2D<<0),
NVM_CMD_ERASE_EEPROM_gc = (0x30<<0),
NVM_CMD_ERASE_EEPROM_PAGE_gc = (0x32<<0),
NVM_CMD_LOAD_EEPROM_BUFFER_gc = (0x33<<0),
NVM_CMD_WRITE_EEPROM_PAGE_gc = (0x34<<0),
NVM_CMD_ERASE_WRITE_EEPROM_PAGE_gc = (0x35<<0),
NVM_CMD_ERASE_EEPROM_BUFFER_gc = (0x36<<0),
NVM_CMD_APP_CRC_gc = (0x38<<0),
NVM_CMD_BOOT_CRC_gc = (0x39<<0),
NVM_CMD_FLASH_RANGE_CRC_gc = (0x3A<<0),
NVM_CMD_NO_OPERATION_gc = (0x00<<0),
NVM_CMD_READ_CALIB_ROW_gc = (0x02<<0),
NVM_CMD_READ_USER_SIG_ROW_gc = (0x01<<0),
NVM_CMD_READ_EEPROM_gc = (0x06<<0),
NVM_CMD_READ_FUSES_gc = (0x07<<0),
NVM_CMD_WRITE_LOCK_BITS_gc = (0x08<<0),
NVM_CMD_ERASE_USER_SIG_ROW_gc = (0x18<<0),
NVM_CMD_WRITE_USER_SIG_ROW_gc = (0x1A<<0),
NVM_CMD_ERASE_APP_gc = (0x20<<0),
NVM_CMD_ERASE_APP_PAGE_gc = (0x22<<0),
NVM_CMD_LOAD_FLASH_BUFFER_gc = (0x23<<0),
NVM_CMD_WRITE_APP_PAGE_gc = (0x24<<0),
NVM_CMD_ERASE_WRITE_APP_PAGE_gc = (0x25<<0),
NVM_CMD_ERASE_FLASH_BUFFER_gc = (0x26<<0),
NVM_CMD_ERASE_BOOT_PAGE_gc = (0x2A<<0),
NVM_CMD_WRITE_BOOT_PAGE_gc = (0x2C<<0),
NVM_CMD_ERASE_WRITE_BOOT_PAGE_gc = (0x2D<<0),
NVM_CMD_ERASE_EEPROM_gc = (0x30<<0),
NVM_CMD_ERASE_EEPROM_PAGE_gc = (0x32<<0),
NVM_CMD_LOAD_EEPROM_BUFFER_gc = (0x33<<0),
NVM_CMD_WRITE_EEPROM_PAGE_gc = (0x34<<0),
NVM_CMD_ERASE_WRITE_EEPROM_PAGE_gc = (0x35<<0),
NVM_CMD_ERASE_EEPROM_BUFFER_gc = (0x36<<0),
NVM_CMD_APP_CRC_gc = (0x38<<0),
NVM_CMD_BOOT_CRC_gc = (0x39<<0),
NVM_CMD_FLASH_RANGE_CRC_gc = (0x3A<<0),
NVM_CMD_NO_OPERATION_gc = (0x00<<0),
NVM_CMD_READ_CALIB_ROW_gc = (0x02<<0),
NVM_CMD_READ_USER_SIG_ROW_gc = (0x01<<0),
NVM_CMD_READ_EEPROM_gc = (0x06<<0),
NVM_CMD_READ_FUSES_gc = (0x07<<0),
NVM_CMD_WRITE_LOCK_BITS_gc = (0x08<<0),
NVM_CMD_ERASE_USER_SIG_ROW_gc = (0x18<<0),
NVM_CMD_WRITE_USER_SIG_ROW_gc = (0x1A<<0),
NVM_CMD_ERASE_APP_gc = (0x20<<0),
NVM_CMD_ERASE_APP_PAGE_gc = (0x22<<0),
NVM_CMD_LOAD_FLASH_BUFFER_gc = (0x23<<0),
NVM_CMD_WRITE_APP_PAGE_gc = (0x24<<0),
NVM_CMD_ERASE_WRITE_APP_PAGE_gc = (0x25<<0),
NVM_CMD_ERASE_FLASH_BUFFER_gc = (0x26<<0),
NVM_CMD_ERASE_BOOT_PAGE_gc = (0x2A<<0),
NVM_CMD_WRITE_BOOT_PAGE_gc = (0x2C<<0),
NVM_CMD_ERASE_WRITE_BOOT_PAGE_gc = (0x2D<<0),
NVM_CMD_ERASE_EEPROM_gc = (0x30<<0),
NVM_CMD_ERASE_EEPROM_PAGE_gc = (0x32<<0),
NVM_CMD_LOAD_EEPROM_BUFFER_gc = (0x33<<0),
NVM_CMD_WRITE_EEPROM_PAGE_gc = (0x34<<0),
NVM_CMD_ERASE_WRITE_EEPROM_PAGE_gc = (0x35<<0),
NVM_CMD_ERASE_EEPROM_BUFFER_gc = (0x36<<0),
NVM_CMD_APP_CRC_gc = (0x38<<0),
NVM_CMD_BOOT_CRC_gc = (0x39<<0),
NVM_CMD_FLASH_RANGE_CRC_gc = (0x3A<<0),
NVM_CMD_NO_OPERATION_gc = (0x00<<0),
NVM_CMD_READ_CALIB_ROW_gc = (0x02<<0),
NVM_CMD_READ_USER_SIG_ROW_gc = (0x01<<0),
NVM_CMD_READ_EEPROM_gc = (0x06<<0),
NVM_CMD_READ_FUSES_gc = (0x07<<0),
NVM_CMD_WRITE_LOCK_BITS_gc = (0x08<<0),
NVM_CMD_ERASE_USER_SIG_ROW_gc = (0x18<<0),
NVM_CMD_WRITE_USER_SIG_ROW_gc = (0x1A<<0),
NVM_CMD_ERASE_APP_gc = (0x20<<0),
NVM_CMD_ERASE_APP_PAGE_gc = (0x22<<0),
NVM_CMD_LOAD_FLASH_BUFFER_gc = (0x23<<0),
NVM_CMD_WRITE_APP_PAGE_gc = (0x24<<0),
NVM_CMD_ERASE_WRITE_APP_PAGE_gc = (0x25<<0),
NVM_CMD_ERASE_FLASH_BUFFER_gc = (0x26<<0),
NVM_CMD_ERASE_BOOT_PAGE_gc = (0x2A<<0),
NVM_CMD_WRITE_BOOT_PAGE_gc = (0x2C<<0),
NVM_CMD_ERASE_WRITE_BOOT_PAGE_gc = (0x2D<<0),
NVM_CMD_ERASE_EEPROM_gc = (0x30<<0),
NVM_CMD_ERASE_EEPROM_PAGE_gc = (0x32<<0),
NVM_CMD_LOAD_EEPROM_BUFFER_gc = (0x33<<0),
NVM_CMD_WRITE_EEPROM_PAGE_gc = (0x34<<0),
NVM_CMD_ERASE_WRITE_EEPROM_PAGE_gc = (0x35<<0),
NVM_CMD_ERASE_EEPROM_BUFFER_gc = (0x36<<0),
NVM_CMD_APP_CRC_gc = (0x38<<0),
NVM_CMD_BOOT_CRC_gc = (0x39<<0),
NVM_CMD_FLASH_RANGE_CRC_gc = (0x3A<<0),
NVM_CMD_NO_OPERATION_gc = (0x00<<0),
NVM_CMD_READ_CALIB_ROW_gc = (0x02<<0),
NVM_CMD_READ_USER_SIG_ROW_gc = (0x01<<0),
NVM_CMD_READ_EEPROM_gc = (0x06<<0),
NVM_CMD_READ_FUSES_gc = (0x07<<0),
NVM_CMD_WRITE_LOCK_BITS_gc = (0x08<<0),
NVM_CMD_ERASE_USER_SIG_ROW_gc = (0x18<<0),
NVM_CMD_WRITE_USER_SIG_ROW_gc = (0x1A<<0),
NVM_CMD_ERASE_APP_gc = (0x20<<0),
NVM_CMD_ERASE_APP_PAGE_gc = (0x22<<0),
NVM_CMD_LOAD_FLASH_BUFFER_gc = (0x23<<0),
NVM_CMD_WRITE_APP_PAGE_gc = (0x24<<0),
NVM_CMD_ERASE_WRITE_APP_PAGE_gc = (0x25<<0),
NVM_CMD_ERASE_FLASH_BUFFER_gc = (0x26<<0),
NVM_CMD_ERASE_BOOT_PAGE_gc = (0x2A<<0),
NVM_CMD_WRITE_BOOT_PAGE_gc = (0x2C<<0),
NVM_CMD_ERASE_WRITE_BOOT_PAGE_gc = (0x2D<<0),
NVM_CMD_ERASE_EEPROM_gc = (0x30<<0),
NVM_CMD_ERASE_EEPROM_PAGE_gc = (0x32<<0),
NVM_CMD_LOAD_EEPROM_BUFFER_gc = (0x33<<0),
NVM_CMD_WRITE_EEPROM_PAGE_gc = (0x34<<0),
NVM_CMD_ERASE_WRITE_EEPROM_PAGE_gc = (0x35<<0),
NVM_CMD_ERASE_EEPROM_BUFFER_gc = (0x36<<0),
NVM_CMD_APP_CRC_gc = (0x38<<0),
NVM_CMD_BOOT_CRC_gc = (0x39<<0),
NVM_CMD_FLASH_RANGE_CRC_gc = (0x3A<<0),
NVM_CMD_NO_OPERATION_gc = (0x00<<0),
NVM_CMD_READ_CALIB_ROW_gc = (0x02<<0),
NVM_CMD_READ_USER_SIG_ROW_gc = (0x01<<0),
NVM_CMD_READ_EEPROM_gc = (0x06<<0),
NVM_CMD_READ_FUSES_gc = (0x07<<0),
NVM_CMD_WRITE_LOCK_BITS_gc = (0x08<<0),
NVM_CMD_ERASE_USER_SIG_ROW_gc = (0x18<<0),
NVM_CMD_WRITE_USER_SIG_ROW_gc = (0x1A<<0),
NVM_CMD_ERASE_APP_gc = (0x20<<0),
NVM_CMD_ERASE_APP_PAGE_gc = (0x22<<0),
NVM_CMD_LOAD_FLASH_BUFFER_gc = (0x23<<0),
NVM_CMD_WRITE_APP_PAGE_gc = (0x24<<0),
NVM_CMD_ERASE_WRITE_APP_PAGE_gc = (0x25<<0),
NVM_CMD_ERASE_FLASH_BUFFER_gc = (0x26<<0),
NVM_CMD_ERASE_BOOT_PAGE_gc = (0x2A<<0),
NVM_CMD_WRITE_BOOT_PAGE_gc = (0x2C<<0),
NVM_CMD_ERASE_WRITE_BOOT_PAGE_gc = (0x2D<<0),
NVM_CMD_ERASE_EEPROM_gc = (0x30<<0),
NVM_CMD_ERASE_EEPROM_PAGE_gc = (0x32<<0),
NVM_CMD_LOAD_EEPROM_BUFFER_gc = (0x33<<0),
NVM_CMD_WRITE_EEPROM_PAGE_gc = (0x34<<0),
NVM_CMD_ERASE_WRITE_EEPROM_PAGE_gc = (0x35<<0),
NVM_CMD_ERASE_EEPROM_BUFFER_gc = (0x36<<0),
NVM_CMD_APP_CRC_gc = (0x38<<0),
NVM_CMD_BOOT_CRC_gc = (0x39<<0),
NVM_CMD_FLASH_RANGE_CRC_gc = (0x3A<<0),
NVM_CMD_NO_OPERATION_gc = (0x00<<0),
NVM_CMD_READ_CALIB_ROW_gc = (0x02<<0),
NVM_CMD_READ_USER_SIG_ROW_gc = (0x01<<0),
NVM_CMD_READ_EEPROM_gc = (0x06<<0),
NVM_CMD_READ_FUSES_gc = (0x07<<0),
NVM_CMD_WRITE_LOCK_BITS_gc = (0x08<<0),
NVM_CMD_ERASE_USER_SIG_ROW_gc = (0x18<<0),
NVM_CMD_WRITE_USER_SIG_ROW_gc = (0x1A<<0),
NVM_CMD_ERASE_APP_gc = (0x20<<0),
NVM_CMD_ERASE_APP_PAGE_gc = (0x22<<0),
NVM_CMD_LOAD_FLASH_BUFFER_gc = (0x23<<0),
NVM_CMD_WRITE_APP_PAGE_gc = (0x24<<0),
NVM_CMD_ERASE_WRITE_APP_PAGE_gc = (0x25<<0),
NVM_CMD_ERASE_FLASH_BUFFER_gc = (0x26<<0),
NVM_CMD_ERASE_BOOT_PAGE_gc = (0x2A<<0),
NVM_CMD_WRITE_BOOT_PAGE_gc = (0x2C<<0),
NVM_CMD_ERASE_WRITE_BOOT_PAGE_gc = (0x2D<<0),
NVM_CMD_ERASE_EEPROM_gc = (0x30<<0),
NVM_CMD_ERASE_EEPROM_PAGE_gc = (0x32<<0),
NVM_CMD_LOAD_EEPROM_BUFFER_gc = (0x33<<0),
NVM_CMD_WRITE_EEPROM_PAGE_gc = (0x34<<0),
NVM_CMD_ERASE_WRITE_EEPROM_PAGE_gc = (0x35<<0),
NVM_CMD_ERASE_EEPROM_BUFFER_gc = (0x36<<0),
NVM_CMD_APP_CRC_gc = (0x38<<0),
NVM_CMD_BOOT_CRC_gc = (0x39<<0),
NVM_CMD_FLASH_RANGE_CRC_gc = (0x3A<<0),
NVM_CMD_NO_OPERATION_gc = (0x00<<0),
NVM_CMD_READ_CALIB_ROW_gc = (0x02<<0),
NVM_CMD_READ_USER_SIG_ROW_gc = (0x01<<0),
NVM_CMD_READ_EEPROM_gc = (0x06<<0),
NVM_CMD_READ_FUSES_gc = (0x07<<0),
NVM_CMD_WRITE_LOCK_BITS_gc = (0x08<<0),
NVM_CMD_ERASE_USER_SIG_ROW_gc = (0x18<<0),
NVM_CMD_WRITE_USER_SIG_ROW_gc = (0x1A<<0),
NVM_CMD_ERASE_APP_gc = (0x20<<0),
NVM_CMD_ERASE_APP_PAGE_gc = (0x22<<0),
NVM_CMD_LOAD_FLASH_BUFFER_gc = (0x23<<0),
NVM_CMD_WRITE_APP_PAGE_gc = (0x24<<0),
NVM_CMD_ERASE_WRITE_APP_PAGE_gc = (0x25<<0),
NVM_CMD_ERASE_FLASH_BUFFER_gc = (0x26<<0),
NVM_CMD_ERASE_BOOT_PAGE_gc = (0x2A<<0),
NVM_CMD_WRITE_BOOT_PAGE_gc = (0x2C<<0),
NVM_CMD_ERASE_WRITE_BOOT_PAGE_gc = (0x2D<<0),
NVM_CMD_ERASE_EEPROM_gc = (0x30<<0),
NVM_CMD_ERASE_EEPROM_PAGE_gc = (0x32<<0),
NVM_CMD_LOAD_EEPROM_BUFFER_gc = (0x33<<0),
NVM_CMD_WRITE_EEPROM_PAGE_gc = (0x34<<0),
NVM_CMD_ERASE_WRITE_EEPROM_PAGE_gc = (0x35<<0),
NVM_CMD_ERASE_EEPROM_BUFFER_gc = (0x36<<0),
NVM_CMD_APP_CRC_gc = (0x38<<0),
NVM_CMD_BOOT_CRC_gc = (0x39<<0),
NVM_CMD_FLASH_RANGE_CRC_gc = (0x3A<<0),
NVM_CMD_NO_OPERATION_gc = (0x00<<0),
NVM_CMD_READ_CALIB_ROW_gc = (0x02<<0),
NVM_CMD_READ_USER_SIG_ROW_gc = (0x01<<0),
NVM_CMD_READ_EEPROM_gc = (0x06<<0),
NVM_CMD_READ_FUSES_gc = (0x07<<0),
NVM_CMD_WRITE_LOCK_BITS_gc = (0x08<<0),
NVM_CMD_ERASE_USER_SIG_ROW_gc = (0x18<<0),
NVM_CMD_WRITE_USER_SIG_ROW_gc = (0x1A<<0),
NVM_CMD_ERASE_APP_gc = (0x20<<0),
NVM_CMD_ERASE_APP_PAGE_gc = (0x22<<0),
NVM_CMD_LOAD_FLASH_BUFFER_gc = (0x23<<0),
NVM_CMD_WRITE_APP_PAGE_gc = (0x24<<0),
NVM_CMD_ERASE_WRITE_APP_PAGE_gc = (0x25<<0),
NVM_CMD_ERASE_FLASH_BUFFER_gc = (0x26<<0),
NVM_CMD_ERASE_BOOT_PAGE_gc = (0x2A<<0),
NVM_CMD_WRITE_BOOT_PAGE_gc = (0x2C<<0),
NVM_CMD_ERASE_WRITE_BOOT_PAGE_gc = (0x2D<<0),
NVM_CMD_ERASE_EEPROM_gc = (0x30<<0),
NVM_CMD_ERASE_EEPROM_PAGE_gc = (0x32<<0),
NVM_CMD_LOAD_EEPROM_BUFFER_gc = (0x33<<0),
NVM_CMD_WRITE_EEPROM_PAGE_gc = (0x34<<0),
NVM_CMD_ERASE_WRITE_EEPROM_PAGE_gc = (0x35<<0),
NVM_CMD_ERASE_EEPROM_BUFFER_gc = (0x36<<0),
NVM_CMD_APP_CRC_gc = (0x38<<0),
NVM_CMD_BOOT_CRC_gc = (0x39<<0),
NVM_CMD_FLASH_RANGE_CRC_gc = (0x3A<<0),
NVM_CMD_NO_OPERATION_gc = (0x00<<0),
NVM_CMD_READ_CALIB_ROW_gc = (0x02<<0),
NVM_CMD_READ_USER_SIG_ROW_gc = (0x01<<0),
NVM_CMD_READ_EEPROM_gc = (0x06<<0),
NVM_CMD_READ_FUSES_gc = (0x07<<0),
NVM_CMD_WRITE_LOCK_BITS_gc = (0x08<<0),
NVM_CMD_ERASE_USER_SIG_ROW_gc = (0x18<<0),
NVM_CMD_WRITE_USER_SIG_ROW_gc = (0x1A<<0),
NVM_CMD_ERASE_APP_gc = (0x20<<0),
NVM_CMD_ERASE_APP_PAGE_gc = (0x22<<0),
NVM_CMD_LOAD_FLASH_BUFFER_gc = (0x23<<0),
NVM_CMD_WRITE_APP_PAGE_gc = (0x24<<0),
NVM_CMD_ERASE_WRITE_APP_PAGE_gc = (0x25<<0),
NVM_CMD_ERASE_FLASH_BUFFER_gc = (0x26<<0),
NVM_CMD_ERASE_BOOT_PAGE_gc = (0x2A<<0),
NVM_CMD_WRITE_BOOT_PAGE_gc = (0x2C<<0),
NVM_CMD_ERASE_WRITE_BOOT_PAGE_gc = (0x2D<<0),
NVM_CMD_ERASE_EEPROM_gc = (0x30<<0),
NVM_CMD_ERASE_EEPROM_PAGE_gc = (0x32<<0),
NVM_CMD_LOAD_EEPROM_BUFFER_gc = (0x33<<0),
NVM_CMD_WRITE_EEPROM_PAGE_gc = (0x34<<0),
NVM_CMD_ERASE_WRITE_EEPROM_PAGE_gc = (0x35<<0),
NVM_CMD_ERASE_EEPROM_BUFFER_gc = (0x36<<0),
NVM_CMD_APP_CRC_gc = (0x38<<0),
NVM_CMD_BOOT_CRC_gc = (0x39<<0),
NVM_CMD_FLASH_RANGE_CRC_gc = (0x3A<<0),
NVM_CMD_NO_OPERATION_gc = (0x00<<0),
NVM_CMD_READ_CALIB_ROW_gc = (0x02<<0),
NVM_CMD_READ_USER_SIG_ROW_gc = (0x01<<0),
NVM_CMD_READ_EEPROM_gc = (0x06<<0),
NVM_CMD_READ_FUSES_gc = (0x07<<0),
NVM_CMD_WRITE_LOCK_BITS_gc = (0x08<<0),
NVM_CMD_ERASE_USER_SIG_ROW_gc = (0x18<<0),
NVM_CMD_WRITE_USER_SIG_ROW_gc = (0x1A<<0),
NVM_CMD_ERASE_APP_gc = (0x20<<0),
NVM_CMD_ERASE_APP_PAGE_gc = (0x22<<0),
NVM_CMD_LOAD_FLASH_BUFFER_gc = (0x23<<0),
NVM_CMD_WRITE_APP_PAGE_gc = (0x24<<0),
NVM_CMD_ERASE_WRITE_APP_PAGE_gc = (0x25<<0),
NVM_CMD_ERASE_FLASH_BUFFER_gc = (0x26<<0),
NVM_CMD_ERASE_BOOT_PAGE_gc = (0x2A<<0),
NVM_CMD_WRITE_BOOT_PAGE_gc = (0x2C<<0),
NVM_CMD_ERASE_WRITE_BOOT_PAGE_gc = (0x2D<<0),
NVM_CMD_ERASE_EEPROM_gc = (0x30<<0),
NVM_CMD_ERASE_EEPROM_PAGE_gc = (0x32<<0),
NVM_CMD_LOAD_EEPROM_BUFFER_gc = (0x33<<0),
NVM_CMD_WRITE_EEPROM_PAGE_gc = (0x34<<0),
NVM_CMD_ERASE_WRITE_EEPROM_PAGE_gc = (0x35<<0),
NVM_CMD_ERASE_EEPROM_BUFFER_gc = (0x36<<0),
NVM_CMD_APP_CRC_gc = (0x38<<0),
NVM_CMD_BOOT_CRC_gc = (0x39<<0),
NVM_CMD_FLASH_RANGE_CRC_gc = (0x3A<<0),
NVM_CMD_NO_OPERATION_gc = (0x00<<0),
NVM_CMD_READ_CALIB_ROW_gc = (0x02<<0),
NVM_CMD_READ_USER_SIG_ROW_gc = (0x01<<0),
NVM_CMD_READ_EEPROM_gc = (0x06<<0),
NVM_CMD_READ_FUSES_gc = (0x07<<0),
NVM_CMD_WRITE_LOCK_BITS_gc = (0x08<<0),
NVM_CMD_ERASE_USER_SIG_ROW_gc = (0x18<<0),
NVM_CMD_WRITE_USER_SIG_ROW_gc = (0x1A<<0),
NVM_CMD_ERASE_APP_gc = (0x20<<0),
NVM_CMD_ERASE_APP_PAGE_gc = (0x22<<0),
NVM_CMD_LOAD_FLASH_BUFFER_gc = (0x23<<0),
NVM_CMD_WRITE_APP_PAGE_gc = (0x24<<0),
NVM_CMD_ERASE_WRITE_APP_PAGE_gc = (0x25<<0),
NVM_CMD_ERASE_FLASH_BUFFER_gc = (0x26<<0),
NVM_CMD_ERASE_BOOT_PAGE_gc = (0x2A<<0),
NVM_CMD_WRITE_BOOT_PAGE_gc = (0x2C<<0),
NVM_CMD_ERASE_WRITE_BOOT_PAGE_gc = (0x2D<<0),
NVM_CMD_ERASE_EEPROM_gc = (0x30<<0),
NVM_CMD_ERASE_EEPROM_PAGE_gc = (0x32<<0),
NVM_CMD_LOAD_EEPROM_BUFFER_gc = (0x33<<0),
NVM_CMD_WRITE_EEPROM_PAGE_gc = (0x34<<0),
NVM_CMD_ERASE_WRITE_EEPROM_PAGE_gc = (0x35<<0),
NVM_CMD_ERASE_EEPROM_BUFFER_gc = (0x36<<0),
NVM_CMD_APP_CRC_gc = (0x38<<0),
NVM_CMD_BOOT_CRC_gc = (0x39<<0),
NVM_CMD_FLASH_RANGE_CRC_gc = (0x3A<<0),
NVM_CMD_NO_OPERATION_gc = (0x00<<0),
NVM_CMD_READ_CALIB_ROW_gc = (0x02<<0),
NVM_CMD_READ_USER_SIG_ROW_gc = (0x01<<0),
NVM_CMD_READ_EEPROM_gc = (0x06<<0),
NVM_CMD_READ_FUSES_gc = (0x07<<0),
NVM_CMD_WRITE_LOCK_BITS_gc = (0x08<<0),
NVM_CMD_ERASE_USER_SIG_ROW_gc = (0x18<<0),
NVM_CMD_WRITE_USER_SIG_ROW_gc = (0x1A<<0),
NVM_CMD_ERASE_APP_gc = (0x20<<0),
NVM_CMD_ERASE_APP_PAGE_gc = (0x22<<0),
NVM_CMD_LOAD_FLASH_BUFFER_gc = (0x23<<0),
NVM_CMD_WRITE_APP_PAGE_gc = (0x24<<0),
NVM_CMD_ERASE_WRITE_APP_PAGE_gc = (0x25<<0),
NVM_CMD_ERASE_FLASH_BUFFER_gc = (0x26<<0),
NVM_CMD_ERASE_BOOT_PAGE_gc = (0x2A<<0),
NVM_CMD_WRITE_BOOT_PAGE_gc = (0x2C<<0),
NVM_CMD_ERASE_WRITE_BOOT_PAGE_gc = (0x2D<<0),
NVM_CMD_ERASE_EEPROM_gc = (0x30<<0),
NVM_CMD_ERASE_EEPROM_PAGE_gc = (0x32<<0),
NVM_CMD_LOAD_EEPROM_BUFFER_gc = (0x33<<0),
NVM_CMD_WRITE_EEPROM_PAGE_gc = (0x34<<0),
NVM_CMD_ERASE_WRITE_EEPROM_PAGE_gc = (0x35<<0),
NVM_CMD_ERASE_EEPROM_BUFFER_gc = (0x36<<0),
NVM_CMD_APP_CRC_gc = (0x38<<0),
NVM_CMD_BOOT_CRC_gc = (0x39<<0),
NVM_CMD_FLASH_RANGE_CRC_gc = (0x3A<<0),
NVM_CMD_NO_OPERATION_gc = (0x00<<0),
NVM_CMD_READ_CALIB_ROW_gc = (0x02<<0),
NVM_CMD_READ_USER_SIG_ROW_gc = (0x01<<0),
NVM_CMD_READ_EEPROM_gc = (0x06<<0),
NVM_CMD_READ_FUSES_gc = (0x07<<0),
NVM_CMD_WRITE_LOCK_BITS_gc = (0x08<<0),
NVM_CMD_ERASE_USER_SIG_ROW_gc = (0x18<<0),
NVM_CMD_WRITE_USER_SIG_ROW_gc = (0x1A<<0),
NVM_CMD_ERASE_APP_gc = (0x20<<0),
NVM_CMD_ERASE_APP_PAGE_gc = (0x22<<0),
NVM_CMD_LOAD_FLASH_BUFFER_gc = (0x23<<0),
NVM_CMD_WRITE_APP_PAGE_gc = (0x24<<0),
NVM_CMD_ERASE_WRITE_APP_PAGE_gc = (0x25<<0),
NVM_CMD_ERASE_FLASH_BUFFER_gc = (0x26<<0),
NVM_CMD_ERASE_BOOT_PAGE_gc = (0x2A<<0),
NVM_CMD_WRITE_BOOT_PAGE_gc = (0x2C<<0),
NVM_CMD_ERASE_WRITE_BOOT_PAGE_gc = (0x2D<<0),
NVM_CMD_ERASE_EEPROM_gc = (0x30<<0),
NVM_CMD_ERASE_EEPROM_PAGE_gc = (0x32<<0),
NVM_CMD_LOAD_EEPROM_BUFFER_gc = (0x33<<0),
NVM_CMD_WRITE_EEPROM_PAGE_gc = (0x34<<0),
NVM_CMD_ERASE_WRITE_EEPROM_PAGE_gc = (0x35<<0),
NVM_CMD_ERASE_EEPROM_BUFFER_gc = (0x36<<0),
NVM_CMD_APP_CRC_gc = (0x38<<0),
NVM_CMD_BOOT_CRC_gc = (0x39<<0),
NVM_CMD_FLASH_RANGE_CRC_gc = (0x3A<<0),
NVM_CMD_NO_OPERATION_gc = (0x00<<0),
NVM_CMD_READ_CALIB_ROW_gc = (0x02<<0),
NVM_CMD_READ_USER_SIG_ROW_gc = (0x01<<0),
NVM_CMD_READ_EEPROM_gc = (0x06<<0),
NVM_CMD_READ_FUSES_gc = (0x07<<0),
NVM_CMD_WRITE_LOCK_BITS_gc = (0x08<<0),
NVM_CMD_ERASE_USER_SIG_ROW_gc = (0x18<<0),
NVM_CMD_WRITE_USER_SIG_ROW_gc = (0x1A<<0),
NVM_CMD_ERASE_APP_gc = (0x20<<0),
NVM_CMD_ERASE_APP_PAGE_gc = (0x22<<0),
NVM_CMD_LOAD_FLASH_BUFFER_gc = (0x23<<0),
NVM_CMD_WRITE_APP_PAGE_gc = (0x24<<0),
NVM_CMD_ERASE_WRITE_APP_PAGE_gc = (0x25<<0),
NVM_CMD_ERASE_FLASH_BUFFER_gc = (0x26<<0),
NVM_CMD_ERASE_BOOT_PAGE_gc = (0x2A<<0),
NVM_CMD_WRITE_BOOT_PAGE_gc = (0x2C<<0),
NVM_CMD_ERASE_WRITE_BOOT_PAGE_gc = (0x2D<<0),
NVM_CMD_ERASE_EEPROM_gc = (0x30<<0),
NVM_CMD_ERASE_EEPROM_PAGE_gc = (0x32<<0),
NVM_CMD_LOAD_EEPROM_BUFFER_gc = (0x33<<0),
NVM_CMD_WRITE_EEPROM_PAGE_gc = (0x34<<0),
NVM_CMD_ERASE_WRITE_EEPROM_PAGE_gc = (0x35<<0),
NVM_CMD_ERASE_EEPROM_BUFFER_gc = (0x36<<0),
NVM_CMD_APP_CRC_gc = (0x38<<0),
NVM_CMD_BOOT_CRC_gc = (0x39<<0),
NVM_CMD_FLASH_RANGE_CRC_gc = (0x3A<<0)
} |
|
enum | NVM_SPMLVL_enum {
NVM_SPMLVL_OFF_gc = (0x00<<2),
NVM_SPMLVL_LO_gc = (0x01<<2),
NVM_SPMLVL_MED_gc = (0x02<<2),
NVM_SPMLVL_HI_gc = (0x03<<2),
NVM_SPMLVL_OFF_gc = (0x00<<2),
NVM_SPMLVL_LO_gc = (0x01<<2),
NVM_SPMLVL_MED_gc = (0x02<<2),
NVM_SPMLVL_HI_gc = (0x03<<2),
NVM_SPMLVL_OFF_gc = (0x00<<2),
NVM_SPMLVL_LO_gc = (0x01<<2),
NVM_SPMLVL_MED_gc = (0x02<<2),
NVM_SPMLVL_HI_gc = (0x03<<2),
NVM_SPMLVL_OFF_gc = (0x00<<2),
NVM_SPMLVL_LO_gc = (0x01<<2),
NVM_SPMLVL_MED_gc = (0x02<<2),
NVM_SPMLVL_HI_gc = (0x03<<2),
NVM_SPMLVL_OFF_gc = (0x00<<2),
NVM_SPMLVL_LO_gc = (0x01<<2),
NVM_SPMLVL_MED_gc = (0x02<<2),
NVM_SPMLVL_HI_gc = (0x03<<2),
NVM_SPMLVL_OFF_gc = (0x00<<2),
NVM_SPMLVL_LO_gc = (0x01<<2),
NVM_SPMLVL_MED_gc = (0x02<<2),
NVM_SPMLVL_HI_gc = (0x03<<2),
NVM_SPMLVL_OFF_gc = (0x00<<2),
NVM_SPMLVL_LO_gc = (0x01<<2),
NVM_SPMLVL_MED_gc = (0x02<<2),
NVM_SPMLVL_HI_gc = (0x03<<2),
NVM_SPMLVL_OFF_gc = (0x00<<2),
NVM_SPMLVL_LO_gc = (0x01<<2),
NVM_SPMLVL_MED_gc = (0x02<<2),
NVM_SPMLVL_HI_gc = (0x03<<2),
NVM_SPMLVL_OFF_gc = (0x00<<2),
NVM_SPMLVL_LO_gc = (0x01<<2),
NVM_SPMLVL_MED_gc = (0x02<<2),
NVM_SPMLVL_HI_gc = (0x03<<2),
NVM_SPMLVL_OFF_gc = (0x00<<2),
NVM_SPMLVL_LO_gc = (0x01<<2),
NVM_SPMLVL_MED_gc = (0x02<<2),
NVM_SPMLVL_HI_gc = (0x03<<2),
NVM_SPMLVL_OFF_gc = (0x00<<2),
NVM_SPMLVL_LO_gc = (0x01<<2),
NVM_SPMLVL_MED_gc = (0x02<<2),
NVM_SPMLVL_HI_gc = (0x03<<2),
NVM_SPMLVL_OFF_gc = (0x00<<2),
NVM_SPMLVL_LO_gc = (0x01<<2),
NVM_SPMLVL_MED_gc = (0x02<<2),
NVM_SPMLVL_HI_gc = (0x03<<2),
NVM_SPMLVL_OFF_gc = (0x00<<2),
NVM_SPMLVL_LO_gc = (0x01<<2),
NVM_SPMLVL_MED_gc = (0x02<<2),
NVM_SPMLVL_HI_gc = (0x03<<2),
NVM_SPMLVL_OFF_gc = (0x00<<2),
NVM_SPMLVL_LO_gc = (0x01<<2),
NVM_SPMLVL_MED_gc = (0x02<<2),
NVM_SPMLVL_HI_gc = (0x03<<2),
NVM_SPMLVL_OFF_gc = (0x00<<2),
NVM_SPMLVL_LO_gc = (0x01<<2),
NVM_SPMLVL_MED_gc = (0x02<<2),
NVM_SPMLVL_HI_gc = (0x03<<2)
} |
|
enum | NVM_EELVL_enum {
NVM_EELVL_OFF_gc = (0x00<<0),
NVM_EELVL_LO_gc = (0x01<<0),
NVM_EELVL_MED_gc = (0x02<<0),
NVM_EELVL_HI_gc = (0x03<<0),
NVM_EELVL_OFF_gc = (0x00<<0),
NVM_EELVL_LO_gc = (0x01<<0),
NVM_EELVL_MED_gc = (0x02<<0),
NVM_EELVL_HI_gc = (0x03<<0),
NVM_EELVL_OFF_gc = (0x00<<0),
NVM_EELVL_LO_gc = (0x01<<0),
NVM_EELVL_MED_gc = (0x02<<0),
NVM_EELVL_HI_gc = (0x03<<0),
NVM_EELVL_OFF_gc = (0x00<<0),
NVM_EELVL_LO_gc = (0x01<<0),
NVM_EELVL_MED_gc = (0x02<<0),
NVM_EELVL_HI_gc = (0x03<<0),
NVM_EELVL_OFF_gc = (0x00<<0),
NVM_EELVL_LO_gc = (0x01<<0),
NVM_EELVL_MED_gc = (0x02<<0),
NVM_EELVL_HI_gc = (0x03<<0),
NVM_EELVL_OFF_gc = (0x00<<0),
NVM_EELVL_LO_gc = (0x01<<0),
NVM_EELVL_MED_gc = (0x02<<0),
NVM_EELVL_HI_gc = (0x03<<0),
NVM_EELVL_OFF_gc = (0x00<<0),
NVM_EELVL_LO_gc = (0x01<<0),
NVM_EELVL_MED_gc = (0x02<<0),
NVM_EELVL_HI_gc = (0x03<<0),
NVM_EELVL_OFF_gc = (0x00<<0),
NVM_EELVL_LO_gc = (0x01<<0),
NVM_EELVL_MED_gc = (0x02<<0),
NVM_EELVL_HI_gc = (0x03<<0),
NVM_EELVL_OFF_gc = (0x00<<0),
NVM_EELVL_LO_gc = (0x01<<0),
NVM_EELVL_MED_gc = (0x02<<0),
NVM_EELVL_HI_gc = (0x03<<0),
NVM_EELVL_OFF_gc = (0x00<<0),
NVM_EELVL_LO_gc = (0x01<<0),
NVM_EELVL_MED_gc = (0x02<<0),
NVM_EELVL_HI_gc = (0x03<<0),
NVM_EELVL_OFF_gc = (0x00<<0),
NVM_EELVL_LO_gc = (0x01<<0),
NVM_EELVL_MED_gc = (0x02<<0),
NVM_EELVL_HI_gc = (0x03<<0),
NVM_EELVL_OFF_gc = (0x00<<0),
NVM_EELVL_LO_gc = (0x01<<0),
NVM_EELVL_MED_gc = (0x02<<0),
NVM_EELVL_HI_gc = (0x03<<0),
NVM_EELVL_OFF_gc = (0x00<<0),
NVM_EELVL_LO_gc = (0x01<<0),
NVM_EELVL_MED_gc = (0x02<<0),
NVM_EELVL_HI_gc = (0x03<<0),
NVM_EELVL_OFF_gc = (0x00<<0),
NVM_EELVL_LO_gc = (0x01<<0),
NVM_EELVL_MED_gc = (0x02<<0),
NVM_EELVL_HI_gc = (0x03<<0),
NVM_EELVL_OFF_gc = (0x00<<0),
NVM_EELVL_LO_gc = (0x01<<0),
NVM_EELVL_MED_gc = (0x02<<0),
NVM_EELVL_HI_gc = (0x03<<0)
} |
|
enum | NVM_BLBB_enum {
NVM_BLBB_NOLOCK_gc = (0x03<<6),
NVM_BLBB_WLOCK_gc = (0x02<<6),
NVM_BLBB_RLOCK_gc = (0x01<<6),
NVM_BLBB_RWLOCK_gc = (0x00<<6),
NVM_BLBB_NOLOCK_gc = (0x03<<6),
NVM_BLBB_WLOCK_gc = (0x02<<6),
NVM_BLBB_RLOCK_gc = (0x01<<6),
NVM_BLBB_RWLOCK_gc = (0x00<<6),
NVM_BLBB_NOLOCK_gc = (0x03<<6),
NVM_BLBB_WLOCK_gc = (0x02<<6),
NVM_BLBB_RLOCK_gc = (0x01<<6),
NVM_BLBB_RWLOCK_gc = (0x00<<6),
NVM_BLBB_NOLOCK_gc = (0x03<<6),
NVM_BLBB_WLOCK_gc = (0x02<<6),
NVM_BLBB_RLOCK_gc = (0x01<<6),
NVM_BLBB_RWLOCK_gc = (0x00<<6),
NVM_BLBB_NOLOCK_gc = (0x03<<6),
NVM_BLBB_WLOCK_gc = (0x02<<6),
NVM_BLBB_RLOCK_gc = (0x01<<6),
NVM_BLBB_RWLOCK_gc = (0x00<<6),
NVM_BLBB_NOLOCK_gc = (0x03<<6),
NVM_BLBB_WLOCK_gc = (0x02<<6),
NVM_BLBB_RLOCK_gc = (0x01<<6),
NVM_BLBB_RWLOCK_gc = (0x00<<6),
NVM_BLBB_NOLOCK_gc = (0x03<<6),
NVM_BLBB_WLOCK_gc = (0x02<<6),
NVM_BLBB_RLOCK_gc = (0x01<<6),
NVM_BLBB_RWLOCK_gc = (0x00<<6),
NVM_BLBB_NOLOCK_gc = (0x03<<6),
NVM_BLBB_WLOCK_gc = (0x02<<6),
NVM_BLBB_RLOCK_gc = (0x01<<6),
NVM_BLBB_RWLOCK_gc = (0x00<<6),
NVM_BLBB_NOLOCK_gc = (0x03<<6),
NVM_BLBB_WLOCK_gc = (0x02<<6),
NVM_BLBB_RLOCK_gc = (0x01<<6),
NVM_BLBB_RWLOCK_gc = (0x00<<6),
NVM_BLBB_NOLOCK_gc = (0x03<<6),
NVM_BLBB_WLOCK_gc = (0x02<<6),
NVM_BLBB_RLOCK_gc = (0x01<<6),
NVM_BLBB_RWLOCK_gc = (0x00<<6),
NVM_BLBB_NOLOCK_gc = (0x03<<6),
NVM_BLBB_WLOCK_gc = (0x02<<6),
NVM_BLBB_RLOCK_gc = (0x01<<6),
NVM_BLBB_RWLOCK_gc = (0x00<<6),
NVM_BLBB_NOLOCK_gc = (0x03<<6),
NVM_BLBB_WLOCK_gc = (0x02<<6),
NVM_BLBB_RLOCK_gc = (0x01<<6),
NVM_BLBB_RWLOCK_gc = (0x00<<6),
NVM_BLBB_NOLOCK_gc = (0x03<<6),
NVM_BLBB_WLOCK_gc = (0x02<<6),
NVM_BLBB_RLOCK_gc = (0x01<<6),
NVM_BLBB_RWLOCK_gc = (0x00<<6),
NVM_BLBB_NOLOCK_gc = (0x03<<6),
NVM_BLBB_WLOCK_gc = (0x02<<6),
NVM_BLBB_RLOCK_gc = (0x01<<6),
NVM_BLBB_RWLOCK_gc = (0x00<<6),
NVM_BLBB_NOLOCK_gc = (0x03<<6),
NVM_BLBB_WLOCK_gc = (0x02<<6),
NVM_BLBB_RLOCK_gc = (0x01<<6),
NVM_BLBB_RWLOCK_gc = (0x00<<6)
} |
|
enum | NVM_BLBA_enum {
NVM_BLBA_NOLOCK_gc = (0x03<<4),
NVM_BLBA_WLOCK_gc = (0x02<<4),
NVM_BLBA_RLOCK_gc = (0x01<<4),
NVM_BLBA_RWLOCK_gc = (0x00<<4),
NVM_BLBA_NOLOCK_gc = (0x03<<4),
NVM_BLBA_WLOCK_gc = (0x02<<4),
NVM_BLBA_RLOCK_gc = (0x01<<4),
NVM_BLBA_RWLOCK_gc = (0x00<<4),
NVM_BLBA_NOLOCK_gc = (0x03<<4),
NVM_BLBA_WLOCK_gc = (0x02<<4),
NVM_BLBA_RLOCK_gc = (0x01<<4),
NVM_BLBA_RWLOCK_gc = (0x00<<4),
NVM_BLBA_NOLOCK_gc = (0x03<<4),
NVM_BLBA_WLOCK_gc = (0x02<<4),
NVM_BLBA_RLOCK_gc = (0x01<<4),
NVM_BLBA_RWLOCK_gc = (0x00<<4),
NVM_BLBA_NOLOCK_gc = (0x03<<4),
NVM_BLBA_WLOCK_gc = (0x02<<4),
NVM_BLBA_RLOCK_gc = (0x01<<4),
NVM_BLBA_RWLOCK_gc = (0x00<<4),
NVM_BLBA_NOLOCK_gc = (0x03<<4),
NVM_BLBA_WLOCK_gc = (0x02<<4),
NVM_BLBA_RLOCK_gc = (0x01<<4),
NVM_BLBA_RWLOCK_gc = (0x00<<4),
NVM_BLBA_NOLOCK_gc = (0x03<<4),
NVM_BLBA_WLOCK_gc = (0x02<<4),
NVM_BLBA_RLOCK_gc = (0x01<<4),
NVM_BLBA_RWLOCK_gc = (0x00<<4),
NVM_BLBA_NOLOCK_gc = (0x03<<4),
NVM_BLBA_WLOCK_gc = (0x02<<4),
NVM_BLBA_RLOCK_gc = (0x01<<4),
NVM_BLBA_RWLOCK_gc = (0x00<<4),
NVM_BLBA_NOLOCK_gc = (0x03<<4),
NVM_BLBA_WLOCK_gc = (0x02<<4),
NVM_BLBA_RLOCK_gc = (0x01<<4),
NVM_BLBA_RWLOCK_gc = (0x00<<4),
NVM_BLBA_NOLOCK_gc = (0x03<<4),
NVM_BLBA_WLOCK_gc = (0x02<<4),
NVM_BLBA_RLOCK_gc = (0x01<<4),
NVM_BLBA_RWLOCK_gc = (0x00<<4),
NVM_BLBA_NOLOCK_gc = (0x03<<4),
NVM_BLBA_WLOCK_gc = (0x02<<4),
NVM_BLBA_RLOCK_gc = (0x01<<4),
NVM_BLBA_RWLOCK_gc = (0x00<<4),
NVM_BLBA_NOLOCK_gc = (0x03<<4),
NVM_BLBA_WLOCK_gc = (0x02<<4),
NVM_BLBA_RLOCK_gc = (0x01<<4),
NVM_BLBA_RWLOCK_gc = (0x00<<4),
NVM_BLBA_NOLOCK_gc = (0x03<<4),
NVM_BLBA_WLOCK_gc = (0x02<<4),
NVM_BLBA_RLOCK_gc = (0x01<<4),
NVM_BLBA_RWLOCK_gc = (0x00<<4),
NVM_BLBA_NOLOCK_gc = (0x03<<4),
NVM_BLBA_WLOCK_gc = (0x02<<4),
NVM_BLBA_RLOCK_gc = (0x01<<4),
NVM_BLBA_RWLOCK_gc = (0x00<<4),
NVM_BLBA_NOLOCK_gc = (0x03<<4),
NVM_BLBA_WLOCK_gc = (0x02<<4),
NVM_BLBA_RLOCK_gc = (0x01<<4),
NVM_BLBA_RWLOCK_gc = (0x00<<4)
} |
|
enum | NVM_BLBAT_enum {
NVM_BLBAT_NOLOCK_gc = (0x03<<2),
NVM_BLBAT_WLOCK_gc = (0x02<<2),
NVM_BLBAT_RLOCK_gc = (0x01<<2),
NVM_BLBAT_RWLOCK_gc = (0x00<<2),
NVM_BLBAT_NOLOCK_gc = (0x03<<2),
NVM_BLBAT_WLOCK_gc = (0x02<<2),
NVM_BLBAT_RLOCK_gc = (0x01<<2),
NVM_BLBAT_RWLOCK_gc = (0x00<<2),
NVM_BLBAT_NOLOCK_gc = (0x03<<2),
NVM_BLBAT_WLOCK_gc = (0x02<<2),
NVM_BLBAT_RLOCK_gc = (0x01<<2),
NVM_BLBAT_RWLOCK_gc = (0x00<<2),
NVM_BLBAT_NOLOCK_gc = (0x03<<2),
NVM_BLBAT_WLOCK_gc = (0x02<<2),
NVM_BLBAT_RLOCK_gc = (0x01<<2),
NVM_BLBAT_RWLOCK_gc = (0x00<<2),
NVM_BLBAT_NOLOCK_gc = (0x03<<2),
NVM_BLBAT_WLOCK_gc = (0x02<<2),
NVM_BLBAT_RLOCK_gc = (0x01<<2),
NVM_BLBAT_RWLOCK_gc = (0x00<<2),
NVM_BLBAT_NOLOCK_gc = (0x03<<2),
NVM_BLBAT_WLOCK_gc = (0x02<<2),
NVM_BLBAT_RLOCK_gc = (0x01<<2),
NVM_BLBAT_RWLOCK_gc = (0x00<<2),
NVM_BLBAT_NOLOCK_gc = (0x03<<2),
NVM_BLBAT_WLOCK_gc = (0x02<<2),
NVM_BLBAT_RLOCK_gc = (0x01<<2),
NVM_BLBAT_RWLOCK_gc = (0x00<<2),
NVM_BLBAT_NOLOCK_gc = (0x03<<2),
NVM_BLBAT_WLOCK_gc = (0x02<<2),
NVM_BLBAT_RLOCK_gc = (0x01<<2),
NVM_BLBAT_RWLOCK_gc = (0x00<<2),
NVM_BLBAT_NOLOCK_gc = (0x03<<2),
NVM_BLBAT_WLOCK_gc = (0x02<<2),
NVM_BLBAT_RLOCK_gc = (0x01<<2),
NVM_BLBAT_RWLOCK_gc = (0x00<<2),
NVM_BLBAT_NOLOCK_gc = (0x03<<2),
NVM_BLBAT_WLOCK_gc = (0x02<<2),
NVM_BLBAT_RLOCK_gc = (0x01<<2),
NVM_BLBAT_RWLOCK_gc = (0x00<<2),
NVM_BLBAT_NOLOCK_gc = (0x03<<2),
NVM_BLBAT_WLOCK_gc = (0x02<<2),
NVM_BLBAT_RLOCK_gc = (0x01<<2),
NVM_BLBAT_RWLOCK_gc = (0x00<<2),
NVM_BLBAT_NOLOCK_gc = (0x03<<2),
NVM_BLBAT_WLOCK_gc = (0x02<<2),
NVM_BLBAT_RLOCK_gc = (0x01<<2),
NVM_BLBAT_RWLOCK_gc = (0x00<<2),
NVM_BLBAT_NOLOCK_gc = (0x03<<2),
NVM_BLBAT_WLOCK_gc = (0x02<<2),
NVM_BLBAT_RLOCK_gc = (0x01<<2),
NVM_BLBAT_RWLOCK_gc = (0x00<<2),
NVM_BLBAT_NOLOCK_gc = (0x03<<2),
NVM_BLBAT_WLOCK_gc = (0x02<<2),
NVM_BLBAT_RLOCK_gc = (0x01<<2),
NVM_BLBAT_RWLOCK_gc = (0x00<<2),
NVM_BLBAT_NOLOCK_gc = (0x03<<2),
NVM_BLBAT_WLOCK_gc = (0x02<<2),
NVM_BLBAT_RLOCK_gc = (0x01<<2),
NVM_BLBAT_RWLOCK_gc = (0x00<<2)
} |
|
enum | NVM_LB_enum {
NVM_LB_NOLOCK_gc = (0x03<<0),
NVM_LB_WLOCK_gc = (0x02<<0),
NVM_LB_RWLOCK_gc = (0x00<<0),
NVM_LB_NOLOCK_gc = (0x03<<0),
NVM_LB_WLOCK_gc = (0x02<<0),
NVM_LB_RWLOCK_gc = (0x00<<0),
NVM_LB_NOLOCK_gc = (0x03<<0),
NVM_LB_WLOCK_gc = (0x02<<0),
NVM_LB_RWLOCK_gc = (0x00<<0),
NVM_LB_NOLOCK_gc = (0x03<<0),
NVM_LB_WLOCK_gc = (0x02<<0),
NVM_LB_RWLOCK_gc = (0x00<<0),
NVM_LB_NOLOCK_gc = (0x03<<0),
NVM_LB_WLOCK_gc = (0x02<<0),
NVM_LB_RWLOCK_gc = (0x00<<0),
NVM_LB_NOLOCK_gc = (0x03<<0),
NVM_LB_WLOCK_gc = (0x02<<0),
NVM_LB_RWLOCK_gc = (0x00<<0),
NVM_LB_NOLOCK_gc = (0x03<<0),
NVM_LB_WLOCK_gc = (0x02<<0),
NVM_LB_RWLOCK_gc = (0x00<<0),
NVM_LB_NOLOCK_gc = (0x03<<0),
NVM_LB_WLOCK_gc = (0x02<<0),
NVM_LB_RWLOCK_gc = (0x00<<0),
NVM_LB_NOLOCK_gc = (0x03<<0),
NVM_LB_WLOCK_gc = (0x02<<0),
NVM_LB_RWLOCK_gc = (0x00<<0),
NVM_LB_NOLOCK_gc = (0x03<<0),
NVM_LB_WLOCK_gc = (0x02<<0),
NVM_LB_RWLOCK_gc = (0x00<<0),
NVM_LB_NOLOCK_gc = (0x03<<0),
NVM_LB_WLOCK_gc = (0x02<<0),
NVM_LB_RWLOCK_gc = (0x00<<0),
NVM_LB_NOLOCK_gc = (0x03<<0),
NVM_LB_WLOCK_gc = (0x02<<0),
NVM_LB_RWLOCK_gc = (0x00<<0),
NVM_LB_NOLOCK_gc = (0x03<<0),
NVM_LB_WLOCK_gc = (0x02<<0),
NVM_LB_RWLOCK_gc = (0x00<<0),
NVM_LB_NOLOCK_gc = (0x03<<0),
NVM_LB_WLOCK_gc = (0x02<<0),
NVM_LB_RWLOCK_gc = (0x00<<0),
NVM_LB_NOLOCK_gc = (0x03<<0),
NVM_LB_WLOCK_gc = (0x02<<0),
NVM_LB_RWLOCK_gc = (0x00<<0)
} |
|
enum | BOOTRST_enum {
BOOTRST_BOOTLDR_gc = (0x00<<6),
BOOTRST_APPLICATION_gc = (0x01<<6),
BOOTRST_BOOTLDR_gc = (0x00<<6),
BOOTRST_APPLICATION_gc = (0x01<<6),
BOOTRST_BOOTLDR_gc = (0x00<<6),
BOOTRST_APPLICATION_gc = (0x01<<6),
BOOTRST_BOOTLDR_gc = (0x00<<6),
BOOTRST_APPLICATION_gc = (0x01<<6),
BOOTRST_BOOTLDR_gc = (0x00<<6),
BOOTRST_APPLICATION_gc = (0x01<<6),
BOOTRST_BOOTLDR_gc = (0x00<<6),
BOOTRST_APPLICATION_gc = (0x01<<6),
BOOTRST_BOOTLDR_gc = (0x00<<6),
BOOTRST_APPLICATION_gc = (0x01<<6),
BOOTRST_BOOTLDR_gc = (0x00<<6),
BOOTRST_APPLICATION_gc = (0x01<<6),
BOOTRST_BOOTLDR_gc = (0x00<<6),
BOOTRST_APPLICATION_gc = (0x01<<6),
BOOTRST_BOOTLDR_gc = (0x00<<6),
BOOTRST_APPLICATION_gc = (0x01<<6),
BOOTRST_BOOTLDR_gc = (0x00<<6),
BOOTRST_APPLICATION_gc = (0x01<<6),
BOOTRST_BOOTLDR_gc = (0x00<<6),
BOOTRST_APPLICATION_gc = (0x01<<6),
BOOTRST_BOOTLDR_gc = (0x00<<6),
BOOTRST_APPLICATION_gc = (0x01<<6),
BOOTRST_BOOTLDR_gc = (0x00<<6),
BOOTRST_APPLICATION_gc = (0x01<<6),
BOOTRST_BOOTLDR_gc = (0x00<<6),
BOOTRST_APPLICATION_gc = (0x01<<6)
} |
|
enum | BOD_enum {
BOD_INSAMPLEDMODE_gc = (0x01<<2),
BOD_CONTINOUSLY_gc = (0x02<<2),
BOD_DISABLED_gc = (0x03<<2),
BOD_INSAMPLEDMODE_gc = (0x01<<0),
BOD_CONTINOUSLY_gc = (0x02<<0),
BOD_DISABLED_gc = (0x03<<0),
BOD_INSAMPLEDMODE_gc = (0x01<<0),
BOD_CONTINOUSLY_gc = (0x02<<0),
BOD_DISABLED_gc = (0x03<<0),
BOD_INSAMPLEDMODE_gc = (0x01<<0),
BOD_CONTINOUSLY_gc = (0x02<<0),
BOD_DISABLED_gc = (0x03<<0),
BOD_INSAMPLEDMODE_gc = (0x01<<0),
BOD_CONTINOUSLY_gc = (0x02<<0),
BOD_DISABLED_gc = (0x03<<0),
BOD_INSAMPLEDMODE_gc = (0x01<<0),
BOD_CONTINOUSLY_gc = (0x02<<0),
BOD_DISABLED_gc = (0x03<<0),
BOD_INSAMPLEDMODE_gc = (0x01<<0),
BOD_CONTINOUSLY_gc = (0x02<<0),
BOD_DISABLED_gc = (0x03<<0),
BOD_INSAMPLEDMODE_gc = (0x01<<0),
BOD_CONTINOUSLY_gc = (0x02<<0),
BOD_DISABLED_gc = (0x03<<0),
BOD_INSAMPLEDMODE_gc = (0x01<<0),
BOD_CONTINOUSLY_gc = (0x02<<0),
BOD_DISABLED_gc = (0x03<<0),
BOD_INSAMPLEDMODE_gc = (0x01<<0),
BOD_CONTINOUSLY_gc = (0x02<<0),
BOD_DISABLED_gc = (0x03<<0),
BOD_INSAMPLEDMODE_gc = (0x01<<0),
BOD_CONTINOUSLY_gc = (0x02<<0),
BOD_DISABLED_gc = (0x03<<0),
BOD_INSAMPLEDMODE_gc = (0x01<<0),
BOD_CONTINOUSLY_gc = (0x02<<0),
BOD_DISABLED_gc = (0x03<<0),
BOD_INSAMPLEDMODE_gc = (0x01<<2),
BOD_CONTINOUSLY_gc = (0x02<<2),
BOD_DISABLED_gc = (0x03<<2),
BOD_INSAMPLEDMODE_gc = (0x01<<0),
BOD_CONTINOUSLY_gc = (0x02<<0),
BOD_DISABLED_gc = (0x03<<0),
BOD_INSAMPLEDMODE_gc = (0x01<<0),
BOD_CONTINOUSLY_gc = (0x02<<0),
BOD_DISABLED_gc = (0x03<<0)
} |
|
enum | WD_enum {
WD_8CLK_gc = (0x00<<4),
WD_16CLK_gc = (0x01<<4),
WD_32CLK_gc = (0x02<<4),
WD_64CLK_gc = (0x03<<4),
WD_128CLK_gc = (0x04<<4),
WD_256CLK_gc = (0x05<<4),
WD_512CLK_gc = (0x06<<4),
WD_1KCLK_gc = (0x07<<4),
WD_2KCLK_gc = (0x08<<4),
WD_4KCLK_gc = (0x09<<4),
WD_8KCLK_gc = (0x0A<<4),
WD_8CLK_gc = (0x00<<4),
WD_16CLK_gc = (0x01<<4),
WD_32CLK_gc = (0x02<<4),
WD_64CLK_gc = (0x03<<4),
WD_128CLK_gc = (0x04<<4),
WD_256CLK_gc = (0x05<<4),
WD_512CLK_gc = (0x06<<4),
WD_1KCLK_gc = (0x07<<4),
WD_2KCLK_gc = (0x08<<4),
WD_4KCLK_gc = (0x09<<4),
WD_8KCLK_gc = (0x0A<<4),
WD_8CLK_gc = (0x00<<4),
WD_16CLK_gc = (0x01<<4),
WD_32CLK_gc = (0x02<<4),
WD_64CLK_gc = (0x03<<4),
WD_128CLK_gc = (0x04<<4),
WD_256CLK_gc = (0x05<<4),
WD_512CLK_gc = (0x06<<4),
WD_1KCLK_gc = (0x07<<4),
WD_2KCLK_gc = (0x08<<4),
WD_4KCLK_gc = (0x09<<4),
WD_8KCLK_gc = (0x0A<<4),
WD_8CLK_gc = (0x00<<4),
WD_16CLK_gc = (0x01<<4),
WD_32CLK_gc = (0x02<<4),
WD_64CLK_gc = (0x03<<4),
WD_128CLK_gc = (0x04<<4),
WD_256CLK_gc = (0x05<<4),
WD_512CLK_gc = (0x06<<4),
WD_1KCLK_gc = (0x07<<4),
WD_2KCLK_gc = (0x08<<4),
WD_4KCLK_gc = (0x09<<4),
WD_8KCLK_gc = (0x0A<<4),
WD_8CLK_gc = (0x00<<4),
WD_16CLK_gc = (0x01<<4),
WD_32CLK_gc = (0x02<<4),
WD_64CLK_gc = (0x03<<4),
WD_128CLK_gc = (0x04<<4),
WD_256CLK_gc = (0x05<<4),
WD_512CLK_gc = (0x06<<4),
WD_1KCLK_gc = (0x07<<4),
WD_2KCLK_gc = (0x08<<4),
WD_4KCLK_gc = (0x09<<4),
WD_8KCLK_gc = (0x0A<<4),
WD_8CLK_gc = (0x00<<4),
WD_16CLK_gc = (0x01<<4),
WD_32CLK_gc = (0x02<<4),
WD_64CLK_gc = (0x03<<4),
WD_128CLK_gc = (0x04<<4),
WD_256CLK_gc = (0x05<<4),
WD_512CLK_gc = (0x06<<4),
WD_1KCLK_gc = (0x07<<4),
WD_2KCLK_gc = (0x08<<4),
WD_4KCLK_gc = (0x09<<4),
WD_8KCLK_gc = (0x0A<<4),
WD_8CLK_gc = (0x00<<4),
WD_16CLK_gc = (0x01<<4),
WD_32CLK_gc = (0x02<<4),
WD_64CLK_gc = (0x03<<4),
WD_128CLK_gc = (0x04<<4),
WD_256CLK_gc = (0x05<<4),
WD_512CLK_gc = (0x06<<4),
WD_1KCLK_gc = (0x07<<4),
WD_2KCLK_gc = (0x08<<4),
WD_4KCLK_gc = (0x09<<4),
WD_8KCLK_gc = (0x0A<<4),
WD_8CLK_gc = (0x00<<4),
WD_16CLK_gc = (0x01<<4),
WD_32CLK_gc = (0x02<<4),
WD_64CLK_gc = (0x03<<4),
WD_128CLK_gc = (0x04<<4),
WD_256CLK_gc = (0x05<<4),
WD_512CLK_gc = (0x06<<4),
WD_1KCLK_gc = (0x07<<4),
WD_2KCLK_gc = (0x08<<4),
WD_4KCLK_gc = (0x09<<4),
WD_8KCLK_gc = (0x0A<<4),
WD_8CLK_gc = (0x00<<4),
WD_16CLK_gc = (0x01<<4),
WD_32CLK_gc = (0x02<<4),
WD_64CLK_gc = (0x03<<4),
WD_128CLK_gc = (0x04<<4),
WD_256CLK_gc = (0x05<<4),
WD_512CLK_gc = (0x06<<4),
WD_1KCLK_gc = (0x07<<4),
WD_2KCLK_gc = (0x08<<4),
WD_4KCLK_gc = (0x09<<4),
WD_8KCLK_gc = (0x0A<<4),
WD_8CLK_gc = (0x00<<4),
WD_16CLK_gc = (0x01<<4),
WD_32CLK_gc = (0x02<<4),
WD_64CLK_gc = (0x03<<4),
WD_128CLK_gc = (0x04<<4),
WD_256CLK_gc = (0x05<<4),
WD_512CLK_gc = (0x06<<4),
WD_1KCLK_gc = (0x07<<4),
WD_2KCLK_gc = (0x08<<4),
WD_4KCLK_gc = (0x09<<4),
WD_8KCLK_gc = (0x0A<<4),
WD_8CLK_gc = (0x00<<4),
WD_16CLK_gc = (0x01<<4),
WD_32CLK_gc = (0x02<<4),
WD_64CLK_gc = (0x03<<4),
WD_128CLK_gc = (0x04<<4),
WD_256CLK_gc = (0x05<<4),
WD_512CLK_gc = (0x06<<4),
WD_1KCLK_gc = (0x07<<4),
WD_2KCLK_gc = (0x08<<4),
WD_4KCLK_gc = (0x09<<4),
WD_8KCLK_gc = (0x0A<<4),
WD_8CLK_gc = (0x00<<4),
WD_16CLK_gc = (0x01<<4),
WD_32CLK_gc = (0x02<<4),
WD_64CLK_gc = (0x03<<4),
WD_128CLK_gc = (0x04<<4),
WD_256CLK_gc = (0x05<<4),
WD_512CLK_gc = (0x06<<4),
WD_1KCLK_gc = (0x07<<4),
WD_2KCLK_gc = (0x08<<4),
WD_4KCLK_gc = (0x09<<4),
WD_8KCLK_gc = (0x0A<<4),
WD_8CLK_gc = (0x00<<4),
WD_16CLK_gc = (0x01<<4),
WD_32CLK_gc = (0x02<<4),
WD_64CLK_gc = (0x03<<4),
WD_128CLK_gc = (0x04<<4),
WD_256CLK_gc = (0x05<<4),
WD_512CLK_gc = (0x06<<4),
WD_1KCLK_gc = (0x07<<4),
WD_2KCLK_gc = (0x08<<4),
WD_4KCLK_gc = (0x09<<4),
WD_8KCLK_gc = (0x0A<<4),
WD_8CLK_gc = (0x00<<4),
WD_16CLK_gc = (0x01<<4),
WD_32CLK_gc = (0x02<<4),
WD_64CLK_gc = (0x03<<4),
WD_128CLK_gc = (0x04<<4),
WD_256CLK_gc = (0x05<<4),
WD_512CLK_gc = (0x06<<4),
WD_1KCLK_gc = (0x07<<4),
WD_2KCLK_gc = (0x08<<4),
WD_4KCLK_gc = (0x09<<4),
WD_8KCLK_gc = (0x0A<<4),
WD_8CLK_gc = (0x00<<4),
WD_16CLK_gc = (0x01<<4),
WD_32CLK_gc = (0x02<<4),
WD_64CLK_gc = (0x03<<4),
WD_128CLK_gc = (0x04<<4),
WD_256CLK_gc = (0x05<<4),
WD_512CLK_gc = (0x06<<4),
WD_1KCLK_gc = (0x07<<4),
WD_2KCLK_gc = (0x08<<4),
WD_4KCLK_gc = (0x09<<4),
WD_8KCLK_gc = (0x0A<<4)
} |
|
enum | SUT_enum {
SUT_0MS_gc = (0x03<<2),
SUT_4MS_gc = (0x01<<2),
SUT_64MS_gc = (0x00<<2),
SUT_0MS_gc = (0x03<<2),
SUT_4MS_gc = (0x01<<2),
SUT_64MS_gc = (0x00<<2),
SUT_0MS_gc = (0x03<<2),
SUT_4MS_gc = (0x01<<2),
SUT_64MS_gc = (0x00<<2),
SUT_0MS_gc = (0x03<<2),
SUT_4MS_gc = (0x01<<2),
SUT_64MS_gc = (0x00<<2),
SUT_0MS_gc = (0x03<<2),
SUT_4MS_gc = (0x01<<2),
SUT_64MS_gc = (0x00<<2),
SUT_0MS_gc = (0x03<<2),
SUT_4MS_gc = (0x01<<2),
SUT_64MS_gc = (0x00<<2),
SUT_0MS_gc = (0x03<<2),
SUT_4MS_gc = (0x01<<2),
SUT_64MS_gc = (0x00<<2),
SUT_0MS_gc = (0x03<<2),
SUT_4MS_gc = (0x01<<2),
SUT_64MS_gc = (0x00<<2),
SUT_0MS_gc = (0x03<<2),
SUT_4MS_gc = (0x01<<2),
SUT_64MS_gc = (0x00<<2),
SUT_0MS_gc = (0x03<<2),
SUT_4MS_gc = (0x01<<2),
SUT_64MS_gc = (0x00<<2),
SUT_0MS_gc = (0x03<<2),
SUT_4MS_gc = (0x01<<2),
SUT_64MS_gc = (0x00<<2),
SUT_0MS_gc = (0x03<<2),
SUT_4MS_gc = (0x01<<2),
SUT_64MS_gc = (0x00<<2),
SUT_0MS_gc = (0x03<<2),
SUT_4MS_gc = (0x01<<2),
SUT_64MS_gc = (0x00<<2),
SUT_0MS_gc = (0x03<<2),
SUT_4MS_gc = (0x01<<2),
SUT_64MS_gc = (0x00<<2),
SUT_0MS_gc = (0x03<<2),
SUT_4MS_gc = (0x01<<2),
SUT_64MS_gc = (0x00<<2)
} |
|
enum | BODLVL_enum {
BODLVL_1V6_gc = (0x07<<0),
BODLVL_1V9_gc = (0x06<<0),
BODLVL_2V1_gc = (0x05<<0),
BODLVL_2V4_gc = (0x04<<0),
BODLVL_2V6_gc = (0x03<<0),
BODLVL_2V9_gc = (0x02<<0),
BODLVL_3V2_gc = (0x01<<0),
BODLVL_1V6_gc = (0x07<<0),
BODLVL_1V9_gc = (0x06<<0),
BODLVL_2V1_gc = (0x05<<0),
BODLVL_2V4_gc = (0x04<<0),
BODLVL_2V6_gc = (0x03<<0),
BODLVL_2V9_gc = (0x02<<0),
BODLVL_3V2_gc = (0x01<<0),
BODLVL_1V6_gc = (0x07<<0),
BODLVL_1V9_gc = (0x06<<0),
BODLVL_2V1_gc = (0x05<<0),
BODLVL_2V4_gc = (0x04<<0),
BODLVL_2V6_gc = (0x03<<0),
BODLVL_2V9_gc = (0x02<<0),
BODLVL_3V2_gc = (0x01<<0),
BODLVL_1V6_gc = (0x07<<0),
BODLVL_1V9_gc = (0x06<<0),
BODLVL_2V1_gc = (0x05<<0),
BODLVL_2V4_gc = (0x04<<0),
BODLVL_2V6_gc = (0x03<<0),
BODLVL_2V9_gc = (0x02<<0),
BODLVL_3V2_gc = (0x01<<0),
BODLVL_1V6_gc = (0x07<<0),
BODLVL_1V9_gc = (0x06<<0),
BODLVL_2V1_gc = (0x05<<0),
BODLVL_2V4_gc = (0x04<<0),
BODLVL_2V6_gc = (0x03<<0),
BODLVL_2V9_gc = (0x02<<0),
BODLVL_3V2_gc = (0x01<<0),
BODLVL_1V6_gc = (0x07<<0),
BODLVL_1V9_gc = (0x06<<0),
BODLVL_2V1_gc = (0x05<<0),
BODLVL_2V4_gc = (0x04<<0),
BODLVL_2V6_gc = (0x03<<0),
BODLVL_2V9_gc = (0x02<<0),
BODLVL_3V2_gc = (0x01<<0),
BODLVL_1V6_gc = (0x07<<0),
BODLVL_1V9_gc = (0x06<<0),
BODLVL_2V1_gc = (0x05<<0),
BODLVL_2V4_gc = (0x04<<0),
BODLVL_2V6_gc = (0x03<<0),
BODLVL_2V9_gc = (0x02<<0),
BODLVL_3V2_gc = (0x01<<0),
BODLVL_1V6_gc = (0x07<<0),
BODLVL_1V9_gc = (0x06<<0),
BODLVL_2V1_gc = (0x05<<0),
BODLVL_2V4_gc = (0x04<<0),
BODLVL_2V6_gc = (0x03<<0),
BODLVL_2V9_gc = (0x02<<0),
BODLVL_3V2_gc = (0x01<<0),
BODLVL_1V6_gc = (0x07<<0),
BODLVL_1V9_gc = (0x06<<0),
BODLVL_2V1_gc = (0x05<<0),
BODLVL_2V4_gc = (0x04<<0),
BODLVL_2V6_gc = (0x03<<0),
BODLVL_2V9_gc = (0x02<<0),
BODLVL_3V2_gc = (0x01<<0),
BODLVL_1V6_gc = (0x07<<0),
BODLVL_1V9_gc = (0x06<<0),
BODLVL_2V1_gc = (0x05<<0),
BODLVL_2V4_gc = (0x04<<0),
BODLVL_2V6_gc = (0x03<<0),
BODLVL_2V9_gc = (0x02<<0),
BODLVL_3V2_gc = (0x01<<0),
BODLVL_1V6_gc = (0x07<<0),
BODLVL_1V9_gc = (0x06<<0),
BODLVL_2V1_gc = (0x05<<0),
BODLVL_2V4_gc = (0x04<<0),
BODLVL_2V6_gc = (0x03<<0),
BODLVL_2V9_gc = (0x02<<0),
BODLVL_3V2_gc = (0x01<<0),
BODLVL_1V6_gc = (0x07<<0),
BODLVL_1V9_gc = (0x06<<0),
BODLVL_2V1_gc = (0x05<<0),
BODLVL_2V4_gc = (0x04<<0),
BODLVL_2V6_gc = (0x03<<0),
BODLVL_2V9_gc = (0x02<<0),
BODLVL_3V2_gc = (0x01<<0),
BODLVL_1V6_gc = (0x07<<0),
BODLVL_1V9_gc = (0x06<<0),
BODLVL_2V1_gc = (0x05<<0),
BODLVL_2V4_gc = (0x04<<0),
BODLVL_2V6_gc = (0x03<<0),
BODLVL_2V9_gc = (0x02<<0),
BODLVL_3V2_gc = (0x01<<0),
BODLVL_1V6_gc = (0x07<<0),
BODLVL_1V9_gc = (0x06<<0),
BODLVL_2V1_gc = (0x05<<0),
BODLVL_2V4_gc = (0x04<<0),
BODLVL_2V6_gc = (0x03<<0),
BODLVL_2V9_gc = (0x02<<0),
BODLVL_3V2_gc = (0x01<<0),
BODLVL_1V6_gc = (0x07<<0),
BODLVL_1V9_gc = (0x06<<0),
BODLVL_2V1_gc = (0x05<<0),
BODLVL_2V4_gc = (0x04<<0),
BODLVL_2V6_gc = (0x03<<0),
BODLVL_2V9_gc = (0x02<<0),
BODLVL_3V2_gc = (0x01<<0)
} |
|
enum | AC_INTMODE_enum {
AC_INTMODE_BOTHEDGES_gc = (0x00<<6),
AC_INTMODE_FALLING_gc = (0x02<<6),
AC_INTMODE_RISING_gc = (0x03<<6),
AC_INTMODE_BOTHEDGES_gc = (0x00<<6),
AC_INTMODE_FALLING_gc = (0x02<<6),
AC_INTMODE_RISING_gc = (0x03<<6),
AC_INTMODE_BOTHEDGES_gc = (0x00<<6),
AC_INTMODE_FALLING_gc = (0x02<<6),
AC_INTMODE_RISING_gc = (0x03<<6),
AC_INTMODE_BOTHEDGES_gc = (0x00<<6),
AC_INTMODE_FALLING_gc = (0x02<<6),
AC_INTMODE_RISING_gc = (0x03<<6),
AC_INTMODE_BOTHEDGES_gc = (0x00<<6),
AC_INTMODE_FALLING_gc = (0x02<<6),
AC_INTMODE_RISING_gc = (0x03<<6),
AC_INTMODE_BOTHEDGES_gc = (0x00<<6),
AC_INTMODE_FALLING_gc = (0x02<<6),
AC_INTMODE_RISING_gc = (0x03<<6),
AC_INTMODE_BOTHEDGES_gc = (0x00<<6),
AC_INTMODE_FALLING_gc = (0x02<<6),
AC_INTMODE_RISING_gc = (0x03<<6),
AC_INTMODE_BOTHEDGES_gc = (0x00<<6),
AC_INTMODE_FALLING_gc = (0x02<<6),
AC_INTMODE_RISING_gc = (0x03<<6),
AC_INTMODE_BOTHEDGES_gc = (0x00<<6),
AC_INTMODE_FALLING_gc = (0x02<<6),
AC_INTMODE_RISING_gc = (0x03<<6),
AC_INTMODE_BOTHEDGES_gc = (0x00<<6),
AC_INTMODE_FALLING_gc = (0x02<<6),
AC_INTMODE_RISING_gc = (0x03<<6),
AC_INTMODE_BOTHEDGES_gc = (0x00<<6),
AC_INTMODE_FALLING_gc = (0x02<<6),
AC_INTMODE_RISING_gc = (0x03<<6),
AC_INTMODE_BOTHEDGES_gc = (0x00<<6),
AC_INTMODE_FALLING_gc = (0x02<<6),
AC_INTMODE_RISING_gc = (0x03<<6),
AC_INTMODE_BOTHEDGES_gc = (0x00<<6),
AC_INTMODE_FALLING_gc = (0x02<<6),
AC_INTMODE_RISING_gc = (0x03<<6),
AC_INTMODE_BOTHEDGES_gc = (0x00<<6),
AC_INTMODE_FALLING_gc = (0x02<<6),
AC_INTMODE_RISING_gc = (0x03<<6),
AC_INTMODE_BOTHEDGES_gc = (0x00<<6),
AC_INTMODE_FALLING_gc = (0x02<<6),
AC_INTMODE_RISING_gc = (0x03<<6)
} |
|
enum | AC_INTLVL_enum {
AC_INTLVL_OFF_gc = (0x00<<4),
AC_INTLVL_LO_gc = (0x01<<4),
AC_INTLVL_MED_gc = (0x02<<4),
AC_INTLVL_HI_gc = (0x03<<4),
AC_INTLVL_OFF_gc = (0x00<<4),
AC_INTLVL_LO_gc = (0x01<<4),
AC_INTLVL_MED_gc = (0x02<<4),
AC_INTLVL_HI_gc = (0x03<<4),
AC_INTLVL_OFF_gc = (0x00<<4),
AC_INTLVL_LO_gc = (0x01<<4),
AC_INTLVL_MED_gc = (0x02<<4),
AC_INTLVL_HI_gc = (0x03<<4),
AC_INTLVL_OFF_gc = (0x00<<4),
AC_INTLVL_LO_gc = (0x01<<4),
AC_INTLVL_MED_gc = (0x02<<4),
AC_INTLVL_HI_gc = (0x03<<4),
AC_INTLVL_OFF_gc = (0x00<<4),
AC_INTLVL_LO_gc = (0x01<<4),
AC_INTLVL_MED_gc = (0x02<<4),
AC_INTLVL_HI_gc = (0x03<<4),
AC_INTLVL_OFF_gc = (0x00<<4),
AC_INTLVL_LO_gc = (0x01<<4),
AC_INTLVL_MED_gc = (0x02<<4),
AC_INTLVL_HI_gc = (0x03<<4),
AC_INTLVL_OFF_gc = (0x00<<4),
AC_INTLVL_LO_gc = (0x01<<4),
AC_INTLVL_MED_gc = (0x02<<4),
AC_INTLVL_HI_gc = (0x03<<4),
AC_INTLVL_OFF_gc = (0x00<<4),
AC_INTLVL_LO_gc = (0x01<<4),
AC_INTLVL_MED_gc = (0x02<<4),
AC_INTLVL_HI_gc = (0x03<<4),
AC_INTLVL_OFF_gc = (0x00<<4),
AC_INTLVL_LO_gc = (0x01<<4),
AC_INTLVL_MED_gc = (0x02<<4),
AC_INTLVL_HI_gc = (0x03<<4),
AC_INTLVL_OFF_gc = (0x00<<4),
AC_INTLVL_LO_gc = (0x01<<4),
AC_INTLVL_MED_gc = (0x02<<4),
AC_INTLVL_HI_gc = (0x03<<4),
AC_INTLVL_OFF_gc = (0x00<<4),
AC_INTLVL_LO_gc = (0x01<<4),
AC_INTLVL_MED_gc = (0x02<<4),
AC_INTLVL_HI_gc = (0x03<<4),
AC_INTLVL_OFF_gc = (0x00<<4),
AC_INTLVL_LO_gc = (0x01<<4),
AC_INTLVL_MED_gc = (0x02<<4),
AC_INTLVL_HI_gc = (0x03<<4),
AC_INTLVL_OFF_gc = (0x00<<4),
AC_INTLVL_LO_gc = (0x01<<4),
AC_INTLVL_MED_gc = (0x02<<4),
AC_INTLVL_HI_gc = (0x03<<4),
AC_INTLVL_OFF_gc = (0x00<<4),
AC_INTLVL_LO_gc = (0x01<<4),
AC_INTLVL_MED_gc = (0x02<<4),
AC_INTLVL_HI_gc = (0x03<<4),
AC_INTLVL_OFF_gc = (0x00<<4),
AC_INTLVL_LO_gc = (0x01<<4),
AC_INTLVL_MED_gc = (0x02<<4),
AC_INTLVL_HI_gc = (0x03<<4)
} |
|
enum | AC_HYSMODE_enum {
AC_HYSMODE_NO_gc = (0x00<<1),
AC_HYSMODE_SMALL_gc = (0x01<<1),
AC_HYSMODE_LARGE_gc = (0x02<<1),
AC_HYSMODE_NO_gc = (0x00<<1),
AC_HYSMODE_SMALL_gc = (0x01<<1),
AC_HYSMODE_LARGE_gc = (0x02<<1),
AC_HYSMODE_NO_gc = (0x00<<1),
AC_HYSMODE_SMALL_gc = (0x01<<1),
AC_HYSMODE_LARGE_gc = (0x02<<1),
AC_HYSMODE_NO_gc = (0x00<<1),
AC_HYSMODE_SMALL_gc = (0x01<<1),
AC_HYSMODE_LARGE_gc = (0x02<<1),
AC_HYSMODE_NO_gc = (0x00<<1),
AC_HYSMODE_SMALL_gc = (0x01<<1),
AC_HYSMODE_LARGE_gc = (0x02<<1),
AC_HYSMODE_NO_gc = (0x00<<1),
AC_HYSMODE_SMALL_gc = (0x01<<1),
AC_HYSMODE_LARGE_gc = (0x02<<1),
AC_HYSMODE_NO_gc = (0x00<<1),
AC_HYSMODE_SMALL_gc = (0x01<<1),
AC_HYSMODE_LARGE_gc = (0x02<<1),
AC_HYSMODE_NO_gc = (0x00<<1),
AC_HYSMODE_SMALL_gc = (0x01<<1),
AC_HYSMODE_LARGE_gc = (0x02<<1),
AC_HYSMODE_NO_gc = (0x00<<1),
AC_HYSMODE_SMALL_gc = (0x01<<1),
AC_HYSMODE_LARGE_gc = (0x02<<1),
AC_HYSMODE_NO_gc = (0x00<<1),
AC_HYSMODE_SMALL_gc = (0x01<<1),
AC_HYSMODE_LARGE_gc = (0x02<<1),
AC_HYSMODE_NO_gc = (0x00<<1),
AC_HYSMODE_SMALL_gc = (0x01<<1),
AC_HYSMODE_LARGE_gc = (0x02<<1),
AC_HYSMODE_NO_gc = (0x00<<1),
AC_HYSMODE_SMALL_gc = (0x01<<1),
AC_HYSMODE_LARGE_gc = (0x02<<1),
AC_HYSMODE_NO_gc = (0x00<<1),
AC_HYSMODE_SMALL_gc = (0x01<<1),
AC_HYSMODE_LARGE_gc = (0x02<<1),
AC_HYSMODE_NO_gc = (0x00<<1),
AC_HYSMODE_SMALL_gc = (0x01<<1),
AC_HYSMODE_LARGE_gc = (0x02<<1),
AC_HYSMODE_NO_gc = (0x00<<1),
AC_HYSMODE_SMALL_gc = (0x01<<1),
AC_HYSMODE_LARGE_gc = (0x02<<1)
} |
|
enum | AC_MUXPOS_enum {
AC_MUXPOS_PIN0_gc = (0x00<<3),
AC_MUXPOS_PIN1_gc = (0x01<<3),
AC_MUXPOS_PIN2_gc = (0x02<<3),
AC_MUXPOS_PIN3_gc = (0x03<<3),
AC_MUXPOS_PIN4_gc = (0x04<<3),
AC_MUXPOS_PIN5_gc = (0x05<<3),
AC_MUXPOS_PIN6_gc = (0x06<<3),
AC_MUXPOS_DAC_gc = (0x07<<3),
AC_MUXPOS_PIN0_gc = (0x00<<3),
AC_MUXPOS_PIN1_gc = (0x01<<3),
AC_MUXPOS_PIN2_gc = (0x02<<3),
AC_MUXPOS_PIN3_gc = (0x03<<3),
AC_MUXPOS_PIN4_gc = (0x04<<3),
AC_MUXPOS_PIN5_gc = (0x05<<3),
AC_MUXPOS_PIN6_gc = (0x06<<3),
AC_MUXPOS_DAC_gc = (0x07<<3),
AC_MUXPOS_PIN0_gc = (0x00<<3),
AC_MUXPOS_PIN1_gc = (0x01<<3),
AC_MUXPOS_PIN2_gc = (0x02<<3),
AC_MUXPOS_PIN3_gc = (0x03<<3),
AC_MUXPOS_PIN4_gc = (0x04<<3),
AC_MUXPOS_PIN5_gc = (0x05<<3),
AC_MUXPOS_PIN6_gc = (0x06<<3),
AC_MUXPOS_DAC_gc = (0x07<<3),
AC_MUXPOS_PIN0_gc = (0x00<<3),
AC_MUXPOS_PIN1_gc = (0x01<<3),
AC_MUXPOS_PIN2_gc = (0x02<<3),
AC_MUXPOS_PIN3_gc = (0x03<<3),
AC_MUXPOS_PIN4_gc = (0x04<<3),
AC_MUXPOS_PIN5_gc = (0x05<<3),
AC_MUXPOS_PIN6_gc = (0x06<<3),
AC_MUXPOS_DAC_gc = (0x07<<3),
AC_MUXPOS_PIN0_gc = (0x00<<3),
AC_MUXPOS_PIN1_gc = (0x01<<3),
AC_MUXPOS_PIN2_gc = (0x02<<3),
AC_MUXPOS_PIN3_gc = (0x03<<3),
AC_MUXPOS_PIN4_gc = (0x04<<3),
AC_MUXPOS_PIN5_gc = (0x05<<3),
AC_MUXPOS_PIN6_gc = (0x06<<3),
AC_MUXPOS_DAC_gc = (0x07<<3),
AC_MUXPOS_PIN0_gc = (0x00<<3),
AC_MUXPOS_PIN1_gc = (0x01<<3),
AC_MUXPOS_PIN2_gc = (0x02<<3),
AC_MUXPOS_PIN3_gc = (0x03<<3),
AC_MUXPOS_PIN4_gc = (0x04<<3),
AC_MUXPOS_PIN5_gc = (0x05<<3),
AC_MUXPOS_PIN6_gc = (0x06<<3),
AC_MUXPOS_DAC_gc = (0x07<<3),
AC_MUXPOS_PIN0_gc = (0x00<<3),
AC_MUXPOS_PIN1_gc = (0x01<<3),
AC_MUXPOS_PIN2_gc = (0x02<<3),
AC_MUXPOS_PIN3_gc = (0x03<<3),
AC_MUXPOS_PIN4_gc = (0x04<<3),
AC_MUXPOS_PIN5_gc = (0x05<<3),
AC_MUXPOS_PIN6_gc = (0x06<<3),
AC_MUXPOS_DAC_gc = (0x07<<3),
AC_MUXPOS_PIN0_gc = (0x00<<3),
AC_MUXPOS_PIN1_gc = (0x01<<3),
AC_MUXPOS_PIN2_gc = (0x02<<3),
AC_MUXPOS_PIN3_gc = (0x03<<3),
AC_MUXPOS_PIN4_gc = (0x04<<3),
AC_MUXPOS_PIN5_gc = (0x05<<3),
AC_MUXPOS_PIN6_gc = (0x06<<3),
AC_MUXPOS_DAC_gc = (0x07<<3),
AC_MUXPOS_PIN0_gc = (0x00<<3),
AC_MUXPOS_PIN1_gc = (0x01<<3),
AC_MUXPOS_PIN2_gc = (0x02<<3),
AC_MUXPOS_PIN3_gc = (0x03<<3),
AC_MUXPOS_PIN4_gc = (0x04<<3),
AC_MUXPOS_PIN5_gc = (0x05<<3),
AC_MUXPOS_PIN6_gc = (0x06<<3),
AC_MUXPOS_DAC_gc = (0x07<<3),
AC_MUXPOS_PIN0_gc = (0x00<<3),
AC_MUXPOS_PIN1_gc = (0x01<<3),
AC_MUXPOS_PIN2_gc = (0x02<<3),
AC_MUXPOS_PIN3_gc = (0x03<<3),
AC_MUXPOS_PIN4_gc = (0x04<<3),
AC_MUXPOS_PIN5_gc = (0x05<<3),
AC_MUXPOS_PIN6_gc = (0x06<<3),
AC_MUXPOS_PIN0_gc = (0x00<<3),
AC_MUXPOS_PIN1_gc = (0x01<<3),
AC_MUXPOS_PIN2_gc = (0x02<<3),
AC_MUXPOS_PIN3_gc = (0x03<<3),
AC_MUXPOS_PIN4_gc = (0x04<<3),
AC_MUXPOS_PIN5_gc = (0x05<<3),
AC_MUXPOS_PIN6_gc = (0x06<<3),
AC_MUXPOS_DAC_gc = (0x07<<3),
AC_MUXPOS_PIN0_gc = (0x00<<3),
AC_MUXPOS_PIN1_gc = (0x01<<3),
AC_MUXPOS_PIN2_gc = (0x02<<3),
AC_MUXPOS_PIN3_gc = (0x03<<3),
AC_MUXPOS_PIN4_gc = (0x04<<3),
AC_MUXPOS_PIN5_gc = (0x05<<3),
AC_MUXPOS_PIN6_gc = (0x06<<3),
AC_MUXPOS_DAC_gc = (0x07<<3),
AC_MUXPOS_PIN0_gc = (0x00<<3),
AC_MUXPOS_PIN1_gc = (0x01<<3),
AC_MUXPOS_PIN2_gc = (0x02<<3),
AC_MUXPOS_PIN3_gc = (0x03<<3),
AC_MUXPOS_PIN4_gc = (0x04<<3),
AC_MUXPOS_PIN5_gc = (0x05<<3),
AC_MUXPOS_PIN6_gc = (0x06<<3),
AC_MUXPOS_DAC_gc = (0x07<<3),
AC_MUXPOS_PIN0_gc = (0x00<<3),
AC_MUXPOS_PIN1_gc = (0x01<<3),
AC_MUXPOS_PIN2_gc = (0x02<<3),
AC_MUXPOS_PIN3_gc = (0x03<<3),
AC_MUXPOS_PIN4_gc = (0x04<<3),
AC_MUXPOS_PIN5_gc = (0x05<<3),
AC_MUXPOS_PIN6_gc = (0x06<<3),
AC_MUXPOS_DAC_gc = (0x07<<3),
AC_MUXPOS_PIN0_gc = (0x00<<3),
AC_MUXPOS_PIN1_gc = (0x01<<3),
AC_MUXPOS_PIN2_gc = (0x02<<3),
AC_MUXPOS_PIN3_gc = (0x03<<3),
AC_MUXPOS_PIN4_gc = (0x04<<3),
AC_MUXPOS_PIN5_gc = (0x05<<3),
AC_MUXPOS_PIN6_gc = (0x06<<3),
AC_MUXPOS_DAC_gc = (0x07<<3)
} |
|
enum | AC_MUXNEG_enum {
AC_MUXNEG_PIN0_gc = (0x00<<0),
AC_MUXNEG_PIN1_gc = (0x01<<0),
AC_MUXNEG_PIN3_gc = (0x02<<0),
AC_MUXNEG_PIN5_gc = (0x03<<0),
AC_MUXNEG_PIN7_gc = (0x04<<0),
AC_MUXNEG_DAC_gc = (0x05<<0),
AC_MUXNEG_BANDGAP_gc = (0x06<<0),
AC_MUXNEG_SCALER_gc = (0x07<<0),
AC_MUXNEG_PIN0_gc = (0x00<<0),
AC_MUXNEG_PIN1_gc = (0x01<<0),
AC_MUXNEG_PIN3_gc = (0x02<<0),
AC_MUXNEG_PIN5_gc = (0x03<<0),
AC_MUXNEG_PIN7_gc = (0x04<<0),
AC_MUXNEG_DAC_gc = (0x05<<0),
AC_MUXNEG_BANDGAP_gc = (0x06<<0),
AC_MUXNEG_SCALER_gc = (0x07<<0),
AC_MUXNEG_PIN0_gc = (0x00<<0),
AC_MUXNEG_PIN1_gc = (0x01<<0),
AC_MUXNEG_PIN3_gc = (0x02<<0),
AC_MUXNEG_PIN5_gc = (0x03<<0),
AC_MUXNEG_PIN7_gc = (0x04<<0),
AC_MUXNEG_DAC_gc = (0x05<<0),
AC_MUXNEG_BANDGAP_gc = (0x06<<0),
AC_MUXNEG_SCALER_gc = (0x07<<0),
AC_MUXNEG_PIN0_gc = (0x00<<0),
AC_MUXNEG_PIN1_gc = (0x01<<0),
AC_MUXNEG_PIN3_gc = (0x02<<0),
AC_MUXNEG_PIN5_gc = (0x03<<0),
AC_MUXNEG_PIN7_gc = (0x04<<0),
AC_MUXNEG_DAC_gc = (0x05<<0),
AC_MUXNEG_BANDGAP_gc = (0x06<<0),
AC_MUXNEG_SCALER_gc = (0x07<<0),
AC_MUXNEG_PIN0_gc = (0x00<<0),
AC_MUXNEG_PIN1_gc = (0x01<<0),
AC_MUXNEG_PIN3_gc = (0x02<<0),
AC_MUXNEG_PIN5_gc = (0x03<<0),
AC_MUXNEG_PIN7_gc = (0x04<<0),
AC_MUXNEG_DAC_gc = (0x05<<0),
AC_MUXNEG_BANDGAP_gc = (0x06<<0),
AC_MUXNEG_SCALER_gc = (0x07<<0),
AC_MUXNEG_PIN0_gc = (0x00<<0),
AC_MUXNEG_PIN1_gc = (0x01<<0),
AC_MUXNEG_PIN3_gc = (0x02<<0),
AC_MUXNEG_PIN5_gc = (0x03<<0),
AC_MUXNEG_PIN7_gc = (0x04<<0),
AC_MUXNEG_DAC_gc = (0x05<<0),
AC_MUXNEG_BANDGAP_gc = (0x06<<0),
AC_MUXNEG_SCALER_gc = (0x07<<0),
AC_MUXNEG_PIN0_gc = (0x00<<0),
AC_MUXNEG_PIN1_gc = (0x01<<0),
AC_MUXNEG_PIN3_gc = (0x02<<0),
AC_MUXNEG_PIN5_gc = (0x03<<0),
AC_MUXNEG_PIN7_gc = (0x04<<0),
AC_MUXNEG_DAC_gc = (0x05<<0),
AC_MUXNEG_BANDGAP_gc = (0x06<<0),
AC_MUXNEG_SCALER_gc = (0x07<<0),
AC_MUXNEG_PIN0_gc = (0x00<<0),
AC_MUXNEG_PIN1_gc = (0x01<<0),
AC_MUXNEG_PIN3_gc = (0x02<<0),
AC_MUXNEG_PIN5_gc = (0x03<<0),
AC_MUXNEG_PIN7_gc = (0x04<<0),
AC_MUXNEG_DAC_gc = (0x05<<0),
AC_MUXNEG_BANDGAP_gc = (0x06<<0),
AC_MUXNEG_SCALER_gc = (0x07<<0),
AC_MUXNEG_PIN0_gc = (0x00<<0),
AC_MUXNEG_PIN1_gc = (0x01<<0),
AC_MUXNEG_PIN3_gc = (0x02<<0),
AC_MUXNEG_PIN5_gc = (0x03<<0),
AC_MUXNEG_PIN7_gc = (0x04<<0),
AC_MUXNEG_DAC_gc = (0x05<<0),
AC_MUXNEG_BANDGAP_gc = (0x06<<0),
AC_MUXNEG_SCALER_gc = (0x07<<0),
AC_MUXNEG_PIN0_gc = (0x00<<0),
AC_MUXNEG_PIN1_gc = (0x01<<0),
AC_MUXNEG_PIN3_gc = (0x02<<0),
AC_MUXNEG_PIN5_gc = (0x03<<0),
AC_MUXNEG_PIN7_gc = (0x04<<0),
AC_MUXNEG_BANDGAP_gc = (0x06<<0),
AC_MUXNEG_SCALER_gc = (0x07<<0),
AC_MUXNEG_PIN0_gc = (0x00<<0),
AC_MUXNEG_PIN1_gc = (0x01<<0),
AC_MUXNEG_PIN3_gc = (0x02<<0),
AC_MUXNEG_PIN5_gc = (0x03<<0),
AC_MUXNEG_PIN7_gc = (0x04<<0),
AC_MUXNEG_DAC_gc = (0x05<<0),
AC_MUXNEG_BANDGAP_gc = (0x06<<0),
AC_MUXNEG_SCALER_gc = (0x07<<0),
AC_MUXNEG_PIN0_gc = (0x00<<0),
AC_MUXNEG_PIN1_gc = (0x01<<0),
AC_MUXNEG_PIN3_gc = (0x02<<0),
AC_MUXNEG_PIN5_gc = (0x03<<0),
AC_MUXNEG_PIN7_gc = (0x04<<0),
AC_MUXNEG_DAC_gc = (0x05<<0),
AC_MUXNEG_BANDGAP_gc = (0x06<<0),
AC_MUXNEG_SCALER_gc = (0x07<<0),
AC_MUXNEG_PIN0_gc = (0x00<<0),
AC_MUXNEG_PIN1_gc = (0x01<<0),
AC_MUXNEG_PIN3_gc = (0x02<<0),
AC_MUXNEG_PIN5_gc = (0x03<<0),
AC_MUXNEG_PIN7_gc = (0x04<<0),
AC_MUXNEG_DAC_gc = (0x05<<0),
AC_MUXNEG_BANDGAP_gc = (0x06<<0),
AC_MUXNEG_SCALER_gc = (0x07<<0),
AC_MUXNEG_PIN0_gc = (0x00<<0),
AC_MUXNEG_PIN1_gc = (0x01<<0),
AC_MUXNEG_PIN3_gc = (0x02<<0),
AC_MUXNEG_PIN5_gc = (0x03<<0),
AC_MUXNEG_PIN7_gc = (0x04<<0),
AC_MUXNEG_DAC_gc = (0x05<<0),
AC_MUXNEG_BANDGAP_gc = (0x06<<0),
AC_MUXNEG_SCALER_gc = (0x07<<0),
AC_MUXNEG_PIN0_gc = (0x00<<0),
AC_MUXNEG_PIN1_gc = (0x01<<0),
AC_MUXNEG_PIN3_gc = (0x02<<0),
AC_MUXNEG_PIN5_gc = (0x03<<0),
AC_MUXNEG_PIN7_gc = (0x04<<0),
AC_MUXNEG_DAC_gc = (0x05<<0),
AC_MUXNEG_BANDGAP_gc = (0x06<<0),
AC_MUXNEG_SCALER_gc = (0x07<<0)
} |
|
enum | AC_WINTMODE_enum {
AC_WINTMODE_ABOVE_gc = (0x00<<2),
AC_WINTMODE_INSIDE_gc = (0x01<<2),
AC_WINTMODE_BELOW_gc = (0x02<<2),
AC_WINTMODE_OUTSIDE_gc = (0x03<<2),
AC_WINTMODE_ABOVE_gc = (0x00<<2),
AC_WINTMODE_INSIDE_gc = (0x01<<2),
AC_WINTMODE_BELOW_gc = (0x02<<2),
AC_WINTMODE_OUTSIDE_gc = (0x03<<2),
AC_WINTMODE_ABOVE_gc = (0x00<<2),
AC_WINTMODE_INSIDE_gc = (0x01<<2),
AC_WINTMODE_BELOW_gc = (0x02<<2),
AC_WINTMODE_OUTSIDE_gc = (0x03<<2),
AC_WINTMODE_ABOVE_gc = (0x00<<2),
AC_WINTMODE_INSIDE_gc = (0x01<<2),
AC_WINTMODE_BELOW_gc = (0x02<<2),
AC_WINTMODE_OUTSIDE_gc = (0x03<<2),
AC_WINTMODE_ABOVE_gc = (0x00<<2),
AC_WINTMODE_INSIDE_gc = (0x01<<2),
AC_WINTMODE_BELOW_gc = (0x02<<2),
AC_WINTMODE_OUTSIDE_gc = (0x03<<2),
AC_WINTMODE_ABOVE_gc = (0x00<<2),
AC_WINTMODE_INSIDE_gc = (0x01<<2),
AC_WINTMODE_BELOW_gc = (0x02<<2),
AC_WINTMODE_OUTSIDE_gc = (0x03<<2),
AC_WINTMODE_ABOVE_gc = (0x00<<2),
AC_WINTMODE_INSIDE_gc = (0x01<<2),
AC_WINTMODE_BELOW_gc = (0x02<<2),
AC_WINTMODE_OUTSIDE_gc = (0x03<<2),
AC_WINTMODE_ABOVE_gc = (0x00<<2),
AC_WINTMODE_INSIDE_gc = (0x01<<2),
AC_WINTMODE_BELOW_gc = (0x02<<2),
AC_WINTMODE_OUTSIDE_gc = (0x03<<2),
AC_WINTMODE_ABOVE_gc = (0x00<<2),
AC_WINTMODE_INSIDE_gc = (0x01<<2),
AC_WINTMODE_BELOW_gc = (0x02<<2),
AC_WINTMODE_OUTSIDE_gc = (0x03<<2),
AC_WINTMODE_ABOVE_gc = (0x00<<2),
AC_WINTMODE_INSIDE_gc = (0x01<<2),
AC_WINTMODE_BELOW_gc = (0x02<<2),
AC_WINTMODE_OUTSIDE_gc = (0x03<<2),
AC_WINTMODE_ABOVE_gc = (0x00<<2),
AC_WINTMODE_INSIDE_gc = (0x01<<2),
AC_WINTMODE_BELOW_gc = (0x02<<2),
AC_WINTMODE_OUTSIDE_gc = (0x03<<2),
AC_WINTMODE_ABOVE_gc = (0x00<<2),
AC_WINTMODE_INSIDE_gc = (0x01<<2),
AC_WINTMODE_BELOW_gc = (0x02<<2),
AC_WINTMODE_OUTSIDE_gc = (0x03<<2),
AC_WINTMODE_ABOVE_gc = (0x00<<2),
AC_WINTMODE_INSIDE_gc = (0x01<<2),
AC_WINTMODE_BELOW_gc = (0x02<<2),
AC_WINTMODE_OUTSIDE_gc = (0x03<<2),
AC_WINTMODE_ABOVE_gc = (0x00<<2),
AC_WINTMODE_INSIDE_gc = (0x01<<2),
AC_WINTMODE_BELOW_gc = (0x02<<2),
AC_WINTMODE_OUTSIDE_gc = (0x03<<2),
AC_WINTMODE_ABOVE_gc = (0x00<<2),
AC_WINTMODE_INSIDE_gc = (0x01<<2),
AC_WINTMODE_BELOW_gc = (0x02<<2),
AC_WINTMODE_OUTSIDE_gc = (0x03<<2)
} |
|
enum | AC_WINTLVL_enum {
AC_WINTLVL_OFF_gc = (0x00<<0),
AC_WINTLVL_LO_gc = (0x01<<0),
AC_WINTLVL_MED_gc = (0x02<<0),
AC_WINTLVL_HI_gc = (0x03<<0),
AC_WINTLVL_OFF_gc = (0x00<<0),
AC_WINTLVL_LO_gc = (0x01<<0),
AC_WINTLVL_MED_gc = (0x02<<0),
AC_WINTLVL_HI_gc = (0x03<<0),
AC_WINTLVL_OFF_gc = (0x00<<0),
AC_WINTLVL_LO_gc = (0x01<<0),
AC_WINTLVL_MED_gc = (0x02<<0),
AC_WINTLVL_HI_gc = (0x03<<0),
AC_WINTLVL_OFF_gc = (0x00<<0),
AC_WINTLVL_LO_gc = (0x01<<0),
AC_WINTLVL_MED_gc = (0x02<<0),
AC_WINTLVL_HI_gc = (0x03<<0),
AC_WINTLVL_OFF_gc = (0x00<<0),
AC_WINTLVL_LO_gc = (0x01<<0),
AC_WINTLVL_MED_gc = (0x02<<0),
AC_WINTLVL_HI_gc = (0x03<<0),
AC_WINTLVL_OFF_gc = (0x00<<0),
AC_WINTLVL_LO_gc = (0x01<<0),
AC_WINTLVL_MED_gc = (0x02<<0),
AC_WINTLVL_HI_gc = (0x03<<0),
AC_WINTLVL_OFF_gc = (0x00<<0),
AC_WINTLVL_LO_gc = (0x01<<0),
AC_WINTLVL_MED_gc = (0x02<<0),
AC_WINTLVL_HI_gc = (0x03<<0),
AC_WINTLVL_OFF_gc = (0x00<<0),
AC_WINTLVL_LO_gc = (0x01<<0),
AC_WINTLVL_MED_gc = (0x02<<0),
AC_WINTLVL_HI_gc = (0x03<<0),
AC_WINTLVL_OFF_gc = (0x00<<0),
AC_WINTLVL_LO_gc = (0x01<<0),
AC_WINTLVL_MED_gc = (0x02<<0),
AC_WINTLVL_HI_gc = (0x03<<0),
AC_WINTLVL_OFF_gc = (0x00<<0),
AC_WINTLVL_LO_gc = (0x01<<0),
AC_WINTLVL_MED_gc = (0x02<<0),
AC_WINTLVL_HI_gc = (0x03<<0),
AC_WINTLVL_OFF_gc = (0x00<<0),
AC_WINTLVL_LO_gc = (0x01<<0),
AC_WINTLVL_MED_gc = (0x02<<0),
AC_WINTLVL_HI_gc = (0x03<<0),
AC_WINTLVL_OFF_gc = (0x00<<0),
AC_WINTLVL_LO_gc = (0x01<<0),
AC_WINTLVL_MED_gc = (0x02<<0),
AC_WINTLVL_HI_gc = (0x03<<0),
AC_WINTLVL_OFF_gc = (0x00<<0),
AC_WINTLVL_LO_gc = (0x01<<0),
AC_WINTLVL_MED_gc = (0x02<<0),
AC_WINTLVL_HI_gc = (0x03<<0),
AC_WINTLVL_OFF_gc = (0x00<<0),
AC_WINTLVL_LO_gc = (0x01<<0),
AC_WINTLVL_MED_gc = (0x02<<0),
AC_WINTLVL_HI_gc = (0x03<<0),
AC_WINTLVL_OFF_gc = (0x00<<0),
AC_WINTLVL_LO_gc = (0x01<<0),
AC_WINTLVL_MED_gc = (0x02<<0),
AC_WINTLVL_HI_gc = (0x03<<0)
} |
|
enum | AC_WSTATE_enum {
AC_WSTATE_ABOVE_gc = (0x00<<6),
AC_WSTATE_INSIDE_gc = (0x01<<6),
AC_WSTATE_BELOW_gc = (0x02<<6),
AC_WSTATE_ABOVE_gc = (0x00<<6),
AC_WSTATE_INSIDE_gc = (0x01<<6),
AC_WSTATE_BELOW_gc = (0x02<<6),
AC_WSTATE_ABOVE_gc = (0x00<<6),
AC_WSTATE_INSIDE_gc = (0x01<<6),
AC_WSTATE_BELOW_gc = (0x02<<6),
AC_WSTATE_ABOVE_gc = (0x00<<6),
AC_WSTATE_INSIDE_gc = (0x01<<6),
AC_WSTATE_BELOW_gc = (0x02<<6),
AC_WSTATE_ABOVE_gc = (0x00<<6),
AC_WSTATE_INSIDE_gc = (0x01<<6),
AC_WSTATE_BELOW_gc = (0x02<<6),
AC_WSTATE_ABOVE_gc = (0x00<<6),
AC_WSTATE_INSIDE_gc = (0x01<<6),
AC_WSTATE_BELOW_gc = (0x02<<6),
AC_WSTATE_ABOVE_gc = (0x00<<6),
AC_WSTATE_INSIDE_gc = (0x01<<6),
AC_WSTATE_BELOW_gc = (0x02<<6),
AC_WSTATE_ABOVE_gc = (0x00<<6),
AC_WSTATE_INSIDE_gc = (0x01<<6),
AC_WSTATE_BELOW_gc = (0x02<<6),
AC_WSTATE_ABOVE_gc = (0x00<<6),
AC_WSTATE_INSIDE_gc = (0x01<<6),
AC_WSTATE_BELOW_gc = (0x02<<6),
AC_WSTATE_ABOVE_gc = (0x00<<6),
AC_WSTATE_INSIDE_gc = (0x01<<6),
AC_WSTATE_BELOW_gc = (0x02<<6),
AC_WSTATE_ABOVE_gc = (0x00<<6),
AC_WSTATE_INSIDE_gc = (0x01<<6),
AC_WSTATE_BELOW_gc = (0x02<<6),
AC_WSTATE_ABOVE_gc = (0x00<<6),
AC_WSTATE_INSIDE_gc = (0x01<<6),
AC_WSTATE_BELOW_gc = (0x02<<6),
AC_WSTATE_ABOVE_gc = (0x00<<6),
AC_WSTATE_INSIDE_gc = (0x01<<6),
AC_WSTATE_BELOW_gc = (0x02<<6),
AC_WSTATE_ABOVE_gc = (0x00<<6),
AC_WSTATE_INSIDE_gc = (0x01<<6),
AC_WSTATE_BELOW_gc = (0x02<<6),
AC_WSTATE_ABOVE_gc = (0x00<<6),
AC_WSTATE_INSIDE_gc = (0x01<<6),
AC_WSTATE_BELOW_gc = (0x02<<6)
} |
|
enum | ADC_CH_MUXPOS_enum {
ADC_CH_MUXPOS_PIN0_gc = (0x00<<3),
ADC_CH_MUXPOS_PIN1_gc = (0x01<<3),
ADC_CH_MUXPOS_PIN2_gc = (0x02<<3),
ADC_CH_MUXPOS_PIN3_gc = (0x03<<3),
ADC_CH_MUXPOS_PIN4_gc = (0x04<<3),
ADC_CH_MUXPOS_PIN5_gc = (0x05<<3),
ADC_CH_MUXPOS_PIN6_gc = (0x06<<3),
ADC_CH_MUXPOS_PIN7_gc = (0x07<<3),
ADC_CH_MUXPOS_PIN0_gc = (0x00<<3),
ADC_CH_MUXPOS_PIN1_gc = (0x01<<3),
ADC_CH_MUXPOS_PIN2_gc = (0x02<<3),
ADC_CH_MUXPOS_PIN3_gc = (0x03<<3),
ADC_CH_MUXPOS_PIN4_gc = (0x04<<3),
ADC_CH_MUXPOS_PIN5_gc = (0x05<<3),
ADC_CH_MUXPOS_PIN6_gc = (0x06<<3),
ADC_CH_MUXPOS_PIN7_gc = (0x07<<3),
ADC_CH_MUXPOS_PIN0_gc = (0x00<<3),
ADC_CH_MUXPOS_PIN1_gc = (0x01<<3),
ADC_CH_MUXPOS_PIN2_gc = (0x02<<3),
ADC_CH_MUXPOS_PIN3_gc = (0x03<<3),
ADC_CH_MUXPOS_PIN4_gc = (0x04<<3),
ADC_CH_MUXPOS_PIN5_gc = (0x05<<3),
ADC_CH_MUXPOS_PIN6_gc = (0x06<<3),
ADC_CH_MUXPOS_PIN7_gc = (0x07<<3),
ADC_CH_MUXPOS_PIN0_gc = (0x00<<3),
ADC_CH_MUXPOS_PIN1_gc = (0x01<<3),
ADC_CH_MUXPOS_PIN2_gc = (0x02<<3),
ADC_CH_MUXPOS_PIN3_gc = (0x03<<3),
ADC_CH_MUXPOS_PIN4_gc = (0x04<<3),
ADC_CH_MUXPOS_PIN5_gc = (0x05<<3),
ADC_CH_MUXPOS_PIN6_gc = (0x06<<3),
ADC_CH_MUXPOS_PIN7_gc = (0x07<<3),
ADC_CH_MUXPOS_PIN0_gc = (0x00<<3),
ADC_CH_MUXPOS_PIN1_gc = (0x01<<3),
ADC_CH_MUXPOS_PIN2_gc = (0x02<<3),
ADC_CH_MUXPOS_PIN3_gc = (0x03<<3),
ADC_CH_MUXPOS_PIN4_gc = (0x04<<3),
ADC_CH_MUXPOS_PIN5_gc = (0x05<<3),
ADC_CH_MUXPOS_PIN6_gc = (0x06<<3),
ADC_CH_MUXPOS_PIN7_gc = (0x07<<3),
ADC_CH_MUXPOS_PIN0_gc = (0x00<<3),
ADC_CH_MUXPOS_PIN1_gc = (0x01<<3),
ADC_CH_MUXPOS_PIN2_gc = (0x02<<3),
ADC_CH_MUXPOS_PIN3_gc = (0x03<<3),
ADC_CH_MUXPOS_PIN4_gc = (0x04<<3),
ADC_CH_MUXPOS_PIN5_gc = (0x05<<3),
ADC_CH_MUXPOS_PIN6_gc = (0x06<<3),
ADC_CH_MUXPOS_PIN7_gc = (0x07<<3),
ADC_CH_MUXPOS_PIN0_gc = (0x00<<3),
ADC_CH_MUXPOS_PIN1_gc = (0x01<<3),
ADC_CH_MUXPOS_PIN2_gc = (0x02<<3),
ADC_CH_MUXPOS_PIN3_gc = (0x03<<3),
ADC_CH_MUXPOS_PIN4_gc = (0x04<<3),
ADC_CH_MUXPOS_PIN5_gc = (0x05<<3),
ADC_CH_MUXPOS_PIN6_gc = (0x06<<3),
ADC_CH_MUXPOS_PIN7_gc = (0x07<<3),
ADC_CH_MUXPOS_PIN0_gc = (0x00<<3),
ADC_CH_MUXPOS_PIN1_gc = (0x01<<3),
ADC_CH_MUXPOS_PIN2_gc = (0x02<<3),
ADC_CH_MUXPOS_PIN3_gc = (0x03<<3),
ADC_CH_MUXPOS_PIN4_gc = (0x04<<3),
ADC_CH_MUXPOS_PIN5_gc = (0x05<<3),
ADC_CH_MUXPOS_PIN6_gc = (0x06<<3),
ADC_CH_MUXPOS_PIN7_gc = (0x07<<3),
ADC_CH_MUXPOS_PIN0_gc = (0x00<<3),
ADC_CH_MUXPOS_PIN1_gc = (0x01<<3),
ADC_CH_MUXPOS_PIN2_gc = (0x02<<3),
ADC_CH_MUXPOS_PIN3_gc = (0x03<<3),
ADC_CH_MUXPOS_PIN4_gc = (0x04<<3),
ADC_CH_MUXPOS_PIN5_gc = (0x05<<3),
ADC_CH_MUXPOS_PIN6_gc = (0x06<<3),
ADC_CH_MUXPOS_PIN7_gc = (0x07<<3),
ADC_CH_MUXPOS_PIN0_gc = (0x00<<3),
ADC_CH_MUXPOS_PIN1_gc = (0x01<<3),
ADC_CH_MUXPOS_PIN2_gc = (0x02<<3),
ADC_CH_MUXPOS_PIN3_gc = (0x03<<3),
ADC_CH_MUXPOS_PIN4_gc = (0x04<<3),
ADC_CH_MUXPOS_PIN5_gc = (0x05<<3),
ADC_CH_MUXPOS_PIN6_gc = (0x06<<3),
ADC_CH_MUXPOS_PIN7_gc = (0x07<<3),
ADC_CH_MUXPOS_PIN0_gc = (0x00<<3),
ADC_CH_MUXPOS_PIN1_gc = (0x01<<3),
ADC_CH_MUXPOS_PIN2_gc = (0x02<<3),
ADC_CH_MUXPOS_PIN3_gc = (0x03<<3),
ADC_CH_MUXPOS_PIN4_gc = (0x04<<3),
ADC_CH_MUXPOS_PIN5_gc = (0x05<<3),
ADC_CH_MUXPOS_PIN6_gc = (0x06<<3),
ADC_CH_MUXPOS_PIN7_gc = (0x07<<3),
ADC_CH_MUXPOS_PIN0_gc = (0x00<<3),
ADC_CH_MUXPOS_PIN1_gc = (0x01<<3),
ADC_CH_MUXPOS_PIN2_gc = (0x02<<3),
ADC_CH_MUXPOS_PIN3_gc = (0x03<<3),
ADC_CH_MUXPOS_PIN4_gc = (0x04<<3),
ADC_CH_MUXPOS_PIN5_gc = (0x05<<3),
ADC_CH_MUXPOS_PIN6_gc = (0x06<<3),
ADC_CH_MUXPOS_PIN7_gc = (0x07<<3),
ADC_CH_MUXPOS_PIN0_gc = (0x00<<3),
ADC_CH_MUXPOS_PIN1_gc = (0x01<<3),
ADC_CH_MUXPOS_PIN2_gc = (0x02<<3),
ADC_CH_MUXPOS_PIN3_gc = (0x03<<3),
ADC_CH_MUXPOS_PIN4_gc = (0x04<<3),
ADC_CH_MUXPOS_PIN5_gc = (0x05<<3),
ADC_CH_MUXPOS_PIN6_gc = (0x06<<3),
ADC_CH_MUXPOS_PIN7_gc = (0x07<<3),
ADC_CH_MUXPOS_PIN0_gc = (0x00<<3),
ADC_CH_MUXPOS_PIN1_gc = (0x01<<3),
ADC_CH_MUXPOS_PIN2_gc = (0x02<<3),
ADC_CH_MUXPOS_PIN3_gc = (0x03<<3),
ADC_CH_MUXPOS_PIN4_gc = (0x04<<3),
ADC_CH_MUXPOS_PIN5_gc = (0x05<<3),
ADC_CH_MUXPOS_PIN6_gc = (0x06<<3),
ADC_CH_MUXPOS_PIN7_gc = (0x07<<3),
ADC_CH_MUXPOS_PIN0_gc = (0x00<<3),
ADC_CH_MUXPOS_PIN1_gc = (0x01<<3),
ADC_CH_MUXPOS_PIN2_gc = (0x02<<3),
ADC_CH_MUXPOS_PIN3_gc = (0x03<<3),
ADC_CH_MUXPOS_PIN4_gc = (0x04<<3),
ADC_CH_MUXPOS_PIN5_gc = (0x05<<3),
ADC_CH_MUXPOS_PIN6_gc = (0x06<<3),
ADC_CH_MUXPOS_PIN7_gc = (0x07<<3)
} |
|
enum | ADC_CH_MUXINT_enum {
ADC_CH_MUXINT_TEMP_gc = (0x00<<3),
ADC_CH_MUXINT_BANDGAP_gc = (0x01<<3),
ADC_CH_MUXINT_SCALEDVCC_gc = (0x02<<3),
ADC_CH_MUXINT_DAC_gc = (0x03<<3),
ADC_CH_MUXINT_TEMP_gc = (0x00<<3),
ADC_CH_MUXINT_BANDGAP_gc = (0x01<<3),
ADC_CH_MUXINT_SCALEDVCC_gc = (0x02<<3),
ADC_CH_MUXINT_DAC_gc = (0x03<<3),
ADC_CH_MUXINT_TEMP_gc = (0x00<<3),
ADC_CH_MUXINT_BANDGAP_gc = (0x01<<3),
ADC_CH_MUXINT_SCALEDVCC_gc = (0x02<<3),
ADC_CH_MUXINT_DAC_gc = (0x03<<3),
ADC_CH_MUXINT_TEMP_gc = (0x00<<3),
ADC_CH_MUXINT_BANDGAP_gc = (0x01<<3),
ADC_CH_MUXINT_SCALEDVCC_gc = (0x02<<3),
ADC_CH_MUXINT_DAC_gc = (0x03<<3),
ADC_CH_MUXINT_TEMP_gc = (0x00<<3),
ADC_CH_MUXINT_BANDGAP_gc = (0x01<<3),
ADC_CH_MUXINT_SCALEDVCC_gc = (0x02<<3),
ADC_CH_MUXINT_DAC_gc = (0x03<<3),
ADC_CH_MUXINT_TEMP_gc = (0x00<<3),
ADC_CH_MUXINT_BANDGAP_gc = (0x01<<3),
ADC_CH_MUXINT_SCALEDVCC_gc = (0x02<<3),
ADC_CH_MUXINT_DAC_gc = (0x03<<3),
ADC_CH_MUXINT_TEMP_gc = (0x00<<3),
ADC_CH_MUXINT_BANDGAP_gc = (0x01<<3),
ADC_CH_MUXINT_SCALEDVCC_gc = (0x02<<3),
ADC_CH_MUXINT_DAC_gc = (0x03<<3),
ADC_CH_MUXINT_TEMP_gc = (0x00<<3),
ADC_CH_MUXINT_BANDGAP_gc = (0x01<<3),
ADC_CH_MUXINT_SCALEDVCC_gc = (0x02<<3),
ADC_CH_MUXINT_DAC_gc = (0x03<<3),
ADC_CH_MUXINT_TEMP_gc = (0x00<<3),
ADC_CH_MUXINT_BANDGAP_gc = (0x01<<3),
ADC_CH_MUXINT_SCALEDVCC_gc = (0x02<<3),
ADC_CH_MUXINT_DAC_gc = (0x03<<3),
ADC_CH_MUXINT_TEMP_gc = (0x00<<3),
ADC_CH_MUXINT_BANDGAP_gc = (0x01<<3),
ADC_CH_MUXINT_SCALEDVCC_gc = (0x02<<3),
ADC_CH_MUXINT_DAC_gc = (0x03<<3),
ADC_CH_MUXINT_TEMP_gc = (0x00<<3),
ADC_CH_MUXINT_BANDGAP_gc = (0x01<<3),
ADC_CH_MUXINT_SCALEDVCC_gc = (0x02<<3),
ADC_CH_MUXINT_DAC_gc = (0x03<<3),
ADC_CH_MUXINT_TEMP_gc = (0x00<<3),
ADC_CH_MUXINT_BANDGAP_gc = (0x01<<3),
ADC_CH_MUXINT_SCALEDVCC_gc = (0x02<<3),
ADC_CH_MUXINT_DAC_gc = (0x03<<3),
ADC_CH_MUXINT_TEMP_gc = (0x00<<3),
ADC_CH_MUXINT_BANDGAP_gc = (0x01<<3),
ADC_CH_MUXINT_SCALEDVCC_gc = (0x02<<3),
ADC_CH_MUXINT_DAC_gc = (0x03<<3),
ADC_CH_MUXINT_TEMP_gc = (0x00<<3),
ADC_CH_MUXINT_BANDGAP_gc = (0x01<<3),
ADC_CH_MUXINT_SCALEDVCC_gc = (0x02<<3),
ADC_CH_MUXINT_DAC_gc = (0x03<<3)
} |
|
enum | ADC_CH_MUXNEG_enum {
ADC_CH_MUXNEG_PIN0_gc = (0x00<<0),
ADC_CH_MUXNEG_PIN1_gc = (0x01<<0),
ADC_CH_MUXNEG_PIN2_gc = (0x02<<0),
ADC_CH_MUXNEG_PIN3_gc = (0x03<<0),
ADC_CH_MUXNEG_PIN4_gc = (0x04<<0),
ADC_CH_MUXNEG_PIN5_gc = (0x05<<0),
ADC_CH_MUXNEG_PIN6_gc = (0x06<<0),
ADC_CH_MUXNEG_PIN7_gc = (0x07<<0),
ADC_CH_MUXNEG_PIN0_gc = (0x00<<0),
ADC_CH_MUXNEG_PIN1_gc = (0x01<<0),
ADC_CH_MUXNEG_PIN2_gc = (0x02<<0),
ADC_CH_MUXNEG_PIN3_gc = (0x03<<0),
ADC_CH_MUXNEG_PIN4_gc = (0x04<<0),
ADC_CH_MUXNEG_PIN5_gc = (0x05<<0),
ADC_CH_MUXNEG_PIN6_gc = (0x06<<0),
ADC_CH_MUXNEG_PIN7_gc = (0x07<<0),
ADC_CH_MUXNEG_PIN0_gc = (0x00<<0),
ADC_CH_MUXNEG_PIN1_gc = (0x01<<0),
ADC_CH_MUXNEG_PIN2_gc = (0x02<<0),
ADC_CH_MUXNEG_PIN3_gc = (0x03<<0),
ADC_CH_MUXNEG_PIN4_gc = (0x04<<0),
ADC_CH_MUXNEG_PIN5_gc = (0x05<<0),
ADC_CH_MUXNEG_PIN6_gc = (0x06<<0),
ADC_CH_MUXNEG_PIN7_gc = (0x07<<0),
ADC_CH_MUXNEG_PIN0_gc = (0x00<<0),
ADC_CH_MUXNEG_PIN1_gc = (0x01<<0),
ADC_CH_MUXNEG_PIN2_gc = (0x02<<0),
ADC_CH_MUXNEG_PIN3_gc = (0x03<<0),
ADC_CH_MUXNEG_PIN4_gc = (0x04<<0),
ADC_CH_MUXNEG_PIN5_gc = (0x05<<0),
ADC_CH_MUXNEG_PIN6_gc = (0x06<<0),
ADC_CH_MUXNEG_PIN7_gc = (0x07<<0),
ADC_CH_MUXNEG_PIN0_gc = (0x00<<0),
ADC_CH_MUXNEG_PIN1_gc = (0x01<<0),
ADC_CH_MUXNEG_PIN2_gc = (0x02<<0),
ADC_CH_MUXNEG_PIN3_gc = (0x03<<0),
ADC_CH_MUXNEG_PIN4_gc = (0x04<<0),
ADC_CH_MUXNEG_PIN5_gc = (0x05<<0),
ADC_CH_MUXNEG_PIN6_gc = (0x06<<0),
ADC_CH_MUXNEG_PIN7_gc = (0x07<<0),
ADC_CH_MUXNEG_PIN0_gc = (0x00<<0),
ADC_CH_MUXNEG_PIN1_gc = (0x01<<0),
ADC_CH_MUXNEG_PIN2_gc = (0x02<<0),
ADC_CH_MUXNEG_PIN3_gc = (0x03<<0),
ADC_CH_MUXNEG_PIN4_gc = (0x04<<0),
ADC_CH_MUXNEG_PIN5_gc = (0x05<<0),
ADC_CH_MUXNEG_PIN6_gc = (0x06<<0),
ADC_CH_MUXNEG_PIN7_gc = (0x07<<0),
ADC_CH_MUXNEG_PIN0_gc = (0x00<<0),
ADC_CH_MUXNEG_PIN1_gc = (0x01<<0),
ADC_CH_MUXNEG_PIN2_gc = (0x02<<0),
ADC_CH_MUXNEG_PIN3_gc = (0x03<<0),
ADC_CH_MUXNEG_PIN4_gc = (0x04<<0),
ADC_CH_MUXNEG_PIN5_gc = (0x05<<0),
ADC_CH_MUXNEG_PIN6_gc = (0x06<<0),
ADC_CH_MUXNEG_PIN7_gc = (0x07<<0),
ADC_CH_MUXNEG_PIN0_gc = (0x00<<0),
ADC_CH_MUXNEG_PIN1_gc = (0x01<<0),
ADC_CH_MUXNEG_PIN2_gc = (0x02<<0),
ADC_CH_MUXNEG_PIN3_gc = (0x03<<0),
ADC_CH_MUXNEG_PIN4_gc = (0x04<<0),
ADC_CH_MUXNEG_PIN5_gc = (0x05<<0),
ADC_CH_MUXNEG_PIN6_gc = (0x06<<0),
ADC_CH_MUXNEG_PIN7_gc = (0x07<<0),
ADC_CH_MUXNEG_PIN0_gc = (0x00<<0),
ADC_CH_MUXNEG_PIN1_gc = (0x01<<0),
ADC_CH_MUXNEG_PIN2_gc = (0x02<<0),
ADC_CH_MUXNEG_PIN3_gc = (0x03<<0),
ADC_CH_MUXNEG_PIN4_gc = (0x04<<0),
ADC_CH_MUXNEG_PIN5_gc = (0x05<<0),
ADC_CH_MUXNEG_PIN6_gc = (0x06<<0),
ADC_CH_MUXNEG_PIN7_gc = (0x07<<0),
ADC_CH_MUXNEG_PIN0_gc = (0x00<<0),
ADC_CH_MUXNEG_PIN1_gc = (0x01<<0),
ADC_CH_MUXNEG_PIN2_gc = (0x02<<0),
ADC_CH_MUXNEG_PIN3_gc = (0x03<<0),
ADC_CH_MUXNEG_PIN4_gc = (0x04<<0),
ADC_CH_MUXNEG_PIN5_gc = (0x05<<0),
ADC_CH_MUXNEG_PIN6_gc = (0x06<<0),
ADC_CH_MUXNEG_PIN7_gc = (0x07<<0),
ADC_CH_MUXNEG_PIN0_gc = (0x00<<0),
ADC_CH_MUXNEG_PIN1_gc = (0x01<<0),
ADC_CH_MUXNEG_PIN2_gc = (0x02<<0),
ADC_CH_MUXNEG_PIN3_gc = (0x03<<0),
ADC_CH_MUXNEG_PIN4_gc = (0x04<<0),
ADC_CH_MUXNEG_PIN5_gc = (0x05<<0),
ADC_CH_MUXNEG_PIN6_gc = (0x06<<0),
ADC_CH_MUXNEG_PIN7_gc = (0x07<<0),
ADC_CH_MUXNEG_PIN0_gc = (0x00<<0),
ADC_CH_MUXNEG_PIN1_gc = (0x01<<0),
ADC_CH_MUXNEG_PIN2_gc = (0x02<<0),
ADC_CH_MUXNEG_PIN3_gc = (0x03<<0),
ADC_CH_MUXNEG_PIN4_gc = (0x04<<0),
ADC_CH_MUXNEG_PIN5_gc = (0x05<<0),
ADC_CH_MUXNEG_PIN6_gc = (0x06<<0),
ADC_CH_MUXNEG_PIN7_gc = (0x07<<0),
ADC_CH_MUXNEG_PIN0_gc = (0x00<<0),
ADC_CH_MUXNEG_PIN1_gc = (0x01<<0),
ADC_CH_MUXNEG_PIN2_gc = (0x02<<0),
ADC_CH_MUXNEG_PIN3_gc = (0x03<<0),
ADC_CH_MUXNEG_PIN4_gc = (0x04<<0),
ADC_CH_MUXNEG_PIN5_gc = (0x05<<0),
ADC_CH_MUXNEG_PIN6_gc = (0x06<<0),
ADC_CH_MUXNEG_PIN7_gc = (0x07<<0),
ADC_CH_MUXNEG_PIN0_gc = (0x00<<0),
ADC_CH_MUXNEG_PIN1_gc = (0x01<<0),
ADC_CH_MUXNEG_PIN2_gc = (0x02<<0),
ADC_CH_MUXNEG_PIN3_gc = (0x03<<0),
ADC_CH_MUXNEG_PIN4_gc = (0x04<<0),
ADC_CH_MUXNEG_PIN5_gc = (0x05<<0),
ADC_CH_MUXNEG_PIN6_gc = (0x06<<0),
ADC_CH_MUXNEG_PIN7_gc = (0x07<<0),
ADC_CH_MUXNEG_PIN0_gc = (0x00<<0),
ADC_CH_MUXNEG_PIN1_gc = (0x01<<0),
ADC_CH_MUXNEG_PIN2_gc = (0x02<<0),
ADC_CH_MUXNEG_PIN3_gc = (0x03<<0),
ADC_CH_MUXNEG_PIN4_gc = (0x04<<0),
ADC_CH_MUXNEG_PIN5_gc = (0x05<<0),
ADC_CH_MUXNEG_PIN6_gc = (0x06<<0),
ADC_CH_MUXNEG_PIN7_gc = (0x07<<0)
} |
|
enum | ADC_CH_INPUTMODE_enum {
ADC_CH_INPUTMODE_INTERNAL_gc = (0x00<<0),
ADC_CH_INPUTMODE_SINGLEENDED_gc = (0x01<<0),
ADC_CH_INPUTMODE_DIFF_gc = (0x02<<0),
ADC_CH_INPUTMODE_DIFFWGAIN_gc = (0x03<<0),
ADC_CH_INPUTMODE_INTERNAL_gc = (0x00<<0),
ADC_CH_INPUTMODE_SINGLEENDED_gc = (0x01<<0),
ADC_CH_INPUTMODE_DIFF_gc = (0x02<<0),
ADC_CH_INPUTMODE_DIFFWGAIN_gc = (0x03<<0),
ADC_CH_INPUTMODE_INTERNAL_gc = (0x00<<0),
ADC_CH_INPUTMODE_SINGLEENDED_gc = (0x01<<0),
ADC_CH_INPUTMODE_DIFF_gc = (0x02<<0),
ADC_CH_INPUTMODE_DIFFWGAIN_gc = (0x03<<0),
ADC_CH_INPUTMODE_INTERNAL_gc = (0x00<<0),
ADC_CH_INPUTMODE_SINGLEENDED_gc = (0x01<<0),
ADC_CH_INPUTMODE_DIFF_gc = (0x02<<0),
ADC_CH_INPUTMODE_DIFFWGAIN_gc = (0x03<<0),
ADC_CH_INPUTMODE_INTERNAL_gc = (0x00<<0),
ADC_CH_INPUTMODE_SINGLEENDED_gc = (0x01<<0),
ADC_CH_INPUTMODE_DIFF_gc = (0x02<<0),
ADC_CH_INPUTMODE_DIFFWGAIN_gc = (0x03<<0),
ADC_CH_INPUTMODE_INTERNAL_gc = (0x00<<0),
ADC_CH_INPUTMODE_SINGLEENDED_gc = (0x01<<0),
ADC_CH_INPUTMODE_DIFF_gc = (0x02<<0),
ADC_CH_INPUTMODE_DIFFWGAIN_gc = (0x03<<0),
ADC_CH_INPUTMODE_INTERNAL_gc = (0x00<<0),
ADC_CH_INPUTMODE_SINGLEENDED_gc = (0x01<<0),
ADC_CH_INPUTMODE_DIFF_gc = (0x02<<0),
ADC_CH_INPUTMODE_DIFFWGAIN_gc = (0x03<<0),
ADC_CH_INPUTMODE_INTERNAL_gc = (0x00<<0),
ADC_CH_INPUTMODE_SINGLEENDED_gc = (0x01<<0),
ADC_CH_INPUTMODE_DIFF_gc = (0x02<<0),
ADC_CH_INPUTMODE_DIFFWGAIN_gc = (0x03<<0),
ADC_CH_INPUTMODE_INTERNAL_gc = (0x00<<0),
ADC_CH_INPUTMODE_SINGLEENDED_gc = (0x01<<0),
ADC_CH_INPUTMODE_DIFF_gc = (0x02<<0),
ADC_CH_INPUTMODE_DIFFWGAIN_gc = (0x03<<0),
ADC_CH_INPUTMODE_INTERNAL_gc = (0x00<<0),
ADC_CH_INPUTMODE_SINGLEENDED_gc = (0x01<<0),
ADC_CH_INPUTMODE_DIFF_gc = (0x02<<0),
ADC_CH_INPUTMODE_DIFFWGAIN_gc = (0x03<<0),
ADC_CH_INPUTMODE_INTERNAL_gc = (0x00<<0),
ADC_CH_INPUTMODE_SINGLEENDED_gc = (0x01<<0),
ADC_CH_INPUTMODE_DIFF_gc = (0x02<<0),
ADC_CH_INPUTMODE_DIFFWGAIN_gc = (0x03<<0),
ADC_CH_INPUTMODE_INTERNAL_gc = (0x00<<0),
ADC_CH_INPUTMODE_SINGLEENDED_gc = (0x01<<0),
ADC_CH_INPUTMODE_DIFF_gc = (0x02<<0),
ADC_CH_INPUTMODE_DIFFWGAIN_gc = (0x03<<0),
ADC_CH_INPUTMODE_INTERNAL_gc = (0x00<<0),
ADC_CH_INPUTMODE_SINGLEENDED_gc = (0x01<<0),
ADC_CH_INPUTMODE_DIFF_gc = (0x02<<0),
ADC_CH_INPUTMODE_DIFFWGAIN_gc = (0x03<<0),
ADC_CH_INPUTMODE_INTERNAL_gc = (0x00<<0),
ADC_CH_INPUTMODE_SINGLEENDED_gc = (0x01<<0),
ADC_CH_INPUTMODE_DIFF_gc = (0x02<<0),
ADC_CH_INPUTMODE_DIFFWGAIN_gc = (0x03<<0),
ADC_CH_INPUTMODE_INTERNAL_gc = (0x00<<0),
ADC_CH_INPUTMODE_SINGLEENDED_gc = (0x01<<0),
ADC_CH_INPUTMODE_DIFF_gc = (0x02<<0),
ADC_CH_INPUTMODE_DIFFWGAIN_gc = (0x03<<0)
} |
|
enum | ADC_CH_GAIN_enum {
ADC_CH_GAIN_1X_gc = (0x00<<2),
ADC_CH_GAIN_2X_gc = (0x01<<2),
ADC_CH_GAIN_4X_gc = (0x02<<2),
ADC_CH_GAIN_8X_gc = (0x03<<2),
ADC_CH_GAIN_16X_gc = (0x04<<2),
ADC_CH_GAIN_32X_gc = (0x05<<2),
ADC_CH_GAIN_64X_gc = (0x06<<2),
ADC_CH_GAIN_1X_gc = (0x00<<2),
ADC_CH_GAIN_2X_gc = (0x01<<2),
ADC_CH_GAIN_4X_gc = (0x02<<2),
ADC_CH_GAIN_8X_gc = (0x03<<2),
ADC_CH_GAIN_16X_gc = (0x04<<2),
ADC_CH_GAIN_32X_gc = (0x05<<2),
ADC_CH_GAIN_64X_gc = (0x06<<2),
ADC_CH_GAIN_1X_gc = (0x00<<2),
ADC_CH_GAIN_2X_gc = (0x01<<2),
ADC_CH_GAIN_4X_gc = (0x02<<2),
ADC_CH_GAIN_8X_gc = (0x03<<2),
ADC_CH_GAIN_16X_gc = (0x04<<2),
ADC_CH_GAIN_32X_gc = (0x05<<2),
ADC_CH_GAIN_64X_gc = (0x06<<2),
ADC_CH_GAIN_1X_gc = (0x00<<2),
ADC_CH_GAIN_2X_gc = (0x01<<2),
ADC_CH_GAIN_4X_gc = (0x02<<2),
ADC_CH_GAIN_8X_gc = (0x03<<2),
ADC_CH_GAIN_16X_gc = (0x04<<2),
ADC_CH_GAIN_32X_gc = (0x05<<2),
ADC_CH_GAIN_64X_gc = (0x06<<2),
ADC_CH_GAIN_1X_gc = (0x00<<2),
ADC_CH_GAIN_2X_gc = (0x01<<2),
ADC_CH_GAIN_4X_gc = (0x02<<2),
ADC_CH_GAIN_8X_gc = (0x03<<2),
ADC_CH_GAIN_16X_gc = (0x04<<2),
ADC_CH_GAIN_32X_gc = (0x05<<2),
ADC_CH_GAIN_64X_gc = (0x06<<2),
ADC_CH_GAIN_1X_gc = (0x00<<2),
ADC_CH_GAIN_2X_gc = (0x01<<2),
ADC_CH_GAIN_4X_gc = (0x02<<2),
ADC_CH_GAIN_8X_gc = (0x03<<2),
ADC_CH_GAIN_16X_gc = (0x04<<2),
ADC_CH_GAIN_32X_gc = (0x05<<2),
ADC_CH_GAIN_64X_gc = (0x06<<2),
ADC_CH_GAIN_1X_gc = (0x00<<2),
ADC_CH_GAIN_2X_gc = (0x01<<2),
ADC_CH_GAIN_4X_gc = (0x02<<2),
ADC_CH_GAIN_8X_gc = (0x03<<2),
ADC_CH_GAIN_16X_gc = (0x04<<2),
ADC_CH_GAIN_32X_gc = (0x05<<2),
ADC_CH_GAIN_64X_gc = (0x06<<2),
ADC_CH_GAIN_1X_gc = (0x00<<2),
ADC_CH_GAIN_2X_gc = (0x01<<2),
ADC_CH_GAIN_4X_gc = (0x02<<2),
ADC_CH_GAIN_8X_gc = (0x03<<2),
ADC_CH_GAIN_16X_gc = (0x04<<2),
ADC_CH_GAIN_32X_gc = (0x05<<2),
ADC_CH_GAIN_64X_gc = (0x06<<2),
ADC_CH_GAIN_1X_gc = (0x00<<2),
ADC_CH_GAIN_2X_gc = (0x01<<2),
ADC_CH_GAIN_4X_gc = (0x02<<2),
ADC_CH_GAIN_8X_gc = (0x03<<2),
ADC_CH_GAIN_16X_gc = (0x04<<2),
ADC_CH_GAIN_32X_gc = (0x05<<2),
ADC_CH_GAIN_64X_gc = (0x06<<2),
ADC_CH_GAIN_1X_gc = (0x00<<2),
ADC_CH_GAIN_2X_gc = (0x01<<2),
ADC_CH_GAIN_4X_gc = (0x02<<2),
ADC_CH_GAIN_8X_gc = (0x03<<2),
ADC_CH_GAIN_16X_gc = (0x04<<2),
ADC_CH_GAIN_32X_gc = (0x05<<2),
ADC_CH_GAIN_64X_gc = (0x06<<2),
ADC_CH_GAIN_1X_gc = (0x00<<2),
ADC_CH_GAIN_2X_gc = (0x01<<2),
ADC_CH_GAIN_4X_gc = (0x02<<2),
ADC_CH_GAIN_8X_gc = (0x03<<2),
ADC_CH_GAIN_16X_gc = (0x04<<2),
ADC_CH_GAIN_32X_gc = (0x05<<2),
ADC_CH_GAIN_64X_gc = (0x06<<2),
ADC_CH_GAIN_1X_gc = (0x00<<2),
ADC_CH_GAIN_2X_gc = (0x01<<2),
ADC_CH_GAIN_4X_gc = (0x02<<2),
ADC_CH_GAIN_8X_gc = (0x03<<2),
ADC_CH_GAIN_16X_gc = (0x04<<2),
ADC_CH_GAIN_32X_gc = (0x05<<2),
ADC_CH_GAIN_64X_gc = (0x06<<2),
ADC_CH_GAIN_1X_gc = (0x00<<2),
ADC_CH_GAIN_2X_gc = (0x01<<2),
ADC_CH_GAIN_4X_gc = (0x02<<2),
ADC_CH_GAIN_8X_gc = (0x03<<2),
ADC_CH_GAIN_16X_gc = (0x04<<2),
ADC_CH_GAIN_32X_gc = (0x05<<2),
ADC_CH_GAIN_64X_gc = (0x06<<2),
ADC_CH_GAIN_1X_gc = (0x00<<2),
ADC_CH_GAIN_2X_gc = (0x01<<2),
ADC_CH_GAIN_4X_gc = (0x02<<2),
ADC_CH_GAIN_8X_gc = (0x03<<2),
ADC_CH_GAIN_16X_gc = (0x04<<2),
ADC_CH_GAIN_32X_gc = (0x05<<2),
ADC_CH_GAIN_64X_gc = (0x06<<2),
ADC_CH_GAIN_1X_gc = (0x00<<2),
ADC_CH_GAIN_2X_gc = (0x01<<2),
ADC_CH_GAIN_4X_gc = (0x02<<2),
ADC_CH_GAIN_8X_gc = (0x03<<2),
ADC_CH_GAIN_16X_gc = (0x04<<2),
ADC_CH_GAIN_32X_gc = (0x05<<2),
ADC_CH_GAIN_64X_gc = (0x06<<2)
} |
|
enum | ADC_RESOLUTION_enum {
ADC_RESOLUTION_12BIT_gc = (0x00<<1),
ADC_RESOLUTION_8BIT_gc = (0x02<<1),
ADC_RESOLUTION_LEFT12BIT_gc = (0x03<<1),
ADC_RESOLUTION_12BIT_gc = (0x00<<1),
ADC_RESOLUTION_8BIT_gc = (0x02<<1),
ADC_RESOLUTION_LEFT12BIT_gc = (0x03<<1),
ADC_RESOLUTION_12BIT_gc = (0x00<<1),
ADC_RESOLUTION_8BIT_gc = (0x02<<1),
ADC_RESOLUTION_LEFT12BIT_gc = (0x03<<1),
ADC_RESOLUTION_12BIT_gc = (0x00<<1),
ADC_RESOLUTION_8BIT_gc = (0x02<<1),
ADC_RESOLUTION_LEFT12BIT_gc = (0x03<<1),
ADC_RESOLUTION_12BIT_gc = (0x00<<1),
ADC_RESOLUTION_8BIT_gc = (0x02<<1),
ADC_RESOLUTION_LEFT12BIT_gc = (0x03<<1),
ADC_RESOLUTION_12BIT_gc = (0x00<<1),
ADC_RESOLUTION_8BIT_gc = (0x02<<1),
ADC_RESOLUTION_LEFT12BIT_gc = (0x03<<1),
ADC_RESOLUTION_12BIT_gc = (0x00<<1),
ADC_RESOLUTION_8BIT_gc = (0x02<<1),
ADC_RESOLUTION_LEFT12BIT_gc = (0x03<<1),
ADC_RESOLUTION_12BIT_gc = (0x00<<1),
ADC_RESOLUTION_8BIT_gc = (0x02<<1),
ADC_RESOLUTION_LEFT12BIT_gc = (0x03<<1),
ADC_RESOLUTION_12BIT_gc = (0x00<<1),
ADC_RESOLUTION_8BIT_gc = (0x02<<1),
ADC_RESOLUTION_LEFT12BIT_gc = (0x03<<1),
ADC_RESOLUTION_12BIT_gc = (0x00<<1),
ADC_RESOLUTION_8BIT_gc = (0x02<<1),
ADC_RESOLUTION_LEFT12BIT_gc = (0x03<<1),
ADC_RESOLUTION_12BIT_gc = (0x00<<1),
ADC_RESOLUTION_8BIT_gc = (0x02<<1),
ADC_RESOLUTION_LEFT12BIT_gc = (0x03<<1),
ADC_RESOLUTION_12BIT_gc = (0x00<<1),
ADC_RESOLUTION_8BIT_gc = (0x02<<1),
ADC_RESOLUTION_LEFT12BIT_gc = (0x03<<1),
ADC_RESOLUTION_12BIT_gc = (0x00<<1),
ADC_RESOLUTION_8BIT_gc = (0x02<<1),
ADC_RESOLUTION_LEFT12BIT_gc = (0x03<<1),
ADC_RESOLUTION_12BIT_gc = (0x00<<1),
ADC_RESOLUTION_8BIT_gc = (0x02<<1),
ADC_RESOLUTION_LEFT12BIT_gc = (0x03<<1),
ADC_RESOLUTION_12BIT_gc = (0x00<<1),
ADC_RESOLUTION_8BIT_gc = (0x02<<1),
ADC_RESOLUTION_LEFT12BIT_gc = (0x03<<1)
} |
|
enum | ADC_REFSEL_enum {
ADC_REFSEL_INT1V_gc = (0x00<<4),
ADC_REFSEL_VCC_gc = (0x01<<4),
ADC_REFSEL_AREFA_gc = (0x02<<4),
ADC_REFSEL_AREFB_gc = (0x03<<4),
ADC_REFSEL_INT1V_gc = (0x00<<4),
ADC_REFSEL_VCC_gc = (0x01<<4),
ADC_REFSEL_AREFA_gc = (0x02<<4),
ADC_REFSEL_AREFB_gc = (0x03<<4),
ADC_REFSEL_INT1V_gc = (0x00<<4),
ADC_REFSEL_VCC_gc = (0x01<<4),
ADC_REFSEL_AREFA_gc = (0x02<<4),
ADC_REFSEL_AREFB_gc = (0x03<<4),
ADC_REFSEL_INT1V_gc = (0x00<<4),
ADC_REFSEL_VCC_gc = (0x01<<4),
ADC_REFSEL_AREFA_gc = (0x02<<4),
ADC_REFSEL_AREFB_gc = (0x03<<4),
ADC_REFSEL_INT1V_gc = (0x00<<4),
ADC_REFSEL_VCC_gc = (0x01<<4),
ADC_REFSEL_AREFA_gc = (0x02<<4),
ADC_REFSEL_AREFB_gc = (0x03<<4),
ADC_REFSEL_INT1V_gc = (0x00<<4),
ADC_REFSEL_VCC_gc = (0x01<<4),
ADC_REFSEL_AREFA_gc = (0x02<<4),
ADC_REFSEL_AREFB_gc = (0x03<<4),
ADC_REFSEL_INT1V_gc = (0x00<<4),
ADC_REFSEL_VCC_gc = (0x01<<4),
ADC_REFSEL_AREFA_gc = (0x02<<4),
ADC_REFSEL_AREFB_gc = (0x03<<4),
ADC_REFSEL_INT1V_gc = (0x00<<4),
ADC_REFSEL_VCC_gc = (0x01<<4),
ADC_REFSEL_AREFA_gc = (0x02<<4),
ADC_REFSEL_AREFB_gc = (0x03<<4),
ADC_REFSEL_INT1V_gc = (0x00<<4),
ADC_REFSEL_VCC_gc = (0x01<<4),
ADC_REFSEL_AREFA_gc = (0x02<<4),
ADC_REFSEL_AREFB_gc = (0x03<<4),
ADC_REFSEL_INT1V_gc = (0x00<<4),
ADC_REFSEL_VCC_gc = (0x01<<4),
ADC_REFSEL_AREFA_gc = (0x02<<4),
ADC_REFSEL_AREFB_gc = (0x03<<4),
ADC_REFSEL_INT1V_gc = (0x00<<4),
ADC_REFSEL_VCC_gc = (0x01<<4),
ADC_REFSEL_AREFA_gc = (0x02<<4),
ADC_REFSEL_AREFB_gc = (0x03<<4),
ADC_REFSEL_INT1V_gc = (0x00<<4),
ADC_REFSEL_VCC_gc = (0x01<<4),
ADC_REFSEL_AREFA_gc = (0x02<<4),
ADC_REFSEL_AREFB_gc = (0x03<<4),
ADC_REFSEL_INT1V_gc = (0x00<<4),
ADC_REFSEL_VCC_gc = (0x01<<4),
ADC_REFSEL_AREFA_gc = (0x02<<4),
ADC_REFSEL_AREFB_gc = (0x03<<4),
ADC_REFSEL_INT1V_gc = (0x00<<4),
ADC_REFSEL_VCC_gc = (0x01<<4),
ADC_REFSEL_AREFA_gc = (0x02<<4),
ADC_REFSEL_AREFB_gc = (0x03<<4),
ADC_REFSEL_INT1V_gc = (0x00<<4),
ADC_REFSEL_VCC_gc = (0x01<<4),
ADC_REFSEL_AREFA_gc = (0x02<<4),
ADC_REFSEL_AREFB_gc = (0x03<<4)
} |
|
enum | ADC_SWEEP_enum {
ADC_SWEEP_0_gc = (0x00<<6),
ADC_SWEEP_01_gc = (0x01<<6),
ADC_SWEEP_012_gc = (0x02<<6),
ADC_SWEEP_0123_gc = (0x03<<6),
ADC_SWEEP_0_gc = (0x00<<6),
ADC_SWEEP_01_gc = (0x01<<6),
ADC_SWEEP_012_gc = (0x02<<6),
ADC_SWEEP_0123_gc = (0x03<<6),
ADC_SWEEP_0_gc = (0x00<<6),
ADC_SWEEP_0_gc = (0x00<<6),
ADC_SWEEP_01_gc = (0x01<<6),
ADC_SWEEP_012_gc = (0x02<<6),
ADC_SWEEP_0123_gc = (0x03<<6),
ADC_SWEEP_0_gc = (0x00<<6),
ADC_SWEEP_0_gc = (0x00<<6),
ADC_SWEEP_01_gc = (0x01<<6),
ADC_SWEEP_012_gc = (0x02<<6),
ADC_SWEEP_0123_gc = (0x03<<6),
ADC_SWEEP_0_gc = (0x00<<6),
ADC_SWEEP_0_gc = (0x00<<6),
ADC_SWEEP_01_gc = (0x01<<6),
ADC_SWEEP_012_gc = (0x02<<6),
ADC_SWEEP_0123_gc = (0x03<<6),
ADC_SWEEP_0_gc = (0x00<<6),
ADC_SWEEP_01_gc = (0x01<<6),
ADC_SWEEP_012_gc = (0x02<<6),
ADC_SWEEP_0123_gc = (0x03<<6),
ADC_SWEEP_0_gc = (0x00<<6),
ADC_SWEEP_01_gc = (0x01<<6),
ADC_SWEEP_012_gc = (0x02<<6),
ADC_SWEEP_0123_gc = (0x03<<6),
ADC_SWEEP_0_gc = (0x00<<6),
ADC_SWEEP_0_gc = (0x00<<6),
ADC_SWEEP_01_gc = (0x01<<6),
ADC_SWEEP_012_gc = (0x02<<6),
ADC_SWEEP_0123_gc = (0x03<<6),
ADC_SWEEP_0_gc = (0x00<<6),
ADC_SWEEP_01_gc = (0x01<<6),
ADC_SWEEP_012_gc = (0x02<<6),
ADC_SWEEP_0123_gc = (0x03<<6),
ADC_SWEEP_0_gc = (0x00<<6)
} |
|
enum | ADC_EVSEL_enum {
ADC_EVSEL_0123_gc = (0x00<<3),
ADC_EVSEL_1234_gc = (0x01<<3),
ADC_EVSEL_2345_gc = (0x02<<3),
ADC_EVSEL_3456_gc = (0x03<<3),
ADC_EVSEL_4567_gc = (0x04<<3),
ADC_EVSEL_567_gc = (0x05<<3),
ADC_EVSEL_67_gc = (0x06<<3),
ADC_EVSEL_7_gc = (0x07<<3),
ADC_EVSEL_0123_gc = (0x00<<3),
ADC_EVSEL_1234_gc = (0x01<<3),
ADC_EVSEL_2345_gc = (0x02<<3),
ADC_EVSEL_3456_gc = (0x03<<3),
ADC_EVSEL_4567_gc = (0x04<<3),
ADC_EVSEL_567_gc = (0x05<<3),
ADC_EVSEL_67_gc = (0x06<<3),
ADC_EVSEL_7_gc = (0x07<<3),
ADC_EVSEL_0123_gc = (0x00<<3),
ADC_EVSEL_1234_gc = (0x01<<3),
ADC_EVSEL_2345_gc = (0x02<<3),
ADC_EVSEL_3456_gc = (0x03<<3),
ADC_EVSEL_4567_gc = (0x04<<3),
ADC_EVSEL_567_gc = (0x05<<3),
ADC_EVSEL_67_gc = (0x06<<3),
ADC_EVSEL_7_gc = (0x07<<3),
ADC_EVSEL_0123_gc = (0x00<<3),
ADC_EVSEL_1234_gc = (0x01<<3),
ADC_EVSEL_2345_gc = (0x02<<3),
ADC_EVSEL_3456_gc = (0x03<<3),
ADC_EVSEL_4567_gc = (0x04<<3),
ADC_EVSEL_567_gc = (0x05<<3),
ADC_EVSEL_67_gc = (0x06<<3),
ADC_EVSEL_7_gc = (0x07<<3),
ADC_EVSEL_0123_gc = (0x00<<3),
ADC_EVSEL_1234_gc = (0x01<<3),
ADC_EVSEL_2345_gc = (0x02<<3),
ADC_EVSEL_3456_gc = (0x03<<3),
ADC_EVSEL_4567_gc = (0x04<<3),
ADC_EVSEL_567_gc = (0x05<<3),
ADC_EVSEL_67_gc = (0x06<<3),
ADC_EVSEL_7_gc = (0x07<<3),
ADC_EVSEL_0123_gc = (0x00<<3),
ADC_EVSEL_1234_gc = (0x01<<3),
ADC_EVSEL_2345_gc = (0x02<<3),
ADC_EVSEL_3456_gc = (0x03<<3),
ADC_EVSEL_4567_gc = (0x04<<3),
ADC_EVSEL_567_gc = (0x05<<3),
ADC_EVSEL_67_gc = (0x06<<3),
ADC_EVSEL_7_gc = (0x07<<3),
ADC_EVSEL_0123_gc = (0x00<<3),
ADC_EVSEL_1234_gc = (0x01<<3),
ADC_EVSEL_2345_gc = (0x02<<3),
ADC_EVSEL_3456_gc = (0x03<<3),
ADC_EVSEL_4567_gc = (0x04<<3),
ADC_EVSEL_567_gc = (0x05<<3),
ADC_EVSEL_67_gc = (0x06<<3),
ADC_EVSEL_7_gc = (0x07<<3),
ADC_EVSEL_0123_gc = (0x00<<3),
ADC_EVSEL_1234_gc = (0x01<<3),
ADC_EVSEL_2345_gc = (0x02<<3),
ADC_EVSEL_3456_gc = (0x03<<3),
ADC_EVSEL_4567_gc = (0x04<<3),
ADC_EVSEL_567_gc = (0x05<<3),
ADC_EVSEL_67_gc = (0x06<<3),
ADC_EVSEL_7_gc = (0x07<<3),
ADC_EVSEL_0123_gc = (0x00<<3),
ADC_EVSEL_1234_gc = (0x01<<3),
ADC_EVSEL_2345_gc = (0x02<<3),
ADC_EVSEL_3456_gc = (0x03<<3),
ADC_EVSEL_4567_gc = (0x04<<3),
ADC_EVSEL_567_gc = (0x05<<3),
ADC_EVSEL_67_gc = (0x06<<3),
ADC_EVSEL_7_gc = (0x07<<3),
ADC_EVSEL_0123_gc = (0x00<<3),
ADC_EVSEL_1234_gc = (0x01<<3),
ADC_EVSEL_2345_gc = (0x02<<3),
ADC_EVSEL_3456_gc = (0x03<<3),
ADC_EVSEL_4567_gc = (0x04<<3),
ADC_EVSEL_567_gc = (0x05<<3),
ADC_EVSEL_67_gc = (0x06<<3),
ADC_EVSEL_7_gc = (0x07<<3),
ADC_EVSEL_0123_gc = (0x00<<3),
ADC_EVSEL_1234_gc = (0x01<<3),
ADC_EVSEL_2345_gc = (0x02<<3),
ADC_EVSEL_3456_gc = (0x03<<3),
ADC_EVSEL_4567_gc = (0x04<<3),
ADC_EVSEL_567_gc = (0x05<<3),
ADC_EVSEL_67_gc = (0x06<<3),
ADC_EVSEL_7_gc = (0x07<<3),
ADC_EVSEL_0123_gc = (0x00<<3),
ADC_EVSEL_1234_gc = (0x01<<3),
ADC_EVSEL_2345_gc = (0x02<<3),
ADC_EVSEL_3456_gc = (0x03<<3),
ADC_EVSEL_4567_gc = (0x04<<3),
ADC_EVSEL_567_gc = (0x05<<3),
ADC_EVSEL_67_gc = (0x06<<3),
ADC_EVSEL_7_gc = (0x07<<3),
ADC_EVSEL_0123_gc = (0x00<<3),
ADC_EVSEL_1234_gc = (0x01<<3),
ADC_EVSEL_2345_gc = (0x02<<3),
ADC_EVSEL_3456_gc = (0x03<<3),
ADC_EVSEL_4567_gc = (0x04<<3),
ADC_EVSEL_567_gc = (0x05<<3),
ADC_EVSEL_67_gc = (0x06<<3),
ADC_EVSEL_7_gc = (0x07<<3),
ADC_EVSEL_0123_gc = (0x00<<3),
ADC_EVSEL_1234_gc = (0x01<<3),
ADC_EVSEL_2345_gc = (0x02<<3),
ADC_EVSEL_3456_gc = (0x03<<3),
ADC_EVSEL_4567_gc = (0x04<<3),
ADC_EVSEL_567_gc = (0x05<<3),
ADC_EVSEL_67_gc = (0x06<<3),
ADC_EVSEL_7_gc = (0x07<<3),
ADC_EVSEL_0123_gc = (0x00<<3),
ADC_EVSEL_1234_gc = (0x01<<3),
ADC_EVSEL_2345_gc = (0x02<<3),
ADC_EVSEL_3456_gc = (0x03<<3),
ADC_EVSEL_4567_gc = (0x04<<3),
ADC_EVSEL_567_gc = (0x05<<3),
ADC_EVSEL_67_gc = (0x06<<3),
ADC_EVSEL_7_gc = (0x07<<3)
} |
|
enum | ADC_EVACT_enum {
ADC_EVACT_NONE_gc = (0x00<<0),
ADC_EVACT_CH0_gc = (0x01<<0),
ADC_EVACT_CH01_gc = (0x02<<0),
ADC_EVACT_CH012_gc = (0x03<<0),
ADC_EVACT_CH0123_gc = (0x04<<0),
ADC_EVACT_SWEEP_gc = (0x05<<0),
ADC_EVACT_SYNCHSWEEP_gc = (0x06<<0),
ADC_EVACT_NONE_gc = (0x00<<0),
ADC_EVACT_CH0_gc = (0x01<<0),
ADC_EVACT_CH01_gc = (0x02<<0),
ADC_EVACT_CH012_gc = (0x03<<0),
ADC_EVACT_CH0123_gc = (0x04<<0),
ADC_EVACT_SWEEP_gc = (0x05<<0),
ADC_EVACT_SYNCHSWEEP_gc = (0x06<<0),
ADC_EVACT_NONE_gc = (0x00<<0),
ADC_EVACT_CH0_gc = (0x01<<0),
ADC_EVACT_NONE_gc = (0x00<<0),
ADC_EVACT_CH0_gc = (0x01<<0),
ADC_EVACT_CH01_gc = (0x02<<0),
ADC_EVACT_CH012_gc = (0x03<<0),
ADC_EVACT_CH0123_gc = (0x04<<0),
ADC_EVACT_SWEEP_gc = (0x05<<0),
ADC_EVACT_SYNCHSWEEP_gc = (0x06<<0),
ADC_EVACT_NONE_gc = (0x00<<0),
ADC_EVACT_CH0_gc = (0x01<<0),
ADC_EVACT_NONE_gc = (0x00<<0),
ADC_EVACT_CH0_gc = (0x01<<0),
ADC_EVACT_CH01_gc = (0x02<<0),
ADC_EVACT_CH012_gc = (0x03<<0),
ADC_EVACT_CH0123_gc = (0x04<<0),
ADC_EVACT_SWEEP_gc = (0x05<<0),
ADC_EVACT_SYNCHSWEEP_gc = (0x06<<0),
ADC_EVACT_NONE_gc = (0x00<<0),
ADC_EVACT_CH0_gc = (0x01<<0),
ADC_EVACT_NONE_gc = (0x00<<0),
ADC_EVACT_CH0_gc = (0x01<<0),
ADC_EVACT_CH01_gc = (0x02<<0),
ADC_EVACT_CH012_gc = (0x03<<0),
ADC_EVACT_CH0123_gc = (0x04<<0),
ADC_EVACT_SWEEP_gc = (0x05<<0),
ADC_EVACT_SYNCHSWEEP_gc = (0x06<<0),
ADC_EVACT_NONE_gc = (0x00<<0),
ADC_EVACT_CH0_gc = (0x01<<0),
ADC_EVACT_CH01_gc = (0x02<<0),
ADC_EVACT_CH012_gc = (0x03<<0),
ADC_EVACT_CH0123_gc = (0x04<<0),
ADC_EVACT_SWEEP_gc = (0x05<<0),
ADC_EVACT_SYNCHSWEEP_gc = (0x06<<0),
ADC_EVACT_NONE_gc = (0x00<<0),
ADC_EVACT_CH0_gc = (0x01<<0),
ADC_EVACT_NONE_gc = (0x00<<0),
ADC_EVACT_CH0_gc = (0x01<<0),
ADC_EVACT_CH01_gc = (0x02<<0),
ADC_EVACT_CH012_gc = (0x03<<0),
ADC_EVACT_CH0123_gc = (0x04<<0),
ADC_EVACT_SWEEP_gc = (0x05<<0),
ADC_EVACT_SYNCHSWEEP_gc = (0x06<<0),
ADC_EVACT_NONE_gc = (0x00<<0),
ADC_EVACT_CH0_gc = (0x01<<0),
ADC_EVACT_NONE_gc = (0x00<<0),
ADC_EVACT_CH0_gc = (0x01<<0),
ADC_EVACT_CH01_gc = (0x02<<0),
ADC_EVACT_CH012_gc = (0x03<<0),
ADC_EVACT_CH0123_gc = (0x04<<0),
ADC_EVACT_SWEEP_gc = (0x05<<0),
ADC_EVACT_SYNCHSWEEP_gc = (0x06<<0),
ADC_EVACT_NONE_gc = (0x00<<0),
ADC_EVACT_CH0_gc = (0x01<<0),
ADC_EVACT_CH01_gc = (0x02<<0),
ADC_EVACT_CH012_gc = (0x03<<0),
ADC_EVACT_CH0123_gc = (0x04<<0),
ADC_EVACT_SWEEP_gc = (0x05<<0),
ADC_EVACT_SYNCHSWEEP_gc = (0x06<<0),
ADC_EVACT_NONE_gc = (0x00<<0),
ADC_EVACT_CH0_gc = (0x01<<0)
} |
|
enum | ADC_CH_INTMODE_enum {
ADC_CH_INTMODE_COMPLETE_gc = (0x00<<2),
ADC_CH_INTMODE_BELOW_gc = (0x01<<2),
ADC_CH_INTMODE_ABOVE_gc = (0x03<<2),
ADC_CH_INTMODE_COMPLETE_gc = (0x00<<2),
ADC_CH_INTMODE_BELOW_gc = (0x01<<2),
ADC_CH_INTMODE_ABOVE_gc = (0x03<<2),
ADC_CH_INTMODE_COMPLETE_gc = (0x00<<2),
ADC_CH_INTMODE_BELOW_gc = (0x01<<2),
ADC_CH_INTMODE_ABOVE_gc = (0x03<<2),
ADC_CH_INTMODE_COMPLETE_gc = (0x00<<2),
ADC_CH_INTMODE_BELOW_gc = (0x01<<2),
ADC_CH_INTMODE_ABOVE_gc = (0x03<<2),
ADC_CH_INTMODE_COMPLETE_gc = (0x00<<2),
ADC_CH_INTMODE_BELOW_gc = (0x01<<2),
ADC_CH_INTMODE_ABOVE_gc = (0x03<<2),
ADC_CH_INTMODE_COMPLETE_gc = (0x00<<2),
ADC_CH_INTMODE_BELOW_gc = (0x01<<2),
ADC_CH_INTMODE_ABOVE_gc = (0x03<<2),
ADC_CH_INTMODE_COMPLETE_gc = (0x00<<2),
ADC_CH_INTMODE_BELOW_gc = (0x01<<2),
ADC_CH_INTMODE_ABOVE_gc = (0x03<<2),
ADC_CH_INTMODE_COMPLETE_gc = (0x00<<2),
ADC_CH_INTMODE_BELOW_gc = (0x01<<2),
ADC_CH_INTMODE_ABOVE_gc = (0x03<<2),
ADC_CH_INTMODE_COMPLETE_gc = (0x00<<2),
ADC_CH_INTMODE_BELOW_gc = (0x01<<2),
ADC_CH_INTMODE_ABOVE_gc = (0x03<<2),
ADC_CH_INTMODE_COMPLETE_gc = (0x00<<2),
ADC_CH_INTMODE_BELOW_gc = (0x01<<2),
ADC_CH_INTMODE_ABOVE_gc = (0x03<<2),
ADC_CH_INTMODE_COMPLETE_gc = (0x00<<2),
ADC_CH_INTMODE_BELOW_gc = (0x01<<2),
ADC_CH_INTMODE_ABOVE_gc = (0x03<<2),
ADC_CH_INTMODE_COMPLETE_gc = (0x00<<2),
ADC_CH_INTMODE_BELOW_gc = (0x01<<2),
ADC_CH_INTMODE_ABOVE_gc = (0x03<<2),
ADC_CH_INTMODE_COMPLETE_gc = (0x00<<2),
ADC_CH_INTMODE_BELOW_gc = (0x01<<2),
ADC_CH_INTMODE_ABOVE_gc = (0x03<<2),
ADC_CH_INTMODE_COMPLETE_gc = (0x00<<2),
ADC_CH_INTMODE_BELOW_gc = (0x01<<2),
ADC_CH_INTMODE_ABOVE_gc = (0x03<<2),
ADC_CH_INTMODE_COMPLETE_gc = (0x00<<2),
ADC_CH_INTMODE_BELOW_gc = (0x01<<2),
ADC_CH_INTMODE_ABOVE_gc = (0x03<<2)
} |
|
enum | ADC_CH_INTLVL_enum {
ADC_CH_INTLVL_OFF_gc = (0x00<<0),
ADC_CH_INTLVL_LO_gc = (0x01<<0),
ADC_CH_INTLVL_MED_gc = (0x02<<0),
ADC_CH_INTLVL_HI_gc = (0x03<<0),
ADC_CH_INTLVL_OFF_gc = (0x00<<0),
ADC_CH_INTLVL_LO_gc = (0x01<<0),
ADC_CH_INTLVL_MED_gc = (0x02<<0),
ADC_CH_INTLVL_HI_gc = (0x03<<0),
ADC_CH_INTLVL_OFF_gc = (0x00<<0),
ADC_CH_INTLVL_LO_gc = (0x01<<0),
ADC_CH_INTLVL_MED_gc = (0x02<<0),
ADC_CH_INTLVL_HI_gc = (0x03<<0),
ADC_CH_INTLVL_OFF_gc = (0x00<<0),
ADC_CH_INTLVL_LO_gc = (0x01<<0),
ADC_CH_INTLVL_MED_gc = (0x02<<0),
ADC_CH_INTLVL_HI_gc = (0x03<<0),
ADC_CH_INTLVL_OFF_gc = (0x00<<0),
ADC_CH_INTLVL_LO_gc = (0x01<<0),
ADC_CH_INTLVL_MED_gc = (0x02<<0),
ADC_CH_INTLVL_HI_gc = (0x03<<0),
ADC_CH_INTLVL_OFF_gc = (0x00<<0),
ADC_CH_INTLVL_LO_gc = (0x01<<0),
ADC_CH_INTLVL_MED_gc = (0x02<<0),
ADC_CH_INTLVL_HI_gc = (0x03<<0),
ADC_CH_INTLVL_OFF_gc = (0x00<<0),
ADC_CH_INTLVL_LO_gc = (0x01<<0),
ADC_CH_INTLVL_MED_gc = (0x02<<0),
ADC_CH_INTLVL_HI_gc = (0x03<<0),
ADC_CH_INTLVL_OFF_gc = (0x00<<0),
ADC_CH_INTLVL_LO_gc = (0x01<<0),
ADC_CH_INTLVL_MED_gc = (0x02<<0),
ADC_CH_INTLVL_HI_gc = (0x03<<0),
ADC_CH_INTLVL_OFF_gc = (0x00<<0),
ADC_CH_INTLVL_LO_gc = (0x01<<0),
ADC_CH_INTLVL_MED_gc = (0x02<<0),
ADC_CH_INTLVL_HI_gc = (0x03<<0),
ADC_CH_INTLVL_OFF_gc = (0x00<<0),
ADC_CH_INTLVL_LO_gc = (0x01<<0),
ADC_CH_INTLVL_MED_gc = (0x02<<0),
ADC_CH_INTLVL_HI_gc = (0x03<<0),
ADC_CH_INTLVL_OFF_gc = (0x00<<0),
ADC_CH_INTLVL_LO_gc = (0x01<<0),
ADC_CH_INTLVL_MED_gc = (0x02<<0),
ADC_CH_INTLVL_HI_gc = (0x03<<0),
ADC_CH_INTLVL_OFF_gc = (0x00<<0),
ADC_CH_INTLVL_LO_gc = (0x01<<0),
ADC_CH_INTLVL_MED_gc = (0x02<<0),
ADC_CH_INTLVL_HI_gc = (0x03<<0),
ADC_CH_INTLVL_OFF_gc = (0x00<<0),
ADC_CH_INTLVL_LO_gc = (0x01<<0),
ADC_CH_INTLVL_MED_gc = (0x02<<0),
ADC_CH_INTLVL_HI_gc = (0x03<<0),
ADC_CH_INTLVL_OFF_gc = (0x00<<0),
ADC_CH_INTLVL_LO_gc = (0x01<<0),
ADC_CH_INTLVL_MED_gc = (0x02<<0),
ADC_CH_INTLVL_HI_gc = (0x03<<0),
ADC_CH_INTLVL_OFF_gc = (0x00<<0),
ADC_CH_INTLVL_LO_gc = (0x01<<0),
ADC_CH_INTLVL_MED_gc = (0x02<<0),
ADC_CH_INTLVL_HI_gc = (0x03<<0)
} |
|
enum | ADC_DMASEL_enum {
ADC_DMASEL_OFF_gc = (0x00<<6),
ADC_DMASEL_CH01_gc = (0x01<<6),
ADC_DMASEL_CH012_gc = (0x02<<6),
ADC_DMASEL_CH0123_gc = (0x03<<6),
ADC_DMASEL_OFF_gc = (0x00<<6),
ADC_DMASEL_CH01_gc = (0x01<<6),
ADC_DMASEL_CH012_gc = (0x02<<6),
ADC_DMASEL_CH0123_gc = (0x03<<6),
ADC_DMASEL_OFF_gc = (0x00<<6),
ADC_DMASEL_CH01_gc = (0x01<<6),
ADC_DMASEL_CH012_gc = (0x02<<6),
ADC_DMASEL_CH0123_gc = (0x03<<6),
ADC_DMASEL_OFF_gc = (0x00<<6),
ADC_DMASEL_CH01_gc = (0x01<<6),
ADC_DMASEL_CH012_gc = (0x02<<6),
ADC_DMASEL_CH0123_gc = (0x03<<6),
ADC_DMASEL_OFF_gc = (0x00<<6),
ADC_DMASEL_CH01_gc = (0x01<<6),
ADC_DMASEL_CH012_gc = (0x02<<6),
ADC_DMASEL_CH0123_gc = (0x03<<6),
ADC_DMASEL_OFF_gc = (0x00<<6),
ADC_DMASEL_CH01_gc = (0x01<<6),
ADC_DMASEL_CH012_gc = (0x02<<6),
ADC_DMASEL_CH0123_gc = (0x03<<6),
ADC_DMASEL_OFF_gc = (0x00<<6),
ADC_DMASEL_CH01_gc = (0x01<<6),
ADC_DMASEL_CH012_gc = (0x02<<6),
ADC_DMASEL_CH0123_gc = (0x03<<6),
ADC_DMASEL_OFF_gc = (0x00<<6),
ADC_DMASEL_CH01_gc = (0x01<<6),
ADC_DMASEL_CH012_gc = (0x02<<6),
ADC_DMASEL_CH0123_gc = (0x03<<6),
ADC_DMASEL_OFF_gc = (0x00<<6),
ADC_DMASEL_CH01_gc = (0x01<<6),
ADC_DMASEL_CH012_gc = (0x02<<6),
ADC_DMASEL_CH0123_gc = (0x03<<6)
} |
|
enum | ADC_PRESCALER_enum {
ADC_PRESCALER_DIV4_gc = (0x00<<0),
ADC_PRESCALER_DIV8_gc = (0x01<<0),
ADC_PRESCALER_DIV16_gc = (0x02<<0),
ADC_PRESCALER_DIV32_gc = (0x03<<0),
ADC_PRESCALER_DIV64_gc = (0x04<<0),
ADC_PRESCALER_DIV128_gc = (0x05<<0),
ADC_PRESCALER_DIV256_gc = (0x06<<0),
ADC_PRESCALER_DIV512_gc = (0x07<<0),
ADC_PRESCALER_DIV4_gc = (0x00<<0),
ADC_PRESCALER_DIV8_gc = (0x01<<0),
ADC_PRESCALER_DIV16_gc = (0x02<<0),
ADC_PRESCALER_DIV32_gc = (0x03<<0),
ADC_PRESCALER_DIV64_gc = (0x04<<0),
ADC_PRESCALER_DIV128_gc = (0x05<<0),
ADC_PRESCALER_DIV256_gc = (0x06<<0),
ADC_PRESCALER_DIV512_gc = (0x07<<0),
ADC_PRESCALER_DIV4_gc = (0x00<<0),
ADC_PRESCALER_DIV8_gc = (0x01<<0),
ADC_PRESCALER_DIV16_gc = (0x02<<0),
ADC_PRESCALER_DIV32_gc = (0x03<<0),
ADC_PRESCALER_DIV64_gc = (0x04<<0),
ADC_PRESCALER_DIV128_gc = (0x05<<0),
ADC_PRESCALER_DIV256_gc = (0x06<<0),
ADC_PRESCALER_DIV512_gc = (0x07<<0),
ADC_PRESCALER_DIV4_gc = (0x00<<0),
ADC_PRESCALER_DIV8_gc = (0x01<<0),
ADC_PRESCALER_DIV16_gc = (0x02<<0),
ADC_PRESCALER_DIV32_gc = (0x03<<0),
ADC_PRESCALER_DIV64_gc = (0x04<<0),
ADC_PRESCALER_DIV128_gc = (0x05<<0),
ADC_PRESCALER_DIV256_gc = (0x06<<0),
ADC_PRESCALER_DIV512_gc = (0x07<<0),
ADC_PRESCALER_DIV4_gc = (0x00<<0),
ADC_PRESCALER_DIV8_gc = (0x01<<0),
ADC_PRESCALER_DIV16_gc = (0x02<<0),
ADC_PRESCALER_DIV32_gc = (0x03<<0),
ADC_PRESCALER_DIV64_gc = (0x04<<0),
ADC_PRESCALER_DIV128_gc = (0x05<<0),
ADC_PRESCALER_DIV256_gc = (0x06<<0),
ADC_PRESCALER_DIV512_gc = (0x07<<0),
ADC_PRESCALER_DIV4_gc = (0x00<<0),
ADC_PRESCALER_DIV8_gc = (0x01<<0),
ADC_PRESCALER_DIV16_gc = (0x02<<0),
ADC_PRESCALER_DIV32_gc = (0x03<<0),
ADC_PRESCALER_DIV64_gc = (0x04<<0),
ADC_PRESCALER_DIV128_gc = (0x05<<0),
ADC_PRESCALER_DIV256_gc = (0x06<<0),
ADC_PRESCALER_DIV512_gc = (0x07<<0),
ADC_PRESCALER_DIV4_gc = (0x00<<0),
ADC_PRESCALER_DIV8_gc = (0x01<<0),
ADC_PRESCALER_DIV16_gc = (0x02<<0),
ADC_PRESCALER_DIV32_gc = (0x03<<0),
ADC_PRESCALER_DIV64_gc = (0x04<<0),
ADC_PRESCALER_DIV128_gc = (0x05<<0),
ADC_PRESCALER_DIV256_gc = (0x06<<0),
ADC_PRESCALER_DIV512_gc = (0x07<<0),
ADC_PRESCALER_DIV4_gc = (0x00<<0),
ADC_PRESCALER_DIV8_gc = (0x01<<0),
ADC_PRESCALER_DIV16_gc = (0x02<<0),
ADC_PRESCALER_DIV32_gc = (0x03<<0),
ADC_PRESCALER_DIV64_gc = (0x04<<0),
ADC_PRESCALER_DIV128_gc = (0x05<<0),
ADC_PRESCALER_DIV256_gc = (0x06<<0),
ADC_PRESCALER_DIV512_gc = (0x07<<0),
ADC_PRESCALER_DIV4_gc = (0x00<<0),
ADC_PRESCALER_DIV8_gc = (0x01<<0),
ADC_PRESCALER_DIV16_gc = (0x02<<0),
ADC_PRESCALER_DIV32_gc = (0x03<<0),
ADC_PRESCALER_DIV64_gc = (0x04<<0),
ADC_PRESCALER_DIV128_gc = (0x05<<0),
ADC_PRESCALER_DIV256_gc = (0x06<<0),
ADC_PRESCALER_DIV512_gc = (0x07<<0),
ADC_PRESCALER_DIV4_gc = (0x00<<0),
ADC_PRESCALER_DIV8_gc = (0x01<<0),
ADC_PRESCALER_DIV16_gc = (0x02<<0),
ADC_PRESCALER_DIV32_gc = (0x03<<0),
ADC_PRESCALER_DIV64_gc = (0x04<<0),
ADC_PRESCALER_DIV128_gc = (0x05<<0),
ADC_PRESCALER_DIV256_gc = (0x06<<0),
ADC_PRESCALER_DIV512_gc = (0x07<<0),
ADC_PRESCALER_DIV4_gc = (0x00<<0),
ADC_PRESCALER_DIV8_gc = (0x01<<0),
ADC_PRESCALER_DIV16_gc = (0x02<<0),
ADC_PRESCALER_DIV32_gc = (0x03<<0),
ADC_PRESCALER_DIV64_gc = (0x04<<0),
ADC_PRESCALER_DIV128_gc = (0x05<<0),
ADC_PRESCALER_DIV256_gc = (0x06<<0),
ADC_PRESCALER_DIV512_gc = (0x07<<0),
ADC_PRESCALER_DIV4_gc = (0x00<<0),
ADC_PRESCALER_DIV8_gc = (0x01<<0),
ADC_PRESCALER_DIV16_gc = (0x02<<0),
ADC_PRESCALER_DIV32_gc = (0x03<<0),
ADC_PRESCALER_DIV64_gc = (0x04<<0),
ADC_PRESCALER_DIV128_gc = (0x05<<0),
ADC_PRESCALER_DIV256_gc = (0x06<<0),
ADC_PRESCALER_DIV512_gc = (0x07<<0),
ADC_PRESCALER_DIV4_gc = (0x00<<0),
ADC_PRESCALER_DIV8_gc = (0x01<<0),
ADC_PRESCALER_DIV16_gc = (0x02<<0),
ADC_PRESCALER_DIV32_gc = (0x03<<0),
ADC_PRESCALER_DIV64_gc = (0x04<<0),
ADC_PRESCALER_DIV128_gc = (0x05<<0),
ADC_PRESCALER_DIV256_gc = (0x06<<0),
ADC_PRESCALER_DIV512_gc = (0x07<<0),
ADC_PRESCALER_DIV4_gc = (0x00<<0),
ADC_PRESCALER_DIV8_gc = (0x01<<0),
ADC_PRESCALER_DIV16_gc = (0x02<<0),
ADC_PRESCALER_DIV32_gc = (0x03<<0),
ADC_PRESCALER_DIV64_gc = (0x04<<0),
ADC_PRESCALER_DIV128_gc = (0x05<<0),
ADC_PRESCALER_DIV256_gc = (0x06<<0),
ADC_PRESCALER_DIV512_gc = (0x07<<0),
ADC_PRESCALER_DIV4_gc = (0x00<<0),
ADC_PRESCALER_DIV8_gc = (0x01<<0),
ADC_PRESCALER_DIV16_gc = (0x02<<0),
ADC_PRESCALER_DIV32_gc = (0x03<<0),
ADC_PRESCALER_DIV64_gc = (0x04<<0),
ADC_PRESCALER_DIV128_gc = (0x05<<0),
ADC_PRESCALER_DIV256_gc = (0x06<<0),
ADC_PRESCALER_DIV512_gc = (0x07<<0)
} |
|
enum | DAC_CHSEL_enum {
DAC_CHSEL_SINGLE_gc = (0x00<<5),
DAC_CHSEL_DUAL_gc = (0x02<<5),
DAC_CHSEL_SINGLE_gc = (0x00<<5),
DAC_CHSEL_DUAL_gc = (0x02<<5),
DAC_CHSEL_SINGLE_gc = (0x00<<5),
DAC_CHSEL_DUAL_gc = (0x02<<5),
DAC_CHSEL_SINGLE_gc = (0x00<<5),
DAC_CHSEL_DUAL_gc = (0x02<<5),
DAC_CHSEL_SINGLE_gc = (0x00<<5),
DAC_CHSEL_DUAL_gc = (0x02<<5),
DAC_CHSEL_SINGLE_gc = (0x00<<5),
DAC_CHSEL_DUAL_gc = (0x02<<5),
DAC_CHSEL_SINGLE_gc = (0x00<<5),
DAC_CHSEL_DUAL_gc = (0x02<<5),
DAC_CHSEL_SINGLE_gc = (0x00<<5),
DAC_CHSEL_DUAL_gc = (0x02<<5),
DAC_CHSEL_SINGLE_gc = (0x00<<5),
DAC_CHSEL_DUAL_gc = (0x02<<5)
} |
|
enum | DAC_REFSEL_enum {
DAC_REFSEL_INT1V_gc = (0x00<<3),
DAC_REFSEL_AVCC_gc = (0x01<<3),
DAC_REFSEL_AREFA_gc = (0x02<<3),
DAC_REFSEL_AREFB_gc = (0x03<<3),
DAC_REFSEL_INT1V_gc = (0x00<<3),
DAC_REFSEL_AVCC_gc = (0x01<<3),
DAC_REFSEL_AREFA_gc = (0x02<<3),
DAC_REFSEL_AREFB_gc = (0x03<<3),
DAC_REFSEL_INT1V_gc = (0x00<<3),
DAC_REFSEL_AVCC_gc = (0x01<<3),
DAC_REFSEL_AREFA_gc = (0x02<<3),
DAC_REFSEL_AREFB_gc = (0x03<<3),
DAC_REFSEL_INT1V_gc = (0x00<<3),
DAC_REFSEL_AVCC_gc = (0x01<<3),
DAC_REFSEL_AREFA_gc = (0x02<<3),
DAC_REFSEL_AREFB_gc = (0x03<<3),
DAC_REFSEL_INT1V_gc = (0x00<<3),
DAC_REFSEL_AVCC_gc = (0x01<<3),
DAC_REFSEL_AREFA_gc = (0x02<<3),
DAC_REFSEL_AREFB_gc = (0x03<<3),
DAC_REFSEL_INT1V_gc = (0x00<<3),
DAC_REFSEL_AVCC_gc = (0x01<<3),
DAC_REFSEL_AREFA_gc = (0x02<<3),
DAC_REFSEL_AREFB_gc = (0x03<<3),
DAC_REFSEL_INT1V_gc = (0x00<<3),
DAC_REFSEL_AVCC_gc = (0x01<<3),
DAC_REFSEL_AREFA_gc = (0x02<<3),
DAC_REFSEL_AREFB_gc = (0x03<<3),
DAC_REFSEL_INT1V_gc = (0x00<<3),
DAC_REFSEL_AVCC_gc = (0x01<<3),
DAC_REFSEL_AREFA_gc = (0x02<<3),
DAC_REFSEL_AREFB_gc = (0x03<<3),
DAC_REFSEL_INT1V_gc = (0x00<<3),
DAC_REFSEL_AVCC_gc = (0x01<<3),
DAC_REFSEL_AREFA_gc = (0x02<<3),
DAC_REFSEL_AREFB_gc = (0x03<<3)
} |
|
enum | DAC_EVSEL_enum {
DAC_EVSEL_0_gc = (0x00<<0),
DAC_EVSEL_1_gc = (0x01<<0),
DAC_EVSEL_2_gc = (0x02<<0),
DAC_EVSEL_3_gc = (0x03<<0),
DAC_EVSEL_4_gc = (0x04<<0),
DAC_EVSEL_5_gc = (0x05<<0),
DAC_EVSEL_6_gc = (0x06<<0),
DAC_EVSEL_7_gc = (0x07<<0),
DAC_EVSEL_0_gc = (0x00<<0),
DAC_EVSEL_1_gc = (0x01<<0),
DAC_EVSEL_2_gc = (0x02<<0),
DAC_EVSEL_3_gc = (0x03<<0),
DAC_EVSEL_4_gc = (0x04<<0),
DAC_EVSEL_5_gc = (0x05<<0),
DAC_EVSEL_6_gc = (0x06<<0),
DAC_EVSEL_7_gc = (0x07<<0),
DAC_EVSEL_0_gc = (0x00<<0),
DAC_EVSEL_1_gc = (0x01<<0),
DAC_EVSEL_2_gc = (0x02<<0),
DAC_EVSEL_3_gc = (0x03<<0),
DAC_EVSEL_4_gc = (0x04<<0),
DAC_EVSEL_5_gc = (0x05<<0),
DAC_EVSEL_6_gc = (0x06<<0),
DAC_EVSEL_7_gc = (0x07<<0),
DAC_EVSEL_0_gc = (0x00<<0),
DAC_EVSEL_1_gc = (0x01<<0),
DAC_EVSEL_2_gc = (0x02<<0),
DAC_EVSEL_3_gc = (0x03<<0),
DAC_EVSEL_4_gc = (0x04<<0),
DAC_EVSEL_5_gc = (0x05<<0),
DAC_EVSEL_6_gc = (0x06<<0),
DAC_EVSEL_7_gc = (0x07<<0),
DAC_EVSEL_0_gc = (0x00<<0),
DAC_EVSEL_1_gc = (0x01<<0),
DAC_EVSEL_2_gc = (0x02<<0),
DAC_EVSEL_3_gc = (0x03<<0),
DAC_EVSEL_4_gc = (0x04<<0),
DAC_EVSEL_5_gc = (0x05<<0),
DAC_EVSEL_6_gc = (0x06<<0),
DAC_EVSEL_7_gc = (0x07<<0),
DAC_EVSEL_0_gc = (0x00<<0),
DAC_EVSEL_1_gc = (0x01<<0),
DAC_EVSEL_2_gc = (0x02<<0),
DAC_EVSEL_3_gc = (0x03<<0),
DAC_EVSEL_4_gc = (0x04<<0),
DAC_EVSEL_5_gc = (0x05<<0),
DAC_EVSEL_6_gc = (0x06<<0),
DAC_EVSEL_7_gc = (0x07<<0),
DAC_EVSEL_0_gc = (0x00<<0),
DAC_EVSEL_1_gc = (0x01<<0),
DAC_EVSEL_2_gc = (0x02<<0),
DAC_EVSEL_3_gc = (0x03<<0),
DAC_EVSEL_4_gc = (0x04<<0),
DAC_EVSEL_5_gc = (0x05<<0),
DAC_EVSEL_6_gc = (0x06<<0),
DAC_EVSEL_7_gc = (0x07<<0),
DAC_EVSEL_0_gc = (0x00<<0),
DAC_EVSEL_1_gc = (0x01<<0),
DAC_EVSEL_2_gc = (0x02<<0),
DAC_EVSEL_3_gc = (0x03<<0),
DAC_EVSEL_4_gc = (0x04<<0),
DAC_EVSEL_5_gc = (0x05<<0),
DAC_EVSEL_6_gc = (0x06<<0),
DAC_EVSEL_7_gc = (0x07<<0),
DAC_EVSEL_0_gc = (0x00<<0),
DAC_EVSEL_1_gc = (0x01<<0),
DAC_EVSEL_2_gc = (0x02<<0),
DAC_EVSEL_3_gc = (0x03<<0),
DAC_EVSEL_4_gc = (0x04<<0),
DAC_EVSEL_5_gc = (0x05<<0),
DAC_EVSEL_6_gc = (0x06<<0),
DAC_EVSEL_7_gc = (0x07<<0)
} |
|
enum | DAC_CONINTVAL_enum {
DAC_CONINTVAL_1CLK_gc = (0x00<<4),
DAC_CONINTVAL_2CLK_gc = (0x01<<4),
DAC_CONINTVAL_4CLK_gc = (0x02<<4),
DAC_CONINTVAL_8CLK_gc = (0x03<<4),
DAC_CONINTVAL_16CLK_gc = (0x04<<4),
DAC_CONINTVAL_32CLK_gc = (0x05<<4),
DAC_CONINTVAL_64CLK_gc = (0x06<<4),
DAC_CONINTVAL_128CLK_gc = (0x07<<4),
DAC_CONINTVAL_1CLK_gc = (0x00<<4),
DAC_CONINTVAL_2CLK_gc = (0x01<<4),
DAC_CONINTVAL_4CLK_gc = (0x02<<4),
DAC_CONINTVAL_8CLK_gc = (0x03<<4),
DAC_CONINTVAL_16CLK_gc = (0x04<<4),
DAC_CONINTVAL_32CLK_gc = (0x05<<4),
DAC_CONINTVAL_64CLK_gc = (0x06<<4),
DAC_CONINTVAL_128CLK_gc = (0x07<<4),
DAC_CONINTVAL_1CLK_gc = (0x00<<4),
DAC_CONINTVAL_2CLK_gc = (0x01<<4),
DAC_CONINTVAL_4CLK_gc = (0x02<<4),
DAC_CONINTVAL_8CLK_gc = (0x03<<4),
DAC_CONINTVAL_16CLK_gc = (0x04<<4),
DAC_CONINTVAL_32CLK_gc = (0x05<<4),
DAC_CONINTVAL_64CLK_gc = (0x06<<4),
DAC_CONINTVAL_128CLK_gc = (0x07<<4),
DAC_CONINTVAL_1CLK_gc = (0x00<<4),
DAC_CONINTVAL_2CLK_gc = (0x01<<4),
DAC_CONINTVAL_4CLK_gc = (0x02<<4),
DAC_CONINTVAL_8CLK_gc = (0x03<<4),
DAC_CONINTVAL_16CLK_gc = (0x04<<4),
DAC_CONINTVAL_32CLK_gc = (0x05<<4),
DAC_CONINTVAL_64CLK_gc = (0x06<<4),
DAC_CONINTVAL_128CLK_gc = (0x07<<4),
DAC_CONINTVAL_1CLK_gc = (0x00<<4),
DAC_CONINTVAL_2CLK_gc = (0x01<<4),
DAC_CONINTVAL_4CLK_gc = (0x02<<4),
DAC_CONINTVAL_8CLK_gc = (0x03<<4),
DAC_CONINTVAL_16CLK_gc = (0x04<<4),
DAC_CONINTVAL_32CLK_gc = (0x05<<4),
DAC_CONINTVAL_64CLK_gc = (0x06<<4),
DAC_CONINTVAL_128CLK_gc = (0x07<<4),
DAC_CONINTVAL_1CLK_gc = (0x00<<4),
DAC_CONINTVAL_2CLK_gc = (0x01<<4),
DAC_CONINTVAL_4CLK_gc = (0x02<<4),
DAC_CONINTVAL_8CLK_gc = (0x03<<4),
DAC_CONINTVAL_16CLK_gc = (0x04<<4),
DAC_CONINTVAL_32CLK_gc = (0x05<<4),
DAC_CONINTVAL_64CLK_gc = (0x06<<4),
DAC_CONINTVAL_128CLK_gc = (0x07<<4),
DAC_CONINTVAL_1CLK_gc = (0x00<<4),
DAC_CONINTVAL_2CLK_gc = (0x01<<4),
DAC_CONINTVAL_4CLK_gc = (0x02<<4),
DAC_CONINTVAL_8CLK_gc = (0x03<<4),
DAC_CONINTVAL_16CLK_gc = (0x04<<4),
DAC_CONINTVAL_32CLK_gc = (0x05<<4),
DAC_CONINTVAL_64CLK_gc = (0x06<<4),
DAC_CONINTVAL_128CLK_gc = (0x07<<4),
DAC_CONINTVAL_1CLK_gc = (0x00<<4),
DAC_CONINTVAL_2CLK_gc = (0x01<<4),
DAC_CONINTVAL_4CLK_gc = (0x02<<4),
DAC_CONINTVAL_8CLK_gc = (0x03<<4),
DAC_CONINTVAL_16CLK_gc = (0x04<<4),
DAC_CONINTVAL_32CLK_gc = (0x05<<4),
DAC_CONINTVAL_64CLK_gc = (0x06<<4),
DAC_CONINTVAL_128CLK_gc = (0x07<<4),
DAC_CONINTVAL_1CLK_gc = (0x00<<4),
DAC_CONINTVAL_2CLK_gc = (0x01<<4),
DAC_CONINTVAL_4CLK_gc = (0x02<<4),
DAC_CONINTVAL_8CLK_gc = (0x03<<4),
DAC_CONINTVAL_16CLK_gc = (0x04<<4),
DAC_CONINTVAL_32CLK_gc = (0x05<<4),
DAC_CONINTVAL_64CLK_gc = (0x06<<4),
DAC_CONINTVAL_128CLK_gc = (0x07<<4)
} |
|
enum | DAC_REFRESH_enum {
DAC_REFRESH_16CLK_gc = (0x00<<0),
DAC_REFRESH_32CLK_gc = (0x01<<0),
DAC_REFRESH_64CLK_gc = (0x02<<0),
DAC_REFRESH_128CLK_gc = (0x03<<0),
DAC_REFRESH_256CLK_gc = (0x04<<0),
DAC_REFRESH_512CLK_gc = (0x05<<0),
DAC_REFRESH_1024CLK_gc = (0x06<<0),
DAC_REFRESH_2048CLK_gc = (0x07<<0),
DAC_REFRESH_4086CLK_gc = (0x08<<0),
DAC_REFRESH_8192CLK_gc = (0x09<<0),
DAC_REFRESH_16384CLK_gc = (0x0A<<0),
DAC_REFRESH_32768CLK_gc = (0x0B<<0),
DAC_REFRESH_65536CLK_gc = (0x0C<<0),
DAC_REFRESH_OFF_gc = (0x0F<<0),
DAC_REFRESH_16CLK_gc = (0x00<<0),
DAC_REFRESH_32CLK_gc = (0x01<<0),
DAC_REFRESH_64CLK_gc = (0x02<<0),
DAC_REFRESH_128CLK_gc = (0x03<<0),
DAC_REFRESH_256CLK_gc = (0x04<<0),
DAC_REFRESH_512CLK_gc = (0x05<<0),
DAC_REFRESH_1024CLK_gc = (0x06<<0),
DAC_REFRESH_2048CLK_gc = (0x07<<0),
DAC_REFRESH_4086CLK_gc = (0x08<<0),
DAC_REFRESH_8192CLK_gc = (0x09<<0),
DAC_REFRESH_16384CLK_gc = (0x0A<<0),
DAC_REFRESH_32768CLK_gc = (0x0B<<0),
DAC_REFRESH_65536CLK_gc = (0x0C<<0),
DAC_REFRESH_OFF_gc = (0x0F<<0),
DAC_REFRESH_16CLK_gc = (0x00<<0),
DAC_REFRESH_32CLK_gc = (0x01<<0),
DAC_REFRESH_64CLK_gc = (0x02<<0),
DAC_REFRESH_128CLK_gc = (0x03<<0),
DAC_REFRESH_256CLK_gc = (0x04<<0),
DAC_REFRESH_512CLK_gc = (0x05<<0),
DAC_REFRESH_1024CLK_gc = (0x06<<0),
DAC_REFRESH_2048CLK_gc = (0x07<<0),
DAC_REFRESH_4086CLK_gc = (0x08<<0),
DAC_REFRESH_8192CLK_gc = (0x09<<0),
DAC_REFRESH_16384CLK_gc = (0x0A<<0),
DAC_REFRESH_32768CLK_gc = (0x0B<<0),
DAC_REFRESH_65536CLK_gc = (0x0C<<0),
DAC_REFRESH_OFF_gc = (0x0F<<0),
DAC_REFRESH_16CLK_gc = (0x00<<0),
DAC_REFRESH_32CLK_gc = (0x01<<0),
DAC_REFRESH_64CLK_gc = (0x02<<0),
DAC_REFRESH_128CLK_gc = (0x03<<0),
DAC_REFRESH_256CLK_gc = (0x04<<0),
DAC_REFRESH_512CLK_gc = (0x05<<0),
DAC_REFRESH_1024CLK_gc = (0x06<<0),
DAC_REFRESH_2048CLK_gc = (0x07<<0),
DAC_REFRESH_4086CLK_gc = (0x08<<0),
DAC_REFRESH_8192CLK_gc = (0x09<<0),
DAC_REFRESH_16384CLK_gc = (0x0A<<0),
DAC_REFRESH_32768CLK_gc = (0x0B<<0),
DAC_REFRESH_65536CLK_gc = (0x0C<<0),
DAC_REFRESH_OFF_gc = (0x0F<<0),
DAC_REFRESH_16CLK_gc = (0x00<<0),
DAC_REFRESH_32CLK_gc = (0x01<<0),
DAC_REFRESH_64CLK_gc = (0x02<<0),
DAC_REFRESH_128CLK_gc = (0x03<<0),
DAC_REFRESH_256CLK_gc = (0x04<<0),
DAC_REFRESH_512CLK_gc = (0x05<<0),
DAC_REFRESH_1024CLK_gc = (0x06<<0),
DAC_REFRESH_2048CLK_gc = (0x07<<0),
DAC_REFRESH_4086CLK_gc = (0x08<<0),
DAC_REFRESH_8192CLK_gc = (0x09<<0),
DAC_REFRESH_16384CLK_gc = (0x0A<<0),
DAC_REFRESH_32768CLK_gc = (0x0B<<0),
DAC_REFRESH_65536CLK_gc = (0x0C<<0),
DAC_REFRESH_OFF_gc = (0x0F<<0),
DAC_REFRESH_16CLK_gc = (0x00<<0),
DAC_REFRESH_32CLK_gc = (0x01<<0),
DAC_REFRESH_64CLK_gc = (0x02<<0),
DAC_REFRESH_128CLK_gc = (0x03<<0),
DAC_REFRESH_256CLK_gc = (0x04<<0),
DAC_REFRESH_512CLK_gc = (0x05<<0),
DAC_REFRESH_1024CLK_gc = (0x06<<0),
DAC_REFRESH_2048CLK_gc = (0x07<<0),
DAC_REFRESH_4086CLK_gc = (0x08<<0),
DAC_REFRESH_8192CLK_gc = (0x09<<0),
DAC_REFRESH_16384CLK_gc = (0x0A<<0),
DAC_REFRESH_32768CLK_gc = (0x0B<<0),
DAC_REFRESH_65536CLK_gc = (0x0C<<0),
DAC_REFRESH_OFF_gc = (0x0F<<0),
DAC_REFRESH_16CLK_gc = (0x00<<0),
DAC_REFRESH_32CLK_gc = (0x01<<0),
DAC_REFRESH_64CLK_gc = (0x02<<0),
DAC_REFRESH_128CLK_gc = (0x03<<0),
DAC_REFRESH_256CLK_gc = (0x04<<0),
DAC_REFRESH_512CLK_gc = (0x05<<0),
DAC_REFRESH_1024CLK_gc = (0x06<<0),
DAC_REFRESH_2048CLK_gc = (0x07<<0),
DAC_REFRESH_4086CLK_gc = (0x08<<0),
DAC_REFRESH_8192CLK_gc = (0x09<<0),
DAC_REFRESH_16384CLK_gc = (0x0A<<0),
DAC_REFRESH_32768CLK_gc = (0x0B<<0),
DAC_REFRESH_65536CLK_gc = (0x0C<<0),
DAC_REFRESH_OFF_gc = (0x0F<<0),
DAC_REFRESH_16CLK_gc = (0x00<<0),
DAC_REFRESH_32CLK_gc = (0x01<<0),
DAC_REFRESH_64CLK_gc = (0x02<<0),
DAC_REFRESH_128CLK_gc = (0x03<<0),
DAC_REFRESH_256CLK_gc = (0x04<<0),
DAC_REFRESH_512CLK_gc = (0x05<<0),
DAC_REFRESH_1024CLK_gc = (0x06<<0),
DAC_REFRESH_2048CLK_gc = (0x07<<0),
DAC_REFRESH_4086CLK_gc = (0x08<<0),
DAC_REFRESH_8192CLK_gc = (0x09<<0),
DAC_REFRESH_16384CLK_gc = (0x0A<<0),
DAC_REFRESH_32768CLK_gc = (0x0B<<0),
DAC_REFRESH_65536CLK_gc = (0x0C<<0),
DAC_REFRESH_OFF_gc = (0x0F<<0),
DAC_REFRESH_16CLK_gc = (0x00<<0),
DAC_REFRESH_32CLK_gc = (0x01<<0),
DAC_REFRESH_64CLK_gc = (0x02<<0),
DAC_REFRESH_128CLK_gc = (0x03<<0),
DAC_REFRESH_256CLK_gc = (0x04<<0),
DAC_REFRESH_512CLK_gc = (0x05<<0),
DAC_REFRESH_1024CLK_gc = (0x06<<0),
DAC_REFRESH_2048CLK_gc = (0x07<<0),
DAC_REFRESH_4086CLK_gc = (0x08<<0),
DAC_REFRESH_8192CLK_gc = (0x09<<0),
DAC_REFRESH_16384CLK_gc = (0x0A<<0),
DAC_REFRESH_32768CLK_gc = (0x0B<<0),
DAC_REFRESH_65536CLK_gc = (0x0C<<0),
DAC_REFRESH_OFF_gc = (0x0F<<0)
} |
|
enum | RTC_PRESCALER_enum {
RTC_PRESCALER_OFF_gc = (0x00<<0),
RTC_PRESCALER_DIV1_gc = (0x01<<0),
RTC_PRESCALER_DIV2_gc = (0x02<<0),
RTC_PRESCALER_DIV8_gc = (0x03<<0),
RTC_PRESCALER_DIV16_gc = (0x04<<0),
RTC_PRESCALER_DIV64_gc = (0x05<<0),
RTC_PRESCALER_DIV256_gc = (0x06<<0),
RTC_PRESCALER_DIV1024_gc = (0x07<<0),
RTC_PRESCALER_OFF_gc = (0x00<<0),
RTC_PRESCALER_DIV1_gc = (0x01<<0),
RTC_PRESCALER_DIV2_gc = (0x02<<0),
RTC_PRESCALER_DIV8_gc = (0x03<<0),
RTC_PRESCALER_DIV16_gc = (0x04<<0),
RTC_PRESCALER_DIV64_gc = (0x05<<0),
RTC_PRESCALER_DIV256_gc = (0x06<<0),
RTC_PRESCALER_DIV1024_gc = (0x07<<0),
RTC_PRESCALER_OFF_gc = (0x00<<0),
RTC_PRESCALER_DIV1_gc = (0x01<<0),
RTC_PRESCALER_DIV2_gc = (0x02<<0),
RTC_PRESCALER_DIV8_gc = (0x03<<0),
RTC_PRESCALER_DIV16_gc = (0x04<<0),
RTC_PRESCALER_DIV64_gc = (0x05<<0),
RTC_PRESCALER_DIV256_gc = (0x06<<0),
RTC_PRESCALER_DIV1024_gc = (0x07<<0),
RTC_PRESCALER_OFF_gc = (0x00<<0),
RTC_PRESCALER_DIV1_gc = (0x01<<0),
RTC_PRESCALER_DIV2_gc = (0x02<<0),
RTC_PRESCALER_DIV8_gc = (0x03<<0),
RTC_PRESCALER_DIV16_gc = (0x04<<0),
RTC_PRESCALER_DIV64_gc = (0x05<<0),
RTC_PRESCALER_DIV256_gc = (0x06<<0),
RTC_PRESCALER_DIV1024_gc = (0x07<<0),
RTC_PRESCALER_OFF_gc = (0x00<<0),
RTC_PRESCALER_DIV1_gc = (0x01<<0),
RTC_PRESCALER_DIV2_gc = (0x02<<0),
RTC_PRESCALER_DIV8_gc = (0x03<<0),
RTC_PRESCALER_DIV16_gc = (0x04<<0),
RTC_PRESCALER_DIV64_gc = (0x05<<0),
RTC_PRESCALER_DIV256_gc = (0x06<<0),
RTC_PRESCALER_DIV1024_gc = (0x07<<0),
RTC_PRESCALER_OFF_gc = (0x00<<0),
RTC_PRESCALER_DIV1_gc = (0x01<<0),
RTC_PRESCALER_DIV2_gc = (0x02<<0),
RTC_PRESCALER_DIV8_gc = (0x03<<0),
RTC_PRESCALER_DIV16_gc = (0x04<<0),
RTC_PRESCALER_DIV64_gc = (0x05<<0),
RTC_PRESCALER_DIV256_gc = (0x06<<0),
RTC_PRESCALER_DIV1024_gc = (0x07<<0),
RTC_PRESCALER_OFF_gc = (0x00<<0),
RTC_PRESCALER_DIV1_gc = (0x01<<0),
RTC_PRESCALER_DIV2_gc = (0x02<<0),
RTC_PRESCALER_DIV8_gc = (0x03<<0),
RTC_PRESCALER_DIV16_gc = (0x04<<0),
RTC_PRESCALER_DIV64_gc = (0x05<<0),
RTC_PRESCALER_DIV256_gc = (0x06<<0),
RTC_PRESCALER_DIV1024_gc = (0x07<<0),
RTC_PRESCALER_OFF_gc = (0x00<<0),
RTC_PRESCALER_DIV1_gc = (0x01<<0),
RTC_PRESCALER_DIV2_gc = (0x02<<0),
RTC_PRESCALER_DIV8_gc = (0x03<<0),
RTC_PRESCALER_DIV16_gc = (0x04<<0),
RTC_PRESCALER_DIV64_gc = (0x05<<0),
RTC_PRESCALER_DIV256_gc = (0x06<<0),
RTC_PRESCALER_DIV1024_gc = (0x07<<0),
RTC_PRESCALER_OFF_gc = (0x00<<0),
RTC_PRESCALER_DIV1_gc = (0x01<<0),
RTC_PRESCALER_DIV2_gc = (0x02<<0),
RTC_PRESCALER_DIV8_gc = (0x03<<0),
RTC_PRESCALER_DIV16_gc = (0x04<<0),
RTC_PRESCALER_DIV64_gc = (0x05<<0),
RTC_PRESCALER_DIV256_gc = (0x06<<0),
RTC_PRESCALER_DIV1024_gc = (0x07<<0),
RTC_PRESCALER_OFF_gc = (0x00<<0),
RTC_PRESCALER_DIV1_gc = (0x01<<0),
RTC_PRESCALER_DIV2_gc = (0x02<<0),
RTC_PRESCALER_DIV8_gc = (0x03<<0),
RTC_PRESCALER_DIV16_gc = (0x04<<0),
RTC_PRESCALER_DIV64_gc = (0x05<<0),
RTC_PRESCALER_DIV256_gc = (0x06<<0),
RTC_PRESCALER_DIV1024_gc = (0x07<<0),
RTC_PRESCALER_OFF_gc = (0x00<<0),
RTC_PRESCALER_DIV1_gc = (0x01<<0),
RTC_PRESCALER_DIV2_gc = (0x02<<0),
RTC_PRESCALER_DIV8_gc = (0x03<<0),
RTC_PRESCALER_DIV16_gc = (0x04<<0),
RTC_PRESCALER_DIV64_gc = (0x05<<0),
RTC_PRESCALER_DIV256_gc = (0x06<<0),
RTC_PRESCALER_DIV1024_gc = (0x07<<0),
RTC_PRESCALER_OFF_gc = (0x00<<0),
RTC_PRESCALER_DIV1_gc = (0x01<<0),
RTC_PRESCALER_DIV2_gc = (0x02<<0),
RTC_PRESCALER_DIV8_gc = (0x03<<0),
RTC_PRESCALER_DIV16_gc = (0x04<<0),
RTC_PRESCALER_DIV64_gc = (0x05<<0),
RTC_PRESCALER_DIV256_gc = (0x06<<0),
RTC_PRESCALER_DIV1024_gc = (0x07<<0),
RTC_PRESCALER_OFF_gc = (0x00<<0),
RTC_PRESCALER_DIV1_gc = (0x01<<0),
RTC_PRESCALER_DIV2_gc = (0x02<<0),
RTC_PRESCALER_DIV8_gc = (0x03<<0),
RTC_PRESCALER_DIV16_gc = (0x04<<0),
RTC_PRESCALER_DIV64_gc = (0x05<<0),
RTC_PRESCALER_DIV256_gc = (0x06<<0),
RTC_PRESCALER_DIV1024_gc = (0x07<<0),
RTC_PRESCALER_OFF_gc = (0x00<<0),
RTC_PRESCALER_DIV1_gc = (0x01<<0),
RTC_PRESCALER_DIV2_gc = (0x02<<0),
RTC_PRESCALER_DIV8_gc = (0x03<<0),
RTC_PRESCALER_DIV16_gc = (0x04<<0),
RTC_PRESCALER_DIV64_gc = (0x05<<0),
RTC_PRESCALER_DIV256_gc = (0x06<<0),
RTC_PRESCALER_DIV1024_gc = (0x07<<0)
} |
|
enum | RTC_COMPINTLVL_enum {
RTC_COMPINTLVL_OFF_gc = (0x00<<2),
RTC_COMPINTLVL_LO_gc = (0x01<<2),
RTC_COMPINTLVL_MED_gc = (0x02<<2),
RTC_COMPINTLVL_HI_gc = (0x03<<2),
RTC_COMPINTLVL_OFF_gc = (0x00<<2),
RTC_COMPINTLVL_LO_gc = (0x01<<2),
RTC_COMPINTLVL_MED_gc = (0x02<<2),
RTC_COMPINTLVL_HI_gc = (0x03<<2),
RTC_COMPINTLVL_OFF_gc = (0x00<<2),
RTC_COMPINTLVL_LO_gc = (0x01<<2),
RTC_COMPINTLVL_MED_gc = (0x02<<2),
RTC_COMPINTLVL_HI_gc = (0x03<<2),
RTC_COMPINTLVL_OFF_gc = (0x00<<2),
RTC_COMPINTLVL_LO_gc = (0x01<<2),
RTC_COMPINTLVL_MED_gc = (0x02<<2),
RTC_COMPINTLVL_HI_gc = (0x03<<2),
RTC_COMPINTLVL_OFF_gc = (0x00<<2),
RTC_COMPINTLVL_LO_gc = (0x01<<2),
RTC_COMPINTLVL_MED_gc = (0x02<<2),
RTC_COMPINTLVL_HI_gc = (0x03<<2),
RTC_COMPINTLVL_OFF_gc = (0x00<<2),
RTC_COMPINTLVL_LO_gc = (0x01<<2),
RTC_COMPINTLVL_MED_gc = (0x02<<2),
RTC_COMPINTLVL_HI_gc = (0x03<<2),
RTC_COMPINTLVL_OFF_gc = (0x00<<2),
RTC_COMPINTLVL_LO_gc = (0x01<<2),
RTC_COMPINTLVL_MED_gc = (0x02<<2),
RTC_COMPINTLVL_HI_gc = (0x03<<2),
RTC_COMPINTLVL_OFF_gc = (0x00<<2),
RTC_COMPINTLVL_LO_gc = (0x01<<2),
RTC_COMPINTLVL_MED_gc = (0x02<<2),
RTC_COMPINTLVL_HI_gc = (0x03<<2),
RTC_COMPINTLVL_OFF_gc = (0x00<<2),
RTC_COMPINTLVL_LO_gc = (0x01<<2),
RTC_COMPINTLVL_MED_gc = (0x02<<2),
RTC_COMPINTLVL_HI_gc = (0x03<<2),
RTC_COMPINTLVL_OFF_gc = (0x00<<2),
RTC_COMPINTLVL_LO_gc = (0x01<<2),
RTC_COMPINTLVL_MED_gc = (0x02<<2),
RTC_COMPINTLVL_HI_gc = (0x03<<2),
RTC_COMPINTLVL_OFF_gc = (0x00<<2),
RTC_COMPINTLVL_LO_gc = (0x01<<2),
RTC_COMPINTLVL_MED_gc = (0x02<<2),
RTC_COMPINTLVL_HI_gc = (0x03<<2),
RTC_COMPINTLVL_OFF_gc = (0x00<<2),
RTC_COMPINTLVL_LO_gc = (0x01<<2),
RTC_COMPINTLVL_MED_gc = (0x02<<2),
RTC_COMPINTLVL_HI_gc = (0x03<<2),
RTC_COMPINTLVL_OFF_gc = (0x00<<2),
RTC_COMPINTLVL_LO_gc = (0x01<<2),
RTC_COMPINTLVL_MED_gc = (0x02<<2),
RTC_COMPINTLVL_HI_gc = (0x03<<2),
RTC_COMPINTLVL_OFF_gc = (0x00<<2),
RTC_COMPINTLVL_LO_gc = (0x01<<2),
RTC_COMPINTLVL_MED_gc = (0x02<<2),
RTC_COMPINTLVL_HI_gc = (0x03<<2)
} |
|
enum | RTC_OVFINTLVL_enum {
RTC_OVFINTLVL_OFF_gc = (0x00<<0),
RTC_OVFINTLVL_LO_gc = (0x01<<0),
RTC_OVFINTLVL_MED_gc = (0x02<<0),
RTC_OVFINTLVL_HI_gc = (0x03<<0),
RTC_OVFINTLVL_OFF_gc = (0x00<<0),
RTC_OVFINTLVL_LO_gc = (0x01<<0),
RTC_OVFINTLVL_MED_gc = (0x02<<0),
RTC_OVFINTLVL_HI_gc = (0x03<<0),
RTC_OVFINTLVL_OFF_gc = (0x00<<0),
RTC_OVFINTLVL_LO_gc = (0x01<<0),
RTC_OVFINTLVL_MED_gc = (0x02<<0),
RTC_OVFINTLVL_HI_gc = (0x03<<0),
RTC_OVFINTLVL_OFF_gc = (0x00<<0),
RTC_OVFINTLVL_LO_gc = (0x01<<0),
RTC_OVFINTLVL_MED_gc = (0x02<<0),
RTC_OVFINTLVL_HI_gc = (0x03<<0),
RTC_OVFINTLVL_OFF_gc = (0x00<<0),
RTC_OVFINTLVL_LO_gc = (0x01<<0),
RTC_OVFINTLVL_MED_gc = (0x02<<0),
RTC_OVFINTLVL_HI_gc = (0x03<<0),
RTC_OVFINTLVL_OFF_gc = (0x00<<0),
RTC_OVFINTLVL_LO_gc = (0x01<<0),
RTC_OVFINTLVL_MED_gc = (0x02<<0),
RTC_OVFINTLVL_HI_gc = (0x03<<0),
RTC_OVFINTLVL_OFF_gc = (0x00<<0),
RTC_OVFINTLVL_LO_gc = (0x01<<0),
RTC_OVFINTLVL_MED_gc = (0x02<<0),
RTC_OVFINTLVL_HI_gc = (0x03<<0),
RTC_OVFINTLVL_OFF_gc = (0x00<<0),
RTC_OVFINTLVL_LO_gc = (0x01<<0),
RTC_OVFINTLVL_MED_gc = (0x02<<0),
RTC_OVFINTLVL_HI_gc = (0x03<<0),
RTC_OVFINTLVL_OFF_gc = (0x00<<0),
RTC_OVFINTLVL_LO_gc = (0x01<<0),
RTC_OVFINTLVL_MED_gc = (0x02<<0),
RTC_OVFINTLVL_HI_gc = (0x03<<0),
RTC_OVFINTLVL_OFF_gc = (0x00<<0),
RTC_OVFINTLVL_LO_gc = (0x01<<0),
RTC_OVFINTLVL_MED_gc = (0x02<<0),
RTC_OVFINTLVL_HI_gc = (0x03<<0),
RTC_OVFINTLVL_OFF_gc = (0x00<<0),
RTC_OVFINTLVL_LO_gc = (0x01<<0),
RTC_OVFINTLVL_MED_gc = (0x02<<0),
RTC_OVFINTLVL_HI_gc = (0x03<<0),
RTC_OVFINTLVL_OFF_gc = (0x00<<0),
RTC_OVFINTLVL_LO_gc = (0x01<<0),
RTC_OVFINTLVL_MED_gc = (0x02<<0),
RTC_OVFINTLVL_HI_gc = (0x03<<0),
RTC_OVFINTLVL_OFF_gc = (0x00<<0),
RTC_OVFINTLVL_LO_gc = (0x01<<0),
RTC_OVFINTLVL_MED_gc = (0x02<<0),
RTC_OVFINTLVL_HI_gc = (0x03<<0),
RTC_OVFINTLVL_OFF_gc = (0x00<<0),
RTC_OVFINTLVL_LO_gc = (0x01<<0),
RTC_OVFINTLVL_MED_gc = (0x02<<0),
RTC_OVFINTLVL_HI_gc = (0x03<<0)
} |
|
enum | EBI_CS_ASPACE_enum {
EBI_CS_ASPACE_256B_gc = (0x00<<2),
EBI_CS_ASPACE_512B_gc = (0x01<<2),
EBI_CS_ASPACE_1KB_gc = (0x02<<2),
EBI_CS_ASPACE_2KB_gc = (0x03<<2),
EBI_CS_ASPACE_4KB_gc = (0x04<<2),
EBI_CS_ASPACE_8KB_gc = (0x05<<2),
EBI_CS_ASPACE_16KB_gc = (0x06<<2),
EBI_CS_ASPACE_32KB_gc = (0x07<<2),
EBI_CS_ASPACE_64KB_gc = (0x08<<2),
EBI_CS_ASPACE_128KB_gc = (0x09<<2),
EBI_CS_ASPACE_256KB_gc = (0x0A<<2),
EBI_CS_ASPACE_512KB_gc = (0x0B<<2),
EBI_CS_ASPACE_1MB_gc = (0x0C<<2),
EBI_CS_ASPACE_2MB_gc = (0x0D<<2),
EBI_CS_ASPACE_4MB_gc = (0x0E<<2),
EBI_CS_ASPACE_8MB_gc = (0x0F<<2),
EBI_CS_ASPACE_16M_gc = (0x10<<2),
EBI_CS_ASPACE_256B_gc = (0x00<<2),
EBI_CS_ASPACE_512B_gc = (0x01<<2),
EBI_CS_ASPACE_1KB_gc = (0x02<<2),
EBI_CS_ASPACE_2KB_gc = (0x03<<2),
EBI_CS_ASPACE_4KB_gc = (0x04<<2),
EBI_CS_ASPACE_8KB_gc = (0x05<<2),
EBI_CS_ASPACE_16KB_gc = (0x06<<2),
EBI_CS_ASPACE_32KB_gc = (0x07<<2),
EBI_CS_ASPACE_64KB_gc = (0x08<<2),
EBI_CS_ASPACE_128KB_gc = (0x09<<2),
EBI_CS_ASPACE_256KB_gc = (0x0A<<2),
EBI_CS_ASPACE_512KB_gc = (0x0B<<2),
EBI_CS_ASPACE_1MB_gc = (0x0C<<2),
EBI_CS_ASPACE_2MB_gc = (0x0D<<2),
EBI_CS_ASPACE_4MB_gc = (0x0E<<2),
EBI_CS_ASPACE_8MB_gc = (0x0F<<2),
EBI_CS_ASPACE_16M_gc = (0x10<<2),
EBI_CS_ASPACE_256B_gc = (0x00<<2),
EBI_CS_ASPACE_512B_gc = (0x01<<2),
EBI_CS_ASPACE_1KB_gc = (0x02<<2),
EBI_CS_ASPACE_2KB_gc = (0x03<<2),
EBI_CS_ASPACE_4KB_gc = (0x04<<2),
EBI_CS_ASPACE_8KB_gc = (0x05<<2),
EBI_CS_ASPACE_16KB_gc = (0x06<<2),
EBI_CS_ASPACE_32KB_gc = (0x07<<2),
EBI_CS_ASPACE_64KB_gc = (0x08<<2),
EBI_CS_ASPACE_128KB_gc = (0x09<<2),
EBI_CS_ASPACE_256KB_gc = (0x0A<<2),
EBI_CS_ASPACE_512KB_gc = (0x0B<<2),
EBI_CS_ASPACE_1MB_gc = (0x0C<<2),
EBI_CS_ASPACE_2MB_gc = (0x0D<<2),
EBI_CS_ASPACE_4MB_gc = (0x0E<<2),
EBI_CS_ASPACE_8MB_gc = (0x0F<<2),
EBI_CS_ASPACE_16M_gc = (0x10<<2),
EBI_CS_ASPACE_256B_gc = (0x00<<2),
EBI_CS_ASPACE_512B_gc = (0x01<<2),
EBI_CS_ASPACE_1KB_gc = (0x02<<2),
EBI_CS_ASPACE_2KB_gc = (0x03<<2),
EBI_CS_ASPACE_4KB_gc = (0x04<<2),
EBI_CS_ASPACE_8KB_gc = (0x05<<2),
EBI_CS_ASPACE_16KB_gc = (0x06<<2),
EBI_CS_ASPACE_32KB_gc = (0x07<<2),
EBI_CS_ASPACE_64KB_gc = (0x08<<2),
EBI_CS_ASPACE_128KB_gc = (0x09<<2),
EBI_CS_ASPACE_256KB_gc = (0x0A<<2),
EBI_CS_ASPACE_512KB_gc = (0x0B<<2),
EBI_CS_ASPACE_1MB_gc = (0x0C<<2),
EBI_CS_ASPACE_2MB_gc = (0x0D<<2),
EBI_CS_ASPACE_4MB_gc = (0x0E<<2),
EBI_CS_ASPACE_8MB_gc = (0x0F<<2),
EBI_CS_ASPACE_16M_gc = (0x10<<2),
EBI_CS_ASPACE_256B_gc = (0x00<<2),
EBI_CS_ASPACE_512B_gc = (0x01<<2),
EBI_CS_ASPACE_1KB_gc = (0x02<<2),
EBI_CS_ASPACE_2KB_gc = (0x03<<2),
EBI_CS_ASPACE_4KB_gc = (0x04<<2),
EBI_CS_ASPACE_8KB_gc = (0x05<<2),
EBI_CS_ASPACE_16KB_gc = (0x06<<2),
EBI_CS_ASPACE_32KB_gc = (0x07<<2),
EBI_CS_ASPACE_64KB_gc = (0x08<<2),
EBI_CS_ASPACE_128KB_gc = (0x09<<2),
EBI_CS_ASPACE_256KB_gc = (0x0A<<2),
EBI_CS_ASPACE_512KB_gc = (0x0B<<2),
EBI_CS_ASPACE_1MB_gc = (0x0C<<2),
EBI_CS_ASPACE_2MB_gc = (0x0D<<2),
EBI_CS_ASPACE_4MB_gc = (0x0E<<2),
EBI_CS_ASPACE_8MB_gc = (0x0F<<2),
EBI_CS_ASPACE_16M_gc = (0x10<<2),
EBI_CS_ASPACE_256B_gc = (0x00<<2),
EBI_CS_ASPACE_512B_gc = (0x01<<2),
EBI_CS_ASPACE_1KB_gc = (0x02<<2),
EBI_CS_ASPACE_2KB_gc = (0x03<<2),
EBI_CS_ASPACE_4KB_gc = (0x04<<2),
EBI_CS_ASPACE_8KB_gc = (0x05<<2),
EBI_CS_ASPACE_16KB_gc = (0x06<<2),
EBI_CS_ASPACE_32KB_gc = (0x07<<2),
EBI_CS_ASPACE_64KB_gc = (0x08<<2),
EBI_CS_ASPACE_128KB_gc = (0x09<<2),
EBI_CS_ASPACE_256KB_gc = (0x0A<<2),
EBI_CS_ASPACE_512KB_gc = (0x0B<<2),
EBI_CS_ASPACE_1MB_gc = (0x0C<<2),
EBI_CS_ASPACE_2MB_gc = (0x0D<<2),
EBI_CS_ASPACE_4MB_gc = (0x0E<<2),
EBI_CS_ASPACE_8MB_gc = (0x0F<<2),
EBI_CS_ASPACE_16M_gc = (0x10<<2),
EBI_CS_ASPACE_256B_gc = (0x00<<2),
EBI_CS_ASPACE_512B_gc = (0x01<<2),
EBI_CS_ASPACE_1KB_gc = (0x02<<2),
EBI_CS_ASPACE_2KB_gc = (0x03<<2),
EBI_CS_ASPACE_4KB_gc = (0x04<<2),
EBI_CS_ASPACE_8KB_gc = (0x05<<2),
EBI_CS_ASPACE_16KB_gc = (0x06<<2),
EBI_CS_ASPACE_32KB_gc = (0x07<<2),
EBI_CS_ASPACE_64KB_gc = (0x08<<2),
EBI_CS_ASPACE_128KB_gc = (0x09<<2),
EBI_CS_ASPACE_256KB_gc = (0x0A<<2),
EBI_CS_ASPACE_512KB_gc = (0x0B<<2),
EBI_CS_ASPACE_1MB_gc = (0x0C<<2),
EBI_CS_ASPACE_2MB_gc = (0x0D<<2),
EBI_CS_ASPACE_4MB_gc = (0x0E<<2),
EBI_CS_ASPACE_8MB_gc = (0x0F<<2),
EBI_CS_ASPACE_16M_gc = (0x10<<2),
EBI_CS_ASPACE_256B_gc = (0x00<<2),
EBI_CS_ASPACE_512B_gc = (0x01<<2),
EBI_CS_ASPACE_1KB_gc = (0x02<<2),
EBI_CS_ASPACE_2KB_gc = (0x03<<2),
EBI_CS_ASPACE_4KB_gc = (0x04<<2),
EBI_CS_ASPACE_8KB_gc = (0x05<<2),
EBI_CS_ASPACE_16KB_gc = (0x06<<2),
EBI_CS_ASPACE_32KB_gc = (0x07<<2),
EBI_CS_ASPACE_64KB_gc = (0x08<<2),
EBI_CS_ASPACE_128KB_gc = (0x09<<2),
EBI_CS_ASPACE_256KB_gc = (0x0A<<2),
EBI_CS_ASPACE_512KB_gc = (0x0B<<2),
EBI_CS_ASPACE_1MB_gc = (0x0C<<2),
EBI_CS_ASPACE_2MB_gc = (0x0D<<2),
EBI_CS_ASPACE_4MB_gc = (0x0E<<2),
EBI_CS_ASPACE_8MB_gc = (0x0F<<2),
EBI_CS_ASPACE_16M_gc = (0x10<<2),
EBI_CS_ASPACE_256B_gc = (0x00<<2),
EBI_CS_ASPACE_512B_gc = (0x01<<2),
EBI_CS_ASPACE_1KB_gc = (0x02<<2),
EBI_CS_ASPACE_2KB_gc = (0x03<<2),
EBI_CS_ASPACE_4KB_gc = (0x04<<2),
EBI_CS_ASPACE_8KB_gc = (0x05<<2),
EBI_CS_ASPACE_16KB_gc = (0x06<<2),
EBI_CS_ASPACE_32KB_gc = (0x07<<2),
EBI_CS_ASPACE_64KB_gc = (0x08<<2),
EBI_CS_ASPACE_128KB_gc = (0x09<<2),
EBI_CS_ASPACE_256KB_gc = (0x0A<<2),
EBI_CS_ASPACE_512KB_gc = (0x0B<<2),
EBI_CS_ASPACE_1MB_gc = (0x0C<<2),
EBI_CS_ASPACE_2MB_gc = (0x0D<<2),
EBI_CS_ASPACE_4MB_gc = (0x0E<<2),
EBI_CS_ASPACE_8MB_gc = (0x0F<<2),
EBI_CS_ASPACE_16M_gc = (0x10<<2),
EBI_CS_ASPACE_256B_gc = (0x00<<2),
EBI_CS_ASPACE_512B_gc = (0x01<<2),
EBI_CS_ASPACE_1KB_gc = (0x02<<2),
EBI_CS_ASPACE_2KB_gc = (0x03<<2),
EBI_CS_ASPACE_4KB_gc = (0x04<<2),
EBI_CS_ASPACE_8KB_gc = (0x05<<2),
EBI_CS_ASPACE_16KB_gc = (0x06<<2),
EBI_CS_ASPACE_32KB_gc = (0x07<<2),
EBI_CS_ASPACE_64KB_gc = (0x08<<2),
EBI_CS_ASPACE_128KB_gc = (0x09<<2),
EBI_CS_ASPACE_256KB_gc = (0x0A<<2),
EBI_CS_ASPACE_512KB_gc = (0x0B<<2),
EBI_CS_ASPACE_1MB_gc = (0x0C<<2),
EBI_CS_ASPACE_2MB_gc = (0x0D<<2),
EBI_CS_ASPACE_4MB_gc = (0x0E<<2),
EBI_CS_ASPACE_8MB_gc = (0x0F<<2),
EBI_CS_ASPACE_16M_gc = (0x10<<2),
EBI_CS_ASPACE_256B_gc = (0x00<<2),
EBI_CS_ASPACE_512B_gc = (0x01<<2),
EBI_CS_ASPACE_1KB_gc = (0x02<<2),
EBI_CS_ASPACE_2KB_gc = (0x03<<2),
EBI_CS_ASPACE_4KB_gc = (0x04<<2),
EBI_CS_ASPACE_8KB_gc = (0x05<<2),
EBI_CS_ASPACE_16KB_gc = (0x06<<2),
EBI_CS_ASPACE_32KB_gc = (0x07<<2),
EBI_CS_ASPACE_64KB_gc = (0x08<<2),
EBI_CS_ASPACE_128KB_gc = (0x09<<2),
EBI_CS_ASPACE_256KB_gc = (0x0A<<2),
EBI_CS_ASPACE_512KB_gc = (0x0B<<2),
EBI_CS_ASPACE_1MB_gc = (0x0C<<2),
EBI_CS_ASPACE_2MB_gc = (0x0D<<2),
EBI_CS_ASPACE_4MB_gc = (0x0E<<2),
EBI_CS_ASPACE_8MB_gc = (0x0F<<2),
EBI_CS_ASPACE_16M_gc = (0x10<<2),
EBI_CS_ASPACE_256B_gc = (0x00<<2),
EBI_CS_ASPACE_512B_gc = (0x01<<2),
EBI_CS_ASPACE_1KB_gc = (0x02<<2),
EBI_CS_ASPACE_2KB_gc = (0x03<<2),
EBI_CS_ASPACE_4KB_gc = (0x04<<2),
EBI_CS_ASPACE_8KB_gc = (0x05<<2),
EBI_CS_ASPACE_16KB_gc = (0x06<<2),
EBI_CS_ASPACE_32KB_gc = (0x07<<2),
EBI_CS_ASPACE_64KB_gc = (0x08<<2),
EBI_CS_ASPACE_128KB_gc = (0x09<<2),
EBI_CS_ASPACE_256KB_gc = (0x0A<<2),
EBI_CS_ASPACE_512KB_gc = (0x0B<<2),
EBI_CS_ASPACE_1MB_gc = (0x0C<<2),
EBI_CS_ASPACE_2MB_gc = (0x0D<<2),
EBI_CS_ASPACE_4MB_gc = (0x0E<<2),
EBI_CS_ASPACE_8MB_gc = (0x0F<<2),
EBI_CS_ASPACE_16M_gc = (0x10<<2),
EBI_CS_ASPACE_256B_gc = (0x00<<2),
EBI_CS_ASPACE_512B_gc = (0x01<<2),
EBI_CS_ASPACE_1KB_gc = (0x02<<2),
EBI_CS_ASPACE_2KB_gc = (0x03<<2),
EBI_CS_ASPACE_4KB_gc = (0x04<<2),
EBI_CS_ASPACE_8KB_gc = (0x05<<2),
EBI_CS_ASPACE_16KB_gc = (0x06<<2),
EBI_CS_ASPACE_32KB_gc = (0x07<<2),
EBI_CS_ASPACE_64KB_gc = (0x08<<2),
EBI_CS_ASPACE_128KB_gc = (0x09<<2),
EBI_CS_ASPACE_256KB_gc = (0x0A<<2),
EBI_CS_ASPACE_512KB_gc = (0x0B<<2),
EBI_CS_ASPACE_1MB_gc = (0x0C<<2),
EBI_CS_ASPACE_2MB_gc = (0x0D<<2),
EBI_CS_ASPACE_4MB_gc = (0x0E<<2),
EBI_CS_ASPACE_8MB_gc = (0x0F<<2),
EBI_CS_ASPACE_16M_gc = (0x10<<2),
EBI_CS_ASPACE_256B_gc = (0x00<<2),
EBI_CS_ASPACE_512B_gc = (0x01<<2),
EBI_CS_ASPACE_1KB_gc = (0x02<<2),
EBI_CS_ASPACE_2KB_gc = (0x03<<2),
EBI_CS_ASPACE_4KB_gc = (0x04<<2),
EBI_CS_ASPACE_8KB_gc = (0x05<<2),
EBI_CS_ASPACE_16KB_gc = (0x06<<2),
EBI_CS_ASPACE_32KB_gc = (0x07<<2),
EBI_CS_ASPACE_64KB_gc = (0x08<<2),
EBI_CS_ASPACE_128KB_gc = (0x09<<2),
EBI_CS_ASPACE_256KB_gc = (0x0A<<2),
EBI_CS_ASPACE_512KB_gc = (0x0B<<2),
EBI_CS_ASPACE_1MB_gc = (0x0C<<2),
EBI_CS_ASPACE_2MB_gc = (0x0D<<2),
EBI_CS_ASPACE_4MB_gc = (0x0E<<2),
EBI_CS_ASPACE_8MB_gc = (0x0F<<2),
EBI_CS_ASPACE_16M_gc = (0x10<<2),
EBI_CS_ASPACE_256B_gc = (0x00<<2),
EBI_CS_ASPACE_512B_gc = (0x01<<2),
EBI_CS_ASPACE_1KB_gc = (0x02<<2),
EBI_CS_ASPACE_2KB_gc = (0x03<<2),
EBI_CS_ASPACE_4KB_gc = (0x04<<2),
EBI_CS_ASPACE_8KB_gc = (0x05<<2),
EBI_CS_ASPACE_16KB_gc = (0x06<<2),
EBI_CS_ASPACE_32KB_gc = (0x07<<2),
EBI_CS_ASPACE_64KB_gc = (0x08<<2),
EBI_CS_ASPACE_128KB_gc = (0x09<<2),
EBI_CS_ASPACE_256KB_gc = (0x0A<<2),
EBI_CS_ASPACE_512KB_gc = (0x0B<<2),
EBI_CS_ASPACE_1MB_gc = (0x0C<<2),
EBI_CS_ASPACE_2MB_gc = (0x0D<<2),
EBI_CS_ASPACE_4MB_gc = (0x0E<<2),
EBI_CS_ASPACE_8MB_gc = (0x0F<<2),
EBI_CS_ASPACE_16M_gc = (0x10<<2)
} |
|
enum | EBI_CS_SRWS_enum {
EBI_CS_SRWS_0CLK_gc = (0x00<<0),
EBI_CS_SRWS_1CLK_gc = (0x01<<0),
EBI_CS_SRWS_2CLK_gc = (0x02<<0),
EBI_CS_SRWS_3CLK_gc = (0x03<<0),
EBI_CS_SRWS_4CLK_gc = (0x04<<0),
EBI_CS_SRWS_5CLK_gc = (0x05<<0),
EBI_CS_SRWS_6CLK_gc = (0x06<<0),
EBI_CS_SRWS_7CLK_gc = (0x07<<0),
EBI_CS_SRWS_0CLK_gc = (0x00<<0),
EBI_CS_SRWS_1CLK_gc = (0x01<<0),
EBI_CS_SRWS_2CLK_gc = (0x02<<0),
EBI_CS_SRWS_3CLK_gc = (0x03<<0),
EBI_CS_SRWS_4CLK_gc = (0x04<<0),
EBI_CS_SRWS_5CLK_gc = (0x05<<0),
EBI_CS_SRWS_6CLK_gc = (0x06<<0),
EBI_CS_SRWS_7CLK_gc = (0x07<<0),
EBI_CS_SRWS_0CLK_gc = (0x00<<0),
EBI_CS_SRWS_1CLK_gc = (0x01<<0),
EBI_CS_SRWS_2CLK_gc = (0x02<<0),
EBI_CS_SRWS_3CLK_gc = (0x03<<0),
EBI_CS_SRWS_4CLK_gc = (0x04<<0),
EBI_CS_SRWS_5CLK_gc = (0x05<<0),
EBI_CS_SRWS_6CLK_gc = (0x06<<0),
EBI_CS_SRWS_7CLK_gc = (0x07<<0),
EBI_CS_SRWS_0CLK_gc = (0x00<<0),
EBI_CS_SRWS_1CLK_gc = (0x01<<0),
EBI_CS_SRWS_2CLK_gc = (0x02<<0),
EBI_CS_SRWS_3CLK_gc = (0x03<<0),
EBI_CS_SRWS_4CLK_gc = (0x04<<0),
EBI_CS_SRWS_5CLK_gc = (0x05<<0),
EBI_CS_SRWS_6CLK_gc = (0x06<<0),
EBI_CS_SRWS_7CLK_gc = (0x07<<0),
EBI_CS_SRWS_0CLK_gc = (0x00<<0),
EBI_CS_SRWS_1CLK_gc = (0x01<<0),
EBI_CS_SRWS_2CLK_gc = (0x02<<0),
EBI_CS_SRWS_3CLK_gc = (0x03<<0),
EBI_CS_SRWS_4CLK_gc = (0x04<<0),
EBI_CS_SRWS_5CLK_gc = (0x05<<0),
EBI_CS_SRWS_6CLK_gc = (0x06<<0),
EBI_CS_SRWS_7CLK_gc = (0x07<<0),
EBI_CS_SRWS_0CLK_gc = (0x00<<0),
EBI_CS_SRWS_1CLK_gc = (0x01<<0),
EBI_CS_SRWS_2CLK_gc = (0x02<<0),
EBI_CS_SRWS_3CLK_gc = (0x03<<0),
EBI_CS_SRWS_4CLK_gc = (0x04<<0),
EBI_CS_SRWS_5CLK_gc = (0x05<<0),
EBI_CS_SRWS_6CLK_gc = (0x06<<0),
EBI_CS_SRWS_7CLK_gc = (0x07<<0),
EBI_CS_SRWS_0CLK_gc = (0x00<<0),
EBI_CS_SRWS_1CLK_gc = (0x01<<0),
EBI_CS_SRWS_2CLK_gc = (0x02<<0),
EBI_CS_SRWS_3CLK_gc = (0x03<<0),
EBI_CS_SRWS_4CLK_gc = (0x04<<0),
EBI_CS_SRWS_5CLK_gc = (0x05<<0),
EBI_CS_SRWS_6CLK_gc = (0x06<<0),
EBI_CS_SRWS_7CLK_gc = (0x07<<0),
EBI_CS_SRWS_0CLK_gc = (0x00<<0),
EBI_CS_SRWS_1CLK_gc = (0x01<<0),
EBI_CS_SRWS_2CLK_gc = (0x02<<0),
EBI_CS_SRWS_3CLK_gc = (0x03<<0),
EBI_CS_SRWS_4CLK_gc = (0x04<<0),
EBI_CS_SRWS_5CLK_gc = (0x05<<0),
EBI_CS_SRWS_6CLK_gc = (0x06<<0),
EBI_CS_SRWS_7CLK_gc = (0x07<<0),
EBI_CS_SRWS_0CLK_gc = (0x00<<0),
EBI_CS_SRWS_1CLK_gc = (0x01<<0),
EBI_CS_SRWS_2CLK_gc = (0x02<<0),
EBI_CS_SRWS_3CLK_gc = (0x03<<0),
EBI_CS_SRWS_4CLK_gc = (0x04<<0),
EBI_CS_SRWS_5CLK_gc = (0x05<<0),
EBI_CS_SRWS_6CLK_gc = (0x06<<0),
EBI_CS_SRWS_7CLK_gc = (0x07<<0),
EBI_CS_SRWS_0CLK_gc = (0x00<<0),
EBI_CS_SRWS_1CLK_gc = (0x01<<0),
EBI_CS_SRWS_2CLK_gc = (0x02<<0),
EBI_CS_SRWS_3CLK_gc = (0x03<<0),
EBI_CS_SRWS_4CLK_gc = (0x04<<0),
EBI_CS_SRWS_5CLK_gc = (0x05<<0),
EBI_CS_SRWS_6CLK_gc = (0x06<<0),
EBI_CS_SRWS_7CLK_gc = (0x07<<0),
EBI_CS_SRWS_0CLK_gc = (0x00<<0),
EBI_CS_SRWS_1CLK_gc = (0x01<<0),
EBI_CS_SRWS_2CLK_gc = (0x02<<0),
EBI_CS_SRWS_3CLK_gc = (0x03<<0),
EBI_CS_SRWS_4CLK_gc = (0x04<<0),
EBI_CS_SRWS_5CLK_gc = (0x05<<0),
EBI_CS_SRWS_6CLK_gc = (0x06<<0),
EBI_CS_SRWS_7CLK_gc = (0x07<<0),
EBI_CS_SRWS_0CLK_gc = (0x00<<0),
EBI_CS_SRWS_1CLK_gc = (0x01<<0),
EBI_CS_SRWS_2CLK_gc = (0x02<<0),
EBI_CS_SRWS_3CLK_gc = (0x03<<0),
EBI_CS_SRWS_4CLK_gc = (0x04<<0),
EBI_CS_SRWS_5CLK_gc = (0x05<<0),
EBI_CS_SRWS_6CLK_gc = (0x06<<0),
EBI_CS_SRWS_7CLK_gc = (0x07<<0),
EBI_CS_SRWS_0CLK_gc = (0x00<<0),
EBI_CS_SRWS_1CLK_gc = (0x01<<0),
EBI_CS_SRWS_2CLK_gc = (0x02<<0),
EBI_CS_SRWS_3CLK_gc = (0x03<<0),
EBI_CS_SRWS_4CLK_gc = (0x04<<0),
EBI_CS_SRWS_5CLK_gc = (0x05<<0),
EBI_CS_SRWS_6CLK_gc = (0x06<<0),
EBI_CS_SRWS_7CLK_gc = (0x07<<0),
EBI_CS_SRWS_0CLK_gc = (0x00<<0),
EBI_CS_SRWS_1CLK_gc = (0x01<<0),
EBI_CS_SRWS_2CLK_gc = (0x02<<0),
EBI_CS_SRWS_3CLK_gc = (0x03<<0),
EBI_CS_SRWS_4CLK_gc = (0x04<<0),
EBI_CS_SRWS_5CLK_gc = (0x05<<0),
EBI_CS_SRWS_6CLK_gc = (0x06<<0),
EBI_CS_SRWS_7CLK_gc = (0x07<<0),
EBI_CS_SRWS_0CLK_gc = (0x00<<0),
EBI_CS_SRWS_1CLK_gc = (0x01<<0),
EBI_CS_SRWS_2CLK_gc = (0x02<<0),
EBI_CS_SRWS_3CLK_gc = (0x03<<0),
EBI_CS_SRWS_4CLK_gc = (0x04<<0),
EBI_CS_SRWS_5CLK_gc = (0x05<<0),
EBI_CS_SRWS_6CLK_gc = (0x06<<0),
EBI_CS_SRWS_7CLK_gc = (0x07<<0)
} |
|
enum | EBI_CS_MODE_enum {
EBI_CS_MODE_DISABLED_gc = (0x00<<0),
EBI_CS_MODE_SRAM_gc = (0x01<<0),
EBI_CS_MODE_LPC_gc = (0x02<<0),
EBI_CS_MODE_SDRAM_gc = (0x03<<0),
EBI_CS_MODE_DISABLED_gc = (0x00<<0),
EBI_CS_MODE_SRAM_gc = (0x01<<0),
EBI_CS_MODE_LPC_gc = (0x02<<0),
EBI_CS_MODE_SDRAM_gc = (0x03<<0),
EBI_CS_MODE_DISABLED_gc = (0x00<<0),
EBI_CS_MODE_SRAM_gc = (0x01<<0),
EBI_CS_MODE_LPC_gc = (0x02<<0),
EBI_CS_MODE_SDRAM_gc = (0x03<<0),
EBI_CS_MODE_DISABLED_gc = (0x00<<0),
EBI_CS_MODE_SRAM_gc = (0x01<<0),
EBI_CS_MODE_LPC_gc = (0x02<<0),
EBI_CS_MODE_SDRAM_gc = (0x03<<0),
EBI_CS_MODE_DISABLED_gc = (0x00<<0),
EBI_CS_MODE_SRAM_gc = (0x01<<0),
EBI_CS_MODE_LPC_gc = (0x02<<0),
EBI_CS_MODE_SDRAM_gc = (0x03<<0),
EBI_CS_MODE_DISABLED_gc = (0x00<<0),
EBI_CS_MODE_SRAM_gc = (0x01<<0),
EBI_CS_MODE_LPC_gc = (0x02<<0),
EBI_CS_MODE_SDRAM_gc = (0x03<<0),
EBI_CS_MODE_DISABLED_gc = (0x00<<0),
EBI_CS_MODE_SRAM_gc = (0x01<<0),
EBI_CS_MODE_LPC_gc = (0x02<<0),
EBI_CS_MODE_SDRAM_gc = (0x03<<0),
EBI_CS_MODE_DISABLED_gc = (0x00<<0),
EBI_CS_MODE_SRAM_gc = (0x01<<0),
EBI_CS_MODE_LPC_gc = (0x02<<0),
EBI_CS_MODE_SDRAM_gc = (0x03<<0),
EBI_CS_MODE_DISABLED_gc = (0x00<<0),
EBI_CS_MODE_SRAM_gc = (0x01<<0),
EBI_CS_MODE_LPC_gc = (0x02<<0),
EBI_CS_MODE_SDRAM_gc = (0x03<<0),
EBI_CS_MODE_DISABLED_gc = (0x00<<0),
EBI_CS_MODE_SRAM_gc = (0x01<<0),
EBI_CS_MODE_LPC_gc = (0x02<<0),
EBI_CS_MODE_SDRAM_gc = (0x03<<0),
EBI_CS_MODE_DISABLED_gc = (0x00<<0),
EBI_CS_MODE_SRAM_gc = (0x01<<0),
EBI_CS_MODE_LPC_gc = (0x02<<0),
EBI_CS_MODE_SDRAM_gc = (0x03<<0),
EBI_CS_MODE_DISABLED_gc = (0x00<<0),
EBI_CS_MODE_SRAM_gc = (0x01<<0),
EBI_CS_MODE_LPC_gc = (0x02<<0),
EBI_CS_MODE_SDRAM_gc = (0x03<<0),
EBI_CS_MODE_DISABLED_gc = (0x00<<0),
EBI_CS_MODE_SRAM_gc = (0x01<<0),
EBI_CS_MODE_LPC_gc = (0x02<<0),
EBI_CS_MODE_SDRAM_gc = (0x03<<0),
EBI_CS_MODE_DISABLED_gc = (0x00<<0),
EBI_CS_MODE_SRAM_gc = (0x01<<0),
EBI_CS_MODE_LPC_gc = (0x02<<0),
EBI_CS_MODE_SDRAM_gc = (0x03<<0),
EBI_CS_MODE_DISABLED_gc = (0x00<<0),
EBI_CS_MODE_SRAM_gc = (0x01<<0),
EBI_CS_MODE_LPC_gc = (0x02<<0),
EBI_CS_MODE_SDRAM_gc = (0x03<<0)
} |
|
enum | EBI_CS_SDMODE_enum {
EBI_CS_SDMODE_NORMAL_gc = (0x00<<0),
EBI_CS_SDMODE_LOAD_gc = (0x01<<0),
EBI_CS_SDMODE_NORMAL_gc = (0x00<<0),
EBI_CS_SDMODE_LOAD_gc = (0x01<<0),
EBI_CS_SDMODE_NORMAL_gc = (0x00<<0),
EBI_CS_SDMODE_LOAD_gc = (0x01<<0),
EBI_CS_SDMODE_NORMAL_gc = (0x00<<0),
EBI_CS_SDMODE_LOAD_gc = (0x01<<0),
EBI_CS_SDMODE_NORMAL_gc = (0x00<<0),
EBI_CS_SDMODE_LOAD_gc = (0x01<<0),
EBI_CS_SDMODE_NORMAL_gc = (0x00<<0),
EBI_CS_SDMODE_LOAD_gc = (0x01<<0),
EBI_CS_SDMODE_NORMAL_gc = (0x00<<0),
EBI_CS_SDMODE_LOAD_gc = (0x01<<0),
EBI_CS_SDMODE_NORMAL_gc = (0x00<<0),
EBI_CS_SDMODE_LOAD_gc = (0x01<<0),
EBI_CS_SDMODE_NORMAL_gc = (0x00<<0),
EBI_CS_SDMODE_LOAD_gc = (0x01<<0),
EBI_CS_SDMODE_NORMAL_gc = (0x00<<0),
EBI_CS_SDMODE_LOAD_gc = (0x01<<0),
EBI_CS_SDMODE_NORMAL_gc = (0x00<<0),
EBI_CS_SDMODE_LOAD_gc = (0x01<<0),
EBI_CS_SDMODE_NORMAL_gc = (0x00<<0),
EBI_CS_SDMODE_LOAD_gc = (0x01<<0),
EBI_CS_SDMODE_NORMAL_gc = (0x00<<0),
EBI_CS_SDMODE_LOAD_gc = (0x01<<0),
EBI_CS_SDMODE_NORMAL_gc = (0x00<<0),
EBI_CS_SDMODE_LOAD_gc = (0x01<<0),
EBI_CS_SDMODE_NORMAL_gc = (0x00<<0),
EBI_CS_SDMODE_LOAD_gc = (0x01<<0)
} |
|
enum | EBI_SDDATAW_enum {
EBI_SDDATAW_4BIT_gc = (0x00<<6),
EBI_SDDATAW_8BIT_gc = (0x01<<6),
EBI_SDDATAW_4BIT_gc = (0x00<<6),
EBI_SDDATAW_8BIT_gc = (0x01<<6),
EBI_SDDATAW_4BIT_gc = (0x00<<6),
EBI_SDDATAW_8BIT_gc = (0x01<<6),
EBI_SDDATAW_4BIT_gc = (0x00<<6),
EBI_SDDATAW_8BIT_gc = (0x01<<6),
EBI_SDDATAW_4BIT_gc = (0x00<<6),
EBI_SDDATAW_8BIT_gc = (0x01<<6),
EBI_SDDATAW_4BIT_gc = (0x00<<6),
EBI_SDDATAW_8BIT_gc = (0x01<<6),
EBI_SDDATAW_4BIT_gc = (0x00<<6),
EBI_SDDATAW_8BIT_gc = (0x01<<6),
EBI_SDDATAW_4BIT_gc = (0x00<<6),
EBI_SDDATAW_8BIT_gc = (0x01<<6),
EBI_SDDATAW_4BIT_gc = (0x00<<6),
EBI_SDDATAW_8BIT_gc = (0x01<<6),
EBI_SDDATAW_4BIT_gc = (0x00<<6),
EBI_SDDATAW_8BIT_gc = (0x01<<6),
EBI_SDDATAW_4BIT_gc = (0x00<<6),
EBI_SDDATAW_8BIT_gc = (0x01<<6),
EBI_SDDATAW_4BIT_gc = (0x00<<6),
EBI_SDDATAW_8BIT_gc = (0x01<<6),
EBI_SDDATAW_4BIT_gc = (0x00<<6),
EBI_SDDATAW_8BIT_gc = (0x01<<6),
EBI_SDDATAW_4BIT_gc = (0x00<<6),
EBI_SDDATAW_8BIT_gc = (0x01<<6),
EBI_SDDATAW_4BIT_gc = (0x00<<6),
EBI_SDDATAW_8BIT_gc = (0x01<<6)
} |
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enum | EBI_LPCMODE_enum {
EBI_LPCMODE_ALE1_gc = (0x00<<4),
EBI_LPCMODE_ALE12_gc = (0x02<<4),
EBI_LPCMODE_ALE1_gc = (0x00<<4),
EBI_LPCMODE_ALE12_gc = (0x02<<4),
EBI_LPCMODE_ALE1_gc = (0x00<<4),
EBI_LPCMODE_ALE12_gc = (0x02<<4),
EBI_LPCMODE_ALE1_gc = (0x00<<4),
EBI_LPCMODE_ALE12_gc = (0x02<<4),
EBI_LPCMODE_ALE1_gc = (0x00<<4),
EBI_LPCMODE_ALE12_gc = (0x02<<4),
EBI_LPCMODE_ALE1_gc = (0x00<<4),
EBI_LPCMODE_ALE12_gc = (0x02<<4),
EBI_LPCMODE_ALE1_gc = (0x00<<4),
EBI_LPCMODE_ALE12_gc = (0x02<<4),
EBI_LPCMODE_ALE1_gc = (0x00<<4),
EBI_LPCMODE_ALE12_gc = (0x02<<4),
EBI_LPCMODE_ALE1_gc = (0x00<<4),
EBI_LPCMODE_ALE12_gc = (0x02<<4),
EBI_LPCMODE_ALE1_gc = (0x00<<4),
EBI_LPCMODE_ALE12_gc = (0x02<<4),
EBI_LPCMODE_ALE1_gc = (0x00<<4),
EBI_LPCMODE_ALE12_gc = (0x02<<4),
EBI_LPCMODE_ALE1_gc = (0x00<<4),
EBI_LPCMODE_ALE12_gc = (0x02<<4),
EBI_LPCMODE_ALE1_gc = (0x00<<4),
EBI_LPCMODE_ALE12_gc = (0x02<<4),
EBI_LPCMODE_ALE1_gc = (0x00<<4),
EBI_LPCMODE_ALE12_gc = (0x02<<4),
EBI_LPCMODE_ALE1_gc = (0x00<<4),
EBI_LPCMODE_ALE12_gc = (0x02<<4)
} |
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enum | EBI_SRMODE_enum {
EBI_SRMODE_ALE1_gc = (0x00<<2),
EBI_SRMODE_ALE2_gc = (0x01<<2),
EBI_SRMODE_ALE12_gc = (0x02<<2),
EBI_SRMODE_NOALE_gc = (0x03<<2),
EBI_SRMODE_ALE1_gc = (0x00<<2),
EBI_SRMODE_ALE2_gc = (0x01<<2),
EBI_SRMODE_ALE12_gc = (0x02<<2),
EBI_SRMODE_NOALE_gc = (0x03<<2),
EBI_SRMODE_ALE1_gc = (0x00<<2),
EBI_SRMODE_ALE2_gc = (0x01<<2),
EBI_SRMODE_ALE12_gc = (0x02<<2),
EBI_SRMODE_NOALE_gc = (0x03<<2),
EBI_SRMODE_ALE1_gc = (0x00<<2),
EBI_SRMODE_ALE2_gc = (0x01<<2),
EBI_SRMODE_ALE12_gc = (0x02<<2),
EBI_SRMODE_NOALE_gc = (0x03<<2),
EBI_SRMODE_ALE1_gc = (0x00<<2),
EBI_SRMODE_ALE2_gc = (0x01<<2),
EBI_SRMODE_ALE12_gc = (0x02<<2),
EBI_SRMODE_NOALE_gc = (0x03<<2),
EBI_SRMODE_ALE1_gc = (0x00<<2),
EBI_SRMODE_ALE2_gc = (0x01<<2),
EBI_SRMODE_ALE12_gc = (0x02<<2),
EBI_SRMODE_NOALE_gc = (0x03<<2),
EBI_SRMODE_ALE1_gc = (0x00<<2),
EBI_SRMODE_ALE2_gc = (0x01<<2),
EBI_SRMODE_ALE12_gc = (0x02<<2),
EBI_SRMODE_NOALE_gc = (0x03<<2),
EBI_SRMODE_ALE1_gc = (0x00<<2),
EBI_SRMODE_ALE2_gc = (0x01<<2),
EBI_SRMODE_ALE12_gc = (0x02<<2),
EBI_SRMODE_NOALE_gc = (0x03<<2),
EBI_SRMODE_ALE1_gc = (0x00<<2),
EBI_SRMODE_ALE2_gc = (0x01<<2),
EBI_SRMODE_ALE12_gc = (0x02<<2),
EBI_SRMODE_NOALE_gc = (0x03<<2),
EBI_SRMODE_ALE1_gc = (0x00<<2),
EBI_SRMODE_ALE2_gc = (0x01<<2),
EBI_SRMODE_ALE12_gc = (0x02<<2),
EBI_SRMODE_NOALE_gc = (0x03<<2),
EBI_SRMODE_ALE1_gc = (0x00<<2),
EBI_SRMODE_ALE2_gc = (0x01<<2),
EBI_SRMODE_ALE12_gc = (0x02<<2),
EBI_SRMODE_NOALE_gc = (0x03<<2),
EBI_SRMODE_ALE1_gc = (0x00<<2),
EBI_SRMODE_ALE2_gc = (0x01<<2),
EBI_SRMODE_ALE12_gc = (0x02<<2),
EBI_SRMODE_NOALE_gc = (0x03<<2),
EBI_SRMODE_ALE1_gc = (0x00<<2),
EBI_SRMODE_ALE2_gc = (0x01<<2),
EBI_SRMODE_ALE12_gc = (0x02<<2),
EBI_SRMODE_NOALE_gc = (0x03<<2),
EBI_SRMODE_ALE1_gc = (0x00<<2),
EBI_SRMODE_ALE2_gc = (0x01<<2),
EBI_SRMODE_ALE12_gc = (0x02<<2),
EBI_SRMODE_NOALE_gc = (0x03<<2),
EBI_SRMODE_ALE1_gc = (0x00<<2),
EBI_SRMODE_ALE2_gc = (0x01<<2),
EBI_SRMODE_ALE12_gc = (0x02<<2),
EBI_SRMODE_NOALE_gc = (0x03<<2)
} |
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enum | EBI_IFMODE_enum {
EBI_IFMODE_DISABLED_gc = (0x00<<0),
EBI_IFMODE_3PORT_gc = (0x01<<0),
EBI_IFMODE_4PORT_gc = (0x02<<0),
EBI_IFMODE_2PORT_gc = (0x03<<0),
EBI_IFMODE_DISABLED_gc = (0x00<<0),
EBI_IFMODE_3PORT_gc = (0x01<<0),
EBI_IFMODE_4PORT_gc = (0x02<<0),
EBI_IFMODE_2PORT_gc = (0x03<<0),
EBI_IFMODE_DISABLED_gc = (0x00<<0),
EBI_IFMODE_3PORT_gc = (0x01<<0),
EBI_IFMODE_4PORT_gc = (0x02<<0),
EBI_IFMODE_2PORT_gc = (0x03<<0),
EBI_IFMODE_DISABLED_gc = (0x00<<0),
EBI_IFMODE_3PORT_gc = (0x01<<0),
EBI_IFMODE_4PORT_gc = (0x02<<0),
EBI_IFMODE_2PORT_gc = (0x03<<0),
EBI_IFMODE_DISABLED_gc = (0x00<<0),
EBI_IFMODE_3PORT_gc = (0x01<<0),
EBI_IFMODE_4PORT_gc = (0x02<<0),
EBI_IFMODE_2PORT_gc = (0x03<<0),
EBI_IFMODE_DISABLED_gc = (0x00<<0),
EBI_IFMODE_3PORT_gc = (0x01<<0),
EBI_IFMODE_4PORT_gc = (0x02<<0),
EBI_IFMODE_2PORT_gc = (0x03<<0),
EBI_IFMODE_DISABLED_gc = (0x00<<0),
EBI_IFMODE_3PORT_gc = (0x01<<0),
EBI_IFMODE_4PORT_gc = (0x02<<0),
EBI_IFMODE_2PORT_gc = (0x03<<0),
EBI_IFMODE_DISABLED_gc = (0x00<<0),
EBI_IFMODE_3PORT_gc = (0x01<<0),
EBI_IFMODE_4PORT_gc = (0x02<<0),
EBI_IFMODE_2PORT_gc = (0x03<<0),
EBI_IFMODE_DISABLED_gc = (0x00<<0),
EBI_IFMODE_3PORT_gc = (0x01<<0),
EBI_IFMODE_4PORT_gc = (0x02<<0),
EBI_IFMODE_2PORT_gc = (0x03<<0),
EBI_IFMODE_DISABLED_gc = (0x00<<0),
EBI_IFMODE_3PORT_gc = (0x01<<0),
EBI_IFMODE_4PORT_gc = (0x02<<0),
EBI_IFMODE_2PORT_gc = (0x03<<0),
EBI_IFMODE_DISABLED_gc = (0x00<<0),
EBI_IFMODE_3PORT_gc = (0x01<<0),
EBI_IFMODE_4PORT_gc = (0x02<<0),
EBI_IFMODE_2PORT_gc = (0x03<<0),
EBI_IFMODE_DISABLED_gc = (0x00<<0),
EBI_IFMODE_3PORT_gc = (0x01<<0),
EBI_IFMODE_4PORT_gc = (0x02<<0),
EBI_IFMODE_2PORT_gc = (0x03<<0),
EBI_IFMODE_DISABLED_gc = (0x00<<0),
EBI_IFMODE_3PORT_gc = (0x01<<0),
EBI_IFMODE_4PORT_gc = (0x02<<0),
EBI_IFMODE_2PORT_gc = (0x03<<0),
EBI_IFMODE_DISABLED_gc = (0x00<<0),
EBI_IFMODE_3PORT_gc = (0x01<<0),
EBI_IFMODE_4PORT_gc = (0x02<<0),
EBI_IFMODE_2PORT_gc = (0x03<<0),
EBI_IFMODE_DISABLED_gc = (0x00<<0),
EBI_IFMODE_3PORT_gc = (0x01<<0),
EBI_IFMODE_4PORT_gc = (0x02<<0),
EBI_IFMODE_2PORT_gc = (0x03<<0)
} |
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enum | EBI_SDCOL_enum {
EBI_SDCOL_8BIT_gc = (0x00<<0),
EBI_SDCOL_9BIT_gc = (0x01<<0),
EBI_SDCOL_10BIT_gc = (0x02<<0),
EBI_SDCOL_11BIT_gc = (0x03<<0),
EBI_SDCOL_8BIT_gc = (0x00<<0),
EBI_SDCOL_9BIT_gc = (0x01<<0),
EBI_SDCOL_10BIT_gc = (0x02<<0),
EBI_SDCOL_11BIT_gc = (0x03<<0),
EBI_SDCOL_8BIT_gc = (0x00<<0),
EBI_SDCOL_9BIT_gc = (0x01<<0),
EBI_SDCOL_10BIT_gc = (0x02<<0),
EBI_SDCOL_11BIT_gc = (0x03<<0),
EBI_SDCOL_8BIT_gc = (0x00<<0),
EBI_SDCOL_9BIT_gc = (0x01<<0),
EBI_SDCOL_10BIT_gc = (0x02<<0),
EBI_SDCOL_11BIT_gc = (0x03<<0),
EBI_SDCOL_8BIT_gc = (0x00<<0),
EBI_SDCOL_9BIT_gc = (0x01<<0),
EBI_SDCOL_10BIT_gc = (0x02<<0),
EBI_SDCOL_11BIT_gc = (0x03<<0),
EBI_SDCOL_8BIT_gc = (0x00<<0),
EBI_SDCOL_9BIT_gc = (0x01<<0),
EBI_SDCOL_10BIT_gc = (0x02<<0),
EBI_SDCOL_11BIT_gc = (0x03<<0),
EBI_SDCOL_8BIT_gc = (0x00<<0),
EBI_SDCOL_9BIT_gc = (0x01<<0),
EBI_SDCOL_10BIT_gc = (0x02<<0),
EBI_SDCOL_11BIT_gc = (0x03<<0),
EBI_SDCOL_8BIT_gc = (0x00<<0),
EBI_SDCOL_9BIT_gc = (0x01<<0),
EBI_SDCOL_10BIT_gc = (0x02<<0),
EBI_SDCOL_11BIT_gc = (0x03<<0),
EBI_SDCOL_8BIT_gc = (0x00<<0),
EBI_SDCOL_9BIT_gc = (0x01<<0),
EBI_SDCOL_10BIT_gc = (0x02<<0),
EBI_SDCOL_11BIT_gc = (0x03<<0),
EBI_SDCOL_8BIT_gc = (0x00<<0),
EBI_SDCOL_9BIT_gc = (0x01<<0),
EBI_SDCOL_10BIT_gc = (0x02<<0),
EBI_SDCOL_11BIT_gc = (0x03<<0),
EBI_SDCOL_8BIT_gc = (0x00<<0),
EBI_SDCOL_9BIT_gc = (0x01<<0),
EBI_SDCOL_10BIT_gc = (0x02<<0),
EBI_SDCOL_11BIT_gc = (0x03<<0),
EBI_SDCOL_8BIT_gc = (0x00<<0),
EBI_SDCOL_9BIT_gc = (0x01<<0),
EBI_SDCOL_10BIT_gc = (0x02<<0),
EBI_SDCOL_11BIT_gc = (0x03<<0),
EBI_SDCOL_8BIT_gc = (0x00<<0),
EBI_SDCOL_9BIT_gc = (0x01<<0),
EBI_SDCOL_10BIT_gc = (0x02<<0),
EBI_SDCOL_11BIT_gc = (0x03<<0),
EBI_SDCOL_8BIT_gc = (0x00<<0),
EBI_SDCOL_9BIT_gc = (0x01<<0),
EBI_SDCOL_10BIT_gc = (0x02<<0),
EBI_SDCOL_11BIT_gc = (0x03<<0),
EBI_SDCOL_8BIT_gc = (0x00<<0),
EBI_SDCOL_9BIT_gc = (0x01<<0),
EBI_SDCOL_10BIT_gc = (0x02<<0),
EBI_SDCOL_11BIT_gc = (0x03<<0)
} |
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enum | EBI_MRDLY_enum {
EBI_MRDLY_0CLK_gc = (0x00<<6),
EBI_MRDLY_1CLK_gc = (0x01<<6),
EBI_MRDLY_2CLK_gc = (0x02<<6),
EBI_MRDLY_3CLK_gc = (0x03<<6),
EBI_MRDLY_0CLK_gc = (0x00<<6),
EBI_MRDLY_1CLK_gc = (0x01<<6),
EBI_MRDLY_2CLK_gc = (0x02<<6),
EBI_MRDLY_3CLK_gc = (0x03<<6),
EBI_MRDLY_0CLK_gc = (0x00<<6),
EBI_MRDLY_1CLK_gc = (0x01<<6),
EBI_MRDLY_2CLK_gc = (0x02<<6),
EBI_MRDLY_3CLK_gc = (0x03<<6),
EBI_MRDLY_0CLK_gc = (0x00<<6),
EBI_MRDLY_1CLK_gc = (0x01<<6),
EBI_MRDLY_2CLK_gc = (0x02<<6),
EBI_MRDLY_3CLK_gc = (0x03<<6),
EBI_MRDLY_0CLK_gc = (0x00<<6),
EBI_MRDLY_1CLK_gc = (0x01<<6),
EBI_MRDLY_2CLK_gc = (0x02<<6),
EBI_MRDLY_3CLK_gc = (0x03<<6),
EBI_MRDLY_0CLK_gc = (0x00<<6),
EBI_MRDLY_1CLK_gc = (0x01<<6),
EBI_MRDLY_2CLK_gc = (0x02<<6),
EBI_MRDLY_3CLK_gc = (0x03<<6),
EBI_MRDLY_0CLK_gc = (0x00<<6),
EBI_MRDLY_1CLK_gc = (0x01<<6),
EBI_MRDLY_2CLK_gc = (0x02<<6),
EBI_MRDLY_3CLK_gc = (0x03<<6),
EBI_MRDLY_0CLK_gc = (0x00<<6),
EBI_MRDLY_1CLK_gc = (0x01<<6),
EBI_MRDLY_2CLK_gc = (0x02<<6),
EBI_MRDLY_3CLK_gc = (0x03<<6),
EBI_MRDLY_0CLK_gc = (0x00<<6),
EBI_MRDLY_1CLK_gc = (0x01<<6),
EBI_MRDLY_2CLK_gc = (0x02<<6),
EBI_MRDLY_3CLK_gc = (0x03<<6),
EBI_MRDLY_0CLK_gc = (0x00<<6),
EBI_MRDLY_1CLK_gc = (0x01<<6),
EBI_MRDLY_2CLK_gc = (0x02<<6),
EBI_MRDLY_3CLK_gc = (0x03<<6),
EBI_MRDLY_0CLK_gc = (0x00<<6),
EBI_MRDLY_1CLK_gc = (0x01<<6),
EBI_MRDLY_2CLK_gc = (0x02<<6),
EBI_MRDLY_3CLK_gc = (0x03<<6),
EBI_MRDLY_0CLK_gc = (0x00<<6),
EBI_MRDLY_1CLK_gc = (0x01<<6),
EBI_MRDLY_2CLK_gc = (0x02<<6),
EBI_MRDLY_3CLK_gc = (0x03<<6),
EBI_MRDLY_0CLK_gc = (0x00<<6),
EBI_MRDLY_1CLK_gc = (0x01<<6),
EBI_MRDLY_2CLK_gc = (0x02<<6),
EBI_MRDLY_3CLK_gc = (0x03<<6),
EBI_MRDLY_0CLK_gc = (0x00<<6),
EBI_MRDLY_1CLK_gc = (0x01<<6),
EBI_MRDLY_2CLK_gc = (0x02<<6),
EBI_MRDLY_3CLK_gc = (0x03<<6),
EBI_MRDLY_0CLK_gc = (0x00<<6),
EBI_MRDLY_1CLK_gc = (0x01<<6),
EBI_MRDLY_2CLK_gc = (0x02<<6),
EBI_MRDLY_3CLK_gc = (0x03<<6)
} |
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enum | EBI_ROWCYCDLY_enum {
EBI_ROWCYCDLY_0CLK_gc = (0x00<<3),
EBI_ROWCYCDLY_1CLK_gc = (0x01<<3),
EBI_ROWCYCDLY_2CLK_gc = (0x02<<3),
EBI_ROWCYCDLY_3CLK_gc = (0x03<<3),
EBI_ROWCYCDLY_4CLK_gc = (0x04<<3),
EBI_ROWCYCDLY_5CLK_gc = (0x05<<3),
EBI_ROWCYCDLY_6CLK_gc = (0x06<<3),
EBI_ROWCYCDLY_7CLK_gc = (0x07<<3),
EBI_ROWCYCDLY_0CLK_gc = (0x00<<3),
EBI_ROWCYCDLY_1CLK_gc = (0x01<<3),
EBI_ROWCYCDLY_2CLK_gc = (0x02<<3),
EBI_ROWCYCDLY_3CLK_gc = (0x03<<3),
EBI_ROWCYCDLY_4CLK_gc = (0x04<<3),
EBI_ROWCYCDLY_5CLK_gc = (0x05<<3),
EBI_ROWCYCDLY_6CLK_gc = (0x06<<3),
EBI_ROWCYCDLY_7CLK_gc = (0x07<<3),
EBI_ROWCYCDLY_0CLK_gc = (0x00<<3),
EBI_ROWCYCDLY_1CLK_gc = (0x01<<3),
EBI_ROWCYCDLY_2CLK_gc = (0x02<<3),
EBI_ROWCYCDLY_3CLK_gc = (0x03<<3),
EBI_ROWCYCDLY_4CLK_gc = (0x04<<3),
EBI_ROWCYCDLY_5CLK_gc = (0x05<<3),
EBI_ROWCYCDLY_6CLK_gc = (0x06<<3),
EBI_ROWCYCDLY_7CLK_gc = (0x07<<3),
EBI_ROWCYCDLY_0CLK_gc = (0x00<<3),
EBI_ROWCYCDLY_1CLK_gc = (0x01<<3),
EBI_ROWCYCDLY_2CLK_gc = (0x02<<3),
EBI_ROWCYCDLY_3CLK_gc = (0x03<<3),
EBI_ROWCYCDLY_4CLK_gc = (0x04<<3),
EBI_ROWCYCDLY_5CLK_gc = (0x05<<3),
EBI_ROWCYCDLY_6CLK_gc = (0x06<<3),
EBI_ROWCYCDLY_7CLK_gc = (0x07<<3),
EBI_ROWCYCDLY_0CLK_gc = (0x00<<3),
EBI_ROWCYCDLY_1CLK_gc = (0x01<<3),
EBI_ROWCYCDLY_2CLK_gc = (0x02<<3),
EBI_ROWCYCDLY_3CLK_gc = (0x03<<3),
EBI_ROWCYCDLY_4CLK_gc = (0x04<<3),
EBI_ROWCYCDLY_5CLK_gc = (0x05<<3),
EBI_ROWCYCDLY_6CLK_gc = (0x06<<3),
EBI_ROWCYCDLY_7CLK_gc = (0x07<<3),
EBI_ROWCYCDLY_0CLK_gc = (0x00<<3),
EBI_ROWCYCDLY_1CLK_gc = (0x01<<3),
EBI_ROWCYCDLY_2CLK_gc = (0x02<<3),
EBI_ROWCYCDLY_3CLK_gc = (0x03<<3),
EBI_ROWCYCDLY_4CLK_gc = (0x04<<3),
EBI_ROWCYCDLY_5CLK_gc = (0x05<<3),
EBI_ROWCYCDLY_6CLK_gc = (0x06<<3),
EBI_ROWCYCDLY_7CLK_gc = (0x07<<3),
EBI_ROWCYCDLY_0CLK_gc = (0x00<<3),
EBI_ROWCYCDLY_1CLK_gc = (0x01<<3),
EBI_ROWCYCDLY_2CLK_gc = (0x02<<3),
EBI_ROWCYCDLY_3CLK_gc = (0x03<<3),
EBI_ROWCYCDLY_4CLK_gc = (0x04<<3),
EBI_ROWCYCDLY_5CLK_gc = (0x05<<3),
EBI_ROWCYCDLY_6CLK_gc = (0x06<<3),
EBI_ROWCYCDLY_7CLK_gc = (0x07<<3),
EBI_ROWCYCDLY_0CLK_gc = (0x00<<3),
EBI_ROWCYCDLY_1CLK_gc = (0x01<<3),
EBI_ROWCYCDLY_2CLK_gc = (0x02<<3),
EBI_ROWCYCDLY_3CLK_gc = (0x03<<3),
EBI_ROWCYCDLY_4CLK_gc = (0x04<<3),
EBI_ROWCYCDLY_5CLK_gc = (0x05<<3),
EBI_ROWCYCDLY_6CLK_gc = (0x06<<3),
EBI_ROWCYCDLY_7CLK_gc = (0x07<<3),
EBI_ROWCYCDLY_0CLK_gc = (0x00<<3),
EBI_ROWCYCDLY_1CLK_gc = (0x01<<3),
EBI_ROWCYCDLY_2CLK_gc = (0x02<<3),
EBI_ROWCYCDLY_3CLK_gc = (0x03<<3),
EBI_ROWCYCDLY_4CLK_gc = (0x04<<3),
EBI_ROWCYCDLY_5CLK_gc = (0x05<<3),
EBI_ROWCYCDLY_6CLK_gc = (0x06<<3),
EBI_ROWCYCDLY_7CLK_gc = (0x07<<3),
EBI_ROWCYCDLY_0CLK_gc = (0x00<<3),
EBI_ROWCYCDLY_1CLK_gc = (0x01<<3),
EBI_ROWCYCDLY_2CLK_gc = (0x02<<3),
EBI_ROWCYCDLY_3CLK_gc = (0x03<<3),
EBI_ROWCYCDLY_4CLK_gc = (0x04<<3),
EBI_ROWCYCDLY_5CLK_gc = (0x05<<3),
EBI_ROWCYCDLY_6CLK_gc = (0x06<<3),
EBI_ROWCYCDLY_7CLK_gc = (0x07<<3),
EBI_ROWCYCDLY_0CLK_gc = (0x00<<3),
EBI_ROWCYCDLY_1CLK_gc = (0x01<<3),
EBI_ROWCYCDLY_2CLK_gc = (0x02<<3),
EBI_ROWCYCDLY_3CLK_gc = (0x03<<3),
EBI_ROWCYCDLY_4CLK_gc = (0x04<<3),
EBI_ROWCYCDLY_5CLK_gc = (0x05<<3),
EBI_ROWCYCDLY_6CLK_gc = (0x06<<3),
EBI_ROWCYCDLY_7CLK_gc = (0x07<<3),
EBI_ROWCYCDLY_0CLK_gc = (0x00<<3),
EBI_ROWCYCDLY_1CLK_gc = (0x01<<3),
EBI_ROWCYCDLY_2CLK_gc = (0x02<<3),
EBI_ROWCYCDLY_3CLK_gc = (0x03<<3),
EBI_ROWCYCDLY_4CLK_gc = (0x04<<3),
EBI_ROWCYCDLY_5CLK_gc = (0x05<<3),
EBI_ROWCYCDLY_6CLK_gc = (0x06<<3),
EBI_ROWCYCDLY_7CLK_gc = (0x07<<3),
EBI_ROWCYCDLY_0CLK_gc = (0x00<<3),
EBI_ROWCYCDLY_1CLK_gc = (0x01<<3),
EBI_ROWCYCDLY_2CLK_gc = (0x02<<3),
EBI_ROWCYCDLY_3CLK_gc = (0x03<<3),
EBI_ROWCYCDLY_4CLK_gc = (0x04<<3),
EBI_ROWCYCDLY_5CLK_gc = (0x05<<3),
EBI_ROWCYCDLY_6CLK_gc = (0x06<<3),
EBI_ROWCYCDLY_7CLK_gc = (0x07<<3),
EBI_ROWCYCDLY_0CLK_gc = (0x00<<3),
EBI_ROWCYCDLY_1CLK_gc = (0x01<<3),
EBI_ROWCYCDLY_2CLK_gc = (0x02<<3),
EBI_ROWCYCDLY_3CLK_gc = (0x03<<3),
EBI_ROWCYCDLY_4CLK_gc = (0x04<<3),
EBI_ROWCYCDLY_5CLK_gc = (0x05<<3),
EBI_ROWCYCDLY_6CLK_gc = (0x06<<3),
EBI_ROWCYCDLY_7CLK_gc = (0x07<<3),
EBI_ROWCYCDLY_0CLK_gc = (0x00<<3),
EBI_ROWCYCDLY_1CLK_gc = (0x01<<3),
EBI_ROWCYCDLY_2CLK_gc = (0x02<<3),
EBI_ROWCYCDLY_3CLK_gc = (0x03<<3),
EBI_ROWCYCDLY_4CLK_gc = (0x04<<3),
EBI_ROWCYCDLY_5CLK_gc = (0x05<<3),
EBI_ROWCYCDLY_6CLK_gc = (0x06<<3),
EBI_ROWCYCDLY_7CLK_gc = (0x07<<3)
} |
|
enum | EBI_RPDLY_enum {
EBI_RPDLY_0CLK_gc = (0x00<<0),
EBI_RPDLY_1CLK_gc = (0x01<<0),
EBI_RPDLY_2CLK_gc = (0x02<<0),
EBI_RPDLY_3CLK_gc = (0x03<<0),
EBI_RPDLY_4CLK_gc = (0x04<<0),
EBI_RPDLY_5CLK_gc = (0x05<<0),
EBI_RPDLY_6CLK_gc = (0x06<<0),
EBI_RPDLY_7CLK_gc = (0x07<<0),
EBI_RPDLY_0CLK_gc = (0x00<<0),
EBI_RPDLY_1CLK_gc = (0x01<<0),
EBI_RPDLY_2CLK_gc = (0x02<<0),
EBI_RPDLY_3CLK_gc = (0x03<<0),
EBI_RPDLY_4CLK_gc = (0x04<<0),
EBI_RPDLY_5CLK_gc = (0x05<<0),
EBI_RPDLY_6CLK_gc = (0x06<<0),
EBI_RPDLY_7CLK_gc = (0x07<<0),
EBI_RPDLY_0CLK_gc = (0x00<<0),
EBI_RPDLY_1CLK_gc = (0x01<<0),
EBI_RPDLY_2CLK_gc = (0x02<<0),
EBI_RPDLY_3CLK_gc = (0x03<<0),
EBI_RPDLY_4CLK_gc = (0x04<<0),
EBI_RPDLY_5CLK_gc = (0x05<<0),
EBI_RPDLY_6CLK_gc = (0x06<<0),
EBI_RPDLY_7CLK_gc = (0x07<<0),
EBI_RPDLY_0CLK_gc = (0x00<<0),
EBI_RPDLY_1CLK_gc = (0x01<<0),
EBI_RPDLY_2CLK_gc = (0x02<<0),
EBI_RPDLY_3CLK_gc = (0x03<<0),
EBI_RPDLY_4CLK_gc = (0x04<<0),
EBI_RPDLY_5CLK_gc = (0x05<<0),
EBI_RPDLY_6CLK_gc = (0x06<<0),
EBI_RPDLY_7CLK_gc = (0x07<<0),
EBI_RPDLY_0CLK_gc = (0x00<<0),
EBI_RPDLY_1CLK_gc = (0x01<<0),
EBI_RPDLY_2CLK_gc = (0x02<<0),
EBI_RPDLY_3CLK_gc = (0x03<<0),
EBI_RPDLY_4CLK_gc = (0x04<<0),
EBI_RPDLY_5CLK_gc = (0x05<<0),
EBI_RPDLY_6CLK_gc = (0x06<<0),
EBI_RPDLY_7CLK_gc = (0x07<<0),
EBI_RPDLY_0CLK_gc = (0x00<<0),
EBI_RPDLY_1CLK_gc = (0x01<<0),
EBI_RPDLY_2CLK_gc = (0x02<<0),
EBI_RPDLY_3CLK_gc = (0x03<<0),
EBI_RPDLY_4CLK_gc = (0x04<<0),
EBI_RPDLY_5CLK_gc = (0x05<<0),
EBI_RPDLY_6CLK_gc = (0x06<<0),
EBI_RPDLY_7CLK_gc = (0x07<<0),
EBI_RPDLY_0CLK_gc = (0x00<<0),
EBI_RPDLY_1CLK_gc = (0x01<<0),
EBI_RPDLY_2CLK_gc = (0x02<<0),
EBI_RPDLY_3CLK_gc = (0x03<<0),
EBI_RPDLY_4CLK_gc = (0x04<<0),
EBI_RPDLY_5CLK_gc = (0x05<<0),
EBI_RPDLY_6CLK_gc = (0x06<<0),
EBI_RPDLY_7CLK_gc = (0x07<<0),
EBI_RPDLY_0CLK_gc = (0x00<<0),
EBI_RPDLY_1CLK_gc = (0x01<<0),
EBI_RPDLY_2CLK_gc = (0x02<<0),
EBI_RPDLY_3CLK_gc = (0x03<<0),
EBI_RPDLY_4CLK_gc = (0x04<<0),
EBI_RPDLY_5CLK_gc = (0x05<<0),
EBI_RPDLY_6CLK_gc = (0x06<<0),
EBI_RPDLY_7CLK_gc = (0x07<<0),
EBI_RPDLY_0CLK_gc = (0x00<<0),
EBI_RPDLY_1CLK_gc = (0x01<<0),
EBI_RPDLY_2CLK_gc = (0x02<<0),
EBI_RPDLY_3CLK_gc = (0x03<<0),
EBI_RPDLY_4CLK_gc = (0x04<<0),
EBI_RPDLY_5CLK_gc = (0x05<<0),
EBI_RPDLY_6CLK_gc = (0x06<<0),
EBI_RPDLY_7CLK_gc = (0x07<<0),
EBI_RPDLY_0CLK_gc = (0x00<<0),
EBI_RPDLY_1CLK_gc = (0x01<<0),
EBI_RPDLY_2CLK_gc = (0x02<<0),
EBI_RPDLY_3CLK_gc = (0x03<<0),
EBI_RPDLY_4CLK_gc = (0x04<<0),
EBI_RPDLY_5CLK_gc = (0x05<<0),
EBI_RPDLY_6CLK_gc = (0x06<<0),
EBI_RPDLY_7CLK_gc = (0x07<<0),
EBI_RPDLY_0CLK_gc = (0x00<<0),
EBI_RPDLY_1CLK_gc = (0x01<<0),
EBI_RPDLY_2CLK_gc = (0x02<<0),
EBI_RPDLY_3CLK_gc = (0x03<<0),
EBI_RPDLY_4CLK_gc = (0x04<<0),
EBI_RPDLY_5CLK_gc = (0x05<<0),
EBI_RPDLY_6CLK_gc = (0x06<<0),
EBI_RPDLY_7CLK_gc = (0x07<<0),
EBI_RPDLY_0CLK_gc = (0x00<<0),
EBI_RPDLY_1CLK_gc = (0x01<<0),
EBI_RPDLY_2CLK_gc = (0x02<<0),
EBI_RPDLY_3CLK_gc = (0x03<<0),
EBI_RPDLY_4CLK_gc = (0x04<<0),
EBI_RPDLY_5CLK_gc = (0x05<<0),
EBI_RPDLY_6CLK_gc = (0x06<<0),
EBI_RPDLY_7CLK_gc = (0x07<<0),
EBI_RPDLY_0CLK_gc = (0x00<<0),
EBI_RPDLY_1CLK_gc = (0x01<<0),
EBI_RPDLY_2CLK_gc = (0x02<<0),
EBI_RPDLY_3CLK_gc = (0x03<<0),
EBI_RPDLY_4CLK_gc = (0x04<<0),
EBI_RPDLY_5CLK_gc = (0x05<<0),
EBI_RPDLY_6CLK_gc = (0x06<<0),
EBI_RPDLY_7CLK_gc = (0x07<<0),
EBI_RPDLY_0CLK_gc = (0x00<<0),
EBI_RPDLY_1CLK_gc = (0x01<<0),
EBI_RPDLY_2CLK_gc = (0x02<<0),
EBI_RPDLY_3CLK_gc = (0x03<<0),
EBI_RPDLY_4CLK_gc = (0x04<<0),
EBI_RPDLY_5CLK_gc = (0x05<<0),
EBI_RPDLY_6CLK_gc = (0x06<<0),
EBI_RPDLY_7CLK_gc = (0x07<<0),
EBI_RPDLY_0CLK_gc = (0x00<<0),
EBI_RPDLY_1CLK_gc = (0x01<<0),
EBI_RPDLY_2CLK_gc = (0x02<<0),
EBI_RPDLY_3CLK_gc = (0x03<<0),
EBI_RPDLY_4CLK_gc = (0x04<<0),
EBI_RPDLY_5CLK_gc = (0x05<<0),
EBI_RPDLY_6CLK_gc = (0x06<<0),
EBI_RPDLY_7CLK_gc = (0x07<<0)
} |
|
enum | EBI_WRDLY_enum {
EBI_WRDLY_0CLK_gc = (0x00<<6),
EBI_WRDLY_1CLK_gc = (0x01<<6),
EBI_WRDLY_2CLK_gc = (0x02<<6),
EBI_WRDLY_3CLK_gc = (0x03<<6),
EBI_WRDLY_0CLK_gc = (0x00<<6),
EBI_WRDLY_1CLK_gc = (0x01<<6),
EBI_WRDLY_2CLK_gc = (0x02<<6),
EBI_WRDLY_3CLK_gc = (0x03<<6),
EBI_WRDLY_0CLK_gc = (0x00<<6),
EBI_WRDLY_1CLK_gc = (0x01<<6),
EBI_WRDLY_2CLK_gc = (0x02<<6),
EBI_WRDLY_3CLK_gc = (0x03<<6),
EBI_WRDLY_0CLK_gc = (0x00<<6),
EBI_WRDLY_1CLK_gc = (0x01<<6),
EBI_WRDLY_2CLK_gc = (0x02<<6),
EBI_WRDLY_3CLK_gc = (0x03<<6),
EBI_WRDLY_0CLK_gc = (0x00<<6),
EBI_WRDLY_1CLK_gc = (0x01<<6),
EBI_WRDLY_2CLK_gc = (0x02<<6),
EBI_WRDLY_3CLK_gc = (0x03<<6),
EBI_WRDLY_0CLK_gc = (0x00<<6),
EBI_WRDLY_1CLK_gc = (0x01<<6),
EBI_WRDLY_2CLK_gc = (0x02<<6),
EBI_WRDLY_3CLK_gc = (0x03<<6),
EBI_WRDLY_0CLK_gc = (0x00<<6),
EBI_WRDLY_1CLK_gc = (0x01<<6),
EBI_WRDLY_2CLK_gc = (0x02<<6),
EBI_WRDLY_3CLK_gc = (0x03<<6),
EBI_WRDLY_0CLK_gc = (0x00<<6),
EBI_WRDLY_1CLK_gc = (0x01<<6),
EBI_WRDLY_2CLK_gc = (0x02<<6),
EBI_WRDLY_3CLK_gc = (0x03<<6),
EBI_WRDLY_0CLK_gc = (0x00<<6),
EBI_WRDLY_1CLK_gc = (0x01<<6),
EBI_WRDLY_2CLK_gc = (0x02<<6),
EBI_WRDLY_3CLK_gc = (0x03<<6),
EBI_WRDLY_0CLK_gc = (0x00<<6),
EBI_WRDLY_1CLK_gc = (0x01<<6),
EBI_WRDLY_2CLK_gc = (0x02<<6),
EBI_WRDLY_3CLK_gc = (0x03<<6),
EBI_WRDLY_0CLK_gc = (0x00<<6),
EBI_WRDLY_1CLK_gc = (0x01<<6),
EBI_WRDLY_2CLK_gc = (0x02<<6),
EBI_WRDLY_3CLK_gc = (0x03<<6),
EBI_WRDLY_0CLK_gc = (0x00<<6),
EBI_WRDLY_1CLK_gc = (0x01<<6),
EBI_WRDLY_2CLK_gc = (0x02<<6),
EBI_WRDLY_3CLK_gc = (0x03<<6),
EBI_WRDLY_0CLK_gc = (0x00<<6),
EBI_WRDLY_1CLK_gc = (0x01<<6),
EBI_WRDLY_2CLK_gc = (0x02<<6),
EBI_WRDLY_3CLK_gc = (0x03<<6),
EBI_WRDLY_0CLK_gc = (0x00<<6),
EBI_WRDLY_1CLK_gc = (0x01<<6),
EBI_WRDLY_2CLK_gc = (0x02<<6),
EBI_WRDLY_3CLK_gc = (0x03<<6),
EBI_WRDLY_0CLK_gc = (0x00<<6),
EBI_WRDLY_1CLK_gc = (0x01<<6),
EBI_WRDLY_2CLK_gc = (0x02<<6),
EBI_WRDLY_3CLK_gc = (0x03<<6)
} |
|
enum | EBI_ESRDLY_enum {
EBI_ESRDLY_0CLK_gc = (0x00<<3),
EBI_ESRDLY_1CLK_gc = (0x01<<3),
EBI_ESRDLY_2CLK_gc = (0x02<<3),
EBI_ESRDLY_3CLK_gc = (0x03<<3),
EBI_ESRDLY_4CLK_gc = (0x04<<3),
EBI_ESRDLY_5CLK_gc = (0x05<<3),
EBI_ESRDLY_6CLK_gc = (0x06<<3),
EBI_ESRDLY_7CLK_gc = (0x07<<3),
EBI_ESRDLY_0CLK_gc = (0x00<<3),
EBI_ESRDLY_1CLK_gc = (0x01<<3),
EBI_ESRDLY_2CLK_gc = (0x02<<3),
EBI_ESRDLY_3CLK_gc = (0x03<<3),
EBI_ESRDLY_4CLK_gc = (0x04<<3),
EBI_ESRDLY_5CLK_gc = (0x05<<3),
EBI_ESRDLY_6CLK_gc = (0x06<<3),
EBI_ESRDLY_7CLK_gc = (0x07<<3),
EBI_ESRDLY_0CLK_gc = (0x00<<3),
EBI_ESRDLY_1CLK_gc = (0x01<<3),
EBI_ESRDLY_2CLK_gc = (0x02<<3),
EBI_ESRDLY_3CLK_gc = (0x03<<3),
EBI_ESRDLY_4CLK_gc = (0x04<<3),
EBI_ESRDLY_5CLK_gc = (0x05<<3),
EBI_ESRDLY_6CLK_gc = (0x06<<3),
EBI_ESRDLY_7CLK_gc = (0x07<<3),
EBI_ESRDLY_0CLK_gc = (0x00<<3),
EBI_ESRDLY_1CLK_gc = (0x01<<3),
EBI_ESRDLY_2CLK_gc = (0x02<<3),
EBI_ESRDLY_3CLK_gc = (0x03<<3),
EBI_ESRDLY_4CLK_gc = (0x04<<3),
EBI_ESRDLY_5CLK_gc = (0x05<<3),
EBI_ESRDLY_6CLK_gc = (0x06<<3),
EBI_ESRDLY_7CLK_gc = (0x07<<3),
EBI_ESRDLY_0CLK_gc = (0x00<<3),
EBI_ESRDLY_1CLK_gc = (0x01<<3),
EBI_ESRDLY_2CLK_gc = (0x02<<3),
EBI_ESRDLY_3CLK_gc = (0x03<<3),
EBI_ESRDLY_4CLK_gc = (0x04<<3),
EBI_ESRDLY_5CLK_gc = (0x05<<3),
EBI_ESRDLY_6CLK_gc = (0x06<<3),
EBI_ESRDLY_7CLK_gc = (0x07<<3),
EBI_ESRDLY_0CLK_gc = (0x00<<3),
EBI_ESRDLY_1CLK_gc = (0x01<<3),
EBI_ESRDLY_2CLK_gc = (0x02<<3),
EBI_ESRDLY_3CLK_gc = (0x03<<3),
EBI_ESRDLY_4CLK_gc = (0x04<<3),
EBI_ESRDLY_5CLK_gc = (0x05<<3),
EBI_ESRDLY_6CLK_gc = (0x06<<3),
EBI_ESRDLY_7CLK_gc = (0x07<<3),
EBI_ESRDLY_0CLK_gc = (0x00<<3),
EBI_ESRDLY_1CLK_gc = (0x01<<3),
EBI_ESRDLY_2CLK_gc = (0x02<<3),
EBI_ESRDLY_3CLK_gc = (0x03<<3),
EBI_ESRDLY_4CLK_gc = (0x04<<3),
EBI_ESRDLY_5CLK_gc = (0x05<<3),
EBI_ESRDLY_6CLK_gc = (0x06<<3),
EBI_ESRDLY_7CLK_gc = (0x07<<3),
EBI_ESRDLY_0CLK_gc = (0x00<<3),
EBI_ESRDLY_1CLK_gc = (0x01<<3),
EBI_ESRDLY_2CLK_gc = (0x02<<3),
EBI_ESRDLY_3CLK_gc = (0x03<<3),
EBI_ESRDLY_4CLK_gc = (0x04<<3),
EBI_ESRDLY_5CLK_gc = (0x05<<3),
EBI_ESRDLY_6CLK_gc = (0x06<<3),
EBI_ESRDLY_7CLK_gc = (0x07<<3),
EBI_ESRDLY_0CLK_gc = (0x00<<3),
EBI_ESRDLY_1CLK_gc = (0x01<<3),
EBI_ESRDLY_2CLK_gc = (0x02<<3),
EBI_ESRDLY_3CLK_gc = (0x03<<3),
EBI_ESRDLY_4CLK_gc = (0x04<<3),
EBI_ESRDLY_5CLK_gc = (0x05<<3),
EBI_ESRDLY_6CLK_gc = (0x06<<3),
EBI_ESRDLY_7CLK_gc = (0x07<<3),
EBI_ESRDLY_0CLK_gc = (0x00<<3),
EBI_ESRDLY_1CLK_gc = (0x01<<3),
EBI_ESRDLY_2CLK_gc = (0x02<<3),
EBI_ESRDLY_3CLK_gc = (0x03<<3),
EBI_ESRDLY_4CLK_gc = (0x04<<3),
EBI_ESRDLY_5CLK_gc = (0x05<<3),
EBI_ESRDLY_6CLK_gc = (0x06<<3),
EBI_ESRDLY_7CLK_gc = (0x07<<3),
EBI_ESRDLY_0CLK_gc = (0x00<<3),
EBI_ESRDLY_1CLK_gc = (0x01<<3),
EBI_ESRDLY_2CLK_gc = (0x02<<3),
EBI_ESRDLY_3CLK_gc = (0x03<<3),
EBI_ESRDLY_4CLK_gc = (0x04<<3),
EBI_ESRDLY_5CLK_gc = (0x05<<3),
EBI_ESRDLY_6CLK_gc = (0x06<<3),
EBI_ESRDLY_7CLK_gc = (0x07<<3),
EBI_ESRDLY_0CLK_gc = (0x00<<3),
EBI_ESRDLY_1CLK_gc = (0x01<<3),
EBI_ESRDLY_2CLK_gc = (0x02<<3),
EBI_ESRDLY_3CLK_gc = (0x03<<3),
EBI_ESRDLY_4CLK_gc = (0x04<<3),
EBI_ESRDLY_5CLK_gc = (0x05<<3),
EBI_ESRDLY_6CLK_gc = (0x06<<3),
EBI_ESRDLY_7CLK_gc = (0x07<<3),
EBI_ESRDLY_0CLK_gc = (0x00<<3),
EBI_ESRDLY_1CLK_gc = (0x01<<3),
EBI_ESRDLY_2CLK_gc = (0x02<<3),
EBI_ESRDLY_3CLK_gc = (0x03<<3),
EBI_ESRDLY_4CLK_gc = (0x04<<3),
EBI_ESRDLY_5CLK_gc = (0x05<<3),
EBI_ESRDLY_6CLK_gc = (0x06<<3),
EBI_ESRDLY_7CLK_gc = (0x07<<3),
EBI_ESRDLY_0CLK_gc = (0x00<<3),
EBI_ESRDLY_1CLK_gc = (0x01<<3),
EBI_ESRDLY_2CLK_gc = (0x02<<3),
EBI_ESRDLY_3CLK_gc = (0x03<<3),
EBI_ESRDLY_4CLK_gc = (0x04<<3),
EBI_ESRDLY_5CLK_gc = (0x05<<3),
EBI_ESRDLY_6CLK_gc = (0x06<<3),
EBI_ESRDLY_7CLK_gc = (0x07<<3),
EBI_ESRDLY_0CLK_gc = (0x00<<3),
EBI_ESRDLY_1CLK_gc = (0x01<<3),
EBI_ESRDLY_2CLK_gc = (0x02<<3),
EBI_ESRDLY_3CLK_gc = (0x03<<3),
EBI_ESRDLY_4CLK_gc = (0x04<<3),
EBI_ESRDLY_5CLK_gc = (0x05<<3),
EBI_ESRDLY_6CLK_gc = (0x06<<3),
EBI_ESRDLY_7CLK_gc = (0x07<<3)
} |
|
enum | EBI_ROWCOLDLY_enum {
EBI_ROWCOLDLY_0CLK_gc = (0x00<<0),
EBI_ROWCOLDLY_1CLK_gc = (0x01<<0),
EBI_ROWCOLDLY_2CLK_gc = (0x02<<0),
EBI_ROWCOLDLY_3CLK_gc = (0x03<<0),
EBI_ROWCOLDLY_4CLK_gc = (0x04<<0),
EBI_ROWCOLDLY_5CLK_gc = (0x05<<0),
EBI_ROWCOLDLY_6CLK_gc = (0x06<<0),
EBI_ROWCOLDLY_7CLK_gc = (0x07<<0),
EBI_ROWCOLDLY_0CLK_gc = (0x00<<0),
EBI_ROWCOLDLY_1CLK_gc = (0x01<<0),
EBI_ROWCOLDLY_2CLK_gc = (0x02<<0),
EBI_ROWCOLDLY_3CLK_gc = (0x03<<0),
EBI_ROWCOLDLY_4CLK_gc = (0x04<<0),
EBI_ROWCOLDLY_5CLK_gc = (0x05<<0),
EBI_ROWCOLDLY_6CLK_gc = (0x06<<0),
EBI_ROWCOLDLY_7CLK_gc = (0x07<<0),
EBI_ROWCOLDLY_0CLK_gc = (0x00<<0),
EBI_ROWCOLDLY_1CLK_gc = (0x01<<0),
EBI_ROWCOLDLY_2CLK_gc = (0x02<<0),
EBI_ROWCOLDLY_3CLK_gc = (0x03<<0),
EBI_ROWCOLDLY_4CLK_gc = (0x04<<0),
EBI_ROWCOLDLY_5CLK_gc = (0x05<<0),
EBI_ROWCOLDLY_6CLK_gc = (0x06<<0),
EBI_ROWCOLDLY_7CLK_gc = (0x07<<0),
EBI_ROWCOLDLY_0CLK_gc = (0x00<<0),
EBI_ROWCOLDLY_1CLK_gc = (0x01<<0),
EBI_ROWCOLDLY_2CLK_gc = (0x02<<0),
EBI_ROWCOLDLY_3CLK_gc = (0x03<<0),
EBI_ROWCOLDLY_4CLK_gc = (0x04<<0),
EBI_ROWCOLDLY_5CLK_gc = (0x05<<0),
EBI_ROWCOLDLY_6CLK_gc = (0x06<<0),
EBI_ROWCOLDLY_7CLK_gc = (0x07<<0),
EBI_ROWCOLDLY_0CLK_gc = (0x00<<0),
EBI_ROWCOLDLY_1CLK_gc = (0x01<<0),
EBI_ROWCOLDLY_2CLK_gc = (0x02<<0),
EBI_ROWCOLDLY_3CLK_gc = (0x03<<0),
EBI_ROWCOLDLY_4CLK_gc = (0x04<<0),
EBI_ROWCOLDLY_5CLK_gc = (0x05<<0),
EBI_ROWCOLDLY_6CLK_gc = (0x06<<0),
EBI_ROWCOLDLY_7CLK_gc = (0x07<<0),
EBI_ROWCOLDLY_0CLK_gc = (0x00<<0),
EBI_ROWCOLDLY_1CLK_gc = (0x01<<0),
EBI_ROWCOLDLY_2CLK_gc = (0x02<<0),
EBI_ROWCOLDLY_3CLK_gc = (0x03<<0),
EBI_ROWCOLDLY_4CLK_gc = (0x04<<0),
EBI_ROWCOLDLY_5CLK_gc = (0x05<<0),
EBI_ROWCOLDLY_6CLK_gc = (0x06<<0),
EBI_ROWCOLDLY_7CLK_gc = (0x07<<0),
EBI_ROWCOLDLY_0CLK_gc = (0x00<<0),
EBI_ROWCOLDLY_1CLK_gc = (0x01<<0),
EBI_ROWCOLDLY_2CLK_gc = (0x02<<0),
EBI_ROWCOLDLY_3CLK_gc = (0x03<<0),
EBI_ROWCOLDLY_4CLK_gc = (0x04<<0),
EBI_ROWCOLDLY_5CLK_gc = (0x05<<0),
EBI_ROWCOLDLY_6CLK_gc = (0x06<<0),
EBI_ROWCOLDLY_7CLK_gc = (0x07<<0),
EBI_ROWCOLDLY_0CLK_gc = (0x00<<0),
EBI_ROWCOLDLY_1CLK_gc = (0x01<<0),
EBI_ROWCOLDLY_2CLK_gc = (0x02<<0),
EBI_ROWCOLDLY_3CLK_gc = (0x03<<0),
EBI_ROWCOLDLY_4CLK_gc = (0x04<<0),
EBI_ROWCOLDLY_5CLK_gc = (0x05<<0),
EBI_ROWCOLDLY_6CLK_gc = (0x06<<0),
EBI_ROWCOLDLY_7CLK_gc = (0x07<<0),
EBI_ROWCOLDLY_0CLK_gc = (0x00<<0),
EBI_ROWCOLDLY_1CLK_gc = (0x01<<0),
EBI_ROWCOLDLY_2CLK_gc = (0x02<<0),
EBI_ROWCOLDLY_3CLK_gc = (0x03<<0),
EBI_ROWCOLDLY_4CLK_gc = (0x04<<0),
EBI_ROWCOLDLY_5CLK_gc = (0x05<<0),
EBI_ROWCOLDLY_6CLK_gc = (0x06<<0),
EBI_ROWCOLDLY_7CLK_gc = (0x07<<0),
EBI_ROWCOLDLY_0CLK_gc = (0x00<<0),
EBI_ROWCOLDLY_1CLK_gc = (0x01<<0),
EBI_ROWCOLDLY_2CLK_gc = (0x02<<0),
EBI_ROWCOLDLY_3CLK_gc = (0x03<<0),
EBI_ROWCOLDLY_4CLK_gc = (0x04<<0),
EBI_ROWCOLDLY_5CLK_gc = (0x05<<0),
EBI_ROWCOLDLY_6CLK_gc = (0x06<<0),
EBI_ROWCOLDLY_7CLK_gc = (0x07<<0),
EBI_ROWCOLDLY_0CLK_gc = (0x00<<0),
EBI_ROWCOLDLY_1CLK_gc = (0x01<<0),
EBI_ROWCOLDLY_2CLK_gc = (0x02<<0),
EBI_ROWCOLDLY_3CLK_gc = (0x03<<0),
EBI_ROWCOLDLY_4CLK_gc = (0x04<<0),
EBI_ROWCOLDLY_5CLK_gc = (0x05<<0),
EBI_ROWCOLDLY_6CLK_gc = (0x06<<0),
EBI_ROWCOLDLY_7CLK_gc = (0x07<<0),
EBI_ROWCOLDLY_0CLK_gc = (0x00<<0),
EBI_ROWCOLDLY_1CLK_gc = (0x01<<0),
EBI_ROWCOLDLY_2CLK_gc = (0x02<<0),
EBI_ROWCOLDLY_3CLK_gc = (0x03<<0),
EBI_ROWCOLDLY_4CLK_gc = (0x04<<0),
EBI_ROWCOLDLY_5CLK_gc = (0x05<<0),
EBI_ROWCOLDLY_6CLK_gc = (0x06<<0),
EBI_ROWCOLDLY_7CLK_gc = (0x07<<0),
EBI_ROWCOLDLY_0CLK_gc = (0x00<<0),
EBI_ROWCOLDLY_1CLK_gc = (0x01<<0),
EBI_ROWCOLDLY_2CLK_gc = (0x02<<0),
EBI_ROWCOLDLY_3CLK_gc = (0x03<<0),
EBI_ROWCOLDLY_4CLK_gc = (0x04<<0),
EBI_ROWCOLDLY_5CLK_gc = (0x05<<0),
EBI_ROWCOLDLY_6CLK_gc = (0x06<<0),
EBI_ROWCOLDLY_7CLK_gc = (0x07<<0),
EBI_ROWCOLDLY_0CLK_gc = (0x00<<0),
EBI_ROWCOLDLY_1CLK_gc = (0x01<<0),
EBI_ROWCOLDLY_2CLK_gc = (0x02<<0),
EBI_ROWCOLDLY_3CLK_gc = (0x03<<0),
EBI_ROWCOLDLY_4CLK_gc = (0x04<<0),
EBI_ROWCOLDLY_5CLK_gc = (0x05<<0),
EBI_ROWCOLDLY_6CLK_gc = (0x06<<0),
EBI_ROWCOLDLY_7CLK_gc = (0x07<<0),
EBI_ROWCOLDLY_0CLK_gc = (0x00<<0),
EBI_ROWCOLDLY_1CLK_gc = (0x01<<0),
EBI_ROWCOLDLY_2CLK_gc = (0x02<<0),
EBI_ROWCOLDLY_3CLK_gc = (0x03<<0),
EBI_ROWCOLDLY_4CLK_gc = (0x04<<0),
EBI_ROWCOLDLY_5CLK_gc = (0x05<<0),
EBI_ROWCOLDLY_6CLK_gc = (0x06<<0),
EBI_ROWCOLDLY_7CLK_gc = (0x07<<0)
} |
|
enum | TWI_MASTER_INTLVL_enum {
TWI_MASTER_INTLVL_OFF_gc = (0x00<<6),
TWI_MASTER_INTLVL_LO_gc = (0x01<<6),
TWI_MASTER_INTLVL_MED_gc = (0x02<<6),
TWI_MASTER_INTLVL_HI_gc = (0x03<<6),
TWI_MASTER_INTLVL_OFF_gc = (0x00<<6),
TWI_MASTER_INTLVL_LO_gc = (0x01<<6),
TWI_MASTER_INTLVL_MED_gc = (0x02<<6),
TWI_MASTER_INTLVL_HI_gc = (0x03<<6),
TWI_MASTER_INTLVL_OFF_gc = (0x00<<6),
TWI_MASTER_INTLVL_LO_gc = (0x01<<6),
TWI_MASTER_INTLVL_MED_gc = (0x02<<6),
TWI_MASTER_INTLVL_HI_gc = (0x03<<6),
TWI_MASTER_INTLVL_OFF_gc = (0x00<<6),
TWI_MASTER_INTLVL_LO_gc = (0x01<<6),
TWI_MASTER_INTLVL_MED_gc = (0x02<<6),
TWI_MASTER_INTLVL_HI_gc = (0x03<<6),
TWI_MASTER_INTLVL_OFF_gc = (0x00<<6),
TWI_MASTER_INTLVL_LO_gc = (0x01<<6),
TWI_MASTER_INTLVL_MED_gc = (0x02<<6),
TWI_MASTER_INTLVL_HI_gc = (0x03<<6),
TWI_MASTER_INTLVL_OFF_gc = (0x00<<6),
TWI_MASTER_INTLVL_LO_gc = (0x01<<6),
TWI_MASTER_INTLVL_MED_gc = (0x02<<6),
TWI_MASTER_INTLVL_HI_gc = (0x03<<6),
TWI_MASTER_INTLVL_OFF_gc = (0x00<<6),
TWI_MASTER_INTLVL_LO_gc = (0x01<<6),
TWI_MASTER_INTLVL_MED_gc = (0x02<<6),
TWI_MASTER_INTLVL_HI_gc = (0x03<<6),
TWI_MASTER_INTLVL_OFF_gc = (0x00<<6),
TWI_MASTER_INTLVL_LO_gc = (0x01<<6),
TWI_MASTER_INTLVL_MED_gc = (0x02<<6),
TWI_MASTER_INTLVL_HI_gc = (0x03<<6),
TWI_MASTER_INTLVL_OFF_gc = (0x00<<6),
TWI_MASTER_INTLVL_LO_gc = (0x01<<6),
TWI_MASTER_INTLVL_MED_gc = (0x02<<6),
TWI_MASTER_INTLVL_HI_gc = (0x03<<6),
TWI_MASTER_INTLVL_OFF_gc = (0x00<<6),
TWI_MASTER_INTLVL_LO_gc = (0x01<<6),
TWI_MASTER_INTLVL_MED_gc = (0x02<<6),
TWI_MASTER_INTLVL_HI_gc = (0x03<<6),
TWI_MASTER_INTLVL_OFF_gc = (0x00<<6),
TWI_MASTER_INTLVL_LO_gc = (0x01<<6),
TWI_MASTER_INTLVL_MED_gc = (0x02<<6),
TWI_MASTER_INTLVL_HI_gc = (0x03<<6),
TWI_MASTER_INTLVL_OFF_gc = (0x00<<6),
TWI_MASTER_INTLVL_LO_gc = (0x01<<6),
TWI_MASTER_INTLVL_MED_gc = (0x02<<6),
TWI_MASTER_INTLVL_HI_gc = (0x03<<6),
TWI_MASTER_INTLVL_OFF_gc = (0x00<<6),
TWI_MASTER_INTLVL_LO_gc = (0x01<<6),
TWI_MASTER_INTLVL_MED_gc = (0x02<<6),
TWI_MASTER_INTLVL_HI_gc = (0x03<<6),
TWI_MASTER_INTLVL_OFF_gc = (0x00<<6),
TWI_MASTER_INTLVL_LO_gc = (0x01<<6),
TWI_MASTER_INTLVL_MED_gc = (0x02<<6),
TWI_MASTER_INTLVL_HI_gc = (0x03<<6),
TWI_MASTER_INTLVL_OFF_gc = (0x00<<6),
TWI_MASTER_INTLVL_LO_gc = (0x01<<6),
TWI_MASTER_INTLVL_MED_gc = (0x02<<6),
TWI_MASTER_INTLVL_HI_gc = (0x03<<6)
} |
|
enum | TWI_MASTER_TIMEOUT_enum {
TWI_MASTER_TIMEOUT_DISABLED_gc = (0x00<<2),
TWI_MASTER_TIMEOUT_50US_gc = (0x01<<2),
TWI_MASTER_TIMEOUT_100US_gc = (0x02<<2),
TWI_MASTER_TIMEOUT_200US_gc = (0x03<<2),
TWI_MASTER_TIMEOUT_DISABLED_gc = (0x00<<2),
TWI_MASTER_TIMEOUT_50US_gc = (0x01<<2),
TWI_MASTER_TIMEOUT_100US_gc = (0x02<<2),
TWI_MASTER_TIMEOUT_200US_gc = (0x03<<2),
TWI_MASTER_TIMEOUT_DISABLED_gc = (0x00<<2),
TWI_MASTER_TIMEOUT_50US_gc = (0x01<<2),
TWI_MASTER_TIMEOUT_100US_gc = (0x02<<2),
TWI_MASTER_TIMEOUT_200US_gc = (0x03<<2),
TWI_MASTER_TIMEOUT_DISABLED_gc = (0x00<<2),
TWI_MASTER_TIMEOUT_50US_gc = (0x01<<2),
TWI_MASTER_TIMEOUT_100US_gc = (0x02<<2),
TWI_MASTER_TIMEOUT_200US_gc = (0x03<<2),
TWI_MASTER_TIMEOUT_DISABLED_gc = (0x00<<2),
TWI_MASTER_TIMEOUT_50US_gc = (0x01<<2),
TWI_MASTER_TIMEOUT_100US_gc = (0x02<<2),
TWI_MASTER_TIMEOUT_200US_gc = (0x03<<2),
TWI_MASTER_TIMEOUT_DISABLED_gc = (0x00<<2),
TWI_MASTER_TIMEOUT_50US_gc = (0x01<<2),
TWI_MASTER_TIMEOUT_100US_gc = (0x02<<2),
TWI_MASTER_TIMEOUT_200US_gc = (0x03<<2),
TWI_MASTER_TIMEOUT_DISABLED_gc = (0x00<<2),
TWI_MASTER_TIMEOUT_50US_gc = (0x01<<2),
TWI_MASTER_TIMEOUT_100US_gc = (0x02<<2),
TWI_MASTER_TIMEOUT_200US_gc = (0x03<<2),
TWI_MASTER_TIMEOUT_DISABLED_gc = (0x00<<2),
TWI_MASTER_TIMEOUT_50US_gc = (0x01<<2),
TWI_MASTER_TIMEOUT_100US_gc = (0x02<<2),
TWI_MASTER_TIMEOUT_200US_gc = (0x03<<2),
TWI_MASTER_TIMEOUT_DISABLED_gc = (0x00<<2),
TWI_MASTER_TIMEOUT_50US_gc = (0x01<<2),
TWI_MASTER_TIMEOUT_100US_gc = (0x02<<2),
TWI_MASTER_TIMEOUT_200US_gc = (0x03<<2),
TWI_MASTER_TIMEOUT_DISABLED_gc = (0x00<<2),
TWI_MASTER_TIMEOUT_50US_gc = (0x01<<2),
TWI_MASTER_TIMEOUT_100US_gc = (0x02<<2),
TWI_MASTER_TIMEOUT_200US_gc = (0x03<<2),
TWI_MASTER_TIMEOUT_DISABLED_gc = (0x00<<2),
TWI_MASTER_TIMEOUT_50US_gc = (0x01<<2),
TWI_MASTER_TIMEOUT_100US_gc = (0x02<<2),
TWI_MASTER_TIMEOUT_200US_gc = (0x03<<2),
TWI_MASTER_TIMEOUT_DISABLED_gc = (0x00<<2),
TWI_MASTER_TIMEOUT_50US_gc = (0x01<<2),
TWI_MASTER_TIMEOUT_100US_gc = (0x02<<2),
TWI_MASTER_TIMEOUT_200US_gc = (0x03<<2),
TWI_MASTER_TIMEOUT_DISABLED_gc = (0x00<<2),
TWI_MASTER_TIMEOUT_50US_gc = (0x01<<2),
TWI_MASTER_TIMEOUT_100US_gc = (0x02<<2),
TWI_MASTER_TIMEOUT_200US_gc = (0x03<<2),
TWI_MASTER_TIMEOUT_DISABLED_gc = (0x00<<2),
TWI_MASTER_TIMEOUT_50US_gc = (0x01<<2),
TWI_MASTER_TIMEOUT_100US_gc = (0x02<<2),
TWI_MASTER_TIMEOUT_200US_gc = (0x03<<2),
TWI_MASTER_TIMEOUT_DISABLED_gc = (0x00<<2),
TWI_MASTER_TIMEOUT_50US_gc = (0x01<<2),
TWI_MASTER_TIMEOUT_100US_gc = (0x02<<2),
TWI_MASTER_TIMEOUT_200US_gc = (0x03<<2)
} |
|
enum | TWI_MASTER_CMD_enum {
TWI_MASTER_CMD_NOACT_gc = (0x00<<0),
TWI_MASTER_CMD_REPSTART_gc = (0x01<<0),
TWI_MASTER_CMD_RECVTRANS_gc = (0x02<<0),
TWI_MASTER_CMD_STOP_gc = (0x03<<0),
TWI_MASTER_CMD_NOACT_gc = (0x00<<0),
TWI_MASTER_CMD_REPSTART_gc = (0x01<<0),
TWI_MASTER_CMD_RECVTRANS_gc = (0x02<<0),
TWI_MASTER_CMD_STOP_gc = (0x03<<0),
TWI_MASTER_CMD_NOACT_gc = (0x00<<0),
TWI_MASTER_CMD_REPSTART_gc = (0x01<<0),
TWI_MASTER_CMD_RECVTRANS_gc = (0x02<<0),
TWI_MASTER_CMD_STOP_gc = (0x03<<0),
TWI_MASTER_CMD_NOACT_gc = (0x00<<0),
TWI_MASTER_CMD_REPSTART_gc = (0x01<<0),
TWI_MASTER_CMD_RECVTRANS_gc = (0x02<<0),
TWI_MASTER_CMD_STOP_gc = (0x03<<0),
TWI_MASTER_CMD_NOACT_gc = (0x00<<0),
TWI_MASTER_CMD_REPSTART_gc = (0x01<<0),
TWI_MASTER_CMD_RECVTRANS_gc = (0x02<<0),
TWI_MASTER_CMD_STOP_gc = (0x03<<0),
TWI_MASTER_CMD_NOACT_gc = (0x00<<0),
TWI_MASTER_CMD_REPSTART_gc = (0x01<<0),
TWI_MASTER_CMD_RECVTRANS_gc = (0x02<<0),
TWI_MASTER_CMD_STOP_gc = (0x03<<0),
TWI_MASTER_CMD_NOACT_gc = (0x00<<0),
TWI_MASTER_CMD_REPSTART_gc = (0x01<<0),
TWI_MASTER_CMD_RECVTRANS_gc = (0x02<<0),
TWI_MASTER_CMD_STOP_gc = (0x03<<0),
TWI_MASTER_CMD_NOACT_gc = (0x00<<0),
TWI_MASTER_CMD_REPSTART_gc = (0x01<<0),
TWI_MASTER_CMD_RECVTRANS_gc = (0x02<<0),
TWI_MASTER_CMD_STOP_gc = (0x03<<0),
TWI_MASTER_CMD_NOACT_gc = (0x00<<0),
TWI_MASTER_CMD_REPSTART_gc = (0x01<<0),
TWI_MASTER_CMD_RECVTRANS_gc = (0x02<<0),
TWI_MASTER_CMD_STOP_gc = (0x03<<0),
TWI_MASTER_CMD_NOACT_gc = (0x00<<0),
TWI_MASTER_CMD_REPSTART_gc = (0x01<<0),
TWI_MASTER_CMD_RECVTRANS_gc = (0x02<<0),
TWI_MASTER_CMD_STOP_gc = (0x03<<0),
TWI_MASTER_CMD_NOACT_gc = (0x00<<0),
TWI_MASTER_CMD_REPSTART_gc = (0x01<<0),
TWI_MASTER_CMD_RECVTRANS_gc = (0x02<<0),
TWI_MASTER_CMD_STOP_gc = (0x03<<0),
TWI_MASTER_CMD_NOACT_gc = (0x00<<0),
TWI_MASTER_CMD_REPSTART_gc = (0x01<<0),
TWI_MASTER_CMD_RECVTRANS_gc = (0x02<<0),
TWI_MASTER_CMD_STOP_gc = (0x03<<0),
TWI_MASTER_CMD_NOACT_gc = (0x00<<0),
TWI_MASTER_CMD_REPSTART_gc = (0x01<<0),
TWI_MASTER_CMD_RECVTRANS_gc = (0x02<<0),
TWI_MASTER_CMD_STOP_gc = (0x03<<0),
TWI_MASTER_CMD_NOACT_gc = (0x00<<0),
TWI_MASTER_CMD_REPSTART_gc = (0x01<<0),
TWI_MASTER_CMD_RECVTRANS_gc = (0x02<<0),
TWI_MASTER_CMD_STOP_gc = (0x03<<0),
TWI_MASTER_CMD_NOACT_gc = (0x00<<0),
TWI_MASTER_CMD_REPSTART_gc = (0x01<<0),
TWI_MASTER_CMD_RECVTRANS_gc = (0x02<<0),
TWI_MASTER_CMD_STOP_gc = (0x03<<0)
} |
|
enum | TWI_MASTER_BUSSTATE_enum {
TWI_MASTER_BUSSTATE_UNKNOWN_gc = (0x00<<0),
TWI_MASTER_BUSSTATE_IDLE_gc = (0x01<<0),
TWI_MASTER_BUSSTATE_OWNER_gc = (0x02<<0),
TWI_MASTER_BUSSTATE_BUSY_gc = (0x03<<0),
TWI_MASTER_BUSSTATE_UNKNOWN_gc = (0x00<<0),
TWI_MASTER_BUSSTATE_IDLE_gc = (0x01<<0),
TWI_MASTER_BUSSTATE_OWNER_gc = (0x02<<0),
TWI_MASTER_BUSSTATE_BUSY_gc = (0x03<<0),
TWI_MASTER_BUSSTATE_UNKNOWN_gc = (0x00<<0),
TWI_MASTER_BUSSTATE_IDLE_gc = (0x01<<0),
TWI_MASTER_BUSSTATE_OWNER_gc = (0x02<<0),
TWI_MASTER_BUSSTATE_BUSY_gc = (0x03<<0),
TWI_MASTER_BUSSTATE_UNKNOWN_gc = (0x00<<0),
TWI_MASTER_BUSSTATE_IDLE_gc = (0x01<<0),
TWI_MASTER_BUSSTATE_OWNER_gc = (0x02<<0),
TWI_MASTER_BUSSTATE_BUSY_gc = (0x03<<0),
TWI_MASTER_BUSSTATE_UNKNOWN_gc = (0x00<<0),
TWI_MASTER_BUSSTATE_IDLE_gc = (0x01<<0),
TWI_MASTER_BUSSTATE_OWNER_gc = (0x02<<0),
TWI_MASTER_BUSSTATE_BUSY_gc = (0x03<<0),
TWI_MASTER_BUSSTATE_UNKNOWN_gc = (0x00<<0),
TWI_MASTER_BUSSTATE_IDLE_gc = (0x01<<0),
TWI_MASTER_BUSSTATE_OWNER_gc = (0x02<<0),
TWI_MASTER_BUSSTATE_BUSY_gc = (0x03<<0),
TWI_MASTER_BUSSTATE_UNKNOWN_gc = (0x00<<0),
TWI_MASTER_BUSSTATE_IDLE_gc = (0x01<<0),
TWI_MASTER_BUSSTATE_OWNER_gc = (0x02<<0),
TWI_MASTER_BUSSTATE_BUSY_gc = (0x03<<0),
TWI_MASTER_BUSSTATE_UNKNOWN_gc = (0x00<<0),
TWI_MASTER_BUSSTATE_IDLE_gc = (0x01<<0),
TWI_MASTER_BUSSTATE_OWNER_gc = (0x02<<0),
TWI_MASTER_BUSSTATE_BUSY_gc = (0x03<<0),
TWI_MASTER_BUSSTATE_UNKNOWN_gc = (0x00<<0),
TWI_MASTER_BUSSTATE_IDLE_gc = (0x01<<0),
TWI_MASTER_BUSSTATE_OWNER_gc = (0x02<<0),
TWI_MASTER_BUSSTATE_BUSY_gc = (0x03<<0),
TWI_MASTER_BUSSTATE_UNKNOWN_gc = (0x00<<0),
TWI_MASTER_BUSSTATE_IDLE_gc = (0x01<<0),
TWI_MASTER_BUSSTATE_OWNER_gc = (0x02<<0),
TWI_MASTER_BUSSTATE_BUSY_gc = (0x03<<0),
TWI_MASTER_BUSSTATE_UNKNOWN_gc = (0x00<<0),
TWI_MASTER_BUSSTATE_IDLE_gc = (0x01<<0),
TWI_MASTER_BUSSTATE_OWNER_gc = (0x02<<0),
TWI_MASTER_BUSSTATE_BUSY_gc = (0x03<<0),
TWI_MASTER_BUSSTATE_UNKNOWN_gc = (0x00<<0),
TWI_MASTER_BUSSTATE_IDLE_gc = (0x01<<0),
TWI_MASTER_BUSSTATE_OWNER_gc = (0x02<<0),
TWI_MASTER_BUSSTATE_BUSY_gc = (0x03<<0),
TWI_MASTER_BUSSTATE_UNKNOWN_gc = (0x00<<0),
TWI_MASTER_BUSSTATE_IDLE_gc = (0x01<<0),
TWI_MASTER_BUSSTATE_OWNER_gc = (0x02<<0),
TWI_MASTER_BUSSTATE_BUSY_gc = (0x03<<0),
TWI_MASTER_BUSSTATE_UNKNOWN_gc = (0x00<<0),
TWI_MASTER_BUSSTATE_IDLE_gc = (0x01<<0),
TWI_MASTER_BUSSTATE_OWNER_gc = (0x02<<0),
TWI_MASTER_BUSSTATE_BUSY_gc = (0x03<<0),
TWI_MASTER_BUSSTATE_UNKNOWN_gc = (0x00<<0),
TWI_MASTER_BUSSTATE_IDLE_gc = (0x01<<0),
TWI_MASTER_BUSSTATE_OWNER_gc = (0x02<<0),
TWI_MASTER_BUSSTATE_BUSY_gc = (0x03<<0)
} |
|
enum | TWI_SLAVE_INTLVL_enum {
TWI_SLAVE_INTLVL_OFF_gc = (0x00<<6),
TWI_SLAVE_INTLVL_LO_gc = (0x01<<6),
TWI_SLAVE_INTLVL_MED_gc = (0x02<<6),
TWI_SLAVE_INTLVL_HI_gc = (0x03<<6),
TWI_SLAVE_INTLVL_OFF_gc = (0x00<<6),
TWI_SLAVE_INTLVL_LO_gc = (0x01<<6),
TWI_SLAVE_INTLVL_MED_gc = (0x02<<6),
TWI_SLAVE_INTLVL_HI_gc = (0x03<<6),
TWI_SLAVE_INTLVL_OFF_gc = (0x00<<6),
TWI_SLAVE_INTLVL_LO_gc = (0x01<<6),
TWI_SLAVE_INTLVL_MED_gc = (0x02<<6),
TWI_SLAVE_INTLVL_HI_gc = (0x03<<6),
TWI_SLAVE_INTLVL_OFF_gc = (0x00<<6),
TWI_SLAVE_INTLVL_LO_gc = (0x01<<6),
TWI_SLAVE_INTLVL_MED_gc = (0x02<<6),
TWI_SLAVE_INTLVL_HI_gc = (0x03<<6),
TWI_SLAVE_INTLVL_OFF_gc = (0x00<<6),
TWI_SLAVE_INTLVL_LO_gc = (0x01<<6),
TWI_SLAVE_INTLVL_MED_gc = (0x02<<6),
TWI_SLAVE_INTLVL_HI_gc = (0x03<<6),
TWI_SLAVE_INTLVL_OFF_gc = (0x00<<6),
TWI_SLAVE_INTLVL_LO_gc = (0x01<<6),
TWI_SLAVE_INTLVL_MED_gc = (0x02<<6),
TWI_SLAVE_INTLVL_HI_gc = (0x03<<6),
TWI_SLAVE_INTLVL_OFF_gc = (0x00<<6),
TWI_SLAVE_INTLVL_LO_gc = (0x01<<6),
TWI_SLAVE_INTLVL_MED_gc = (0x02<<6),
TWI_SLAVE_INTLVL_HI_gc = (0x03<<6),
TWI_SLAVE_INTLVL_OFF_gc = (0x00<<6),
TWI_SLAVE_INTLVL_LO_gc = (0x01<<6),
TWI_SLAVE_INTLVL_MED_gc = (0x02<<6),
TWI_SLAVE_INTLVL_HI_gc = (0x03<<6),
TWI_SLAVE_INTLVL_OFF_gc = (0x00<<6),
TWI_SLAVE_INTLVL_LO_gc = (0x01<<6),
TWI_SLAVE_INTLVL_MED_gc = (0x02<<6),
TWI_SLAVE_INTLVL_HI_gc = (0x03<<6),
TWI_SLAVE_INTLVL_OFF_gc = (0x00<<6),
TWI_SLAVE_INTLVL_LO_gc = (0x01<<6),
TWI_SLAVE_INTLVL_MED_gc = (0x02<<6),
TWI_SLAVE_INTLVL_HI_gc = (0x03<<6),
TWI_SLAVE_INTLVL_OFF_gc = (0x00<<6),
TWI_SLAVE_INTLVL_LO_gc = (0x01<<6),
TWI_SLAVE_INTLVL_MED_gc = (0x02<<6),
TWI_SLAVE_INTLVL_HI_gc = (0x03<<6),
TWI_SLAVE_INTLVL_OFF_gc = (0x00<<6),
TWI_SLAVE_INTLVL_LO_gc = (0x01<<6),
TWI_SLAVE_INTLVL_MED_gc = (0x02<<6),
TWI_SLAVE_INTLVL_HI_gc = (0x03<<6),
TWI_SLAVE_INTLVL_OFF_gc = (0x00<<6),
TWI_SLAVE_INTLVL_LO_gc = (0x01<<6),
TWI_SLAVE_INTLVL_MED_gc = (0x02<<6),
TWI_SLAVE_INTLVL_HI_gc = (0x03<<6),
TWI_SLAVE_INTLVL_OFF_gc = (0x00<<6),
TWI_SLAVE_INTLVL_LO_gc = (0x01<<6),
TWI_SLAVE_INTLVL_MED_gc = (0x02<<6),
TWI_SLAVE_INTLVL_HI_gc = (0x03<<6),
TWI_SLAVE_INTLVL_OFF_gc = (0x00<<6),
TWI_SLAVE_INTLVL_LO_gc = (0x01<<6),
TWI_SLAVE_INTLVL_MED_gc = (0x02<<6),
TWI_SLAVE_INTLVL_HI_gc = (0x03<<6)
} |
|
enum | TWI_SLAVE_CMD_enum {
TWI_SLAVE_CMD_NOACT_gc = (0x00<<0),
TWI_SLAVE_CMD_COMPTRANS_gc = (0x02<<0),
TWI_SLAVE_CMD_RESPONSE_gc = (0x03<<0),
TWI_SLAVE_CMD_NOACT_gc = (0x00<<0),
TWI_SLAVE_CMD_COMPTRANS_gc = (0x02<<0),
TWI_SLAVE_CMD_RESPONSE_gc = (0x03<<0),
TWI_SLAVE_CMD_NOACT_gc = (0x00<<0),
TWI_SLAVE_CMD_COMPTRANS_gc = (0x02<<0),
TWI_SLAVE_CMD_RESPONSE_gc = (0x03<<0),
TWI_SLAVE_CMD_NOACT_gc = (0x00<<0),
TWI_SLAVE_CMD_COMPTRANS_gc = (0x02<<0),
TWI_SLAVE_CMD_RESPONSE_gc = (0x03<<0),
TWI_SLAVE_CMD_NOACT_gc = (0x00<<0),
TWI_SLAVE_CMD_COMPTRANS_gc = (0x02<<0),
TWI_SLAVE_CMD_RESPONSE_gc = (0x03<<0),
TWI_SLAVE_CMD_NOACT_gc = (0x00<<0),
TWI_SLAVE_CMD_COMPTRANS_gc = (0x02<<0),
TWI_SLAVE_CMD_RESPONSE_gc = (0x03<<0),
TWI_SLAVE_CMD_NOACT_gc = (0x00<<0),
TWI_SLAVE_CMD_COMPTRANS_gc = (0x02<<0),
TWI_SLAVE_CMD_RESPONSE_gc = (0x03<<0),
TWI_SLAVE_CMD_NOACT_gc = (0x00<<0),
TWI_SLAVE_CMD_COMPTRANS_gc = (0x02<<0),
TWI_SLAVE_CMD_RESPONSE_gc = (0x03<<0),
TWI_SLAVE_CMD_NOACT_gc = (0x00<<0),
TWI_SLAVE_CMD_COMPTRANS_gc = (0x02<<0),
TWI_SLAVE_CMD_RESPONSE_gc = (0x03<<0),
TWI_SLAVE_CMD_NOACT_gc = (0x00<<0),
TWI_SLAVE_CMD_COMPTRANS_gc = (0x02<<0),
TWI_SLAVE_CMD_RESPONSE_gc = (0x03<<0),
TWI_SLAVE_CMD_NOACT_gc = (0x00<<0),
TWI_SLAVE_CMD_COMPTRANS_gc = (0x02<<0),
TWI_SLAVE_CMD_RESPONSE_gc = (0x03<<0),
TWI_SLAVE_CMD_NOACT_gc = (0x00<<0),
TWI_SLAVE_CMD_COMPTRANS_gc = (0x02<<0),
TWI_SLAVE_CMD_RESPONSE_gc = (0x03<<0),
TWI_SLAVE_CMD_NOACT_gc = (0x00<<0),
TWI_SLAVE_CMD_COMPTRANS_gc = (0x02<<0),
TWI_SLAVE_CMD_RESPONSE_gc = (0x03<<0),
TWI_SLAVE_CMD_NOACT_gc = (0x00<<0),
TWI_SLAVE_CMD_COMPTRANS_gc = (0x02<<0),
TWI_SLAVE_CMD_RESPONSE_gc = (0x03<<0),
TWI_SLAVE_CMD_NOACT_gc = (0x00<<0),
TWI_SLAVE_CMD_COMPTRANS_gc = (0x02<<0),
TWI_SLAVE_CMD_RESPONSE_gc = (0x03<<0)
} |
|
enum | PORTCFG_VP0MAP_enum {
PORTCFG_VP0MAP_PORTA_gc = (0x00<<0),
PORTCFG_VP0MAP_PORTB_gc = (0x01<<0),
PORTCFG_VP0MAP_PORTC_gc = (0x02<<0),
PORTCFG_VP0MAP_PORTD_gc = (0x03<<0),
PORTCFG_VP0MAP_PORTE_gc = (0x04<<0),
PORTCFG_VP0MAP_PORTF_gc = (0x05<<0),
PORTCFG_VP0MAP_PORTG_gc = (0x06<<0),
PORTCFG_VP0MAP_PORTH_gc = (0x07<<0),
PORTCFG_VP0MAP_PORTJ_gc = (0x08<<0),
PORTCFG_VP0MAP_PORTK_gc = (0x09<<0),
PORTCFG_VP0MAP_PORTL_gc = (0x0A<<0),
PORTCFG_VP0MAP_PORTM_gc = (0x0B<<0),
PORTCFG_VP0MAP_PORTN_gc = (0x0C<<0),
PORTCFG_VP0MAP_PORTP_gc = (0x0D<<0),
PORTCFG_VP0MAP_PORTQ_gc = (0x0E<<0),
PORTCFG_VP0MAP_PORTR_gc = (0x0F<<0),
PORTCFG_VP0MAP_PORTA_gc = (0x00<<0),
PORTCFG_VP0MAP_PORTB_gc = (0x01<<0),
PORTCFG_VP0MAP_PORTC_gc = (0x02<<0),
PORTCFG_VP0MAP_PORTD_gc = (0x03<<0),
PORTCFG_VP0MAP_PORTE_gc = (0x04<<0),
PORTCFG_VP0MAP_PORTF_gc = (0x05<<0),
PORTCFG_VP0MAP_PORTG_gc = (0x06<<0),
PORTCFG_VP0MAP_PORTH_gc = (0x07<<0),
PORTCFG_VP0MAP_PORTJ_gc = (0x08<<0),
PORTCFG_VP0MAP_PORTK_gc = (0x09<<0),
PORTCFG_VP0MAP_PORTL_gc = (0x0A<<0),
PORTCFG_VP0MAP_PORTM_gc = (0x0B<<0),
PORTCFG_VP0MAP_PORTN_gc = (0x0C<<0),
PORTCFG_VP0MAP_PORTP_gc = (0x0D<<0),
PORTCFG_VP0MAP_PORTQ_gc = (0x0E<<0),
PORTCFG_VP0MAP_PORTR_gc = (0x0F<<0),
PORTCFG_VP0MAP_PORTA_gc = (0x00<<0),
PORTCFG_VP0MAP_PORTB_gc = (0x01<<0),
PORTCFG_VP0MAP_PORTC_gc = (0x02<<0),
PORTCFG_VP0MAP_PORTD_gc = (0x03<<0),
PORTCFG_VP0MAP_PORTE_gc = (0x04<<0),
PORTCFG_VP0MAP_PORTF_gc = (0x05<<0),
PORTCFG_VP0MAP_PORTG_gc = (0x06<<0),
PORTCFG_VP0MAP_PORTH_gc = (0x07<<0),
PORTCFG_VP0MAP_PORTJ_gc = (0x08<<0),
PORTCFG_VP0MAP_PORTK_gc = (0x09<<0),
PORTCFG_VP0MAP_PORTL_gc = (0x0A<<0),
PORTCFG_VP0MAP_PORTM_gc = (0x0B<<0),
PORTCFG_VP0MAP_PORTN_gc = (0x0C<<0),
PORTCFG_VP0MAP_PORTP_gc = (0x0D<<0),
PORTCFG_VP0MAP_PORTQ_gc = (0x0E<<0),
PORTCFG_VP0MAP_PORTR_gc = (0x0F<<0),
PORTCFG_VP0MAP_PORTA_gc = (0x00<<0),
PORTCFG_VP0MAP_PORTB_gc = (0x01<<0),
PORTCFG_VP0MAP_PORTC_gc = (0x02<<0),
PORTCFG_VP0MAP_PORTD_gc = (0x03<<0),
PORTCFG_VP0MAP_PORTE_gc = (0x04<<0),
PORTCFG_VP0MAP_PORTF_gc = (0x05<<0),
PORTCFG_VP0MAP_PORTG_gc = (0x06<<0),
PORTCFG_VP0MAP_PORTH_gc = (0x07<<0),
PORTCFG_VP0MAP_PORTJ_gc = (0x08<<0),
PORTCFG_VP0MAP_PORTK_gc = (0x09<<0),
PORTCFG_VP0MAP_PORTL_gc = (0x0A<<0),
PORTCFG_VP0MAP_PORTM_gc = (0x0B<<0),
PORTCFG_VP0MAP_PORTN_gc = (0x0C<<0),
PORTCFG_VP0MAP_PORTP_gc = (0x0D<<0),
PORTCFG_VP0MAP_PORTQ_gc = (0x0E<<0),
PORTCFG_VP0MAP_PORTR_gc = (0x0F<<0),
PORTCFG_VP0MAP_PORTA_gc = (0x00<<0),
PORTCFG_VP0MAP_PORTB_gc = (0x01<<0),
PORTCFG_VP0MAP_PORTC_gc = (0x02<<0),
PORTCFG_VP0MAP_PORTD_gc = (0x03<<0),
PORTCFG_VP0MAP_PORTE_gc = (0x04<<0),
PORTCFG_VP0MAP_PORTF_gc = (0x05<<0),
PORTCFG_VP0MAP_PORTG_gc = (0x06<<0),
PORTCFG_VP0MAP_PORTH_gc = (0x07<<0),
PORTCFG_VP0MAP_PORTJ_gc = (0x08<<0),
PORTCFG_VP0MAP_PORTK_gc = (0x09<<0),
PORTCFG_VP0MAP_PORTL_gc = (0x0A<<0),
PORTCFG_VP0MAP_PORTM_gc = (0x0B<<0),
PORTCFG_VP0MAP_PORTN_gc = (0x0C<<0),
PORTCFG_VP0MAP_PORTP_gc = (0x0D<<0),
PORTCFG_VP0MAP_PORTQ_gc = (0x0E<<0),
PORTCFG_VP0MAP_PORTR_gc = (0x0F<<0),
PORTCFG_VP0MAP_PORTA_gc = (0x00<<0),
PORTCFG_VP0MAP_PORTB_gc = (0x01<<0),
PORTCFG_VP0MAP_PORTC_gc = (0x02<<0),
PORTCFG_VP0MAP_PORTD_gc = (0x03<<0),
PORTCFG_VP0MAP_PORTE_gc = (0x04<<0),
PORTCFG_VP0MAP_PORTF_gc = (0x05<<0),
PORTCFG_VP0MAP_PORTG_gc = (0x06<<0),
PORTCFG_VP0MAP_PORTH_gc = (0x07<<0),
PORTCFG_VP0MAP_PORTJ_gc = (0x08<<0),
PORTCFG_VP0MAP_PORTK_gc = (0x09<<0),
PORTCFG_VP0MAP_PORTL_gc = (0x0A<<0),
PORTCFG_VP0MAP_PORTM_gc = (0x0B<<0),
PORTCFG_VP0MAP_PORTN_gc = (0x0C<<0),
PORTCFG_VP0MAP_PORTP_gc = (0x0D<<0),
PORTCFG_VP0MAP_PORTQ_gc = (0x0E<<0),
PORTCFG_VP0MAP_PORTR_gc = (0x0F<<0),
PORTCFG_VP0MAP_PORTA_gc = (0x00<<0),
PORTCFG_VP0MAP_PORTB_gc = (0x01<<0),
PORTCFG_VP0MAP_PORTC_gc = (0x02<<0),
PORTCFG_VP0MAP_PORTD_gc = (0x03<<0),
PORTCFG_VP0MAP_PORTE_gc = (0x04<<0),
PORTCFG_VP0MAP_PORTF_gc = (0x05<<0),
PORTCFG_VP0MAP_PORTG_gc = (0x06<<0),
PORTCFG_VP0MAP_PORTH_gc = (0x07<<0),
PORTCFG_VP0MAP_PORTJ_gc = (0x08<<0),
PORTCFG_VP0MAP_PORTK_gc = (0x09<<0),
PORTCFG_VP0MAP_PORTL_gc = (0x0A<<0),
PORTCFG_VP0MAP_PORTM_gc = (0x0B<<0),
PORTCFG_VP0MAP_PORTN_gc = (0x0C<<0),
PORTCFG_VP0MAP_PORTP_gc = (0x0D<<0),
PORTCFG_VP0MAP_PORTQ_gc = (0x0E<<0),
PORTCFG_VP0MAP_PORTR_gc = (0x0F<<0),
PORTCFG_VP0MAP_PORTA_gc = (0x00<<0),
PORTCFG_VP0MAP_PORTB_gc = (0x01<<0),
PORTCFG_VP0MAP_PORTC_gc = (0x02<<0),
PORTCFG_VP0MAP_PORTD_gc = (0x03<<0),
PORTCFG_VP0MAP_PORTE_gc = (0x04<<0),
PORTCFG_VP0MAP_PORTF_gc = (0x05<<0),
PORTCFG_VP0MAP_PORTG_gc = (0x06<<0),
PORTCFG_VP0MAP_PORTH_gc = (0x07<<0),
PORTCFG_VP0MAP_PORTJ_gc = (0x08<<0),
PORTCFG_VP0MAP_PORTK_gc = (0x09<<0),
PORTCFG_VP0MAP_PORTL_gc = (0x0A<<0),
PORTCFG_VP0MAP_PORTM_gc = (0x0B<<0),
PORTCFG_VP0MAP_PORTN_gc = (0x0C<<0),
PORTCFG_VP0MAP_PORTP_gc = (0x0D<<0),
PORTCFG_VP0MAP_PORTQ_gc = (0x0E<<0),
PORTCFG_VP0MAP_PORTR_gc = (0x0F<<0),
PORTCFG_VP0MAP_PORTA_gc = (0x00<<0),
PORTCFG_VP0MAP_PORTB_gc = (0x01<<0),
PORTCFG_VP0MAP_PORTC_gc = (0x02<<0),
PORTCFG_VP0MAP_PORTD_gc = (0x03<<0),
PORTCFG_VP0MAP_PORTE_gc = (0x04<<0),
PORTCFG_VP0MAP_PORTF_gc = (0x05<<0),
PORTCFG_VP0MAP_PORTG_gc = (0x06<<0),
PORTCFG_VP0MAP_PORTH_gc = (0x07<<0),
PORTCFG_VP0MAP_PORTJ_gc = (0x08<<0),
PORTCFG_VP0MAP_PORTK_gc = (0x09<<0),
PORTCFG_VP0MAP_PORTL_gc = (0x0A<<0),
PORTCFG_VP0MAP_PORTM_gc = (0x0B<<0),
PORTCFG_VP0MAP_PORTN_gc = (0x0C<<0),
PORTCFG_VP0MAP_PORTP_gc = (0x0D<<0),
PORTCFG_VP0MAP_PORTQ_gc = (0x0E<<0),
PORTCFG_VP0MAP_PORTR_gc = (0x0F<<0),
PORTCFG_VP0MAP_PORTA_gc = (0x00<<0),
PORTCFG_VP0MAP_PORTB_gc = (0x01<<0),
PORTCFG_VP0MAP_PORTC_gc = (0x02<<0),
PORTCFG_VP0MAP_PORTD_gc = (0x03<<0),
PORTCFG_VP0MAP_PORTE_gc = (0x04<<0),
PORTCFG_VP0MAP_PORTF_gc = (0x05<<0),
PORTCFG_VP0MAP_PORTG_gc = (0x06<<0),
PORTCFG_VP0MAP_PORTH_gc = (0x07<<0),
PORTCFG_VP0MAP_PORTJ_gc = (0x08<<0),
PORTCFG_VP0MAP_PORTK_gc = (0x09<<0),
PORTCFG_VP0MAP_PORTL_gc = (0x0A<<0),
PORTCFG_VP0MAP_PORTM_gc = (0x0B<<0),
PORTCFG_VP0MAP_PORTN_gc = (0x0C<<0),
PORTCFG_VP0MAP_PORTP_gc = (0x0D<<0),
PORTCFG_VP0MAP_PORTQ_gc = (0x0E<<0),
PORTCFG_VP0MAP_PORTR_gc = (0x0F<<0),
PORTCFG_VP0MAP_PORTA_gc = (0x00<<0),
PORTCFG_VP0MAP_PORTB_gc = (0x01<<0),
PORTCFG_VP0MAP_PORTC_gc = (0x02<<0),
PORTCFG_VP0MAP_PORTD_gc = (0x03<<0),
PORTCFG_VP0MAP_PORTE_gc = (0x04<<0),
PORTCFG_VP0MAP_PORTF_gc = (0x05<<0),
PORTCFG_VP0MAP_PORTG_gc = (0x06<<0),
PORTCFG_VP0MAP_PORTH_gc = (0x07<<0),
PORTCFG_VP0MAP_PORTJ_gc = (0x08<<0),
PORTCFG_VP0MAP_PORTK_gc = (0x09<<0),
PORTCFG_VP0MAP_PORTL_gc = (0x0A<<0),
PORTCFG_VP0MAP_PORTM_gc = (0x0B<<0),
PORTCFG_VP0MAP_PORTN_gc = (0x0C<<0),
PORTCFG_VP0MAP_PORTP_gc = (0x0D<<0),
PORTCFG_VP0MAP_PORTQ_gc = (0x0E<<0),
PORTCFG_VP0MAP_PORTR_gc = (0x0F<<0),
PORTCFG_VP0MAP_PORTA_gc = (0x00<<0),
PORTCFG_VP0MAP_PORTB_gc = (0x01<<0),
PORTCFG_VP0MAP_PORTC_gc = (0x02<<0),
PORTCFG_VP0MAP_PORTD_gc = (0x03<<0),
PORTCFG_VP0MAP_PORTE_gc = (0x04<<0),
PORTCFG_VP0MAP_PORTF_gc = (0x05<<0),
PORTCFG_VP0MAP_PORTG_gc = (0x06<<0),
PORTCFG_VP0MAP_PORTH_gc = (0x07<<0),
PORTCFG_VP0MAP_PORTJ_gc = (0x08<<0),
PORTCFG_VP0MAP_PORTK_gc = (0x09<<0),
PORTCFG_VP0MAP_PORTL_gc = (0x0A<<0),
PORTCFG_VP0MAP_PORTM_gc = (0x0B<<0),
PORTCFG_VP0MAP_PORTN_gc = (0x0C<<0),
PORTCFG_VP0MAP_PORTP_gc = (0x0D<<0),
PORTCFG_VP0MAP_PORTQ_gc = (0x0E<<0),
PORTCFG_VP0MAP_PORTR_gc = (0x0F<<0),
PORTCFG_VP0MAP_PORTA_gc = (0x00<<0),
PORTCFG_VP0MAP_PORTB_gc = (0x01<<0),
PORTCFG_VP0MAP_PORTC_gc = (0x02<<0),
PORTCFG_VP0MAP_PORTD_gc = (0x03<<0),
PORTCFG_VP0MAP_PORTE_gc = (0x04<<0),
PORTCFG_VP0MAP_PORTF_gc = (0x05<<0),
PORTCFG_VP0MAP_PORTG_gc = (0x06<<0),
PORTCFG_VP0MAP_PORTH_gc = (0x07<<0),
PORTCFG_VP0MAP_PORTJ_gc = (0x08<<0),
PORTCFG_VP0MAP_PORTK_gc = (0x09<<0),
PORTCFG_VP0MAP_PORTL_gc = (0x0A<<0),
PORTCFG_VP0MAP_PORTM_gc = (0x0B<<0),
PORTCFG_VP0MAP_PORTN_gc = (0x0C<<0),
PORTCFG_VP0MAP_PORTP_gc = (0x0D<<0),
PORTCFG_VP0MAP_PORTQ_gc = (0x0E<<0),
PORTCFG_VP0MAP_PORTR_gc = (0x0F<<0),
PORTCFG_VP0MAP_PORTA_gc = (0x00<<0),
PORTCFG_VP0MAP_PORTB_gc = (0x01<<0),
PORTCFG_VP0MAP_PORTC_gc = (0x02<<0),
PORTCFG_VP0MAP_PORTD_gc = (0x03<<0),
PORTCFG_VP0MAP_PORTE_gc = (0x04<<0),
PORTCFG_VP0MAP_PORTF_gc = (0x05<<0),
PORTCFG_VP0MAP_PORTG_gc = (0x06<<0),
PORTCFG_VP0MAP_PORTH_gc = (0x07<<0),
PORTCFG_VP0MAP_PORTJ_gc = (0x08<<0),
PORTCFG_VP0MAP_PORTK_gc = (0x09<<0),
PORTCFG_VP0MAP_PORTL_gc = (0x0A<<0),
PORTCFG_VP0MAP_PORTM_gc = (0x0B<<0),
PORTCFG_VP0MAP_PORTN_gc = (0x0C<<0),
PORTCFG_VP0MAP_PORTP_gc = (0x0D<<0),
PORTCFG_VP0MAP_PORTQ_gc = (0x0E<<0),
PORTCFG_VP0MAP_PORTR_gc = (0x0F<<0),
PORTCFG_VP0MAP_PORTA_gc = (0x00<<0),
PORTCFG_VP0MAP_PORTB_gc = (0x01<<0),
PORTCFG_VP0MAP_PORTC_gc = (0x02<<0),
PORTCFG_VP0MAP_PORTD_gc = (0x03<<0),
PORTCFG_VP0MAP_PORTE_gc = (0x04<<0),
PORTCFG_VP0MAP_PORTF_gc = (0x05<<0),
PORTCFG_VP0MAP_PORTG_gc = (0x06<<0),
PORTCFG_VP0MAP_PORTH_gc = (0x07<<0),
PORTCFG_VP0MAP_PORTJ_gc = (0x08<<0),
PORTCFG_VP0MAP_PORTK_gc = (0x09<<0),
PORTCFG_VP0MAP_PORTL_gc = (0x0A<<0),
PORTCFG_VP0MAP_PORTM_gc = (0x0B<<0),
PORTCFG_VP0MAP_PORTN_gc = (0x0C<<0),
PORTCFG_VP0MAP_PORTP_gc = (0x0D<<0),
PORTCFG_VP0MAP_PORTQ_gc = (0x0E<<0),
PORTCFG_VP0MAP_PORTR_gc = (0x0F<<0)
} |
|
enum | PORTCFG_VP1MAP_enum {
PORTCFG_VP1MAP_PORTA_gc = (0x00<<4),
PORTCFG_VP1MAP_PORTB_gc = (0x01<<4),
PORTCFG_VP1MAP_PORTC_gc = (0x02<<4),
PORTCFG_VP1MAP_PORTD_gc = (0x03<<4),
PORTCFG_VP1MAP_PORTE_gc = (0x04<<4),
PORTCFG_VP1MAP_PORTF_gc = (0x05<<4),
PORTCFG_VP1MAP_PORTG_gc = (0x06<<4),
PORTCFG_VP1MAP_PORTH_gc = (0x07<<4),
PORTCFG_VP1MAP_PORTJ_gc = (0x08<<4),
PORTCFG_VP1MAP_PORTK_gc = (0x09<<4),
PORTCFG_VP1MAP_PORTL_gc = (0x0A<<4),
PORTCFG_VP1MAP_PORTM_gc = (0x0B<<4),
PORTCFG_VP1MAP_PORTN_gc = (0x0C<<4),
PORTCFG_VP1MAP_PORTP_gc = (0x0D<<4),
PORTCFG_VP1MAP_PORTQ_gc = (0x0E<<4),
PORTCFG_VP1MAP_PORTR_gc = (0x0F<<4),
PORTCFG_VP1MAP_PORTA_gc = (0x00<<4),
PORTCFG_VP1MAP_PORTB_gc = (0x01<<4),
PORTCFG_VP1MAP_PORTC_gc = (0x02<<4),
PORTCFG_VP1MAP_PORTD_gc = (0x03<<4),
PORTCFG_VP1MAP_PORTE_gc = (0x04<<4),
PORTCFG_VP1MAP_PORTF_gc = (0x05<<4),
PORTCFG_VP1MAP_PORTG_gc = (0x06<<4),
PORTCFG_VP1MAP_PORTH_gc = (0x07<<4),
PORTCFG_VP1MAP_PORTJ_gc = (0x08<<4),
PORTCFG_VP1MAP_PORTK_gc = (0x09<<4),
PORTCFG_VP1MAP_PORTL_gc = (0x0A<<4),
PORTCFG_VP1MAP_PORTM_gc = (0x0B<<4),
PORTCFG_VP1MAP_PORTN_gc = (0x0C<<4),
PORTCFG_VP1MAP_PORTP_gc = (0x0D<<4),
PORTCFG_VP1MAP_PORTQ_gc = (0x0E<<4),
PORTCFG_VP1MAP_PORTR_gc = (0x0F<<4),
PORTCFG_VP1MAP_PORTA_gc = (0x00<<4),
PORTCFG_VP1MAP_PORTB_gc = (0x01<<4),
PORTCFG_VP1MAP_PORTC_gc = (0x02<<4),
PORTCFG_VP1MAP_PORTD_gc = (0x03<<4),
PORTCFG_VP1MAP_PORTE_gc = (0x04<<4),
PORTCFG_VP1MAP_PORTF_gc = (0x05<<4),
PORTCFG_VP1MAP_PORTG_gc = (0x06<<4),
PORTCFG_VP1MAP_PORTH_gc = (0x07<<4),
PORTCFG_VP1MAP_PORTJ_gc = (0x08<<4),
PORTCFG_VP1MAP_PORTK_gc = (0x09<<4),
PORTCFG_VP1MAP_PORTL_gc = (0x0A<<4),
PORTCFG_VP1MAP_PORTM_gc = (0x0B<<4),
PORTCFG_VP1MAP_PORTN_gc = (0x0C<<4),
PORTCFG_VP1MAP_PORTP_gc = (0x0D<<4),
PORTCFG_VP1MAP_PORTQ_gc = (0x0E<<4),
PORTCFG_VP1MAP_PORTR_gc = (0x0F<<4),
PORTCFG_VP1MAP_PORTA_gc = (0x00<<4),
PORTCFG_VP1MAP_PORTB_gc = (0x01<<4),
PORTCFG_VP1MAP_PORTC_gc = (0x02<<4),
PORTCFG_VP1MAP_PORTD_gc = (0x03<<4),
PORTCFG_VP1MAP_PORTE_gc = (0x04<<4),
PORTCFG_VP1MAP_PORTF_gc = (0x05<<4),
PORTCFG_VP1MAP_PORTG_gc = (0x06<<4),
PORTCFG_VP1MAP_PORTH_gc = (0x07<<4),
PORTCFG_VP1MAP_PORTJ_gc = (0x08<<4),
PORTCFG_VP1MAP_PORTK_gc = (0x09<<4),
PORTCFG_VP1MAP_PORTL_gc = (0x0A<<4),
PORTCFG_VP1MAP_PORTM_gc = (0x0B<<4),
PORTCFG_VP1MAP_PORTN_gc = (0x0C<<4),
PORTCFG_VP1MAP_PORTP_gc = (0x0D<<4),
PORTCFG_VP1MAP_PORTQ_gc = (0x0E<<4),
PORTCFG_VP1MAP_PORTR_gc = (0x0F<<4),
PORTCFG_VP1MAP_PORTA_gc = (0x00<<4),
PORTCFG_VP1MAP_PORTB_gc = (0x01<<4),
PORTCFG_VP1MAP_PORTC_gc = (0x02<<4),
PORTCFG_VP1MAP_PORTD_gc = (0x03<<4),
PORTCFG_VP1MAP_PORTE_gc = (0x04<<4),
PORTCFG_VP1MAP_PORTF_gc = (0x05<<4),
PORTCFG_VP1MAP_PORTG_gc = (0x06<<4),
PORTCFG_VP1MAP_PORTH_gc = (0x07<<4),
PORTCFG_VP1MAP_PORTJ_gc = (0x08<<4),
PORTCFG_VP1MAP_PORTK_gc = (0x09<<4),
PORTCFG_VP1MAP_PORTL_gc = (0x0A<<4),
PORTCFG_VP1MAP_PORTM_gc = (0x0B<<4),
PORTCFG_VP1MAP_PORTN_gc = (0x0C<<4),
PORTCFG_VP1MAP_PORTP_gc = (0x0D<<4),
PORTCFG_VP1MAP_PORTQ_gc = (0x0E<<4),
PORTCFG_VP1MAP_PORTR_gc = (0x0F<<4),
PORTCFG_VP1MAP_PORTA_gc = (0x00<<4),
PORTCFG_VP1MAP_PORTB_gc = (0x01<<4),
PORTCFG_VP1MAP_PORTC_gc = (0x02<<4),
PORTCFG_VP1MAP_PORTD_gc = (0x03<<4),
PORTCFG_VP1MAP_PORTE_gc = (0x04<<4),
PORTCFG_VP1MAP_PORTF_gc = (0x05<<4),
PORTCFG_VP1MAP_PORTG_gc = (0x06<<4),
PORTCFG_VP1MAP_PORTH_gc = (0x07<<4),
PORTCFG_VP1MAP_PORTJ_gc = (0x08<<4),
PORTCFG_VP1MAP_PORTK_gc = (0x09<<4),
PORTCFG_VP1MAP_PORTL_gc = (0x0A<<4),
PORTCFG_VP1MAP_PORTM_gc = (0x0B<<4),
PORTCFG_VP1MAP_PORTN_gc = (0x0C<<4),
PORTCFG_VP1MAP_PORTP_gc = (0x0D<<4),
PORTCFG_VP1MAP_PORTQ_gc = (0x0E<<4),
PORTCFG_VP1MAP_PORTR_gc = (0x0F<<4),
PORTCFG_VP1MAP_PORTA_gc = (0x00<<4),
PORTCFG_VP1MAP_PORTB_gc = (0x01<<4),
PORTCFG_VP1MAP_PORTC_gc = (0x02<<4),
PORTCFG_VP1MAP_PORTD_gc = (0x03<<4),
PORTCFG_VP1MAP_PORTE_gc = (0x04<<4),
PORTCFG_VP1MAP_PORTF_gc = (0x05<<4),
PORTCFG_VP1MAP_PORTG_gc = (0x06<<4),
PORTCFG_VP1MAP_PORTH_gc = (0x07<<4),
PORTCFG_VP1MAP_PORTJ_gc = (0x08<<4),
PORTCFG_VP1MAP_PORTK_gc = (0x09<<4),
PORTCFG_VP1MAP_PORTL_gc = (0x0A<<4),
PORTCFG_VP1MAP_PORTM_gc = (0x0B<<4),
PORTCFG_VP1MAP_PORTN_gc = (0x0C<<4),
PORTCFG_VP1MAP_PORTP_gc = (0x0D<<4),
PORTCFG_VP1MAP_PORTQ_gc = (0x0E<<4),
PORTCFG_VP1MAP_PORTR_gc = (0x0F<<4),
PORTCFG_VP1MAP_PORTA_gc = (0x00<<4),
PORTCFG_VP1MAP_PORTB_gc = (0x01<<4),
PORTCFG_VP1MAP_PORTC_gc = (0x02<<4),
PORTCFG_VP1MAP_PORTD_gc = (0x03<<4),
PORTCFG_VP1MAP_PORTE_gc = (0x04<<4),
PORTCFG_VP1MAP_PORTF_gc = (0x05<<4),
PORTCFG_VP1MAP_PORTG_gc = (0x06<<4),
PORTCFG_VP1MAP_PORTH_gc = (0x07<<4),
PORTCFG_VP1MAP_PORTJ_gc = (0x08<<4),
PORTCFG_VP1MAP_PORTK_gc = (0x09<<4),
PORTCFG_VP1MAP_PORTL_gc = (0x0A<<4),
PORTCFG_VP1MAP_PORTM_gc = (0x0B<<4),
PORTCFG_VP1MAP_PORTN_gc = (0x0C<<4),
PORTCFG_VP1MAP_PORTP_gc = (0x0D<<4),
PORTCFG_VP1MAP_PORTQ_gc = (0x0E<<4),
PORTCFG_VP1MAP_PORTR_gc = (0x0F<<4),
PORTCFG_VP1MAP_PORTA_gc = (0x00<<4),
PORTCFG_VP1MAP_PORTB_gc = (0x01<<4),
PORTCFG_VP1MAP_PORTC_gc = (0x02<<4),
PORTCFG_VP1MAP_PORTD_gc = (0x03<<4),
PORTCFG_VP1MAP_PORTE_gc = (0x04<<4),
PORTCFG_VP1MAP_PORTF_gc = (0x05<<4),
PORTCFG_VP1MAP_PORTG_gc = (0x06<<4),
PORTCFG_VP1MAP_PORTH_gc = (0x07<<4),
PORTCFG_VP1MAP_PORTJ_gc = (0x08<<4),
PORTCFG_VP1MAP_PORTK_gc = (0x09<<4),
PORTCFG_VP1MAP_PORTL_gc = (0x0A<<4),
PORTCFG_VP1MAP_PORTM_gc = (0x0B<<4),
PORTCFG_VP1MAP_PORTN_gc = (0x0C<<4),
PORTCFG_VP1MAP_PORTP_gc = (0x0D<<4),
PORTCFG_VP1MAP_PORTQ_gc = (0x0E<<4),
PORTCFG_VP1MAP_PORTR_gc = (0x0F<<4),
PORTCFG_VP1MAP_PORTA_gc = (0x00<<4),
PORTCFG_VP1MAP_PORTB_gc = (0x01<<4),
PORTCFG_VP1MAP_PORTC_gc = (0x02<<4),
PORTCFG_VP1MAP_PORTD_gc = (0x03<<4),
PORTCFG_VP1MAP_PORTE_gc = (0x04<<4),
PORTCFG_VP1MAP_PORTF_gc = (0x05<<4),
PORTCFG_VP1MAP_PORTG_gc = (0x06<<4),
PORTCFG_VP1MAP_PORTH_gc = (0x07<<4),
PORTCFG_VP1MAP_PORTJ_gc = (0x08<<4),
PORTCFG_VP1MAP_PORTK_gc = (0x09<<4),
PORTCFG_VP1MAP_PORTL_gc = (0x0A<<4),
PORTCFG_VP1MAP_PORTM_gc = (0x0B<<4),
PORTCFG_VP1MAP_PORTN_gc = (0x0C<<4),
PORTCFG_VP1MAP_PORTP_gc = (0x0D<<4),
PORTCFG_VP1MAP_PORTQ_gc = (0x0E<<4),
PORTCFG_VP1MAP_PORTR_gc = (0x0F<<4),
PORTCFG_VP1MAP_PORTA_gc = (0x00<<4),
PORTCFG_VP1MAP_PORTB_gc = (0x01<<4),
PORTCFG_VP1MAP_PORTC_gc = (0x02<<4),
PORTCFG_VP1MAP_PORTD_gc = (0x03<<4),
PORTCFG_VP1MAP_PORTE_gc = (0x04<<4),
PORTCFG_VP1MAP_PORTF_gc = (0x05<<4),
PORTCFG_VP1MAP_PORTG_gc = (0x06<<4),
PORTCFG_VP1MAP_PORTH_gc = (0x07<<4),
PORTCFG_VP1MAP_PORTJ_gc = (0x08<<4),
PORTCFG_VP1MAP_PORTK_gc = (0x09<<4),
PORTCFG_VP1MAP_PORTL_gc = (0x0A<<4),
PORTCFG_VP1MAP_PORTM_gc = (0x0B<<4),
PORTCFG_VP1MAP_PORTN_gc = (0x0C<<4),
PORTCFG_VP1MAP_PORTP_gc = (0x0D<<4),
PORTCFG_VP1MAP_PORTQ_gc = (0x0E<<4),
PORTCFG_VP1MAP_PORTR_gc = (0x0F<<4),
PORTCFG_VP1MAP_PORTA_gc = (0x00<<4),
PORTCFG_VP1MAP_PORTB_gc = (0x01<<4),
PORTCFG_VP1MAP_PORTC_gc = (0x02<<4),
PORTCFG_VP1MAP_PORTD_gc = (0x03<<4),
PORTCFG_VP1MAP_PORTE_gc = (0x04<<4),
PORTCFG_VP1MAP_PORTF_gc = (0x05<<4),
PORTCFG_VP1MAP_PORTG_gc = (0x06<<4),
PORTCFG_VP1MAP_PORTH_gc = (0x07<<4),
PORTCFG_VP1MAP_PORTJ_gc = (0x08<<4),
PORTCFG_VP1MAP_PORTK_gc = (0x09<<4),
PORTCFG_VP1MAP_PORTL_gc = (0x0A<<4),
PORTCFG_VP1MAP_PORTM_gc = (0x0B<<4),
PORTCFG_VP1MAP_PORTN_gc = (0x0C<<4),
PORTCFG_VP1MAP_PORTP_gc = (0x0D<<4),
PORTCFG_VP1MAP_PORTQ_gc = (0x0E<<4),
PORTCFG_VP1MAP_PORTR_gc = (0x0F<<4),
PORTCFG_VP1MAP_PORTA_gc = (0x00<<4),
PORTCFG_VP1MAP_PORTB_gc = (0x01<<4),
PORTCFG_VP1MAP_PORTC_gc = (0x02<<4),
PORTCFG_VP1MAP_PORTD_gc = (0x03<<4),
PORTCFG_VP1MAP_PORTE_gc = (0x04<<4),
PORTCFG_VP1MAP_PORTF_gc = (0x05<<4),
PORTCFG_VP1MAP_PORTG_gc = (0x06<<4),
PORTCFG_VP1MAP_PORTH_gc = (0x07<<4),
PORTCFG_VP1MAP_PORTJ_gc = (0x08<<4),
PORTCFG_VP1MAP_PORTK_gc = (0x09<<4),
PORTCFG_VP1MAP_PORTL_gc = (0x0A<<4),
PORTCFG_VP1MAP_PORTM_gc = (0x0B<<4),
PORTCFG_VP1MAP_PORTN_gc = (0x0C<<4),
PORTCFG_VP1MAP_PORTP_gc = (0x0D<<4),
PORTCFG_VP1MAP_PORTQ_gc = (0x0E<<4),
PORTCFG_VP1MAP_PORTR_gc = (0x0F<<4),
PORTCFG_VP1MAP_PORTA_gc = (0x00<<4),
PORTCFG_VP1MAP_PORTB_gc = (0x01<<4),
PORTCFG_VP1MAP_PORTC_gc = (0x02<<4),
PORTCFG_VP1MAP_PORTD_gc = (0x03<<4),
PORTCFG_VP1MAP_PORTE_gc = (0x04<<4),
PORTCFG_VP1MAP_PORTF_gc = (0x05<<4),
PORTCFG_VP1MAP_PORTG_gc = (0x06<<4),
PORTCFG_VP1MAP_PORTH_gc = (0x07<<4),
PORTCFG_VP1MAP_PORTJ_gc = (0x08<<4),
PORTCFG_VP1MAP_PORTK_gc = (0x09<<4),
PORTCFG_VP1MAP_PORTL_gc = (0x0A<<4),
PORTCFG_VP1MAP_PORTM_gc = (0x0B<<4),
PORTCFG_VP1MAP_PORTN_gc = (0x0C<<4),
PORTCFG_VP1MAP_PORTP_gc = (0x0D<<4),
PORTCFG_VP1MAP_PORTQ_gc = (0x0E<<4),
PORTCFG_VP1MAP_PORTR_gc = (0x0F<<4),
PORTCFG_VP1MAP_PORTA_gc = (0x00<<4),
PORTCFG_VP1MAP_PORTB_gc = (0x01<<4),
PORTCFG_VP1MAP_PORTC_gc = (0x02<<4),
PORTCFG_VP1MAP_PORTD_gc = (0x03<<4),
PORTCFG_VP1MAP_PORTE_gc = (0x04<<4),
PORTCFG_VP1MAP_PORTF_gc = (0x05<<4),
PORTCFG_VP1MAP_PORTG_gc = (0x06<<4),
PORTCFG_VP1MAP_PORTH_gc = (0x07<<4),
PORTCFG_VP1MAP_PORTJ_gc = (0x08<<4),
PORTCFG_VP1MAP_PORTK_gc = (0x09<<4),
PORTCFG_VP1MAP_PORTL_gc = (0x0A<<4),
PORTCFG_VP1MAP_PORTM_gc = (0x0B<<4),
PORTCFG_VP1MAP_PORTN_gc = (0x0C<<4),
PORTCFG_VP1MAP_PORTP_gc = (0x0D<<4),
PORTCFG_VP1MAP_PORTQ_gc = (0x0E<<4),
PORTCFG_VP1MAP_PORTR_gc = (0x0F<<4)
} |
|
enum | PORTCFG_VP2MAP_enum {
PORTCFG_VP2MAP_PORTA_gc = (0x00<<0),
PORTCFG_VP2MAP_PORTB_gc = (0x01<<0),
PORTCFG_VP2MAP_PORTC_gc = (0x02<<0),
PORTCFG_VP2MAP_PORTD_gc = (0x03<<0),
PORTCFG_VP2MAP_PORTE_gc = (0x04<<0),
PORTCFG_VP2MAP_PORTF_gc = (0x05<<0),
PORTCFG_VP2MAP_PORTG_gc = (0x06<<0),
PORTCFG_VP2MAP_PORTH_gc = (0x07<<0),
PORTCFG_VP2MAP_PORTJ_gc = (0x08<<0),
PORTCFG_VP2MAP_PORTK_gc = (0x09<<0),
PORTCFG_VP2MAP_PORTL_gc = (0x0A<<0),
PORTCFG_VP2MAP_PORTM_gc = (0x0B<<0),
PORTCFG_VP2MAP_PORTN_gc = (0x0C<<0),
PORTCFG_VP2MAP_PORTP_gc = (0x0D<<0),
PORTCFG_VP2MAP_PORTQ_gc = (0x0E<<0),
PORTCFG_VP2MAP_PORTR_gc = (0x0F<<0),
PORTCFG_VP2MAP_PORTA_gc = (0x00<<0),
PORTCFG_VP2MAP_PORTB_gc = (0x01<<0),
PORTCFG_VP2MAP_PORTC_gc = (0x02<<0),
PORTCFG_VP2MAP_PORTD_gc = (0x03<<0),
PORTCFG_VP2MAP_PORTE_gc = (0x04<<0),
PORTCFG_VP2MAP_PORTF_gc = (0x05<<0),
PORTCFG_VP2MAP_PORTG_gc = (0x06<<0),
PORTCFG_VP2MAP_PORTH_gc = (0x07<<0),
PORTCFG_VP2MAP_PORTJ_gc = (0x08<<0),
PORTCFG_VP2MAP_PORTK_gc = (0x09<<0),
PORTCFG_VP2MAP_PORTL_gc = (0x0A<<0),
PORTCFG_VP2MAP_PORTM_gc = (0x0B<<0),
PORTCFG_VP2MAP_PORTN_gc = (0x0C<<0),
PORTCFG_VP2MAP_PORTP_gc = (0x0D<<0),
PORTCFG_VP2MAP_PORTQ_gc = (0x0E<<0),
PORTCFG_VP2MAP_PORTR_gc = (0x0F<<0),
PORTCFG_VP2MAP_PORTA_gc = (0x00<<0),
PORTCFG_VP2MAP_PORTB_gc = (0x01<<0),
PORTCFG_VP2MAP_PORTC_gc = (0x02<<0),
PORTCFG_VP2MAP_PORTD_gc = (0x03<<0),
PORTCFG_VP2MAP_PORTE_gc = (0x04<<0),
PORTCFG_VP2MAP_PORTF_gc = (0x05<<0),
PORTCFG_VP2MAP_PORTG_gc = (0x06<<0),
PORTCFG_VP2MAP_PORTH_gc = (0x07<<0),
PORTCFG_VP2MAP_PORTJ_gc = (0x08<<0),
PORTCFG_VP2MAP_PORTK_gc = (0x09<<0),
PORTCFG_VP2MAP_PORTL_gc = (0x0A<<0),
PORTCFG_VP2MAP_PORTM_gc = (0x0B<<0),
PORTCFG_VP2MAP_PORTN_gc = (0x0C<<0),
PORTCFG_VP2MAP_PORTP_gc = (0x0D<<0),
PORTCFG_VP2MAP_PORTQ_gc = (0x0E<<0),
PORTCFG_VP2MAP_PORTR_gc = (0x0F<<0),
PORTCFG_VP2MAP_PORTA_gc = (0x00<<0),
PORTCFG_VP2MAP_PORTB_gc = (0x01<<0),
PORTCFG_VP2MAP_PORTC_gc = (0x02<<0),
PORTCFG_VP2MAP_PORTD_gc = (0x03<<0),
PORTCFG_VP2MAP_PORTE_gc = (0x04<<0),
PORTCFG_VP2MAP_PORTF_gc = (0x05<<0),
PORTCFG_VP2MAP_PORTG_gc = (0x06<<0),
PORTCFG_VP2MAP_PORTH_gc = (0x07<<0),
PORTCFG_VP2MAP_PORTJ_gc = (0x08<<0),
PORTCFG_VP2MAP_PORTK_gc = (0x09<<0),
PORTCFG_VP2MAP_PORTL_gc = (0x0A<<0),
PORTCFG_VP2MAP_PORTM_gc = (0x0B<<0),
PORTCFG_VP2MAP_PORTN_gc = (0x0C<<0),
PORTCFG_VP2MAP_PORTP_gc = (0x0D<<0),
PORTCFG_VP2MAP_PORTQ_gc = (0x0E<<0),
PORTCFG_VP2MAP_PORTR_gc = (0x0F<<0),
PORTCFG_VP2MAP_PORTA_gc = (0x00<<0),
PORTCFG_VP2MAP_PORTB_gc = (0x01<<0),
PORTCFG_VP2MAP_PORTC_gc = (0x02<<0),
PORTCFG_VP2MAP_PORTD_gc = (0x03<<0),
PORTCFG_VP2MAP_PORTE_gc = (0x04<<0),
PORTCFG_VP2MAP_PORTF_gc = (0x05<<0),
PORTCFG_VP2MAP_PORTG_gc = (0x06<<0),
PORTCFG_VP2MAP_PORTH_gc = (0x07<<0),
PORTCFG_VP2MAP_PORTJ_gc = (0x08<<0),
PORTCFG_VP2MAP_PORTK_gc = (0x09<<0),
PORTCFG_VP2MAP_PORTL_gc = (0x0A<<0),
PORTCFG_VP2MAP_PORTM_gc = (0x0B<<0),
PORTCFG_VP2MAP_PORTN_gc = (0x0C<<0),
PORTCFG_VP2MAP_PORTP_gc = (0x0D<<0),
PORTCFG_VP2MAP_PORTQ_gc = (0x0E<<0),
PORTCFG_VP2MAP_PORTR_gc = (0x0F<<0),
PORTCFG_VP2MAP_PORTA_gc = (0x00<<0),
PORTCFG_VP2MAP_PORTB_gc = (0x01<<0),
PORTCFG_VP2MAP_PORTC_gc = (0x02<<0),
PORTCFG_VP2MAP_PORTD_gc = (0x03<<0),
PORTCFG_VP2MAP_PORTE_gc = (0x04<<0),
PORTCFG_VP2MAP_PORTF_gc = (0x05<<0),
PORTCFG_VP2MAP_PORTG_gc = (0x06<<0),
PORTCFG_VP2MAP_PORTH_gc = (0x07<<0),
PORTCFG_VP2MAP_PORTJ_gc = (0x08<<0),
PORTCFG_VP2MAP_PORTK_gc = (0x09<<0),
PORTCFG_VP2MAP_PORTL_gc = (0x0A<<0),
PORTCFG_VP2MAP_PORTM_gc = (0x0B<<0),
PORTCFG_VP2MAP_PORTN_gc = (0x0C<<0),
PORTCFG_VP2MAP_PORTP_gc = (0x0D<<0),
PORTCFG_VP2MAP_PORTQ_gc = (0x0E<<0),
PORTCFG_VP2MAP_PORTR_gc = (0x0F<<0),
PORTCFG_VP2MAP_PORTA_gc = (0x00<<0),
PORTCFG_VP2MAP_PORTB_gc = (0x01<<0),
PORTCFG_VP2MAP_PORTC_gc = (0x02<<0),
PORTCFG_VP2MAP_PORTD_gc = (0x03<<0),
PORTCFG_VP2MAP_PORTE_gc = (0x04<<0),
PORTCFG_VP2MAP_PORTF_gc = (0x05<<0),
PORTCFG_VP2MAP_PORTG_gc = (0x06<<0),
PORTCFG_VP2MAP_PORTH_gc = (0x07<<0),
PORTCFG_VP2MAP_PORTJ_gc = (0x08<<0),
PORTCFG_VP2MAP_PORTK_gc = (0x09<<0),
PORTCFG_VP2MAP_PORTL_gc = (0x0A<<0),
PORTCFG_VP2MAP_PORTM_gc = (0x0B<<0),
PORTCFG_VP2MAP_PORTN_gc = (0x0C<<0),
PORTCFG_VP2MAP_PORTP_gc = (0x0D<<0),
PORTCFG_VP2MAP_PORTQ_gc = (0x0E<<0),
PORTCFG_VP2MAP_PORTR_gc = (0x0F<<0),
PORTCFG_VP2MAP_PORTA_gc = (0x00<<0),
PORTCFG_VP2MAP_PORTB_gc = (0x01<<0),
PORTCFG_VP2MAP_PORTC_gc = (0x02<<0),
PORTCFG_VP2MAP_PORTD_gc = (0x03<<0),
PORTCFG_VP2MAP_PORTE_gc = (0x04<<0),
PORTCFG_VP2MAP_PORTF_gc = (0x05<<0),
PORTCFG_VP2MAP_PORTG_gc = (0x06<<0),
PORTCFG_VP2MAP_PORTH_gc = (0x07<<0),
PORTCFG_VP2MAP_PORTJ_gc = (0x08<<0),
PORTCFG_VP2MAP_PORTK_gc = (0x09<<0),
PORTCFG_VP2MAP_PORTL_gc = (0x0A<<0),
PORTCFG_VP2MAP_PORTM_gc = (0x0B<<0),
PORTCFG_VP2MAP_PORTN_gc = (0x0C<<0),
PORTCFG_VP2MAP_PORTP_gc = (0x0D<<0),
PORTCFG_VP2MAP_PORTQ_gc = (0x0E<<0),
PORTCFG_VP2MAP_PORTR_gc = (0x0F<<0),
PORTCFG_VP2MAP_PORTA_gc = (0x00<<0),
PORTCFG_VP2MAP_PORTB_gc = (0x01<<0),
PORTCFG_VP2MAP_PORTC_gc = (0x02<<0),
PORTCFG_VP2MAP_PORTD_gc = (0x03<<0),
PORTCFG_VP2MAP_PORTE_gc = (0x04<<0),
PORTCFG_VP2MAP_PORTF_gc = (0x05<<0),
PORTCFG_VP2MAP_PORTG_gc = (0x06<<0),
PORTCFG_VP2MAP_PORTH_gc = (0x07<<0),
PORTCFG_VP2MAP_PORTJ_gc = (0x08<<0),
PORTCFG_VP2MAP_PORTK_gc = (0x09<<0),
PORTCFG_VP2MAP_PORTL_gc = (0x0A<<0),
PORTCFG_VP2MAP_PORTM_gc = (0x0B<<0),
PORTCFG_VP2MAP_PORTN_gc = (0x0C<<0),
PORTCFG_VP2MAP_PORTP_gc = (0x0D<<0),
PORTCFG_VP2MAP_PORTQ_gc = (0x0E<<0),
PORTCFG_VP2MAP_PORTR_gc = (0x0F<<0),
PORTCFG_VP2MAP_PORTA_gc = (0x00<<0),
PORTCFG_VP2MAP_PORTB_gc = (0x01<<0),
PORTCFG_VP2MAP_PORTC_gc = (0x02<<0),
PORTCFG_VP2MAP_PORTD_gc = (0x03<<0),
PORTCFG_VP2MAP_PORTE_gc = (0x04<<0),
PORTCFG_VP2MAP_PORTF_gc = (0x05<<0),
PORTCFG_VP2MAP_PORTG_gc = (0x06<<0),
PORTCFG_VP2MAP_PORTH_gc = (0x07<<0),
PORTCFG_VP2MAP_PORTJ_gc = (0x08<<0),
PORTCFG_VP2MAP_PORTK_gc = (0x09<<0),
PORTCFG_VP2MAP_PORTL_gc = (0x0A<<0),
PORTCFG_VP2MAP_PORTM_gc = (0x0B<<0),
PORTCFG_VP2MAP_PORTN_gc = (0x0C<<0),
PORTCFG_VP2MAP_PORTP_gc = (0x0D<<0),
PORTCFG_VP2MAP_PORTQ_gc = (0x0E<<0),
PORTCFG_VP2MAP_PORTR_gc = (0x0F<<0),
PORTCFG_VP2MAP_PORTA_gc = (0x00<<0),
PORTCFG_VP2MAP_PORTB_gc = (0x01<<0),
PORTCFG_VP2MAP_PORTC_gc = (0x02<<0),
PORTCFG_VP2MAP_PORTD_gc = (0x03<<0),
PORTCFG_VP2MAP_PORTE_gc = (0x04<<0),
PORTCFG_VP2MAP_PORTF_gc = (0x05<<0),
PORTCFG_VP2MAP_PORTG_gc = (0x06<<0),
PORTCFG_VP2MAP_PORTH_gc = (0x07<<0),
PORTCFG_VP2MAP_PORTJ_gc = (0x08<<0),
PORTCFG_VP2MAP_PORTK_gc = (0x09<<0),
PORTCFG_VP2MAP_PORTL_gc = (0x0A<<0),
PORTCFG_VP2MAP_PORTM_gc = (0x0B<<0),
PORTCFG_VP2MAP_PORTN_gc = (0x0C<<0),
PORTCFG_VP2MAP_PORTP_gc = (0x0D<<0),
PORTCFG_VP2MAP_PORTQ_gc = (0x0E<<0),
PORTCFG_VP2MAP_PORTR_gc = (0x0F<<0),
PORTCFG_VP2MAP_PORTA_gc = (0x00<<0),
PORTCFG_VP2MAP_PORTB_gc = (0x01<<0),
PORTCFG_VP2MAP_PORTC_gc = (0x02<<0),
PORTCFG_VP2MAP_PORTD_gc = (0x03<<0),
PORTCFG_VP2MAP_PORTE_gc = (0x04<<0),
PORTCFG_VP2MAP_PORTF_gc = (0x05<<0),
PORTCFG_VP2MAP_PORTG_gc = (0x06<<0),
PORTCFG_VP2MAP_PORTH_gc = (0x07<<0),
PORTCFG_VP2MAP_PORTJ_gc = (0x08<<0),
PORTCFG_VP2MAP_PORTK_gc = (0x09<<0),
PORTCFG_VP2MAP_PORTL_gc = (0x0A<<0),
PORTCFG_VP2MAP_PORTM_gc = (0x0B<<0),
PORTCFG_VP2MAP_PORTN_gc = (0x0C<<0),
PORTCFG_VP2MAP_PORTP_gc = (0x0D<<0),
PORTCFG_VP2MAP_PORTQ_gc = (0x0E<<0),
PORTCFG_VP2MAP_PORTR_gc = (0x0F<<0),
PORTCFG_VP2MAP_PORTA_gc = (0x00<<0),
PORTCFG_VP2MAP_PORTB_gc = (0x01<<0),
PORTCFG_VP2MAP_PORTC_gc = (0x02<<0),
PORTCFG_VP2MAP_PORTD_gc = (0x03<<0),
PORTCFG_VP2MAP_PORTE_gc = (0x04<<0),
PORTCFG_VP2MAP_PORTF_gc = (0x05<<0),
PORTCFG_VP2MAP_PORTG_gc = (0x06<<0),
PORTCFG_VP2MAP_PORTH_gc = (0x07<<0),
PORTCFG_VP2MAP_PORTJ_gc = (0x08<<0),
PORTCFG_VP2MAP_PORTK_gc = (0x09<<0),
PORTCFG_VP2MAP_PORTL_gc = (0x0A<<0),
PORTCFG_VP2MAP_PORTM_gc = (0x0B<<0),
PORTCFG_VP2MAP_PORTN_gc = (0x0C<<0),
PORTCFG_VP2MAP_PORTP_gc = (0x0D<<0),
PORTCFG_VP2MAP_PORTQ_gc = (0x0E<<0),
PORTCFG_VP2MAP_PORTR_gc = (0x0F<<0),
PORTCFG_VP2MAP_PORTA_gc = (0x00<<0),
PORTCFG_VP2MAP_PORTB_gc = (0x01<<0),
PORTCFG_VP2MAP_PORTC_gc = (0x02<<0),
PORTCFG_VP2MAP_PORTD_gc = (0x03<<0),
PORTCFG_VP2MAP_PORTE_gc = (0x04<<0),
PORTCFG_VP2MAP_PORTF_gc = (0x05<<0),
PORTCFG_VP2MAP_PORTG_gc = (0x06<<0),
PORTCFG_VP2MAP_PORTH_gc = (0x07<<0),
PORTCFG_VP2MAP_PORTJ_gc = (0x08<<0),
PORTCFG_VP2MAP_PORTK_gc = (0x09<<0),
PORTCFG_VP2MAP_PORTL_gc = (0x0A<<0),
PORTCFG_VP2MAP_PORTM_gc = (0x0B<<0),
PORTCFG_VP2MAP_PORTN_gc = (0x0C<<0),
PORTCFG_VP2MAP_PORTP_gc = (0x0D<<0),
PORTCFG_VP2MAP_PORTQ_gc = (0x0E<<0),
PORTCFG_VP2MAP_PORTR_gc = (0x0F<<0),
PORTCFG_VP2MAP_PORTA_gc = (0x00<<0),
PORTCFG_VP2MAP_PORTB_gc = (0x01<<0),
PORTCFG_VP2MAP_PORTC_gc = (0x02<<0),
PORTCFG_VP2MAP_PORTD_gc = (0x03<<0),
PORTCFG_VP2MAP_PORTE_gc = (0x04<<0),
PORTCFG_VP2MAP_PORTF_gc = (0x05<<0),
PORTCFG_VP2MAP_PORTG_gc = (0x06<<0),
PORTCFG_VP2MAP_PORTH_gc = (0x07<<0),
PORTCFG_VP2MAP_PORTJ_gc = (0x08<<0),
PORTCFG_VP2MAP_PORTK_gc = (0x09<<0),
PORTCFG_VP2MAP_PORTL_gc = (0x0A<<0),
PORTCFG_VP2MAP_PORTM_gc = (0x0B<<0),
PORTCFG_VP2MAP_PORTN_gc = (0x0C<<0),
PORTCFG_VP2MAP_PORTP_gc = (0x0D<<0),
PORTCFG_VP2MAP_PORTQ_gc = (0x0E<<0),
PORTCFG_VP2MAP_PORTR_gc = (0x0F<<0)
} |
|
enum | PORTCFG_VP3MAP_enum {
PORTCFG_VP3MAP_PORTA_gc = (0x00<<4),
PORTCFG_VP3MAP_PORTB_gc = (0x01<<4),
PORTCFG_VP3MAP_PORTC_gc = (0x02<<4),
PORTCFG_VP3MAP_PORTD_gc = (0x03<<4),
PORTCFG_VP3MAP_PORTE_gc = (0x04<<4),
PORTCFG_VP3MAP_PORTF_gc = (0x05<<4),
PORTCFG_VP3MAP_PORTG_gc = (0x06<<4),
PORTCFG_VP3MAP_PORTH_gc = (0x07<<4),
PORTCFG_VP3MAP_PORTJ_gc = (0x08<<4),
PORTCFG_VP3MAP_PORTK_gc = (0x09<<4),
PORTCFG_VP3MAP_PORTL_gc = (0x0A<<4),
PORTCFG_VP3MAP_PORTM_gc = (0x0B<<4),
PORTCFG_VP3MAP_PORTN_gc = (0x0C<<4),
PORTCFG_VP3MAP_PORTP_gc = (0x0D<<4),
PORTCFG_VP3MAP_PORTQ_gc = (0x0E<<4),
PORTCFG_VP3MAP_PORTR_gc = (0x0F<<4),
PORTCFG_VP3MAP_PORTA_gc = (0x00<<4),
PORTCFG_VP3MAP_PORTB_gc = (0x01<<4),
PORTCFG_VP3MAP_PORTC_gc = (0x02<<4),
PORTCFG_VP3MAP_PORTD_gc = (0x03<<4),
PORTCFG_VP3MAP_PORTE_gc = (0x04<<4),
PORTCFG_VP3MAP_PORTF_gc = (0x05<<4),
PORTCFG_VP3MAP_PORTG_gc = (0x06<<4),
PORTCFG_VP3MAP_PORTH_gc = (0x07<<4),
PORTCFG_VP3MAP_PORTJ_gc = (0x08<<4),
PORTCFG_VP3MAP_PORTK_gc = (0x09<<4),
PORTCFG_VP3MAP_PORTL_gc = (0x0A<<4),
PORTCFG_VP3MAP_PORTM_gc = (0x0B<<4),
PORTCFG_VP3MAP_PORTN_gc = (0x0C<<4),
PORTCFG_VP3MAP_PORTP_gc = (0x0D<<4),
PORTCFG_VP3MAP_PORTQ_gc = (0x0E<<4),
PORTCFG_VP3MAP_PORTR_gc = (0x0F<<4),
PORTCFG_VP3MAP_PORTA_gc = (0x00<<4),
PORTCFG_VP3MAP_PORTB_gc = (0x01<<4),
PORTCFG_VP3MAP_PORTC_gc = (0x02<<4),
PORTCFG_VP3MAP_PORTD_gc = (0x03<<4),
PORTCFG_VP3MAP_PORTE_gc = (0x04<<4),
PORTCFG_VP3MAP_PORTF_gc = (0x05<<4),
PORTCFG_VP3MAP_PORTG_gc = (0x06<<4),
PORTCFG_VP3MAP_PORTH_gc = (0x07<<4),
PORTCFG_VP3MAP_PORTJ_gc = (0x08<<4),
PORTCFG_VP3MAP_PORTK_gc = (0x09<<4),
PORTCFG_VP3MAP_PORTL_gc = (0x0A<<4),
PORTCFG_VP3MAP_PORTM_gc = (0x0B<<4),
PORTCFG_VP3MAP_PORTN_gc = (0x0C<<4),
PORTCFG_VP3MAP_PORTP_gc = (0x0D<<4),
PORTCFG_VP3MAP_PORTQ_gc = (0x0E<<4),
PORTCFG_VP3MAP_PORTR_gc = (0x0F<<4),
PORTCFG_VP3MAP_PORTA_gc = (0x00<<4),
PORTCFG_VP3MAP_PORTB_gc = (0x01<<4),
PORTCFG_VP3MAP_PORTC_gc = (0x02<<4),
PORTCFG_VP3MAP_PORTD_gc = (0x03<<4),
PORTCFG_VP3MAP_PORTE_gc = (0x04<<4),
PORTCFG_VP3MAP_PORTF_gc = (0x05<<4),
PORTCFG_VP3MAP_PORTG_gc = (0x06<<4),
PORTCFG_VP3MAP_PORTH_gc = (0x07<<4),
PORTCFG_VP3MAP_PORTJ_gc = (0x08<<4),
PORTCFG_VP3MAP_PORTK_gc = (0x09<<4),
PORTCFG_VP3MAP_PORTL_gc = (0x0A<<4),
PORTCFG_VP3MAP_PORTM_gc = (0x0B<<4),
PORTCFG_VP3MAP_PORTN_gc = (0x0C<<4),
PORTCFG_VP3MAP_PORTP_gc = (0x0D<<4),
PORTCFG_VP3MAP_PORTQ_gc = (0x0E<<4),
PORTCFG_VP3MAP_PORTR_gc = (0x0F<<4),
PORTCFG_VP3MAP_PORTA_gc = (0x00<<4),
PORTCFG_VP3MAP_PORTB_gc = (0x01<<4),
PORTCFG_VP3MAP_PORTC_gc = (0x02<<4),
PORTCFG_VP3MAP_PORTD_gc = (0x03<<4),
PORTCFG_VP3MAP_PORTE_gc = (0x04<<4),
PORTCFG_VP3MAP_PORTF_gc = (0x05<<4),
PORTCFG_VP3MAP_PORTG_gc = (0x06<<4),
PORTCFG_VP3MAP_PORTH_gc = (0x07<<4),
PORTCFG_VP3MAP_PORTJ_gc = (0x08<<4),
PORTCFG_VP3MAP_PORTK_gc = (0x09<<4),
PORTCFG_VP3MAP_PORTL_gc = (0x0A<<4),
PORTCFG_VP3MAP_PORTM_gc = (0x0B<<4),
PORTCFG_VP3MAP_PORTN_gc = (0x0C<<4),
PORTCFG_VP3MAP_PORTP_gc = (0x0D<<4),
PORTCFG_VP3MAP_PORTQ_gc = (0x0E<<4),
PORTCFG_VP3MAP_PORTR_gc = (0x0F<<4),
PORTCFG_VP3MAP_PORTA_gc = (0x00<<4),
PORTCFG_VP3MAP_PORTB_gc = (0x01<<4),
PORTCFG_VP3MAP_PORTC_gc = (0x02<<4),
PORTCFG_VP3MAP_PORTD_gc = (0x03<<4),
PORTCFG_VP3MAP_PORTE_gc = (0x04<<4),
PORTCFG_VP3MAP_PORTF_gc = (0x05<<4),
PORTCFG_VP3MAP_PORTG_gc = (0x06<<4),
PORTCFG_VP3MAP_PORTH_gc = (0x07<<4),
PORTCFG_VP3MAP_PORTJ_gc = (0x08<<4),
PORTCFG_VP3MAP_PORTK_gc = (0x09<<4),
PORTCFG_VP3MAP_PORTL_gc = (0x0A<<4),
PORTCFG_VP3MAP_PORTM_gc = (0x0B<<4),
PORTCFG_VP3MAP_PORTN_gc = (0x0C<<4),
PORTCFG_VP3MAP_PORTP_gc = (0x0D<<4),
PORTCFG_VP3MAP_PORTQ_gc = (0x0E<<4),
PORTCFG_VP3MAP_PORTR_gc = (0x0F<<4),
PORTCFG_VP3MAP_PORTA_gc = (0x00<<4),
PORTCFG_VP3MAP_PORTB_gc = (0x01<<4),
PORTCFG_VP3MAP_PORTC_gc = (0x02<<4),
PORTCFG_VP3MAP_PORTD_gc = (0x03<<4),
PORTCFG_VP3MAP_PORTE_gc = (0x04<<4),
PORTCFG_VP3MAP_PORTF_gc = (0x05<<4),
PORTCFG_VP3MAP_PORTG_gc = (0x06<<4),
PORTCFG_VP3MAP_PORTH_gc = (0x07<<4),
PORTCFG_VP3MAP_PORTJ_gc = (0x08<<4),
PORTCFG_VP3MAP_PORTK_gc = (0x09<<4),
PORTCFG_VP3MAP_PORTL_gc = (0x0A<<4),
PORTCFG_VP3MAP_PORTM_gc = (0x0B<<4),
PORTCFG_VP3MAP_PORTN_gc = (0x0C<<4),
PORTCFG_VP3MAP_PORTP_gc = (0x0D<<4),
PORTCFG_VP3MAP_PORTQ_gc = (0x0E<<4),
PORTCFG_VP3MAP_PORTR_gc = (0x0F<<4),
PORTCFG_VP3MAP_PORTA_gc = (0x00<<4),
PORTCFG_VP3MAP_PORTB_gc = (0x01<<4),
PORTCFG_VP3MAP_PORTC_gc = (0x02<<4),
PORTCFG_VP3MAP_PORTD_gc = (0x03<<4),
PORTCFG_VP3MAP_PORTE_gc = (0x04<<4),
PORTCFG_VP3MAP_PORTF_gc = (0x05<<4),
PORTCFG_VP3MAP_PORTG_gc = (0x06<<4),
PORTCFG_VP3MAP_PORTH_gc = (0x07<<4),
PORTCFG_VP3MAP_PORTJ_gc = (0x08<<4),
PORTCFG_VP3MAP_PORTK_gc = (0x09<<4),
PORTCFG_VP3MAP_PORTL_gc = (0x0A<<4),
PORTCFG_VP3MAP_PORTM_gc = (0x0B<<4),
PORTCFG_VP3MAP_PORTN_gc = (0x0C<<4),
PORTCFG_VP3MAP_PORTP_gc = (0x0D<<4),
PORTCFG_VP3MAP_PORTQ_gc = (0x0E<<4),
PORTCFG_VP3MAP_PORTR_gc = (0x0F<<4),
PORTCFG_VP3MAP_PORTA_gc = (0x00<<4),
PORTCFG_VP3MAP_PORTB_gc = (0x01<<4),
PORTCFG_VP3MAP_PORTC_gc = (0x02<<4),
PORTCFG_VP3MAP_PORTD_gc = (0x03<<4),
PORTCFG_VP3MAP_PORTE_gc = (0x04<<4),
PORTCFG_VP3MAP_PORTF_gc = (0x05<<4),
PORTCFG_VP3MAP_PORTG_gc = (0x06<<4),
PORTCFG_VP3MAP_PORTH_gc = (0x07<<4),
PORTCFG_VP3MAP_PORTJ_gc = (0x08<<4),
PORTCFG_VP3MAP_PORTK_gc = (0x09<<4),
PORTCFG_VP3MAP_PORTL_gc = (0x0A<<4),
PORTCFG_VP3MAP_PORTM_gc = (0x0B<<4),
PORTCFG_VP3MAP_PORTN_gc = (0x0C<<4),
PORTCFG_VP3MAP_PORTP_gc = (0x0D<<4),
PORTCFG_VP3MAP_PORTQ_gc = (0x0E<<4),
PORTCFG_VP3MAP_PORTR_gc = (0x0F<<4),
PORTCFG_VP3MAP_PORTA_gc = (0x00<<4),
PORTCFG_VP3MAP_PORTB_gc = (0x01<<4),
PORTCFG_VP3MAP_PORTC_gc = (0x02<<4),
PORTCFG_VP3MAP_PORTD_gc = (0x03<<4),
PORTCFG_VP3MAP_PORTE_gc = (0x04<<4),
PORTCFG_VP3MAP_PORTF_gc = (0x05<<4),
PORTCFG_VP3MAP_PORTG_gc = (0x06<<4),
PORTCFG_VP3MAP_PORTH_gc = (0x07<<4),
PORTCFG_VP3MAP_PORTJ_gc = (0x08<<4),
PORTCFG_VP3MAP_PORTK_gc = (0x09<<4),
PORTCFG_VP3MAP_PORTL_gc = (0x0A<<4),
PORTCFG_VP3MAP_PORTM_gc = (0x0B<<4),
PORTCFG_VP3MAP_PORTN_gc = (0x0C<<4),
PORTCFG_VP3MAP_PORTP_gc = (0x0D<<4),
PORTCFG_VP3MAP_PORTQ_gc = (0x0E<<4),
PORTCFG_VP3MAP_PORTR_gc = (0x0F<<4),
PORTCFG_VP3MAP_PORTA_gc = (0x00<<4),
PORTCFG_VP3MAP_PORTB_gc = (0x01<<4),
PORTCFG_VP3MAP_PORTC_gc = (0x02<<4),
PORTCFG_VP3MAP_PORTD_gc = (0x03<<4),
PORTCFG_VP3MAP_PORTE_gc = (0x04<<4),
PORTCFG_VP3MAP_PORTF_gc = (0x05<<4),
PORTCFG_VP3MAP_PORTG_gc = (0x06<<4),
PORTCFG_VP3MAP_PORTH_gc = (0x07<<4),
PORTCFG_VP3MAP_PORTJ_gc = (0x08<<4),
PORTCFG_VP3MAP_PORTK_gc = (0x09<<4),
PORTCFG_VP3MAP_PORTL_gc = (0x0A<<4),
PORTCFG_VP3MAP_PORTM_gc = (0x0B<<4),
PORTCFG_VP3MAP_PORTN_gc = (0x0C<<4),
PORTCFG_VP3MAP_PORTP_gc = (0x0D<<4),
PORTCFG_VP3MAP_PORTQ_gc = (0x0E<<4),
PORTCFG_VP3MAP_PORTR_gc = (0x0F<<4),
PORTCFG_VP3MAP_PORTA_gc = (0x00<<4),
PORTCFG_VP3MAP_PORTB_gc = (0x01<<4),
PORTCFG_VP3MAP_PORTC_gc = (0x02<<4),
PORTCFG_VP3MAP_PORTD_gc = (0x03<<4),
PORTCFG_VP3MAP_PORTE_gc = (0x04<<4),
PORTCFG_VP3MAP_PORTF_gc = (0x05<<4),
PORTCFG_VP3MAP_PORTG_gc = (0x06<<4),
PORTCFG_VP3MAP_PORTH_gc = (0x07<<4),
PORTCFG_VP3MAP_PORTJ_gc = (0x08<<4),
PORTCFG_VP3MAP_PORTK_gc = (0x09<<4),
PORTCFG_VP3MAP_PORTL_gc = (0x0A<<4),
PORTCFG_VP3MAP_PORTM_gc = (0x0B<<4),
PORTCFG_VP3MAP_PORTN_gc = (0x0C<<4),
PORTCFG_VP3MAP_PORTP_gc = (0x0D<<4),
PORTCFG_VP3MAP_PORTQ_gc = (0x0E<<4),
PORTCFG_VP3MAP_PORTR_gc = (0x0F<<4),
PORTCFG_VP3MAP_PORTA_gc = (0x00<<4),
PORTCFG_VP3MAP_PORTB_gc = (0x01<<4),
PORTCFG_VP3MAP_PORTC_gc = (0x02<<4),
PORTCFG_VP3MAP_PORTD_gc = (0x03<<4),
PORTCFG_VP3MAP_PORTE_gc = (0x04<<4),
PORTCFG_VP3MAP_PORTF_gc = (0x05<<4),
PORTCFG_VP3MAP_PORTG_gc = (0x06<<4),
PORTCFG_VP3MAP_PORTH_gc = (0x07<<4),
PORTCFG_VP3MAP_PORTJ_gc = (0x08<<4),
PORTCFG_VP3MAP_PORTK_gc = (0x09<<4),
PORTCFG_VP3MAP_PORTL_gc = (0x0A<<4),
PORTCFG_VP3MAP_PORTM_gc = (0x0B<<4),
PORTCFG_VP3MAP_PORTN_gc = (0x0C<<4),
PORTCFG_VP3MAP_PORTP_gc = (0x0D<<4),
PORTCFG_VP3MAP_PORTQ_gc = (0x0E<<4),
PORTCFG_VP3MAP_PORTR_gc = (0x0F<<4),
PORTCFG_VP3MAP_PORTA_gc = (0x00<<4),
PORTCFG_VP3MAP_PORTB_gc = (0x01<<4),
PORTCFG_VP3MAP_PORTC_gc = (0x02<<4),
PORTCFG_VP3MAP_PORTD_gc = (0x03<<4),
PORTCFG_VP3MAP_PORTE_gc = (0x04<<4),
PORTCFG_VP3MAP_PORTF_gc = (0x05<<4),
PORTCFG_VP3MAP_PORTG_gc = (0x06<<4),
PORTCFG_VP3MAP_PORTH_gc = (0x07<<4),
PORTCFG_VP3MAP_PORTJ_gc = (0x08<<4),
PORTCFG_VP3MAP_PORTK_gc = (0x09<<4),
PORTCFG_VP3MAP_PORTL_gc = (0x0A<<4),
PORTCFG_VP3MAP_PORTM_gc = (0x0B<<4),
PORTCFG_VP3MAP_PORTN_gc = (0x0C<<4),
PORTCFG_VP3MAP_PORTP_gc = (0x0D<<4),
PORTCFG_VP3MAP_PORTQ_gc = (0x0E<<4),
PORTCFG_VP3MAP_PORTR_gc = (0x0F<<4),
PORTCFG_VP3MAP_PORTA_gc = (0x00<<4),
PORTCFG_VP3MAP_PORTB_gc = (0x01<<4),
PORTCFG_VP3MAP_PORTC_gc = (0x02<<4),
PORTCFG_VP3MAP_PORTD_gc = (0x03<<4),
PORTCFG_VP3MAP_PORTE_gc = (0x04<<4),
PORTCFG_VP3MAP_PORTF_gc = (0x05<<4),
PORTCFG_VP3MAP_PORTG_gc = (0x06<<4),
PORTCFG_VP3MAP_PORTH_gc = (0x07<<4),
PORTCFG_VP3MAP_PORTJ_gc = (0x08<<4),
PORTCFG_VP3MAP_PORTK_gc = (0x09<<4),
PORTCFG_VP3MAP_PORTL_gc = (0x0A<<4),
PORTCFG_VP3MAP_PORTM_gc = (0x0B<<4),
PORTCFG_VP3MAP_PORTN_gc = (0x0C<<4),
PORTCFG_VP3MAP_PORTP_gc = (0x0D<<4),
PORTCFG_VP3MAP_PORTQ_gc = (0x0E<<4),
PORTCFG_VP3MAP_PORTR_gc = (0x0F<<4)
} |
|
enum | PORTCFG_CLKOUT_enum {
PORTCFG_CLKOUT_OFF_gc = (0x00<<0),
PORTCFG_CLKOUT_PC7_gc = (0x01<<0),
PORTCFG_CLKOUT_PD7_gc = (0x02<<0),
PORTCFG_CLKOUT_PE7_gc = (0x03<<0),
PORTCFG_CLKOUT_OFF_gc = (0x00<<0),
PORTCFG_CLKOUT_PC7_gc = (0x01<<0),
PORTCFG_CLKOUT_PD7_gc = (0x02<<0),
PORTCFG_CLKOUT_PE7_gc = (0x03<<0),
PORTCFG_CLKOUT_OFF_gc = (0x00<<0),
PORTCFG_CLKOUT_PC7_gc = (0x01<<0),
PORTCFG_CLKOUT_PD7_gc = (0x02<<0),
PORTCFG_CLKOUT_PE7_gc = (0x03<<0),
PORTCFG_CLKOUT_OFF_gc = (0x00<<0),
PORTCFG_CLKOUT_PC7_gc = (0x01<<0),
PORTCFG_CLKOUT_PD7_gc = (0x02<<0),
PORTCFG_CLKOUT_PE7_gc = (0x03<<0),
PORTCFG_CLKOUT_OFF_gc = (0x00<<0),
PORTCFG_CLKOUT_PC7_gc = (0x01<<0),
PORTCFG_CLKOUT_PD7_gc = (0x02<<0),
PORTCFG_CLKOUT_PE7_gc = (0x03<<0),
PORTCFG_CLKOUT_OFF_gc = (0x00<<0),
PORTCFG_CLKOUT_PC7_gc = (0x01<<0),
PORTCFG_CLKOUT_PD7_gc = (0x02<<0),
PORTCFG_CLKOUT_PE7_gc = (0x03<<0),
PORTCFG_CLKOUT_OFF_gc = (0x00<<0),
PORTCFG_CLKOUT_PC7_gc = (0x01<<0),
PORTCFG_CLKOUT_PD7_gc = (0x02<<0),
PORTCFG_CLKOUT_PE7_gc = (0x03<<0),
PORTCFG_CLKOUT_OFF_gc = (0x00<<0),
PORTCFG_CLKOUT_PC7_gc = (0x01<<0),
PORTCFG_CLKOUT_PD7_gc = (0x02<<0),
PORTCFG_CLKOUT_PE7_gc = (0x03<<0),
PORTCFG_CLKOUT_OFF_gc = (0x00<<0),
PORTCFG_CLKOUT_PC7_gc = (0x01<<0),
PORTCFG_CLKOUT_PD7_gc = (0x02<<0),
PORTCFG_CLKOUT_PE7_gc = (0x03<<0),
PORTCFG_CLKOUT_OFF_gc = (0x00<<0),
PORTCFG_CLKOUT_PC7_gc = (0x01<<0),
PORTCFG_CLKOUT_PD7_gc = (0x02<<0),
PORTCFG_CLKOUT_PE7_gc = (0x03<<0),
PORTCFG_CLKOUT_OFF_gc = (0x00<<0),
PORTCFG_CLKOUT_PC7_gc = (0x01<<0),
PORTCFG_CLKOUT_PD7_gc = (0x02<<0),
PORTCFG_CLKOUT_PE7_gc = (0x03<<0),
PORTCFG_CLKOUT_OFF_gc = (0x00<<0),
PORTCFG_CLKOUT_PC7_gc = (0x01<<0),
PORTCFG_CLKOUT_PD7_gc = (0x02<<0),
PORTCFG_CLKOUT_PE7_gc = (0x03<<0),
PORTCFG_CLKOUT_OFF_gc = (0x00<<0),
PORTCFG_CLKOUT_PC7_gc = (0x01<<0),
PORTCFG_CLKOUT_PD7_gc = (0x02<<0),
PORTCFG_CLKOUT_PE7_gc = (0x03<<0),
PORTCFG_CLKOUT_OFF_gc = (0x00<<0),
PORTCFG_CLKOUT_PC7_gc = (0x01<<0),
PORTCFG_CLKOUT_PD7_gc = (0x02<<0),
PORTCFG_CLKOUT_PE7_gc = (0x03<<0),
PORTCFG_CLKOUT_OFF_gc = (0x00<<0),
PORTCFG_CLKOUT_PC7_gc = (0x01<<0),
PORTCFG_CLKOUT_PD7_gc = (0x02<<0),
PORTCFG_CLKOUT_PE7_gc = (0x03<<0)
} |
|
enum | PORTCFG_EVOUT_enum {
PORTCFG_EVOUT_OFF_gc = (0x00<<4),
PORTCFG_EVOUT_PC7_gc = (0x01<<4),
PORTCFG_EVOUT_PD7_gc = (0x02<<4),
PORTCFG_EVOUT_PE7_gc = (0x03<<4),
PORTCFG_EVOUT_OFF_gc = (0x00<<4),
PORTCFG_EVOUT_PC7_gc = (0x01<<4),
PORTCFG_EVOUT_PD7_gc = (0x02<<4),
PORTCFG_EVOUT_PE7_gc = (0x03<<4),
PORTCFG_EVOUT_OFF_gc = (0x00<<4),
PORTCFG_EVOUT_PC7_gc = (0x01<<4),
PORTCFG_EVOUT_PD7_gc = (0x02<<4),
PORTCFG_EVOUT_PE7_gc = (0x03<<4),
PORTCFG_EVOUT_OFF_gc = (0x00<<4),
PORTCFG_EVOUT_PC7_gc = (0x01<<4),
PORTCFG_EVOUT_PD7_gc = (0x02<<4),
PORTCFG_EVOUT_PE7_gc = (0x03<<4),
PORTCFG_EVOUT_OFF_gc = (0x00<<4),
PORTCFG_EVOUT_PC7_gc = (0x01<<4),
PORTCFG_EVOUT_PD7_gc = (0x02<<4),
PORTCFG_EVOUT_PE7_gc = (0x03<<4),
PORTCFG_EVOUT_OFF_gc = (0x00<<4),
PORTCFG_EVOUT_PC7_gc = (0x01<<4),
PORTCFG_EVOUT_PD7_gc = (0x02<<4),
PORTCFG_EVOUT_PE7_gc = (0x03<<4),
PORTCFG_EVOUT_OFF_gc = (0x00<<4),
PORTCFG_EVOUT_PC7_gc = (0x01<<4),
PORTCFG_EVOUT_PD7_gc = (0x02<<4),
PORTCFG_EVOUT_PE7_gc = (0x03<<4),
PORTCFG_EVOUT_OFF_gc = (0x00<<4),
PORTCFG_EVOUT_PC7_gc = (0x01<<4),
PORTCFG_EVOUT_PD7_gc = (0x02<<4),
PORTCFG_EVOUT_PE7_gc = (0x03<<4),
PORTCFG_EVOUT_OFF_gc = (0x00<<4),
PORTCFG_EVOUT_PC7_gc = (0x01<<4),
PORTCFG_EVOUT_PD7_gc = (0x02<<4),
PORTCFG_EVOUT_PE7_gc = (0x03<<4),
PORTCFG_EVOUT_OFF_gc = (0x00<<4),
PORTCFG_EVOUT_PC7_gc = (0x01<<4),
PORTCFG_EVOUT_PD7_gc = (0x02<<4),
PORTCFG_EVOUT_PE7_gc = (0x03<<4),
PORTCFG_EVOUT_OFF_gc = (0x00<<4),
PORTCFG_EVOUT_PC7_gc = (0x01<<4),
PORTCFG_EVOUT_PD7_gc = (0x02<<4),
PORTCFG_EVOUT_PE7_gc = (0x03<<4),
PORTCFG_EVOUT_OFF_gc = (0x00<<4),
PORTCFG_EVOUT_PC7_gc = (0x01<<4),
PORTCFG_EVOUT_PD7_gc = (0x02<<4),
PORTCFG_EVOUT_PE7_gc = (0x03<<4),
PORTCFG_EVOUT_OFF_gc = (0x00<<4),
PORTCFG_EVOUT_PC7_gc = (0x01<<4),
PORTCFG_EVOUT_PD7_gc = (0x02<<4),
PORTCFG_EVOUT_PE7_gc = (0x03<<4),
PORTCFG_EVOUT_OFF_gc = (0x00<<4),
PORTCFG_EVOUT_PC7_gc = (0x01<<4),
PORTCFG_EVOUT_PD7_gc = (0x02<<4),
PORTCFG_EVOUT_PE7_gc = (0x03<<4),
PORTCFG_EVOUT_OFF_gc = (0x00<<4),
PORTCFG_EVOUT_PC7_gc = (0x01<<4),
PORTCFG_EVOUT_PD7_gc = (0x02<<4),
PORTCFG_EVOUT_PE7_gc = (0x03<<4)
} |
|
enum | PORT_INT0LVL_enum {
PORT_INT0LVL_OFF_gc = (0x00<<0),
PORT_INT0LVL_LO_gc = (0x01<<0),
PORT_INT0LVL_MED_gc = (0x02<<0),
PORT_INT0LVL_HI_gc = (0x03<<0),
PORT_INT0LVL_OFF_gc = (0x00<<0),
PORT_INT0LVL_LO_gc = (0x01<<0),
PORT_INT0LVL_MED_gc = (0x02<<0),
PORT_INT0LVL_HI_gc = (0x03<<0),
PORT_INT0LVL_OFF_gc = (0x00<<0),
PORT_INT0LVL_LO_gc = (0x01<<0),
PORT_INT0LVL_MED_gc = (0x02<<0),
PORT_INT0LVL_HI_gc = (0x03<<0),
PORT_INT0LVL_OFF_gc = (0x00<<0),
PORT_INT0LVL_LO_gc = (0x01<<0),
PORT_INT0LVL_MED_gc = (0x02<<0),
PORT_INT0LVL_HI_gc = (0x03<<0),
PORT_INT0LVL_OFF_gc = (0x00<<0),
PORT_INT0LVL_LO_gc = (0x01<<0),
PORT_INT0LVL_MED_gc = (0x02<<0),
PORT_INT0LVL_HI_gc = (0x03<<0),
PORT_INT0LVL_OFF_gc = (0x00<<0),
PORT_INT0LVL_LO_gc = (0x01<<0),
PORT_INT0LVL_MED_gc = (0x02<<0),
PORT_INT0LVL_HI_gc = (0x03<<0),
PORT_INT0LVL_OFF_gc = (0x00<<0),
PORT_INT0LVL_LO_gc = (0x01<<0),
PORT_INT0LVL_MED_gc = (0x02<<0),
PORT_INT0LVL_HI_gc = (0x03<<0),
PORT_INT0LVL_OFF_gc = (0x00<<0),
PORT_INT0LVL_LO_gc = (0x01<<0),
PORT_INT0LVL_MED_gc = (0x02<<0),
PORT_INT0LVL_HI_gc = (0x03<<0),
PORT_INT0LVL_OFF_gc = (0x00<<0),
PORT_INT0LVL_LO_gc = (0x01<<0),
PORT_INT0LVL_MED_gc = (0x02<<0),
PORT_INT0LVL_HI_gc = (0x03<<0),
PORT_INT0LVL_OFF_gc = (0x00<<0),
PORT_INT0LVL_LO_gc = (0x01<<0),
PORT_INT0LVL_MED_gc = (0x02<<0),
PORT_INT0LVL_HI_gc = (0x03<<0),
PORT_INT0LVL_OFF_gc = (0x00<<0),
PORT_INT0LVL_LO_gc = (0x01<<0),
PORT_INT0LVL_MED_gc = (0x02<<0),
PORT_INT0LVL_HI_gc = (0x03<<0),
PORT_INT0LVL_OFF_gc = (0x00<<0),
PORT_INT0LVL_LO_gc = (0x01<<0),
PORT_INT0LVL_MED_gc = (0x02<<0),
PORT_INT0LVL_HI_gc = (0x03<<0),
PORT_INT0LVL_OFF_gc = (0x00<<0),
PORT_INT0LVL_LO_gc = (0x01<<0),
PORT_INT0LVL_MED_gc = (0x02<<0),
PORT_INT0LVL_HI_gc = (0x03<<0),
PORT_INT0LVL_OFF_gc = (0x00<<0),
PORT_INT0LVL_LO_gc = (0x01<<0),
PORT_INT0LVL_MED_gc = (0x02<<0),
PORT_INT0LVL_HI_gc = (0x03<<0),
PORT_INT0LVL_OFF_gc = (0x00<<0),
PORT_INT0LVL_LO_gc = (0x01<<0),
PORT_INT0LVL_MED_gc = (0x02<<0),
PORT_INT0LVL_HI_gc = (0x03<<0)
} |
|
enum | PORT_INT1LVL_enum {
PORT_INT1LVL_OFF_gc = (0x00<<2),
PORT_INT1LVL_LO_gc = (0x01<<2),
PORT_INT1LVL_MED_gc = (0x02<<2),
PORT_INT1LVL_HI_gc = (0x03<<2),
PORT_INT1LVL_OFF_gc = (0x00<<2),
PORT_INT1LVL_LO_gc = (0x01<<2),
PORT_INT1LVL_MED_gc = (0x02<<2),
PORT_INT1LVL_HI_gc = (0x03<<2),
PORT_INT1LVL_OFF_gc = (0x00<<2),
PORT_INT1LVL_LO_gc = (0x01<<2),
PORT_INT1LVL_MED_gc = (0x02<<2),
PORT_INT1LVL_HI_gc = (0x03<<2),
PORT_INT1LVL_OFF_gc = (0x00<<2),
PORT_INT1LVL_LO_gc = (0x01<<2),
PORT_INT1LVL_MED_gc = (0x02<<2),
PORT_INT1LVL_HI_gc = (0x03<<2),
PORT_INT1LVL_OFF_gc = (0x00<<2),
PORT_INT1LVL_LO_gc = (0x01<<2),
PORT_INT1LVL_MED_gc = (0x02<<2),
PORT_INT1LVL_HI_gc = (0x03<<2),
PORT_INT1LVL_OFF_gc = (0x00<<2),
PORT_INT1LVL_LO_gc = (0x01<<2),
PORT_INT1LVL_MED_gc = (0x02<<2),
PORT_INT1LVL_HI_gc = (0x03<<2),
PORT_INT1LVL_OFF_gc = (0x00<<2),
PORT_INT1LVL_LO_gc = (0x01<<2),
PORT_INT1LVL_MED_gc = (0x02<<2),
PORT_INT1LVL_HI_gc = (0x03<<2),
PORT_INT1LVL_OFF_gc = (0x00<<2),
PORT_INT1LVL_LO_gc = (0x01<<2),
PORT_INT1LVL_MED_gc = (0x02<<2),
PORT_INT1LVL_HI_gc = (0x03<<2),
PORT_INT1LVL_OFF_gc = (0x00<<2),
PORT_INT1LVL_LO_gc = (0x01<<2),
PORT_INT1LVL_MED_gc = (0x02<<2),
PORT_INT1LVL_HI_gc = (0x03<<2),
PORT_INT1LVL_OFF_gc = (0x00<<2),
PORT_INT1LVL_LO_gc = (0x01<<2),
PORT_INT1LVL_MED_gc = (0x02<<2),
PORT_INT1LVL_HI_gc = (0x03<<2),
PORT_INT1LVL_OFF_gc = (0x00<<2),
PORT_INT1LVL_LO_gc = (0x01<<2),
PORT_INT1LVL_MED_gc = (0x02<<2),
PORT_INT1LVL_HI_gc = (0x03<<2),
PORT_INT1LVL_OFF_gc = (0x00<<2),
PORT_INT1LVL_LO_gc = (0x01<<2),
PORT_INT1LVL_MED_gc = (0x02<<2),
PORT_INT1LVL_HI_gc = (0x03<<2),
PORT_INT1LVL_OFF_gc = (0x00<<2),
PORT_INT1LVL_LO_gc = (0x01<<2),
PORT_INT1LVL_MED_gc = (0x02<<2),
PORT_INT1LVL_HI_gc = (0x03<<2),
PORT_INT1LVL_OFF_gc = (0x00<<2),
PORT_INT1LVL_LO_gc = (0x01<<2),
PORT_INT1LVL_MED_gc = (0x02<<2),
PORT_INT1LVL_HI_gc = (0x03<<2),
PORT_INT1LVL_OFF_gc = (0x00<<2),
PORT_INT1LVL_LO_gc = (0x01<<2),
PORT_INT1LVL_MED_gc = (0x02<<2),
PORT_INT1LVL_HI_gc = (0x03<<2)
} |
|
enum | PORT_OPC_enum {
PORT_OPC_TOTEM_gc = (0x00<<3),
PORT_OPC_BUSKEEPER_gc = (0x01<<3),
PORT_OPC_PULLDOWN_gc = (0x02<<3),
PORT_OPC_PULLUP_gc = (0x03<<3),
PORT_OPC_WIREDOR_gc = (0x04<<3),
PORT_OPC_WIREDAND_gc = (0x05<<3),
PORT_OPC_WIREDORPULL_gc = (0x06<<3),
PORT_OPC_WIREDANDPULL_gc = (0x07<<3),
PORT_OPC_TOTEM_gc = (0x00<<3),
PORT_OPC_BUSKEEPER_gc = (0x01<<3),
PORT_OPC_PULLDOWN_gc = (0x02<<3),
PORT_OPC_PULLUP_gc = (0x03<<3),
PORT_OPC_WIREDOR_gc = (0x04<<3),
PORT_OPC_WIREDAND_gc = (0x05<<3),
PORT_OPC_WIREDORPULL_gc = (0x06<<3),
PORT_OPC_WIREDANDPULL_gc = (0x07<<3),
PORT_OPC_TOTEM_gc = (0x00<<3),
PORT_OPC_BUSKEEPER_gc = (0x01<<3),
PORT_OPC_PULLDOWN_gc = (0x02<<3),
PORT_OPC_PULLUP_gc = (0x03<<3),
PORT_OPC_WIREDOR_gc = (0x04<<3),
PORT_OPC_WIREDAND_gc = (0x05<<3),
PORT_OPC_WIREDORPULL_gc = (0x06<<3),
PORT_OPC_WIREDANDPULL_gc = (0x07<<3),
PORT_OPC_TOTEM_gc = (0x00<<3),
PORT_OPC_BUSKEEPER_gc = (0x01<<3),
PORT_OPC_PULLDOWN_gc = (0x02<<3),
PORT_OPC_PULLUP_gc = (0x03<<3),
PORT_OPC_WIREDOR_gc = (0x04<<3),
PORT_OPC_WIREDAND_gc = (0x05<<3),
PORT_OPC_WIREDORPULL_gc = (0x06<<3),
PORT_OPC_WIREDANDPULL_gc = (0x07<<3),
PORT_OPC_TOTEM_gc = (0x00<<3),
PORT_OPC_BUSKEEPER_gc = (0x01<<3),
PORT_OPC_PULLDOWN_gc = (0x02<<3),
PORT_OPC_PULLUP_gc = (0x03<<3),
PORT_OPC_WIREDOR_gc = (0x04<<3),
PORT_OPC_WIREDAND_gc = (0x05<<3),
PORT_OPC_WIREDORPULL_gc = (0x06<<3),
PORT_OPC_WIREDANDPULL_gc = (0x07<<3),
PORT_OPC_TOTEM_gc = (0x00<<3),
PORT_OPC_BUSKEEPER_gc = (0x01<<3),
PORT_OPC_PULLDOWN_gc = (0x02<<3),
PORT_OPC_PULLUP_gc = (0x03<<3),
PORT_OPC_WIREDOR_gc = (0x04<<3),
PORT_OPC_WIREDAND_gc = (0x05<<3),
PORT_OPC_WIREDORPULL_gc = (0x06<<3),
PORT_OPC_WIREDANDPULL_gc = (0x07<<3),
PORT_OPC_TOTEM_gc = (0x00<<3),
PORT_OPC_BUSKEEPER_gc = (0x01<<3),
PORT_OPC_PULLDOWN_gc = (0x02<<3),
PORT_OPC_PULLUP_gc = (0x03<<3),
PORT_OPC_WIREDOR_gc = (0x04<<3),
PORT_OPC_WIREDAND_gc = (0x05<<3),
PORT_OPC_WIREDORPULL_gc = (0x06<<3),
PORT_OPC_WIREDANDPULL_gc = (0x07<<3),
PORT_OPC_TOTEM_gc = (0x00<<3),
PORT_OPC_BUSKEEPER_gc = (0x01<<3),
PORT_OPC_PULLDOWN_gc = (0x02<<3),
PORT_OPC_PULLUP_gc = (0x03<<3),
PORT_OPC_WIREDOR_gc = (0x04<<3),
PORT_OPC_WIREDAND_gc = (0x05<<3),
PORT_OPC_WIREDORPULL_gc = (0x06<<3),
PORT_OPC_WIREDANDPULL_gc = (0x07<<3),
PORT_OPC_TOTEM_gc = (0x00<<3),
PORT_OPC_BUSKEEPER_gc = (0x01<<3),
PORT_OPC_PULLDOWN_gc = (0x02<<3),
PORT_OPC_PULLUP_gc = (0x03<<3),
PORT_OPC_WIREDOR_gc = (0x04<<3),
PORT_OPC_WIREDAND_gc = (0x05<<3),
PORT_OPC_WIREDORPULL_gc = (0x06<<3),
PORT_OPC_WIREDANDPULL_gc = (0x07<<3),
PORT_OPC_TOTEM_gc = (0x00<<3),
PORT_OPC_BUSKEEPER_gc = (0x01<<3),
PORT_OPC_PULLDOWN_gc = (0x02<<3),
PORT_OPC_PULLUP_gc = (0x03<<3),
PORT_OPC_WIREDOR_gc = (0x04<<3),
PORT_OPC_WIREDAND_gc = (0x05<<3),
PORT_OPC_WIREDORPULL_gc = (0x06<<3),
PORT_OPC_WIREDANDPULL_gc = (0x07<<3),
PORT_OPC_TOTEM_gc = (0x00<<3),
PORT_OPC_BUSKEEPER_gc = (0x01<<3),
PORT_OPC_PULLDOWN_gc = (0x02<<3),
PORT_OPC_PULLUP_gc = (0x03<<3),
PORT_OPC_WIREDOR_gc = (0x04<<3),
PORT_OPC_WIREDAND_gc = (0x05<<3),
PORT_OPC_WIREDORPULL_gc = (0x06<<3),
PORT_OPC_WIREDANDPULL_gc = (0x07<<3),
PORT_OPC_TOTEM_gc = (0x00<<3),
PORT_OPC_BUSKEEPER_gc = (0x01<<3),
PORT_OPC_PULLDOWN_gc = (0x02<<3),
PORT_OPC_PULLUP_gc = (0x03<<3),
PORT_OPC_WIREDOR_gc = (0x04<<3),
PORT_OPC_WIREDAND_gc = (0x05<<3),
PORT_OPC_WIREDORPULL_gc = (0x06<<3),
PORT_OPC_WIREDANDPULL_gc = (0x07<<3),
PORT_OPC_TOTEM_gc = (0x00<<3),
PORT_OPC_BUSKEEPER_gc = (0x01<<3),
PORT_OPC_PULLDOWN_gc = (0x02<<3),
PORT_OPC_PULLUP_gc = (0x03<<3),
PORT_OPC_WIREDOR_gc = (0x04<<3),
PORT_OPC_WIREDAND_gc = (0x05<<3),
PORT_OPC_WIREDORPULL_gc = (0x06<<3),
PORT_OPC_WIREDANDPULL_gc = (0x07<<3),
PORT_OPC_TOTEM_gc = (0x00<<3),
PORT_OPC_BUSKEEPER_gc = (0x01<<3),
PORT_OPC_PULLDOWN_gc = (0x02<<3),
PORT_OPC_PULLUP_gc = (0x03<<3),
PORT_OPC_WIREDOR_gc = (0x04<<3),
PORT_OPC_WIREDAND_gc = (0x05<<3),
PORT_OPC_WIREDORPULL_gc = (0x06<<3),
PORT_OPC_WIREDANDPULL_gc = (0x07<<3),
PORT_OPC_TOTEM_gc = (0x00<<3),
PORT_OPC_BUSKEEPER_gc = (0x01<<3),
PORT_OPC_PULLDOWN_gc = (0x02<<3),
PORT_OPC_PULLUP_gc = (0x03<<3),
PORT_OPC_WIREDOR_gc = (0x04<<3),
PORT_OPC_WIREDAND_gc = (0x05<<3),
PORT_OPC_WIREDORPULL_gc = (0x06<<3),
PORT_OPC_WIREDANDPULL_gc = (0x07<<3)
} |
|
enum | PORT_ISC_enum {
PORT_ISC_BOTHEDGES_gc = (0x00<<0),
PORT_ISC_RISING_gc = (0x01<<0),
PORT_ISC_FALLING_gc = (0x02<<0),
PORT_ISC_LEVEL_gc = (0x03<<0),
PORT_ISC_INPUT_DISABLE_gc = (0x07<<0),
PORT_ISC_BOTHEDGES_gc = (0x00<<0),
PORT_ISC_RISING_gc = (0x01<<0),
PORT_ISC_FALLING_gc = (0x02<<0),
PORT_ISC_LEVEL_gc = (0x03<<0),
PORT_ISC_INPUT_DISABLE_gc = (0x07<<0),
PORT_ISC_BOTHEDGES_gc = (0x00<<0),
PORT_ISC_RISING_gc = (0x01<<0),
PORT_ISC_FALLING_gc = (0x02<<0),
PORT_ISC_LEVEL_gc = (0x03<<0),
PORT_ISC_INPUT_DISABLE_gc = (0x07<<0),
PORT_ISC_BOTHEDGES_gc = (0x00<<0),
PORT_ISC_RISING_gc = (0x01<<0),
PORT_ISC_FALLING_gc = (0x02<<0),
PORT_ISC_LEVEL_gc = (0x03<<0),
PORT_ISC_INPUT_DISABLE_gc = (0x07<<0),
PORT_ISC_BOTHEDGES_gc = (0x00<<0),
PORT_ISC_RISING_gc = (0x01<<0),
PORT_ISC_FALLING_gc = (0x02<<0),
PORT_ISC_LEVEL_gc = (0x03<<0),
PORT_ISC_INPUT_DISABLE_gc = (0x07<<0),
PORT_ISC_BOTHEDGES_gc = (0x00<<0),
PORT_ISC_RISING_gc = (0x01<<0),
PORT_ISC_FALLING_gc = (0x02<<0),
PORT_ISC_LEVEL_gc = (0x03<<0),
PORT_ISC_INPUT_DISABLE_gc = (0x07<<0),
PORT_ISC_BOTHEDGES_gc = (0x00<<0),
PORT_ISC_RISING_gc = (0x01<<0),
PORT_ISC_FALLING_gc = (0x02<<0),
PORT_ISC_LEVEL_gc = (0x03<<0),
PORT_ISC_INPUT_DISABLE_gc = (0x07<<0),
PORT_ISC_BOTHEDGES_gc = (0x00<<0),
PORT_ISC_RISING_gc = (0x01<<0),
PORT_ISC_FALLING_gc = (0x02<<0),
PORT_ISC_LEVEL_gc = (0x03<<0),
PORT_ISC_INPUT_DISABLE_gc = (0x07<<0),
PORT_ISC_BOTHEDGES_gc = (0x00<<0),
PORT_ISC_RISING_gc = (0x01<<0),
PORT_ISC_FALLING_gc = (0x02<<0),
PORT_ISC_LEVEL_gc = (0x03<<0),
PORT_ISC_INPUT_DISABLE_gc = (0x07<<0),
PORT_ISC_BOTHEDGES_gc = (0x00<<0),
PORT_ISC_RISING_gc = (0x01<<0),
PORT_ISC_FALLING_gc = (0x02<<0),
PORT_ISC_LEVEL_gc = (0x03<<0),
PORT_ISC_INPUT_DISABLE_gc = (0x07<<0),
PORT_ISC_BOTHEDGES_gc = (0x00<<0),
PORT_ISC_RISING_gc = (0x01<<0),
PORT_ISC_FALLING_gc = (0x02<<0),
PORT_ISC_LEVEL_gc = (0x03<<0),
PORT_ISC_INPUT_DISABLE_gc = (0x07<<0),
PORT_ISC_BOTHEDGES_gc = (0x00<<0),
PORT_ISC_RISING_gc = (0x01<<0),
PORT_ISC_FALLING_gc = (0x02<<0),
PORT_ISC_LEVEL_gc = (0x03<<0),
PORT_ISC_INPUT_DISABLE_gc = (0x07<<0),
PORT_ISC_BOTHEDGES_gc = (0x00<<0),
PORT_ISC_RISING_gc = (0x01<<0),
PORT_ISC_FALLING_gc = (0x02<<0),
PORT_ISC_LEVEL_gc = (0x03<<0),
PORT_ISC_INPUT_DISABLE_gc = (0x07<<0),
PORT_ISC_BOTHEDGES_gc = (0x00<<0),
PORT_ISC_RISING_gc = (0x01<<0),
PORT_ISC_FALLING_gc = (0x02<<0),
PORT_ISC_LEVEL_gc = (0x03<<0),
PORT_ISC_INPUT_DISABLE_gc = (0x07<<0),
PORT_ISC_BOTHEDGES_gc = (0x00<<0),
PORT_ISC_RISING_gc = (0x01<<0),
PORT_ISC_FALLING_gc = (0x02<<0),
PORT_ISC_LEVEL_gc = (0x03<<0),
PORT_ISC_INPUT_DISABLE_gc = (0x07<<0)
} |
|
enum | TC_CLKSEL_enum {
TC_CLKSEL_OFF_gc = (0x00<<0),
TC_CLKSEL_DIV1_gc = (0x01<<0),
TC_CLKSEL_DIV2_gc = (0x02<<0),
TC_CLKSEL_DIV4_gc = (0x03<<0),
TC_CLKSEL_DIV8_gc = (0x04<<0),
TC_CLKSEL_DIV64_gc = (0x05<<0),
TC_CLKSEL_DIV256_gc = (0x06<<0),
TC_CLKSEL_DIV1024_gc = (0x07<<0),
TC_CLKSEL_EVCH0_gc = (0x08<<0),
TC_CLKSEL_EVCH1_gc = (0x09<<0),
TC_CLKSEL_EVCH2_gc = (0x0A<<0),
TC_CLKSEL_EVCH3_gc = (0x0B<<0),
TC_CLKSEL_EVCH4_gc = (0x0C<<0),
TC_CLKSEL_EVCH5_gc = (0x0D<<0),
TC_CLKSEL_EVCH6_gc = (0x0E<<0),
TC_CLKSEL_EVCH7_gc = (0x0F<<0),
TC_CLKSEL_OFF_gc = (0x00<<0),
TC_CLKSEL_DIV1_gc = (0x01<<0),
TC_CLKSEL_DIV2_gc = (0x02<<0),
TC_CLKSEL_DIV4_gc = (0x03<<0),
TC_CLKSEL_DIV8_gc = (0x04<<0),
TC_CLKSEL_DIV64_gc = (0x05<<0),
TC_CLKSEL_DIV256_gc = (0x06<<0),
TC_CLKSEL_DIV1024_gc = (0x07<<0),
TC_CLKSEL_EVCH0_gc = (0x08<<0),
TC_CLKSEL_EVCH1_gc = (0x09<<0),
TC_CLKSEL_EVCH2_gc = (0x0A<<0),
TC_CLKSEL_EVCH3_gc = (0x0B<<0),
TC_CLKSEL_EVCH4_gc = (0x0C<<0),
TC_CLKSEL_EVCH5_gc = (0x0D<<0),
TC_CLKSEL_EVCH6_gc = (0x0E<<0),
TC_CLKSEL_EVCH7_gc = (0x0F<<0),
TC_CLKSEL_OFF_gc = (0x00<<0),
TC_CLKSEL_DIV1_gc = (0x01<<0),
TC_CLKSEL_DIV2_gc = (0x02<<0),
TC_CLKSEL_DIV4_gc = (0x03<<0),
TC_CLKSEL_DIV8_gc = (0x04<<0),
TC_CLKSEL_DIV64_gc = (0x05<<0),
TC_CLKSEL_DIV256_gc = (0x06<<0),
TC_CLKSEL_DIV1024_gc = (0x07<<0),
TC_CLKSEL_EVCH0_gc = (0x08<<0),
TC_CLKSEL_EVCH1_gc = (0x09<<0),
TC_CLKSEL_EVCH2_gc = (0x0A<<0),
TC_CLKSEL_EVCH3_gc = (0x0B<<0),
TC_CLKSEL_EVCH4_gc = (0x0C<<0),
TC_CLKSEL_EVCH5_gc = (0x0D<<0),
TC_CLKSEL_EVCH6_gc = (0x0E<<0),
TC_CLKSEL_EVCH7_gc = (0x0F<<0),
TC_CLKSEL_OFF_gc = (0x00<<0),
TC_CLKSEL_DIV1_gc = (0x01<<0),
TC_CLKSEL_DIV2_gc = (0x02<<0),
TC_CLKSEL_DIV4_gc = (0x03<<0),
TC_CLKSEL_DIV8_gc = (0x04<<0),
TC_CLKSEL_DIV64_gc = (0x05<<0),
TC_CLKSEL_DIV256_gc = (0x06<<0),
TC_CLKSEL_DIV1024_gc = (0x07<<0),
TC_CLKSEL_EVCH0_gc = (0x08<<0),
TC_CLKSEL_EVCH1_gc = (0x09<<0),
TC_CLKSEL_EVCH2_gc = (0x0A<<0),
TC_CLKSEL_EVCH3_gc = (0x0B<<0),
TC_CLKSEL_EVCH4_gc = (0x0C<<0),
TC_CLKSEL_EVCH5_gc = (0x0D<<0),
TC_CLKSEL_EVCH6_gc = (0x0E<<0),
TC_CLKSEL_EVCH7_gc = (0x0F<<0),
TC_CLKSEL_OFF_gc = (0x00<<0),
TC_CLKSEL_DIV1_gc = (0x01<<0),
TC_CLKSEL_DIV2_gc = (0x02<<0),
TC_CLKSEL_DIV4_gc = (0x03<<0),
TC_CLKSEL_DIV8_gc = (0x04<<0),
TC_CLKSEL_DIV64_gc = (0x05<<0),
TC_CLKSEL_DIV256_gc = (0x06<<0),
TC_CLKSEL_DIV1024_gc = (0x07<<0),
TC_CLKSEL_EVCH0_gc = (0x08<<0),
TC_CLKSEL_EVCH1_gc = (0x09<<0),
TC_CLKSEL_EVCH2_gc = (0x0A<<0),
TC_CLKSEL_EVCH3_gc = (0x0B<<0),
TC_CLKSEL_EVCH4_gc = (0x0C<<0),
TC_CLKSEL_EVCH5_gc = (0x0D<<0),
TC_CLKSEL_EVCH6_gc = (0x0E<<0),
TC_CLKSEL_EVCH7_gc = (0x0F<<0),
TC_CLKSEL_OFF_gc = (0x00<<0),
TC_CLKSEL_DIV1_gc = (0x01<<0),
TC_CLKSEL_DIV2_gc = (0x02<<0),
TC_CLKSEL_DIV4_gc = (0x03<<0),
TC_CLKSEL_DIV8_gc = (0x04<<0),
TC_CLKSEL_DIV64_gc = (0x05<<0),
TC_CLKSEL_DIV256_gc = (0x06<<0),
TC_CLKSEL_DIV1024_gc = (0x07<<0),
TC_CLKSEL_EVCH0_gc = (0x08<<0),
TC_CLKSEL_EVCH1_gc = (0x09<<0),
TC_CLKSEL_EVCH2_gc = (0x0A<<0),
TC_CLKSEL_EVCH3_gc = (0x0B<<0),
TC_CLKSEL_EVCH4_gc = (0x0C<<0),
TC_CLKSEL_EVCH5_gc = (0x0D<<0),
TC_CLKSEL_EVCH6_gc = (0x0E<<0),
TC_CLKSEL_EVCH7_gc = (0x0F<<0),
TC_CLKSEL_OFF_gc = (0x00<<0),
TC_CLKSEL_DIV1_gc = (0x01<<0),
TC_CLKSEL_DIV2_gc = (0x02<<0),
TC_CLKSEL_DIV4_gc = (0x03<<0),
TC_CLKSEL_DIV8_gc = (0x04<<0),
TC_CLKSEL_DIV64_gc = (0x05<<0),
TC_CLKSEL_DIV256_gc = (0x06<<0),
TC_CLKSEL_DIV1024_gc = (0x07<<0),
TC_CLKSEL_EVCH0_gc = (0x08<<0),
TC_CLKSEL_EVCH1_gc = (0x09<<0),
TC_CLKSEL_EVCH2_gc = (0x0A<<0),
TC_CLKSEL_EVCH3_gc = (0x0B<<0),
TC_CLKSEL_EVCH4_gc = (0x0C<<0),
TC_CLKSEL_EVCH5_gc = (0x0D<<0),
TC_CLKSEL_EVCH6_gc = (0x0E<<0),
TC_CLKSEL_EVCH7_gc = (0x0F<<0),
TC_CLKSEL_OFF_gc = (0x00<<0),
TC_CLKSEL_DIV1_gc = (0x01<<0),
TC_CLKSEL_DIV2_gc = (0x02<<0),
TC_CLKSEL_DIV4_gc = (0x03<<0),
TC_CLKSEL_DIV8_gc = (0x04<<0),
TC_CLKSEL_DIV64_gc = (0x05<<0),
TC_CLKSEL_DIV256_gc = (0x06<<0),
TC_CLKSEL_DIV1024_gc = (0x07<<0),
TC_CLKSEL_EVCH0_gc = (0x08<<0),
TC_CLKSEL_EVCH1_gc = (0x09<<0),
TC_CLKSEL_EVCH2_gc = (0x0A<<0),
TC_CLKSEL_EVCH3_gc = (0x0B<<0),
TC_CLKSEL_EVCH4_gc = (0x0C<<0),
TC_CLKSEL_EVCH5_gc = (0x0D<<0),
TC_CLKSEL_EVCH6_gc = (0x0E<<0),
TC_CLKSEL_EVCH7_gc = (0x0F<<0),
TC_CLKSEL_OFF_gc = (0x00<<0),
TC_CLKSEL_DIV1_gc = (0x01<<0),
TC_CLKSEL_DIV2_gc = (0x02<<0),
TC_CLKSEL_DIV4_gc = (0x03<<0),
TC_CLKSEL_DIV8_gc = (0x04<<0),
TC_CLKSEL_DIV64_gc = (0x05<<0),
TC_CLKSEL_DIV256_gc = (0x06<<0),
TC_CLKSEL_DIV1024_gc = (0x07<<0),
TC_CLKSEL_EVCH0_gc = (0x08<<0),
TC_CLKSEL_EVCH1_gc = (0x09<<0),
TC_CLKSEL_EVCH2_gc = (0x0A<<0),
TC_CLKSEL_EVCH3_gc = (0x0B<<0),
TC_CLKSEL_EVCH4_gc = (0x0C<<0),
TC_CLKSEL_EVCH5_gc = (0x0D<<0),
TC_CLKSEL_EVCH6_gc = (0x0E<<0),
TC_CLKSEL_EVCH7_gc = (0x0F<<0),
TC_CLKSEL_OFF_gc = (0x00<<0),
TC_CLKSEL_DIV1_gc = (0x01<<0),
TC_CLKSEL_DIV2_gc = (0x02<<0),
TC_CLKSEL_DIV4_gc = (0x03<<0),
TC_CLKSEL_DIV8_gc = (0x04<<0),
TC_CLKSEL_DIV64_gc = (0x05<<0),
TC_CLKSEL_DIV256_gc = (0x06<<0),
TC_CLKSEL_DIV1024_gc = (0x07<<0),
TC_CLKSEL_EVCH0_gc = (0x08<<0),
TC_CLKSEL_EVCH1_gc = (0x09<<0),
TC_CLKSEL_EVCH2_gc = (0x0A<<0),
TC_CLKSEL_EVCH3_gc = (0x0B<<0),
TC_CLKSEL_EVCH4_gc = (0x0C<<0),
TC_CLKSEL_EVCH5_gc = (0x0D<<0),
TC_CLKSEL_EVCH6_gc = (0x0E<<0),
TC_CLKSEL_EVCH7_gc = (0x0F<<0),
TC_CLKSEL_OFF_gc = (0x00<<0),
TC_CLKSEL_DIV1_gc = (0x01<<0),
TC_CLKSEL_DIV2_gc = (0x02<<0),
TC_CLKSEL_DIV4_gc = (0x03<<0),
TC_CLKSEL_DIV8_gc = (0x04<<0),
TC_CLKSEL_DIV64_gc = (0x05<<0),
TC_CLKSEL_DIV256_gc = (0x06<<0),
TC_CLKSEL_DIV1024_gc = (0x07<<0),
TC_CLKSEL_EVCH0_gc = (0x08<<0),
TC_CLKSEL_EVCH1_gc = (0x09<<0),
TC_CLKSEL_EVCH2_gc = (0x0A<<0),
TC_CLKSEL_EVCH3_gc = (0x0B<<0),
TC_CLKSEL_EVCH4_gc = (0x0C<<0),
TC_CLKSEL_EVCH5_gc = (0x0D<<0),
TC_CLKSEL_EVCH6_gc = (0x0E<<0),
TC_CLKSEL_EVCH7_gc = (0x0F<<0),
TC_CLKSEL_OFF_gc = (0x00<<0),
TC_CLKSEL_DIV1_gc = (0x01<<0),
TC_CLKSEL_DIV2_gc = (0x02<<0),
TC_CLKSEL_DIV4_gc = (0x03<<0),
TC_CLKSEL_DIV8_gc = (0x04<<0),
TC_CLKSEL_DIV64_gc = (0x05<<0),
TC_CLKSEL_DIV256_gc = (0x06<<0),
TC_CLKSEL_DIV1024_gc = (0x07<<0),
TC_CLKSEL_EVCH0_gc = (0x08<<0),
TC_CLKSEL_EVCH1_gc = (0x09<<0),
TC_CLKSEL_EVCH2_gc = (0x0A<<0),
TC_CLKSEL_EVCH3_gc = (0x0B<<0),
TC_CLKSEL_EVCH4_gc = (0x0C<<0),
TC_CLKSEL_EVCH5_gc = (0x0D<<0),
TC_CLKSEL_EVCH6_gc = (0x0E<<0),
TC_CLKSEL_EVCH7_gc = (0x0F<<0),
TC_CLKSEL_OFF_gc = (0x00<<0),
TC_CLKSEL_DIV1_gc = (0x01<<0),
TC_CLKSEL_DIV2_gc = (0x02<<0),
TC_CLKSEL_DIV4_gc = (0x03<<0),
TC_CLKSEL_DIV8_gc = (0x04<<0),
TC_CLKSEL_DIV64_gc = (0x05<<0),
TC_CLKSEL_DIV256_gc = (0x06<<0),
TC_CLKSEL_DIV1024_gc = (0x07<<0),
TC_CLKSEL_EVCH0_gc = (0x08<<0),
TC_CLKSEL_EVCH1_gc = (0x09<<0),
TC_CLKSEL_EVCH2_gc = (0x0A<<0),
TC_CLKSEL_EVCH3_gc = (0x0B<<0),
TC_CLKSEL_EVCH4_gc = (0x0C<<0),
TC_CLKSEL_EVCH5_gc = (0x0D<<0),
TC_CLKSEL_EVCH6_gc = (0x0E<<0),
TC_CLKSEL_EVCH7_gc = (0x0F<<0),
TC_CLKSEL_OFF_gc = (0x00<<0),
TC_CLKSEL_DIV1_gc = (0x01<<0),
TC_CLKSEL_DIV2_gc = (0x02<<0),
TC_CLKSEL_DIV4_gc = (0x03<<0),
TC_CLKSEL_DIV8_gc = (0x04<<0),
TC_CLKSEL_DIV64_gc = (0x05<<0),
TC_CLKSEL_DIV256_gc = (0x06<<0),
TC_CLKSEL_DIV1024_gc = (0x07<<0),
TC_CLKSEL_EVCH0_gc = (0x08<<0),
TC_CLKSEL_EVCH1_gc = (0x09<<0),
TC_CLKSEL_EVCH2_gc = (0x0A<<0),
TC_CLKSEL_EVCH3_gc = (0x0B<<0),
TC_CLKSEL_EVCH4_gc = (0x0C<<0),
TC_CLKSEL_EVCH5_gc = (0x0D<<0),
TC_CLKSEL_EVCH6_gc = (0x0E<<0),
TC_CLKSEL_EVCH7_gc = (0x0F<<0),
TC_CLKSEL_OFF_gc = (0x00<<0),
TC_CLKSEL_DIV1_gc = (0x01<<0),
TC_CLKSEL_DIV2_gc = (0x02<<0),
TC_CLKSEL_DIV4_gc = (0x03<<0),
TC_CLKSEL_DIV8_gc = (0x04<<0),
TC_CLKSEL_DIV64_gc = (0x05<<0),
TC_CLKSEL_DIV256_gc = (0x06<<0),
TC_CLKSEL_DIV1024_gc = (0x07<<0),
TC_CLKSEL_EVCH0_gc = (0x08<<0),
TC_CLKSEL_EVCH1_gc = (0x09<<0),
TC_CLKSEL_EVCH2_gc = (0x0A<<0),
TC_CLKSEL_EVCH3_gc = (0x0B<<0),
TC_CLKSEL_EVCH4_gc = (0x0C<<0),
TC_CLKSEL_EVCH5_gc = (0x0D<<0),
TC_CLKSEL_EVCH6_gc = (0x0E<<0),
TC_CLKSEL_EVCH7_gc = (0x0F<<0)
} |
|
enum | TC_WGMODE_enum {
TC_WGMODE_NORMAL_gc = (0x00<<0),
TC_WGMODE_FRQ_gc = (0x01<<0),
TC_WGMODE_SS_gc = (0x03<<0),
TC_WGMODE_DS_T_gc = (0x05<<0),
TC_WGMODE_DS_TB_gc = (0x06<<0),
TC_WGMODE_DS_B_gc = (0x07<<0),
TC_WGMODE_NORMAL_gc = (0x00<<0),
TC_WGMODE_FRQ_gc = (0x01<<0),
TC_WGMODE_SS_gc = (0x03<<0),
TC_WGMODE_DS_T_gc = (0x05<<0),
TC_WGMODE_DS_TB_gc = (0x06<<0),
TC_WGMODE_DS_B_gc = (0x07<<0),
TC_WGMODE_NORMAL_gc = (0x00<<0),
TC_WGMODE_FRQ_gc = (0x01<<0),
TC_WGMODE_SS_gc = (0x03<<0),
TC_WGMODE_DS_T_gc = (0x05<<0),
TC_WGMODE_DS_TB_gc = (0x06<<0),
TC_WGMODE_DS_B_gc = (0x07<<0),
TC_WGMODE_NORMAL_gc = (0x00<<0),
TC_WGMODE_FRQ_gc = (0x01<<0),
TC_WGMODE_SS_gc = (0x03<<0),
TC_WGMODE_DS_T_gc = (0x05<<0),
TC_WGMODE_DS_TB_gc = (0x06<<0),
TC_WGMODE_DS_B_gc = (0x07<<0),
TC_WGMODE_NORMAL_gc = (0x00<<0),
TC_WGMODE_FRQ_gc = (0x01<<0),
TC_WGMODE_SS_gc = (0x03<<0),
TC_WGMODE_DS_T_gc = (0x05<<0),
TC_WGMODE_DS_TB_gc = (0x06<<0),
TC_WGMODE_DS_B_gc = (0x07<<0),
TC_WGMODE_NORMAL_gc = (0x00<<0),
TC_WGMODE_FRQ_gc = (0x01<<0),
TC_WGMODE_SS_gc = (0x03<<0),
TC_WGMODE_DS_T_gc = (0x05<<0),
TC_WGMODE_DS_TB_gc = (0x06<<0),
TC_WGMODE_DS_B_gc = (0x07<<0),
TC_WGMODE_NORMAL_gc = (0x00<<0),
TC_WGMODE_FRQ_gc = (0x01<<0),
TC_WGMODE_SS_gc = (0x03<<0),
TC_WGMODE_DS_T_gc = (0x05<<0),
TC_WGMODE_DS_TB_gc = (0x06<<0),
TC_WGMODE_DS_B_gc = (0x07<<0),
TC_WGMODE_NORMAL_gc = (0x00<<0),
TC_WGMODE_FRQ_gc = (0x01<<0),
TC_WGMODE_SS_gc = (0x03<<0),
TC_WGMODE_DS_T_gc = (0x05<<0),
TC_WGMODE_DS_TB_gc = (0x06<<0),
TC_WGMODE_DS_B_gc = (0x07<<0),
TC_WGMODE_NORMAL_gc = (0x00<<0),
TC_WGMODE_FRQ_gc = (0x01<<0),
TC_WGMODE_SS_gc = (0x03<<0),
TC_WGMODE_DS_T_gc = (0x05<<0),
TC_WGMODE_DS_TB_gc = (0x06<<0),
TC_WGMODE_DS_B_gc = (0x07<<0),
TC_WGMODE_NORMAL_gc = (0x00<<0),
TC_WGMODE_FRQ_gc = (0x01<<0),
TC_WGMODE_SS_gc = (0x03<<0),
TC_WGMODE_DS_T_gc = (0x05<<0),
TC_WGMODE_DS_TB_gc = (0x06<<0),
TC_WGMODE_DS_B_gc = (0x07<<0),
TC_WGMODE_NORMAL_gc = (0x00<<0),
TC_WGMODE_FRQ_gc = (0x01<<0),
TC_WGMODE_SS_gc = (0x03<<0),
TC_WGMODE_DS_T_gc = (0x05<<0),
TC_WGMODE_DS_TB_gc = (0x06<<0),
TC_WGMODE_DS_B_gc = (0x07<<0),
TC_WGMODE_NORMAL_gc = (0x00<<0),
TC_WGMODE_FRQ_gc = (0x01<<0),
TC_WGMODE_SS_gc = (0x03<<0),
TC_WGMODE_DS_T_gc = (0x05<<0),
TC_WGMODE_DS_TB_gc = (0x06<<0),
TC_WGMODE_DS_B_gc = (0x07<<0),
TC_WGMODE_NORMAL_gc = (0x00<<0),
TC_WGMODE_FRQ_gc = (0x01<<0),
TC_WGMODE_SS_gc = (0x03<<0),
TC_WGMODE_DS_T_gc = (0x05<<0),
TC_WGMODE_DS_TB_gc = (0x06<<0),
TC_WGMODE_DS_B_gc = (0x07<<0),
TC_WGMODE_NORMAL_gc = (0x00<<0),
TC_WGMODE_FRQ_gc = (0x01<<0),
TC_WGMODE_SS_gc = (0x03<<0),
TC_WGMODE_DS_T_gc = (0x05<<0),
TC_WGMODE_DS_TB_gc = (0x06<<0),
TC_WGMODE_DS_B_gc = (0x07<<0),
TC_WGMODE_NORMAL_gc = (0x00<<0),
TC_WGMODE_FRQ_gc = (0x01<<0),
TC_WGMODE_SS_gc = (0x03<<0),
TC_WGMODE_DS_T_gc = (0x05<<0),
TC_WGMODE_DS_TB_gc = (0x06<<0),
TC_WGMODE_DS_B_gc = (0x07<<0)
} |
|
enum | TC_EVACT_enum {
TC_EVACT_OFF_gc = (0x00<<5),
TC_EVACT_CAPT_gc = (0x01<<5),
TC_EVACT_UPDOWN_gc = (0x02<<5),
TC_EVACT_QDEC_gc = (0x03<<5),
TC_EVACT_RESTART_gc = (0x04<<5),
TC_EVACT_FRW_gc = (0x05<<5),
TC_EVACT_PW_gc = (0x06<<5),
TC_EVACT_OFF_gc = (0x00<<5),
TC_EVACT_CAPT_gc = (0x01<<5),
TC_EVACT_UPDOWN_gc = (0x02<<5),
TC_EVACT_QDEC_gc = (0x03<<5),
TC_EVACT_RESTART_gc = (0x04<<5),
TC_EVACT_FRW_gc = (0x05<<5),
TC_EVACT_PW_gc = (0x06<<5),
TC_EVACT_OFF_gc = (0x00<<5),
TC_EVACT_CAPT_gc = (0x01<<5),
TC_EVACT_UPDOWN_gc = (0x02<<5),
TC_EVACT_QDEC_gc = (0x03<<5),
TC_EVACT_RESTART_gc = (0x04<<5),
TC_EVACT_FRQ_gc = (0x05<<5),
TC_EVACT_PW_gc = (0x06<<5),
TC_EVACT_OFF_gc = (0x00<<5),
TC_EVACT_CAPT_gc = (0x01<<5),
TC_EVACT_UPDOWN_gc = (0x02<<5),
TC_EVACT_QDEC_gc = (0x03<<5),
TC_EVACT_RESTART_gc = (0x04<<5),
TC_EVACT_FRW_gc = (0x05<<5),
TC_EVACT_PW_gc = (0x06<<5),
TC_EVACT_OFF_gc = (0x00<<5),
TC_EVACT_CAPT_gc = (0x01<<5),
TC_EVACT_UPDOWN_gc = (0x02<<5),
TC_EVACT_QDEC_gc = (0x03<<5),
TC_EVACT_RESTART_gc = (0x04<<5),
TC_EVACT_FRW_gc = (0x05<<5),
TC_EVACT_PW_gc = (0x06<<5),
TC_EVACT_OFF_gc = (0x00<<5),
TC_EVACT_CAPT_gc = (0x01<<5),
TC_EVACT_UPDOWN_gc = (0x02<<5),
TC_EVACT_QDEC_gc = (0x03<<5),
TC_EVACT_RESTART_gc = (0x04<<5),
TC_EVACT_FRW_gc = (0x05<<5),
TC_EVACT_PW_gc = (0x06<<5),
TC_EVACT_OFF_gc = (0x00<<5),
TC_EVACT_CAPT_gc = (0x01<<5),
TC_EVACT_UPDOWN_gc = (0x02<<5),
TC_EVACT_QDEC_gc = (0x03<<5),
TC_EVACT_RESTART_gc = (0x04<<5),
TC_EVACT_FRQ_gc = (0x05<<5),
TC_EVACT_PW_gc = (0x06<<5),
TC_EVACT_OFF_gc = (0x00<<5),
TC_EVACT_CAPT_gc = (0x01<<5),
TC_EVACT_UPDOWN_gc = (0x02<<5),
TC_EVACT_QDEC_gc = (0x03<<5),
TC_EVACT_RESTART_gc = (0x04<<5),
TC_EVACT_FRW_gc = (0x05<<5),
TC_EVACT_PW_gc = (0x06<<5),
TC_EVACT_OFF_gc = (0x00<<5),
TC_EVACT_CAPT_gc = (0x01<<5),
TC_EVACT_UPDOWN_gc = (0x02<<5),
TC_EVACT_QDEC_gc = (0x03<<5),
TC_EVACT_RESTART_gc = (0x04<<5),
TC_EVACT_FRW_gc = (0x05<<5),
TC_EVACT_PW_gc = (0x06<<5),
TC_EVACT_OFF_gc = (0x00<<5),
TC_EVACT_CAPT_gc = (0x01<<5),
TC_EVACT_UPDOWN_gc = (0x02<<5),
TC_EVACT_QDEC_gc = (0x03<<5),
TC_EVACT_RESTART_gc = (0x04<<5),
TC_EVACT_FRQ_gc = (0x05<<5),
TC_EVACT_PW_gc = (0x06<<5),
TC_EVACT_OFF_gc = (0x00<<5),
TC_EVACT_CAPT_gc = (0x01<<5),
TC_EVACT_UPDOWN_gc = (0x02<<5),
TC_EVACT_QDEC_gc = (0x03<<5),
TC_EVACT_RESTART_gc = (0x04<<5),
TC_EVACT_FRW_gc = (0x05<<5),
TC_EVACT_PW_gc = (0x06<<5),
TC_EVACT_OFF_gc = (0x00<<5),
TC_EVACT_CAPT_gc = (0x01<<5),
TC_EVACT_UPDOWN_gc = (0x02<<5),
TC_EVACT_QDEC_gc = (0x03<<5),
TC_EVACT_RESTART_gc = (0x04<<5),
TC_EVACT_FRW_gc = (0x05<<5),
TC_EVACT_PW_gc = (0x06<<5),
TC_EVACT_OFF_gc = (0x00<<5),
TC_EVACT_CAPT_gc = (0x01<<5),
TC_EVACT_UPDOWN_gc = (0x02<<5),
TC_EVACT_QDEC_gc = (0x03<<5),
TC_EVACT_RESTART_gc = (0x04<<5),
TC_EVACT_FRW_gc = (0x05<<5),
TC_EVACT_PW_gc = (0x06<<5),
TC_EVACT_OFF_gc = (0x00<<5),
TC_EVACT_CAPT_gc = (0x01<<5),
TC_EVACT_UPDOWN_gc = (0x02<<5),
TC_EVACT_QDEC_gc = (0x03<<5),
TC_EVACT_RESTART_gc = (0x04<<5),
TC_EVACT_FRW_gc = (0x05<<5),
TC_EVACT_PW_gc = (0x06<<5),
TC_EVACT_OFF_gc = (0x00<<5),
TC_EVACT_CAPT_gc = (0x01<<5),
TC_EVACT_UPDOWN_gc = (0x02<<5),
TC_EVACT_QDEC_gc = (0x03<<5),
TC_EVACT_RESTART_gc = (0x04<<5),
TC_EVACT_FRQ_gc = (0x05<<5),
TC_EVACT_PW_gc = (0x06<<5)
} |
|
enum | TC_EVSEL_enum {
TC_EVSEL_OFF_gc = (0x00<<0),
TC_EVSEL_CH0_gc = (0x08<<0),
TC_EVSEL_CH1_gc = (0x09<<0),
TC_EVSEL_CH2_gc = (0x0A<<0),
TC_EVSEL_CH3_gc = (0x0B<<0),
TC_EVSEL_CH4_gc = (0x0C<<0),
TC_EVSEL_CH5_gc = (0x0D<<0),
TC_EVSEL_CH6_gc = (0x0E<<0),
TC_EVSEL_CH7_gc = (0x0F<<0),
TC_EVSEL_OFF_gc = (0x00<<0),
TC_EVSEL_CH0_gc = (0x08<<0),
TC_EVSEL_CH1_gc = (0x09<<0),
TC_EVSEL_CH2_gc = (0x0A<<0),
TC_EVSEL_CH3_gc = (0x0B<<0),
TC_EVSEL_CH4_gc = (0x0C<<0),
TC_EVSEL_CH5_gc = (0x0D<<0),
TC_EVSEL_CH6_gc = (0x0E<<0),
TC_EVSEL_CH7_gc = (0x0F<<0),
TC_EVSEL_OFF_gc = (0x00<<0),
TC_EVSEL_CH0_gc = (0x08<<0),
TC_EVSEL_CH1_gc = (0x09<<0),
TC_EVSEL_CH2_gc = (0x0A<<0),
TC_EVSEL_CH3_gc = (0x0B<<0),
TC_EVSEL_CH4_gc = (0x0C<<0),
TC_EVSEL_CH5_gc = (0x0D<<0),
TC_EVSEL_CH6_gc = (0x0E<<0),
TC_EVSEL_CH7_gc = (0x0F<<0),
TC_EVSEL_OFF_gc = (0x00<<0),
TC_EVSEL_CH0_gc = (0x08<<0),
TC_EVSEL_CH1_gc = (0x09<<0),
TC_EVSEL_CH2_gc = (0x0A<<0),
TC_EVSEL_CH3_gc = (0x0B<<0),
TC_EVSEL_CH4_gc = (0x0C<<0),
TC_EVSEL_CH5_gc = (0x0D<<0),
TC_EVSEL_CH6_gc = (0x0E<<0),
TC_EVSEL_CH7_gc = (0x0F<<0),
TC_EVSEL_OFF_gc = (0x00<<0),
TC_EVSEL_CH0_gc = (0x08<<0),
TC_EVSEL_CH1_gc = (0x09<<0),
TC_EVSEL_CH2_gc = (0x0A<<0),
TC_EVSEL_CH3_gc = (0x0B<<0),
TC_EVSEL_CH4_gc = (0x0C<<0),
TC_EVSEL_CH5_gc = (0x0D<<0),
TC_EVSEL_CH6_gc = (0x0E<<0),
TC_EVSEL_CH7_gc = (0x0F<<0),
TC_EVSEL_OFF_gc = (0x00<<0),
TC_EVSEL_CH0_gc = (0x08<<0),
TC_EVSEL_CH1_gc = (0x09<<0),
TC_EVSEL_CH2_gc = (0x0A<<0),
TC_EVSEL_CH3_gc = (0x0B<<0),
TC_EVSEL_CH4_gc = (0x0C<<0),
TC_EVSEL_CH5_gc = (0x0D<<0),
TC_EVSEL_CH6_gc = (0x0E<<0),
TC_EVSEL_CH7_gc = (0x0F<<0),
TC_EVSEL_OFF_gc = (0x00<<0),
TC_EVSEL_CH0_gc = (0x08<<0),
TC_EVSEL_CH1_gc = (0x09<<0),
TC_EVSEL_CH2_gc = (0x0A<<0),
TC_EVSEL_CH3_gc = (0x0B<<0),
TC_EVSEL_CH4_gc = (0x0C<<0),
TC_EVSEL_CH5_gc = (0x0D<<0),
TC_EVSEL_CH6_gc = (0x0E<<0),
TC_EVSEL_CH7_gc = (0x0F<<0),
TC_EVSEL_OFF_gc = (0x00<<0),
TC_EVSEL_CH0_gc = (0x08<<0),
TC_EVSEL_CH1_gc = (0x09<<0),
TC_EVSEL_CH2_gc = (0x0A<<0),
TC_EVSEL_CH3_gc = (0x0B<<0),
TC_EVSEL_CH4_gc = (0x0C<<0),
TC_EVSEL_CH5_gc = (0x0D<<0),
TC_EVSEL_CH6_gc = (0x0E<<0),
TC_EVSEL_CH7_gc = (0x0F<<0),
TC_EVSEL_OFF_gc = (0x00<<0),
TC_EVSEL_CH0_gc = (0x08<<0),
TC_EVSEL_CH1_gc = (0x09<<0),
TC_EVSEL_CH2_gc = (0x0A<<0),
TC_EVSEL_CH3_gc = (0x0B<<0),
TC_EVSEL_CH4_gc = (0x0C<<0),
TC_EVSEL_CH5_gc = (0x0D<<0),
TC_EVSEL_CH6_gc = (0x0E<<0),
TC_EVSEL_CH7_gc = (0x0F<<0),
TC_EVSEL_OFF_gc = (0x00<<0),
TC_EVSEL_CH0_gc = (0x08<<0),
TC_EVSEL_CH1_gc = (0x09<<0),
TC_EVSEL_CH2_gc = (0x0A<<0),
TC_EVSEL_CH3_gc = (0x0B<<0),
TC_EVSEL_CH4_gc = (0x0C<<0),
TC_EVSEL_CH5_gc = (0x0D<<0),
TC_EVSEL_CH6_gc = (0x0E<<0),
TC_EVSEL_CH7_gc = (0x0F<<0),
TC_EVSEL_OFF_gc = (0x00<<0),
TC_EVSEL_CH0_gc = (0x08<<0),
TC_EVSEL_CH1_gc = (0x09<<0),
TC_EVSEL_CH2_gc = (0x0A<<0),
TC_EVSEL_CH3_gc = (0x0B<<0),
TC_EVSEL_CH4_gc = (0x0C<<0),
TC_EVSEL_CH5_gc = (0x0D<<0),
TC_EVSEL_CH6_gc = (0x0E<<0),
TC_EVSEL_CH7_gc = (0x0F<<0),
TC_EVSEL_OFF_gc = (0x00<<0),
TC_EVSEL_CH0_gc = (0x08<<0),
TC_EVSEL_CH1_gc = (0x09<<0),
TC_EVSEL_CH2_gc = (0x0A<<0),
TC_EVSEL_CH3_gc = (0x0B<<0),
TC_EVSEL_CH4_gc = (0x0C<<0),
TC_EVSEL_CH5_gc = (0x0D<<0),
TC_EVSEL_CH6_gc = (0x0E<<0),
TC_EVSEL_CH7_gc = (0x0F<<0),
TC_EVSEL_OFF_gc = (0x00<<0),
TC_EVSEL_CH0_gc = (0x08<<0),
TC_EVSEL_CH1_gc = (0x09<<0),
TC_EVSEL_CH2_gc = (0x0A<<0),
TC_EVSEL_CH3_gc = (0x0B<<0),
TC_EVSEL_CH4_gc = (0x0C<<0),
TC_EVSEL_CH5_gc = (0x0D<<0),
TC_EVSEL_CH6_gc = (0x0E<<0),
TC_EVSEL_CH7_gc = (0x0F<<0),
TC_EVSEL_OFF_gc = (0x00<<0),
TC_EVSEL_CH0_gc = (0x08<<0),
TC_EVSEL_CH1_gc = (0x09<<0),
TC_EVSEL_CH2_gc = (0x0A<<0),
TC_EVSEL_CH3_gc = (0x0B<<0),
TC_EVSEL_CH4_gc = (0x0C<<0),
TC_EVSEL_CH5_gc = (0x0D<<0),
TC_EVSEL_CH6_gc = (0x0E<<0),
TC_EVSEL_CH7_gc = (0x0F<<0),
TC_EVSEL_OFF_gc = (0x00<<0),
TC_EVSEL_CH0_gc = (0x08<<0),
TC_EVSEL_CH1_gc = (0x09<<0),
TC_EVSEL_CH2_gc = (0x0A<<0),
TC_EVSEL_CH3_gc = (0x0B<<0),
TC_EVSEL_CH4_gc = (0x0C<<0),
TC_EVSEL_CH5_gc = (0x0D<<0),
TC_EVSEL_CH6_gc = (0x0E<<0),
TC_EVSEL_CH7_gc = (0x0F<<0)
} |
|
enum | TC_ERRINTLVL_enum {
TC_ERRINTLVL_OFF_gc = (0x00<<2),
TC_ERRINTLVL_LO_gc = (0x01<<2),
TC_ERRINTLVL_MED_gc = (0x02<<2),
TC_ERRINTLVL_HI_gc = (0x03<<2),
TC_ERRINTLVL_OFF_gc = (0x00<<2),
TC_ERRINTLVL_LO_gc = (0x01<<2),
TC_ERRINTLVL_MED_gc = (0x02<<2),
TC_ERRINTLVL_HI_gc = (0x03<<2),
TC_ERRINTLVL_OFF_gc = (0x00<<2),
TC_ERRINTLVL_LO_gc = (0x01<<2),
TC_ERRINTLVL_MED_gc = (0x02<<2),
TC_ERRINTLVL_HI_gc = (0x03<<2),
TC_ERRINTLVL_OFF_gc = (0x00<<2),
TC_ERRINTLVL_LO_gc = (0x01<<2),
TC_ERRINTLVL_MED_gc = (0x02<<2),
TC_ERRINTLVL_HI_gc = (0x03<<2),
TC_ERRINTLVL_OFF_gc = (0x00<<2),
TC_ERRINTLVL_LO_gc = (0x01<<2),
TC_ERRINTLVL_MED_gc = (0x02<<2),
TC_ERRINTLVL_HI_gc = (0x03<<2),
TC_ERRINTLVL_OFF_gc = (0x00<<2),
TC_ERRINTLVL_LO_gc = (0x01<<2),
TC_ERRINTLVL_MED_gc = (0x02<<2),
TC_ERRINTLVL_HI_gc = (0x03<<2),
TC_ERRINTLVL_OFF_gc = (0x00<<2),
TC_ERRINTLVL_LO_gc = (0x01<<2),
TC_ERRINTLVL_MED_gc = (0x02<<2),
TC_ERRINTLVL_HI_gc = (0x03<<2),
TC_ERRINTLVL_OFF_gc = (0x00<<2),
TC_ERRINTLVL_LO_gc = (0x01<<2),
TC_ERRINTLVL_MED_gc = (0x02<<2),
TC_ERRINTLVL_HI_gc = (0x03<<2),
TC_ERRINTLVL_OFF_gc = (0x00<<2),
TC_ERRINTLVL_LO_gc = (0x01<<2),
TC_ERRINTLVL_MED_gc = (0x02<<2),
TC_ERRINTLVL_HI_gc = (0x03<<2),
TC_ERRINTLVL_OFF_gc = (0x00<<2),
TC_ERRINTLVL_LO_gc = (0x01<<2),
TC_ERRINTLVL_MED_gc = (0x02<<2),
TC_ERRINTLVL_HI_gc = (0x03<<2),
TC_ERRINTLVL_OFF_gc = (0x00<<2),
TC_ERRINTLVL_LO_gc = (0x01<<2),
TC_ERRINTLVL_MED_gc = (0x02<<2),
TC_ERRINTLVL_HI_gc = (0x03<<2),
TC_ERRINTLVL_OFF_gc = (0x00<<2),
TC_ERRINTLVL_LO_gc = (0x01<<2),
TC_ERRINTLVL_MED_gc = (0x02<<2),
TC_ERRINTLVL_HI_gc = (0x03<<2),
TC_ERRINTLVL_OFF_gc = (0x00<<2),
TC_ERRINTLVL_LO_gc = (0x01<<2),
TC_ERRINTLVL_MED_gc = (0x02<<2),
TC_ERRINTLVL_HI_gc = (0x03<<2),
TC_ERRINTLVL_OFF_gc = (0x00<<2),
TC_ERRINTLVL_LO_gc = (0x01<<2),
TC_ERRINTLVL_MED_gc = (0x02<<2),
TC_ERRINTLVL_HI_gc = (0x03<<2),
TC_ERRINTLVL_OFF_gc = (0x00<<2),
TC_ERRINTLVL_LO_gc = (0x01<<2),
TC_ERRINTLVL_MED_gc = (0x02<<2),
TC_ERRINTLVL_HI_gc = (0x03<<2)
} |
|
enum | TC_OVFINTLVL_enum {
TC_OVFINTLVL_OFF_gc = (0x00<<0),
TC_OVFINTLVL_LO_gc = (0x01<<0),
TC_OVFINTLVL_MED_gc = (0x02<<0),
TC_OVFINTLVL_HI_gc = (0x03<<0),
TC_OVFINTLVL_OFF_gc = (0x00<<0),
TC_OVFINTLVL_LO_gc = (0x01<<0),
TC_OVFINTLVL_MED_gc = (0x02<<0),
TC_OVFINTLVL_HI_gc = (0x03<<0),
TC_OVFINTLVL_OFF_gc = (0x00<<0),
TC_OVFINTLVL_LO_gc = (0x01<<0),
TC_OVFINTLVL_MED_gc = (0x02<<0),
TC_OVFINTLVL_HI_gc = (0x03<<0),
TC_OVFINTLVL_OFF_gc = (0x00<<0),
TC_OVFINTLVL_LO_gc = (0x01<<0),
TC_OVFINTLVL_MED_gc = (0x02<<0),
TC_OVFINTLVL_HI_gc = (0x03<<0),
TC_OVFINTLVL_OFF_gc = (0x00<<0),
TC_OVFINTLVL_LO_gc = (0x01<<0),
TC_OVFINTLVL_MED_gc = (0x02<<0),
TC_OVFINTLVL_HI_gc = (0x03<<0),
TC_OVFINTLVL_OFF_gc = (0x00<<0),
TC_OVFINTLVL_LO_gc = (0x01<<0),
TC_OVFINTLVL_MED_gc = (0x02<<0),
TC_OVFINTLVL_HI_gc = (0x03<<0),
TC_OVFINTLVL_OFF_gc = (0x00<<0),
TC_OVFINTLVL_LO_gc = (0x01<<0),
TC_OVFINTLVL_MED_gc = (0x02<<0),
TC_OVFINTLVL_HI_gc = (0x03<<0),
TC_OVFINTLVL_OFF_gc = (0x00<<0),
TC_OVFINTLVL_LO_gc = (0x01<<0),
TC_OVFINTLVL_MED_gc = (0x02<<0),
TC_OVFINTLVL_HI_gc = (0x03<<0),
TC_OVFINTLVL_OFF_gc = (0x00<<0),
TC_OVFINTLVL_LO_gc = (0x01<<0),
TC_OVFINTLVL_MED_gc = (0x02<<0),
TC_OVFINTLVL_HI_gc = (0x03<<0),
TC_OVFINTLVL_OFF_gc = (0x00<<0),
TC_OVFINTLVL_LO_gc = (0x01<<0),
TC_OVFINTLVL_MED_gc = (0x02<<0),
TC_OVFINTLVL_HI_gc = (0x03<<0),
TC_OVFINTLVL_OFF_gc = (0x00<<0),
TC_OVFINTLVL_LO_gc = (0x01<<0),
TC_OVFINTLVL_MED_gc = (0x02<<0),
TC_OVFINTLVL_HI_gc = (0x03<<0),
TC_OVFINTLVL_OFF_gc = (0x00<<0),
TC_OVFINTLVL_LO_gc = (0x01<<0),
TC_OVFINTLVL_MED_gc = (0x02<<0),
TC_OVFINTLVL_HI_gc = (0x03<<0),
TC_OVFINTLVL_OFF_gc = (0x00<<0),
TC_OVFINTLVL_LO_gc = (0x01<<0),
TC_OVFINTLVL_MED_gc = (0x02<<0),
TC_OVFINTLVL_HI_gc = (0x03<<0),
TC_OVFINTLVL_OFF_gc = (0x00<<0),
TC_OVFINTLVL_LO_gc = (0x01<<0),
TC_OVFINTLVL_MED_gc = (0x02<<0),
TC_OVFINTLVL_HI_gc = (0x03<<0),
TC_OVFINTLVL_OFF_gc = (0x00<<0),
TC_OVFINTLVL_LO_gc = (0x01<<0),
TC_OVFINTLVL_MED_gc = (0x02<<0),
TC_OVFINTLVL_HI_gc = (0x03<<0)
} |
|
enum | TC_CCDINTLVL_enum {
TC_CCDINTLVL_OFF_gc = (0x00<<6),
TC_CCDINTLVL_LO_gc = (0x01<<6),
TC_CCDINTLVL_MED_gc = (0x02<<6),
TC_CCDINTLVL_HI_gc = (0x03<<6),
TC_CCDINTLVL_OFF_gc = (0x00<<6),
TC_CCDINTLVL_LO_gc = (0x01<<6),
TC_CCDINTLVL_MED_gc = (0x02<<6),
TC_CCDINTLVL_HI_gc = (0x03<<6),
TC_CCDINTLVL_OFF_gc = (0x00<<6),
TC_CCDINTLVL_LO_gc = (0x01<<6),
TC_CCDINTLVL_MED_gc = (0x02<<6),
TC_CCDINTLVL_HI_gc = (0x03<<6),
TC_CCDINTLVL_OFF_gc = (0x00<<6),
TC_CCDINTLVL_LO_gc = (0x01<<6),
TC_CCDINTLVL_MED_gc = (0x02<<6),
TC_CCDINTLVL_HI_gc = (0x03<<6),
TC_CCDINTLVL_OFF_gc = (0x00<<6),
TC_CCDINTLVL_LO_gc = (0x01<<6),
TC_CCDINTLVL_MED_gc = (0x02<<6),
TC_CCDINTLVL_HI_gc = (0x03<<6),
TC_CCDINTLVL_OFF_gc = (0x00<<6),
TC_CCDINTLVL_LO_gc = (0x01<<6),
TC_CCDINTLVL_MED_gc = (0x02<<6),
TC_CCDINTLVL_HI_gc = (0x03<<6),
TC_CCDINTLVL_OFF_gc = (0x00<<6),
TC_CCDINTLVL_LO_gc = (0x01<<6),
TC_CCDINTLVL_MED_gc = (0x02<<6),
TC_CCDINTLVL_HI_gc = (0x03<<6),
TC_CCDINTLVL_OFF_gc = (0x00<<6),
TC_CCDINTLVL_LO_gc = (0x01<<6),
TC_CCDINTLVL_MED_gc = (0x02<<6),
TC_CCDINTLVL_HI_gc = (0x03<<6),
TC_CCDINTLVL_OFF_gc = (0x00<<6),
TC_CCDINTLVL_LO_gc = (0x01<<6),
TC_CCDINTLVL_MED_gc = (0x02<<6),
TC_CCDINTLVL_HI_gc = (0x03<<6),
TC_CCDINTLVL_OFF_gc = (0x00<<6),
TC_CCDINTLVL_LO_gc = (0x01<<6),
TC_CCDINTLVL_MED_gc = (0x02<<6),
TC_CCDINTLVL_HI_gc = (0x03<<6),
TC_CCDINTLVL_OFF_gc = (0x00<<6),
TC_CCDINTLVL_LO_gc = (0x01<<6),
TC_CCDINTLVL_MED_gc = (0x02<<6),
TC_CCDINTLVL_HI_gc = (0x03<<6),
TC_CCDINTLVL_OFF_gc = (0x00<<6),
TC_CCDINTLVL_LO_gc = (0x01<<6),
TC_CCDINTLVL_MED_gc = (0x02<<6),
TC_CCDINTLVL_HI_gc = (0x03<<6),
TC_CCDINTLVL_OFF_gc = (0x00<<6),
TC_CCDINTLVL_LO_gc = (0x01<<6),
TC_CCDINTLVL_MED_gc = (0x02<<6),
TC_CCDINTLVL_HI_gc = (0x03<<6),
TC_CCDINTLVL_OFF_gc = (0x00<<6),
TC_CCDINTLVL_LO_gc = (0x01<<6),
TC_CCDINTLVL_MED_gc = (0x02<<6),
TC_CCDINTLVL_HI_gc = (0x03<<6),
TC_CCDINTLVL_OFF_gc = (0x00<<6),
TC_CCDINTLVL_LO_gc = (0x01<<6),
TC_CCDINTLVL_MED_gc = (0x02<<6),
TC_CCDINTLVL_HI_gc = (0x03<<6)
} |
|
enum | TC_CCCINTLVL_enum {
TC_CCCINTLVL_OFF_gc = (0x00<<4),
TC_CCCINTLVL_LO_gc = (0x01<<4),
TC_CCCINTLVL_MED_gc = (0x02<<4),
TC_CCCINTLVL_HI_gc = (0x03<<4),
TC_CCCINTLVL_OFF_gc = (0x00<<4),
TC_CCCINTLVL_LO_gc = (0x01<<4),
TC_CCCINTLVL_MED_gc = (0x02<<4),
TC_CCCINTLVL_HI_gc = (0x03<<4),
TC_CCCINTLVL_OFF_gc = (0x00<<4),
TC_CCCINTLVL_LO_gc = (0x01<<4),
TC_CCCINTLVL_MED_gc = (0x02<<4),
TC_CCCINTLVL_HI_gc = (0x03<<4),
TC_CCCINTLVL_OFF_gc = (0x00<<4),
TC_CCCINTLVL_LO_gc = (0x01<<4),
TC_CCCINTLVL_MED_gc = (0x02<<4),
TC_CCCINTLVL_HI_gc = (0x03<<4),
TC_CCCINTLVL_OFF_gc = (0x00<<4),
TC_CCCINTLVL_LO_gc = (0x01<<4),
TC_CCCINTLVL_MED_gc = (0x02<<4),
TC_CCCINTLVL_HI_gc = (0x03<<4),
TC_CCCINTLVL_OFF_gc = (0x00<<4),
TC_CCCINTLVL_LO_gc = (0x01<<4),
TC_CCCINTLVL_MED_gc = (0x02<<4),
TC_CCCINTLVL_HI_gc = (0x03<<4),
TC_CCCINTLVL_OFF_gc = (0x00<<4),
TC_CCCINTLVL_LO_gc = (0x01<<4),
TC_CCCINTLVL_MED_gc = (0x02<<4),
TC_CCCINTLVL_HI_gc = (0x03<<4),
TC_CCCINTLVL_OFF_gc = (0x00<<4),
TC_CCCINTLVL_LO_gc = (0x01<<4),
TC_CCCINTLVL_MED_gc = (0x02<<4),
TC_CCCINTLVL_HI_gc = (0x03<<4),
TC_CCCINTLVL_OFF_gc = (0x00<<4),
TC_CCCINTLVL_LO_gc = (0x01<<4),
TC_CCCINTLVL_MED_gc = (0x02<<4),
TC_CCCINTLVL_HI_gc = (0x03<<4),
TC_CCCINTLVL_OFF_gc = (0x00<<4),
TC_CCCINTLVL_LO_gc = (0x01<<4),
TC_CCCINTLVL_MED_gc = (0x02<<4),
TC_CCCINTLVL_HI_gc = (0x03<<4),
TC_CCCINTLVL_OFF_gc = (0x00<<4),
TC_CCCINTLVL_LO_gc = (0x01<<4),
TC_CCCINTLVL_MED_gc = (0x02<<4),
TC_CCCINTLVL_HI_gc = (0x03<<4),
TC_CCCINTLVL_OFF_gc = (0x00<<4),
TC_CCCINTLVL_LO_gc = (0x01<<4),
TC_CCCINTLVL_MED_gc = (0x02<<4),
TC_CCCINTLVL_HI_gc = (0x03<<4),
TC_CCCINTLVL_OFF_gc = (0x00<<4),
TC_CCCINTLVL_LO_gc = (0x01<<4),
TC_CCCINTLVL_MED_gc = (0x02<<4),
TC_CCCINTLVL_HI_gc = (0x03<<4),
TC_CCCINTLVL_OFF_gc = (0x00<<4),
TC_CCCINTLVL_LO_gc = (0x01<<4),
TC_CCCINTLVL_MED_gc = (0x02<<4),
TC_CCCINTLVL_HI_gc = (0x03<<4),
TC_CCCINTLVL_OFF_gc = (0x00<<4),
TC_CCCINTLVL_LO_gc = (0x01<<4),
TC_CCCINTLVL_MED_gc = (0x02<<4),
TC_CCCINTLVL_HI_gc = (0x03<<4)
} |
|
enum | TC_CCBINTLVL_enum {
TC_CCBINTLVL_OFF_gc = (0x00<<2),
TC_CCBINTLVL_LO_gc = (0x01<<2),
TC_CCBINTLVL_MED_gc = (0x02<<2),
TC_CCBINTLVL_HI_gc = (0x03<<2),
TC_CCBINTLVL_OFF_gc = (0x00<<2),
TC_CCBINTLVL_LO_gc = (0x01<<2),
TC_CCBINTLVL_MED_gc = (0x02<<2),
TC_CCBINTLVL_HI_gc = (0x03<<2),
TC_CCBINTLVL_OFF_gc = (0x00<<2),
TC_CCBINTLVL_LO_gc = (0x01<<2),
TC_CCBINTLVL_MED_gc = (0x02<<2),
TC_CCBINTLVL_HI_gc = (0x03<<2),
TC_CCBINTLVL_OFF_gc = (0x00<<2),
TC_CCBINTLVL_LO_gc = (0x01<<2),
TC_CCBINTLVL_MED_gc = (0x02<<2),
TC_CCBINTLVL_HI_gc = (0x03<<2),
TC_CCBINTLVL_OFF_gc = (0x00<<2),
TC_CCBINTLVL_LO_gc = (0x01<<2),
TC_CCBINTLVL_MED_gc = (0x02<<2),
TC_CCBINTLVL_HI_gc = (0x03<<2),
TC_CCBINTLVL_OFF_gc = (0x00<<2),
TC_CCBINTLVL_LO_gc = (0x01<<2),
TC_CCBINTLVL_MED_gc = (0x02<<2),
TC_CCBINTLVL_HI_gc = (0x03<<2),
TC_CCBINTLVL_OFF_gc = (0x00<<2),
TC_CCBINTLVL_LO_gc = (0x01<<2),
TC_CCBINTLVL_MED_gc = (0x02<<2),
TC_CCBINTLVL_HI_gc = (0x03<<2),
TC_CCBINTLVL_OFF_gc = (0x00<<2),
TC_CCBINTLVL_LO_gc = (0x01<<2),
TC_CCBINTLVL_MED_gc = (0x02<<2),
TC_CCBINTLVL_HI_gc = (0x03<<2),
TC_CCBINTLVL_OFF_gc = (0x00<<2),
TC_CCBINTLVL_LO_gc = (0x01<<2),
TC_CCBINTLVL_MED_gc = (0x02<<2),
TC_CCBINTLVL_HI_gc = (0x03<<2),
TC_CCBINTLVL_OFF_gc = (0x00<<2),
TC_CCBINTLVL_LO_gc = (0x01<<2),
TC_CCBINTLVL_MED_gc = (0x02<<2),
TC_CCBINTLVL_HI_gc = (0x03<<2),
TC_CCBINTLVL_OFF_gc = (0x00<<2),
TC_CCBINTLVL_LO_gc = (0x01<<2),
TC_CCBINTLVL_MED_gc = (0x02<<2),
TC_CCBINTLVL_HI_gc = (0x03<<2),
TC_CCBINTLVL_OFF_gc = (0x00<<2),
TC_CCBINTLVL_LO_gc = (0x01<<2),
TC_CCBINTLVL_MED_gc = (0x02<<2),
TC_CCBINTLVL_HI_gc = (0x03<<2),
TC_CCBINTLVL_OFF_gc = (0x00<<2),
TC_CCBINTLVL_LO_gc = (0x01<<2),
TC_CCBINTLVL_MED_gc = (0x02<<2),
TC_CCBINTLVL_HI_gc = (0x03<<2),
TC_CCBINTLVL_OFF_gc = (0x00<<2),
TC_CCBINTLVL_LO_gc = (0x01<<2),
TC_CCBINTLVL_MED_gc = (0x02<<2),
TC_CCBINTLVL_HI_gc = (0x03<<2),
TC_CCBINTLVL_OFF_gc = (0x00<<2),
TC_CCBINTLVL_LO_gc = (0x01<<2),
TC_CCBINTLVL_MED_gc = (0x02<<2),
TC_CCBINTLVL_HI_gc = (0x03<<2)
} |
|
enum | TC_CCAINTLVL_enum {
TC_CCAINTLVL_OFF_gc = (0x00<<0),
TC_CCAINTLVL_LO_gc = (0x01<<0),
TC_CCAINTLVL_MED_gc = (0x02<<0),
TC_CCAINTLVL_HI_gc = (0x03<<0),
TC_CCAINTLVL_OFF_gc = (0x00<<0),
TC_CCAINTLVL_LO_gc = (0x01<<0),
TC_CCAINTLVL_MED_gc = (0x02<<0),
TC_CCAINTLVL_HI_gc = (0x03<<0),
TC_CCAINTLVL_OFF_gc = (0x00<<0),
TC_CCAINTLVL_LO_gc = (0x01<<0),
TC_CCAINTLVL_MED_gc = (0x02<<0),
TC_CCAINTLVL_HI_gc = (0x03<<0),
TC_CCAINTLVL_OFF_gc = (0x00<<0),
TC_CCAINTLVL_LO_gc = (0x01<<0),
TC_CCAINTLVL_MED_gc = (0x02<<0),
TC_CCAINTLVL_HI_gc = (0x03<<0),
TC_CCAINTLVL_OFF_gc = (0x00<<0),
TC_CCAINTLVL_LO_gc = (0x01<<0),
TC_CCAINTLVL_MED_gc = (0x02<<0),
TC_CCAINTLVL_HI_gc = (0x03<<0),
TC_CCAINTLVL_OFF_gc = (0x00<<0),
TC_CCAINTLVL_LO_gc = (0x01<<0),
TC_CCAINTLVL_MED_gc = (0x02<<0),
TC_CCAINTLVL_HI_gc = (0x03<<0),
TC_CCAINTLVL_OFF_gc = (0x00<<0),
TC_CCAINTLVL_LO_gc = (0x01<<0),
TC_CCAINTLVL_MED_gc = (0x02<<0),
TC_CCAINTLVL_HI_gc = (0x03<<0),
TC_CCAINTLVL_OFF_gc = (0x00<<0),
TC_CCAINTLVL_LO_gc = (0x01<<0),
TC_CCAINTLVL_MED_gc = (0x02<<0),
TC_CCAINTLVL_HI_gc = (0x03<<0),
TC_CCAINTLVL_OFF_gc = (0x00<<0),
TC_CCAINTLVL_LO_gc = (0x01<<0),
TC_CCAINTLVL_MED_gc = (0x02<<0),
TC_CCAINTLVL_HI_gc = (0x03<<0),
TC_CCAINTLVL_OFF_gc = (0x00<<0),
TC_CCAINTLVL_LO_gc = (0x01<<0),
TC_CCAINTLVL_MED_gc = (0x02<<0),
TC_CCAINTLVL_HI_gc = (0x03<<0),
TC_CCAINTLVL_OFF_gc = (0x00<<0),
TC_CCAINTLVL_LO_gc = (0x01<<0),
TC_CCAINTLVL_MED_gc = (0x02<<0),
TC_CCAINTLVL_HI_gc = (0x03<<0),
TC_CCAINTLVL_OFF_gc = (0x00<<0),
TC_CCAINTLVL_LO_gc = (0x01<<0),
TC_CCAINTLVL_MED_gc = (0x02<<0),
TC_CCAINTLVL_HI_gc = (0x03<<0),
TC_CCAINTLVL_OFF_gc = (0x00<<0),
TC_CCAINTLVL_LO_gc = (0x01<<0),
TC_CCAINTLVL_MED_gc = (0x02<<0),
TC_CCAINTLVL_HI_gc = (0x03<<0),
TC_CCAINTLVL_OFF_gc = (0x00<<0),
TC_CCAINTLVL_LO_gc = (0x01<<0),
TC_CCAINTLVL_MED_gc = (0x02<<0),
TC_CCAINTLVL_HI_gc = (0x03<<0),
TC_CCAINTLVL_OFF_gc = (0x00<<0),
TC_CCAINTLVL_LO_gc = (0x01<<0),
TC_CCAINTLVL_MED_gc = (0x02<<0),
TC_CCAINTLVL_HI_gc = (0x03<<0)
} |
|
enum | TC_CMD_enum {
TC_CMD_NONE_gc = (0x00<<2),
TC_CMD_UPDATE_gc = (0x01<<2),
TC_CMD_RESTART_gc = (0x02<<2),
TC_CMD_RESET_gc = (0x03<<2),
TC_CMD_NONE_gc = (0x00<<2),
TC_CMD_UPDATE_gc = (0x01<<2),
TC_CMD_RESTART_gc = (0x02<<2),
TC_CMD_RESET_gc = (0x03<<2),
TC_CMD_NONE_gc = (0x00<<2),
TC_CMD_UPDATE_gc = (0x01<<2),
TC_CMD_RESTART_gc = (0x02<<2),
TC_CMD_RESET_gc = (0x03<<2),
TC_CMD_NONE_gc = (0x00<<2),
TC_CMD_UPDATE_gc = (0x01<<2),
TC_CMD_RESTART_gc = (0x02<<2),
TC_CMD_RESET_gc = (0x03<<2),
TC_CMD_NONE_gc = (0x00<<2),
TC_CMD_UPDATE_gc = (0x01<<2),
TC_CMD_RESTART_gc = (0x02<<2),
TC_CMD_RESET_gc = (0x03<<2),
TC_CMD_NONE_gc = (0x00<<2),
TC_CMD_UPDATE_gc = (0x01<<2),
TC_CMD_RESTART_gc = (0x02<<2),
TC_CMD_RESET_gc = (0x03<<2),
TC_CMD_NONE_gc = (0x00<<2),
TC_CMD_UPDATE_gc = (0x01<<2),
TC_CMD_RESTART_gc = (0x02<<2),
TC_CMD_RESET_gc = (0x03<<2),
TC_CMD_NONE_gc = (0x00<<2),
TC_CMD_UPDATE_gc = (0x01<<2),
TC_CMD_RESTART_gc = (0x02<<2),
TC_CMD_RESET_gc = (0x03<<2),
TC_CMD_NONE_gc = (0x00<<2),
TC_CMD_UPDATE_gc = (0x01<<2),
TC_CMD_RESTART_gc = (0x02<<2),
TC_CMD_RESET_gc = (0x03<<2),
TC_CMD_NONE_gc = (0x00<<2),
TC_CMD_UPDATE_gc = (0x01<<2),
TC_CMD_RESTART_gc = (0x02<<2),
TC_CMD_RESET_gc = (0x03<<2),
TC_CMD_NONE_gc = (0x00<<2),
TC_CMD_UPDATE_gc = (0x01<<2),
TC_CMD_RESTART_gc = (0x02<<2),
TC_CMD_RESET_gc = (0x03<<2),
TC_CMD_NONE_gc = (0x00<<2),
TC_CMD_UPDATE_gc = (0x01<<2),
TC_CMD_RESTART_gc = (0x02<<2),
TC_CMD_RESET_gc = (0x03<<2),
TC_CMD_NONE_gc = (0x00<<2),
TC_CMD_UPDATE_gc = (0x01<<2),
TC_CMD_RESTART_gc = (0x02<<2),
TC_CMD_RESET_gc = (0x03<<2),
TC_CMD_NONE_gc = (0x00<<2),
TC_CMD_UPDATE_gc = (0x01<<2),
TC_CMD_RESTART_gc = (0x02<<2),
TC_CMD_RESET_gc = (0x03<<2),
TC_CMD_NONE_gc = (0x00<<2),
TC_CMD_UPDATE_gc = (0x01<<2),
TC_CMD_RESTART_gc = (0x02<<2),
TC_CMD_RESET_gc = (0x03<<2)
} |
|
enum | AWEX_FDACT_enum {
AWEX_FDACT_NONE_gc = (0x00<<0),
AWEX_FDACT_CLEAROE_gc = (0x01<<0),
AWEX_FDACT_CLEARDIR_gc = (0x03<<0),
AWEX_FDACT_NONE_gc = (0x00<<0),
AWEX_FDACT_CLEAROE_gc = (0x01<<0),
AWEX_FDACT_CLEARDIR_gc = (0x03<<0),
AWEX_FDACT_NONE_gc = (0x00<<0),
AWEX_FDACT_CLEAROE_gc = (0x01<<0),
AWEX_FDACT_CLEARDIR_gc = (0x03<<0),
AWEX_FDACT_NONE_gc = (0x00<<0),
AWEX_FDACT_CLEAROE_gc = (0x01<<0),
AWEX_FDACT_CLEARDIR_gc = (0x03<<0),
AWEX_FDACT_NONE_gc = (0x00<<0),
AWEX_FDACT_CLEAROE_gc = (0x01<<0),
AWEX_FDACT_CLEARDIR_gc = (0x03<<0),
AWEX_FDACT_NONE_gc = (0x00<<0),
AWEX_FDACT_CLEAROE_gc = (0x01<<0),
AWEX_FDACT_CLEARDIR_gc = (0x03<<0),
AWEX_FDACT_NONE_gc = (0x00<<0),
AWEX_FDACT_CLEAROE_gc = (0x01<<0),
AWEX_FDACT_CLEARDIR_gc = (0x03<<0),
AWEX_FDACT_NONE_gc = (0x00<<0),
AWEX_FDACT_CLEAROE_gc = (0x01<<0),
AWEX_FDACT_CLEARDIR_gc = (0x03<<0),
AWEX_FDACT_NONE_gc = (0x00<<0),
AWEX_FDACT_CLEAROE_gc = (0x01<<0),
AWEX_FDACT_CLEARDIR_gc = (0x03<<0),
AWEX_FDACT_NONE_gc = (0x00<<0),
AWEX_FDACT_CLEAROE_gc = (0x01<<0),
AWEX_FDACT_CLEARDIR_gc = (0x03<<0),
AWEX_FDACT_NONE_gc = (0x00<<0),
AWEX_FDACT_CLEAROE_gc = (0x01<<0),
AWEX_FDACT_CLEARDIR_gc = (0x03<<0),
AWEX_FDACT_NONE_gc = (0x00<<0),
AWEX_FDACT_CLEAROE_gc = (0x01<<0),
AWEX_FDACT_CLEARDIR_gc = (0x03<<0),
AWEX_FDACT_NONE_gc = (0x00<<0),
AWEX_FDACT_CLEAROE_gc = (0x01<<0),
AWEX_FDACT_CLEARDIR_gc = (0x03<<0),
AWEX_FDACT_NONE_gc = (0x00<<0),
AWEX_FDACT_CLEAROE_gc = (0x01<<0),
AWEX_FDACT_CLEARDIR_gc = (0x03<<0),
AWEX_FDACT_NONE_gc = (0x00<<0),
AWEX_FDACT_CLEAROE_gc = (0x01<<0),
AWEX_FDACT_CLEARDIR_gc = (0x03<<0)
} |
|
enum | HIRES_HREN_enum {
HIRES_HREN_NONE_gc = (0x00<<0),
HIRES_HREN_TC0_gc = (0x01<<0),
HIRES_HREN_TC1_gc = (0x02<<0),
HIRES_HREN_BOTH_gc = (0x03<<0),
HIRES_HREN_NONE_gc = (0x00<<0),
HIRES_HREN_TC0_gc = (0x01<<0),
HIRES_HREN_TC1_gc = (0x02<<0),
HIRES_HREN_BOTH_gc = (0x03<<0),
HIRES_HREN_NONE_gc = (0x00<<0),
HIRES_HREN_TC0_gc = (0x01<<0),
HIRES_HREN_TC1_gc = (0x02<<0),
HIRES_HREN_BOTH_gc = (0x03<<0),
HIRES_HREN_NONE_gc = (0x00<<0),
HIRES_HREN_TC0_gc = (0x01<<0),
HIRES_HREN_TC1_gc = (0x02<<0),
HIRES_HREN_BOTH_gc = (0x03<<0),
HIRES_HREN_NONE_gc = (0x00<<0),
HIRES_HREN_TC0_gc = (0x01<<0),
HIRES_HREN_TC1_gc = (0x02<<0),
HIRES_HREN_BOTH_gc = (0x03<<0),
HIRES_HREN_NONE_gc = (0x00<<0),
HIRES_HREN_TC0_gc = (0x01<<0),
HIRES_HREN_TC1_gc = (0x02<<0),
HIRES_HREN_BOTH_gc = (0x03<<0),
HIRES_HREN_NONE_gc = (0x00<<0),
HIRES_HREN_TC0_gc = (0x01<<0),
HIRES_HREN_TC1_gc = (0x02<<0),
HIRES_HREN_BOTH_gc = (0x03<<0),
HIRES_HREN_NONE_gc = (0x00<<0),
HIRES_HREN_TC0_gc = (0x01<<0),
HIRES_HREN_TC1_gc = (0x02<<0),
HIRES_HREN_BOTH_gc = (0x03<<0),
HIRES_HREN_NONE_gc = (0x00<<0),
HIRES_HREN_TC0_gc = (0x01<<0),
HIRES_HREN_TC1_gc = (0x02<<0),
HIRES_HREN_BOTH_gc = (0x03<<0),
HIRES_HREN_NONE_gc = (0x00<<0),
HIRES_HREN_TC0_gc = (0x01<<0),
HIRES_HREN_TC1_gc = (0x02<<0),
HIRES_HREN_BOTH_gc = (0x03<<0),
HIRES_HREN_NONE_gc = (0x00<<0),
HIRES_HREN_TC0_gc = (0x01<<0),
HIRES_HREN_TC1_gc = (0x02<<0),
HIRES_HREN_BOTH_gc = (0x03<<0),
HIRES_HREN_NONE_gc = (0x00<<0),
HIRES_HREN_TC0_gc = (0x01<<0),
HIRES_HREN_TC1_gc = (0x02<<0),
HIRES_HREN_BOTH_gc = (0x03<<0),
HIRES_HREN_NONE_gc = (0x00<<0),
HIRES_HREN_TC0_gc = (0x01<<0),
HIRES_HREN_TC1_gc = (0x02<<0),
HIRES_HREN_BOTH_gc = (0x03<<0),
HIRES_HREN_NONE_gc = (0x00<<0),
HIRES_HREN_TC0_gc = (0x01<<0),
HIRES_HREN_TC1_gc = (0x02<<0),
HIRES_HREN_BOTH_gc = (0x03<<0),
HIRES_HREN_NONE_gc = (0x00<<0),
HIRES_HREN_TC0_gc = (0x01<<0),
HIRES_HREN_TC1_gc = (0x02<<0),
HIRES_HREN_BOTH_gc = (0x03<<0)
} |
|
enum | USART_RXCINTLVL_enum {
USART_RXCINTLVL_OFF_gc = (0x00<<4),
USART_RXCINTLVL_LO_gc = (0x01<<4),
USART_RXCINTLVL_MED_gc = (0x02<<4),
USART_RXCINTLVL_HI_gc = (0x03<<4),
USART_RXCINTLVL_OFF_gc = (0x00<<4),
USART_RXCINTLVL_LO_gc = (0x01<<4),
USART_RXCINTLVL_MED_gc = (0x02<<4),
USART_RXCINTLVL_HI_gc = (0x03<<4),
USART_RXCINTLVL_OFF_gc = (0x00<<4),
USART_RXCINTLVL_LO_gc = (0x01<<4),
USART_RXCINTLVL_MED_gc = (0x02<<4),
USART_RXCINTLVL_HI_gc = (0x03<<4),
USART_RXCINTLVL_OFF_gc = (0x00<<4),
USART_RXCINTLVL_LO_gc = (0x01<<4),
USART_RXCINTLVL_MED_gc = (0x02<<4),
USART_RXCINTLVL_HI_gc = (0x03<<4),
USART_RXCINTLVL_OFF_gc = (0x00<<4),
USART_RXCINTLVL_LO_gc = (0x01<<4),
USART_RXCINTLVL_MED_gc = (0x02<<4),
USART_RXCINTLVL_HI_gc = (0x03<<4),
USART_RXCINTLVL_OFF_gc = (0x00<<4),
USART_RXCINTLVL_LO_gc = (0x01<<4),
USART_RXCINTLVL_MED_gc = (0x02<<4),
USART_RXCINTLVL_HI_gc = (0x03<<4),
USART_RXCINTLVL_OFF_gc = (0x00<<4),
USART_RXCINTLVL_LO_gc = (0x01<<4),
USART_RXCINTLVL_MED_gc = (0x02<<4),
USART_RXCINTLVL_HI_gc = (0x03<<4),
USART_RXCINTLVL_OFF_gc = (0x00<<4),
USART_RXCINTLVL_LO_gc = (0x01<<4),
USART_RXCINTLVL_MED_gc = (0x02<<4),
USART_RXCINTLVL_HI_gc = (0x03<<4),
USART_RXCINTLVL_OFF_gc = (0x00<<4),
USART_RXCINTLVL_LO_gc = (0x01<<4),
USART_RXCINTLVL_MED_gc = (0x02<<4),
USART_RXCINTLVL_HI_gc = (0x03<<4),
USART_RXCINTLVL_OFF_gc = (0x00<<4),
USART_RXCINTLVL_LO_gc = (0x01<<4),
USART_RXCINTLVL_MED_gc = (0x02<<4),
USART_RXCINTLVL_HI_gc = (0x03<<4),
USART_RXCINTLVL_OFF_gc = (0x00<<4),
USART_RXCINTLVL_LO_gc = (0x01<<4),
USART_RXCINTLVL_MED_gc = (0x02<<4),
USART_RXCINTLVL_HI_gc = (0x03<<4),
USART_RXCINTLVL_OFF_gc = (0x00<<4),
USART_RXCINTLVL_LO_gc = (0x01<<4),
USART_RXCINTLVL_MED_gc = (0x02<<4),
USART_RXCINTLVL_HI_gc = (0x03<<4),
USART_RXCINTLVL_OFF_gc = (0x00<<4),
USART_RXCINTLVL_LO_gc = (0x01<<4),
USART_RXCINTLVL_MED_gc = (0x02<<4),
USART_RXCINTLVL_HI_gc = (0x03<<4),
USART_RXCINTLVL_OFF_gc = (0x00<<4),
USART_RXCINTLVL_LO_gc = (0x01<<4),
USART_RXCINTLVL_MED_gc = (0x02<<4),
USART_RXCINTLVL_HI_gc = (0x03<<4),
USART_RXCINTLVL_OFF_gc = (0x00<<4),
USART_RXCINTLVL_LO_gc = (0x01<<4),
USART_RXCINTLVL_MED_gc = (0x02<<4),
USART_RXCINTLVL_HI_gc = (0x03<<4)
} |
|
enum | USART_TXCINTLVL_enum {
USART_TXCINTLVL_OFF_gc = (0x00<<2),
USART_TXCINTLVL_LO_gc = (0x01<<2),
USART_TXCINTLVL_MED_gc = (0x02<<2),
USART_TXCINTLVL_HI_gc = (0x03<<2),
USART_TXCINTLVL_OFF_gc = (0x00<<2),
USART_TXCINTLVL_LO_gc = (0x01<<2),
USART_TXCINTLVL_MED_gc = (0x02<<2),
USART_TXCINTLVL_HI_gc = (0x03<<2),
USART_TXCINTLVL_OFF_gc = (0x00<<2),
USART_TXCINTLVL_LO_gc = (0x01<<2),
USART_TXCINTLVL_MED_gc = (0x02<<2),
USART_TXCINTLVL_HI_gc = (0x03<<2),
USART_TXCINTLVL_OFF_gc = (0x00<<2),
USART_TXCINTLVL_LO_gc = (0x01<<2),
USART_TXCINTLVL_MED_gc = (0x02<<2),
USART_TXCINTLVL_HI_gc = (0x03<<2),
USART_TXCINTLVL_OFF_gc = (0x00<<2),
USART_TXCINTLVL_LO_gc = (0x01<<2),
USART_TXCINTLVL_MED_gc = (0x02<<2),
USART_TXCINTLVL_HI_gc = (0x03<<2),
USART_TXCINTLVL_OFF_gc = (0x00<<2),
USART_TXCINTLVL_LO_gc = (0x01<<2),
USART_TXCINTLVL_MED_gc = (0x02<<2),
USART_TXCINTLVL_HI_gc = (0x03<<2),
USART_TXCINTLVL_OFF_gc = (0x00<<2),
USART_TXCINTLVL_LO_gc = (0x01<<2),
USART_TXCINTLVL_MED_gc = (0x02<<2),
USART_TXCINTLVL_HI_gc = (0x03<<2),
USART_TXCINTLVL_OFF_gc = (0x00<<2),
USART_TXCINTLVL_LO_gc = (0x01<<2),
USART_TXCINTLVL_MED_gc = (0x02<<2),
USART_TXCINTLVL_HI_gc = (0x03<<2),
USART_TXCINTLVL_OFF_gc = (0x00<<2),
USART_TXCINTLVL_LO_gc = (0x01<<2),
USART_TXCINTLVL_MED_gc = (0x02<<2),
USART_TXCINTLVL_HI_gc = (0x03<<2),
USART_TXCINTLVL_OFF_gc = (0x00<<2),
USART_TXCINTLVL_LO_gc = (0x01<<2),
USART_TXCINTLVL_MED_gc = (0x02<<2),
USART_TXCINTLVL_HI_gc = (0x03<<2),
USART_TXCINTLVL_OFF_gc = (0x00<<2),
USART_TXCINTLVL_LO_gc = (0x01<<2),
USART_TXCINTLVL_MED_gc = (0x02<<2),
USART_TXCINTLVL_HI_gc = (0x03<<2),
USART_TXCINTLVL_OFF_gc = (0x00<<2),
USART_TXCINTLVL_LO_gc = (0x01<<2),
USART_TXCINTLVL_MED_gc = (0x02<<2),
USART_TXCINTLVL_HI_gc = (0x03<<2),
USART_TXCINTLVL_OFF_gc = (0x00<<2),
USART_TXCINTLVL_LO_gc = (0x01<<2),
USART_TXCINTLVL_MED_gc = (0x02<<2),
USART_TXCINTLVL_HI_gc = (0x03<<2),
USART_TXCINTLVL_OFF_gc = (0x00<<2),
USART_TXCINTLVL_LO_gc = (0x01<<2),
USART_TXCINTLVL_MED_gc = (0x02<<2),
USART_TXCINTLVL_HI_gc = (0x03<<2),
USART_TXCINTLVL_OFF_gc = (0x00<<2),
USART_TXCINTLVL_LO_gc = (0x01<<2),
USART_TXCINTLVL_MED_gc = (0x02<<2),
USART_TXCINTLVL_HI_gc = (0x03<<2)
} |
|
enum | USART_DREINTLVL_enum {
USART_DREINTLVL_OFF_gc = (0x00<<0),
USART_DREINTLVL_LO_gc = (0x01<<0),
USART_DREINTLVL_MED_gc = (0x02<<0),
USART_DREINTLVL_HI_gc = (0x03<<0),
USART_DREINTLVL_OFF_gc = (0x00<<0),
USART_DREINTLVL_LO_gc = (0x01<<0),
USART_DREINTLVL_MED_gc = (0x02<<0),
USART_DREINTLVL_HI_gc = (0x03<<0),
USART_DREINTLVL_OFF_gc = (0x00<<0),
USART_DREINTLVL_LO_gc = (0x01<<0),
USART_DREINTLVL_MED_gc = (0x02<<0),
USART_DREINTLVL_HI_gc = (0x03<<0),
USART_DREINTLVL_OFF_gc = (0x00<<0),
USART_DREINTLVL_LO_gc = (0x01<<0),
USART_DREINTLVL_MED_gc = (0x02<<0),
USART_DREINTLVL_HI_gc = (0x03<<0),
USART_DREINTLVL_OFF_gc = (0x00<<0),
USART_DREINTLVL_LO_gc = (0x01<<0),
USART_DREINTLVL_MED_gc = (0x02<<0),
USART_DREINTLVL_HI_gc = (0x03<<0),
USART_DREINTLVL_OFF_gc = (0x00<<0),
USART_DREINTLVL_LO_gc = (0x01<<0),
USART_DREINTLVL_MED_gc = (0x02<<0),
USART_DREINTLVL_HI_gc = (0x03<<0),
USART_DREINTLVL_OFF_gc = (0x00<<0),
USART_DREINTLVL_LO_gc = (0x01<<0),
USART_DREINTLVL_MED_gc = (0x02<<0),
USART_DREINTLVL_HI_gc = (0x03<<0),
USART_DREINTLVL_OFF_gc = (0x00<<0),
USART_DREINTLVL_LO_gc = (0x01<<0),
USART_DREINTLVL_MED_gc = (0x02<<0),
USART_DREINTLVL_HI_gc = (0x03<<0),
USART_DREINTLVL_OFF_gc = (0x00<<0),
USART_DREINTLVL_LO_gc = (0x01<<0),
USART_DREINTLVL_MED_gc = (0x02<<0),
USART_DREINTLVL_HI_gc = (0x03<<0),
USART_DREINTLVL_OFF_gc = (0x00<<0),
USART_DREINTLVL_LO_gc = (0x01<<0),
USART_DREINTLVL_MED_gc = (0x02<<0),
USART_DREINTLVL_HI_gc = (0x03<<0),
USART_DREINTLVL_OFF_gc = (0x00<<0),
USART_DREINTLVL_LO_gc = (0x01<<0),
USART_DREINTLVL_MED_gc = (0x02<<0),
USART_DREINTLVL_HI_gc = (0x03<<0),
USART_DREINTLVL_OFF_gc = (0x00<<0),
USART_DREINTLVL_LO_gc = (0x01<<0),
USART_DREINTLVL_MED_gc = (0x02<<0),
USART_DREINTLVL_HI_gc = (0x03<<0),
USART_DREINTLVL_OFF_gc = (0x00<<0),
USART_DREINTLVL_LO_gc = (0x01<<0),
USART_DREINTLVL_MED_gc = (0x02<<0),
USART_DREINTLVL_HI_gc = (0x03<<0),
USART_DREINTLVL_OFF_gc = (0x00<<0),
USART_DREINTLVL_LO_gc = (0x01<<0),
USART_DREINTLVL_MED_gc = (0x02<<0),
USART_DREINTLVL_HI_gc = (0x03<<0),
USART_DREINTLVL_OFF_gc = (0x00<<0),
USART_DREINTLVL_LO_gc = (0x01<<0),
USART_DREINTLVL_MED_gc = (0x02<<0),
USART_DREINTLVL_HI_gc = (0x03<<0)
} |
|
enum | USART_CHSIZE_enum {
USART_CHSIZE_5BIT_gc = (0x00<<0),
USART_CHSIZE_6BIT_gc = (0x01<<0),
USART_CHSIZE_7BIT_gc = (0x02<<0),
USART_CHSIZE_8BIT_gc = (0x03<<0),
USART_CHSIZE_9BIT_gc = (0x07<<0),
USART_CHSIZE_5BIT_gc = (0x00<<0),
USART_CHSIZE_6BIT_gc = (0x01<<0),
USART_CHSIZE_7BIT_gc = (0x02<<0),
USART_CHSIZE_8BIT_gc = (0x03<<0),
USART_CHSIZE_9BIT_gc = (0x07<<0),
USART_CHSIZE_5BIT_gc = (0x00<<0),
USART_CHSIZE_6BIT_gc = (0x01<<0),
USART_CHSIZE_7BIT_gc = (0x02<<0),
USART_CHSIZE_8BIT_gc = (0x03<<0),
USART_CHSIZE_9BIT_gc = (0x07<<0),
USART_CHSIZE_5BIT_gc = (0x00<<0),
USART_CHSIZE_6BIT_gc = (0x01<<0),
USART_CHSIZE_7BIT_gc = (0x02<<0),
USART_CHSIZE_8BIT_gc = (0x03<<0),
USART_CHSIZE_9BIT_gc = (0x07<<0),
USART_CHSIZE_5BIT_gc = (0x00<<0),
USART_CHSIZE_6BIT_gc = (0x01<<0),
USART_CHSIZE_7BIT_gc = (0x02<<0),
USART_CHSIZE_8BIT_gc = (0x03<<0),
USART_CHSIZE_9BIT_gc = (0x07<<0),
USART_CHSIZE_5BIT_gc = (0x00<<0),
USART_CHSIZE_6BIT_gc = (0x01<<0),
USART_CHSIZE_7BIT_gc = (0x02<<0),
USART_CHSIZE_8BIT_gc = (0x03<<0),
USART_CHSIZE_9BIT_gc = (0x07<<0),
USART_CHSIZE_5BIT_gc = (0x00<<0),
USART_CHSIZE_6BIT_gc = (0x01<<0),
USART_CHSIZE_7BIT_gc = (0x02<<0),
USART_CHSIZE_8BIT_gc = (0x03<<0),
USART_CHSIZE_9BIT_gc = (0x07<<0),
USART_CHSIZE_5BIT_gc = (0x00<<0),
USART_CHSIZE_6BIT_gc = (0x01<<0),
USART_CHSIZE_7BIT_gc = (0x02<<0),
USART_CHSIZE_8BIT_gc = (0x03<<0),
USART_CHSIZE_9BIT_gc = (0x07<<0),
USART_CHSIZE_5BIT_gc = (0x00<<0),
USART_CHSIZE_6BIT_gc = (0x01<<0),
USART_CHSIZE_7BIT_gc = (0x02<<0),
USART_CHSIZE_8BIT_gc = (0x03<<0),
USART_CHSIZE_9BIT_gc = (0x07<<0),
USART_CHSIZE_5BIT_gc = (0x00<<0),
USART_CHSIZE_6BIT_gc = (0x01<<0),
USART_CHSIZE_7BIT_gc = (0x02<<0),
USART_CHSIZE_8BIT_gc = (0x03<<0),
USART_CHSIZE_9BIT_gc = (0x07<<0),
USART_CHSIZE_5BIT_gc = (0x00<<0),
USART_CHSIZE_6BIT_gc = (0x01<<0),
USART_CHSIZE_7BIT_gc = (0x02<<0),
USART_CHSIZE_8BIT_gc = (0x03<<0),
USART_CHSIZE_9BIT_gc = (0x07<<0),
USART_CHSIZE_5BIT_gc = (0x00<<0),
USART_CHSIZE_6BIT_gc = (0x01<<0),
USART_CHSIZE_7BIT_gc = (0x02<<0),
USART_CHSIZE_8BIT_gc = (0x03<<0),
USART_CHSIZE_9BIT_gc = (0x07<<0),
USART_CHSIZE_5BIT_gc = (0x00<<0),
USART_CHSIZE_6BIT_gc = (0x01<<0),
USART_CHSIZE_7BIT_gc = (0x02<<0),
USART_CHSIZE_8BIT_gc = (0x03<<0),
USART_CHSIZE_9BIT_gc = (0x07<<0),
USART_CHSIZE_5BIT_gc = (0x00<<0),
USART_CHSIZE_6BIT_gc = (0x01<<0),
USART_CHSIZE_7BIT_gc = (0x02<<0),
USART_CHSIZE_8BIT_gc = (0x03<<0),
USART_CHSIZE_9BIT_gc = (0x07<<0),
USART_CHSIZE_5BIT_gc = (0x00<<0),
USART_CHSIZE_6BIT_gc = (0x01<<0),
USART_CHSIZE_7BIT_gc = (0x02<<0),
USART_CHSIZE_8BIT_gc = (0x03<<0),
USART_CHSIZE_9BIT_gc = (0x07<<0)
} |
|
enum | USART_CMODE_enum {
USART_CMODE_ASYNCHRONOUS_gc = (0x00<<6),
USART_CMODE_SYNCHRONOUS_gc = (0x01<<6),
USART_CMODE_IRDA_gc = (0x02<<6),
USART_CMODE_MSPI_gc = (0x03<<6),
USART_CMODE_ASYNCHRONOUS_gc = (0x00<<6),
USART_CMODE_SYNCHRONOUS_gc = (0x01<<6),
USART_CMODE_IRDA_gc = (0x02<<6),
USART_CMODE_MSPI_gc = (0x03<<6),
USART_CMODE_ASYNCHRONOUS_gc = (0x00<<6),
USART_CMODE_SYNCHRONOUS_gc = (0x01<<6),
USART_CMODE_IRDA_gc = (0x02<<6),
USART_CMODE_MSPI_gc = (0x03<<6),
USART_CMODE_ASYNCHRONOUS_gc = (0x00<<6),
USART_CMODE_SYNCHRONOUS_gc = (0x01<<6),
USART_CMODE_IRDA_gc = (0x02<<6),
USART_CMODE_MSPI_gc = (0x03<<6),
USART_CMODE_ASYNCHRONOUS_gc = (0x00<<6),
USART_CMODE_SYNCHRONOUS_gc = (0x01<<6),
USART_CMODE_IRDA_gc = (0x02<<6),
USART_CMODE_MSPI_gc = (0x03<<6),
USART_CMODE_ASYNCHRONOUS_gc = (0x00<<6),
USART_CMODE_SYNCHRONOUS_gc = (0x01<<6),
USART_CMODE_IRDA_gc = (0x02<<6),
USART_CMODE_MSPI_gc = (0x03<<6),
USART_CMODE_ASYNCHRONOUS_gc = (0x00<<6),
USART_CMODE_SYNCHRONOUS_gc = (0x01<<6),
USART_CMODE_IRDA_gc = (0x02<<6),
USART_CMODE_MSPI_gc = (0x03<<6),
USART_CMODE_ASYNCHRONOUS_gc = (0x00<<6),
USART_CMODE_SYNCHRONOUS_gc = (0x01<<6),
USART_CMODE_IRDA_gc = (0x02<<6),
USART_CMODE_MSPI_gc = (0x03<<6),
USART_CMODE_ASYNCHRONOUS_gc = (0x00<<6),
USART_CMODE_SYNCHRONOUS_gc = (0x01<<6),
USART_CMODE_IRDA_gc = (0x02<<6),
USART_CMODE_MSPI_gc = (0x03<<6),
USART_CMODE_ASYNCHRONOUS_gc = (0x00<<6),
USART_CMODE_SYNCHRONOUS_gc = (0x01<<6),
USART_CMODE_IRDA_gc = (0x02<<6),
USART_CMODE_MSPI_gc = (0x03<<6),
USART_CMODE_ASYNCHRONOUS_gc = (0x00<<6),
USART_CMODE_SYNCHRONOUS_gc = (0x01<<6),
USART_CMODE_IRDA_gc = (0x02<<6),
USART_CMODE_MSPI_gc = (0x03<<6),
USART_CMODE_ASYNCHRONOUS_gc = (0x00<<6),
USART_CMODE_SYNCHRONOUS_gc = (0x01<<6),
USART_CMODE_IRDA_gc = (0x02<<6),
USART_CMODE_MSPI_gc = (0x03<<6),
USART_CMODE_ASYNCHRONOUS_gc = (0x00<<6),
USART_CMODE_SYNCHRONOUS_gc = (0x01<<6),
USART_CMODE_IRDA_gc = (0x02<<6),
USART_CMODE_MSPI_gc = (0x03<<6),
USART_CMODE_ASYNCHRONOUS_gc = (0x00<<6),
USART_CMODE_SYNCHRONOUS_gc = (0x01<<6),
USART_CMODE_IRDA_gc = (0x02<<6),
USART_CMODE_MSPI_gc = (0x03<<6),
USART_CMODE_ASYNCHRONOUS_gc = (0x00<<6),
USART_CMODE_SYNCHRONOUS_gc = (0x01<<6),
USART_CMODE_IRDA_gc = (0x02<<6),
USART_CMODE_MSPI_gc = (0x03<<6)
} |
|
enum | USART_PMODE_enum {
USART_PMODE_DISABLED_gc = (0x00<<4),
USART_PMODE_EVEN_gc = (0x02<<4),
USART_PMODE_ODD_gc = (0x03<<4),
USART_PMODE_DISABLED_gc = (0x00<<4),
USART_PMODE_EVEN_gc = (0x02<<4),
USART_PMODE_ODD_gc = (0x03<<4),
USART_PMODE_DISABLED_gc = (0x00<<4),
USART_PMODE_EVEN_gc = (0x02<<4),
USART_PMODE_ODD_gc = (0x03<<4),
USART_PMODE_DISABLED_gc = (0x00<<4),
USART_PMODE_EVEN_gc = (0x02<<4),
USART_PMODE_ODD_gc = (0x03<<4),
USART_PMODE_DISABLED_gc = (0x00<<4),
USART_PMODE_EVEN_gc = (0x02<<4),
USART_PMODE_ODD_gc = (0x03<<4),
USART_PMODE_DISABLED_gc = (0x00<<4),
USART_PMODE_EVEN_gc = (0x02<<4),
USART_PMODE_ODD_gc = (0x03<<4),
USART_PMODE_DISABLED_gc = (0x00<<4),
USART_PMODE_EVEN_gc = (0x02<<4),
USART_PMODE_ODD_gc = (0x03<<4),
USART_PMODE_DISABLED_gc = (0x00<<4),
USART_PMODE_EVEN_gc = (0x02<<4),
USART_PMODE_ODD_gc = (0x03<<4),
USART_PMODE_DISABLED_gc = (0x00<<4),
USART_PMODE_EVEN_gc = (0x02<<4),
USART_PMODE_ODD_gc = (0x03<<4),
USART_PMODE_DISABLED_gc = (0x00<<4),
USART_PMODE_EVEN_gc = (0x02<<4),
USART_PMODE_ODD_gc = (0x03<<4),
USART_PMODE_DISABLED_gc = (0x00<<4),
USART_PMODE_EVEN_gc = (0x02<<4),
USART_PMODE_ODD_gc = (0x03<<4),
USART_PMODE_DISABLED_gc = (0x00<<4),
USART_PMODE_EVEN_gc = (0x02<<4),
USART_PMODE_ODD_gc = (0x03<<4),
USART_PMODE_DISABLED_gc = (0x00<<4),
USART_PMODE_EVEN_gc = (0x02<<4),
USART_PMODE_ODD_gc = (0x03<<4),
USART_PMODE_DISABLED_gc = (0x00<<4),
USART_PMODE_EVEN_gc = (0x02<<4),
USART_PMODE_ODD_gc = (0x03<<4),
USART_PMODE_DISABLED_gc = (0x00<<4),
USART_PMODE_EVEN_gc = (0x02<<4),
USART_PMODE_ODD_gc = (0x03<<4)
} |
|
enum | SPI_MODE_enum {
SPI_MODE_0_gc = (0x00<<2),
SPI_MODE_1_gc = (0x01<<2),
SPI_MODE_2_gc = (0x02<<2),
SPI_MODE_3_gc = (0x03<<2),
SPI_MODE_0_gc = (0x00<<2),
SPI_MODE_1_gc = (0x01<<2),
SPI_MODE_2_gc = (0x02<<2),
SPI_MODE_3_gc = (0x03<<2),
SPI_MODE_0_gc = (0x00<<2),
SPI_MODE_1_gc = (0x01<<2),
SPI_MODE_2_gc = (0x02<<2),
SPI_MODE_3_gc = (0x03<<2),
SPI_MODE_0_gc = (0x00<<2),
SPI_MODE_1_gc = (0x01<<2),
SPI_MODE_2_gc = (0x02<<2),
SPI_MODE_3_gc = (0x03<<2),
SPI_MODE_0_gc = (0x00<<2),
SPI_MODE_1_gc = (0x01<<2),
SPI_MODE_2_gc = (0x02<<2),
SPI_MODE_3_gc = (0x03<<2),
SPI_MODE_0_gc = (0x00<<2),
SPI_MODE_1_gc = (0x01<<2),
SPI_MODE_2_gc = (0x02<<2),
SPI_MODE_3_gc = (0x03<<2),
SPI_MODE_0_gc = (0x00<<2),
SPI_MODE_1_gc = (0x01<<2),
SPI_MODE_2_gc = (0x02<<2),
SPI_MODE_3_gc = (0x03<<2),
SPI_MODE_0_gc = (0x00<<2),
SPI_MODE_1_gc = (0x01<<2),
SPI_MODE_2_gc = (0x02<<2),
SPI_MODE_3_gc = (0x03<<2),
SPI_MODE_0_gc = (0x00<<2),
SPI_MODE_1_gc = (0x01<<2),
SPI_MODE_2_gc = (0x02<<2),
SPI_MODE_3_gc = (0x03<<2),
SPI_MODE_0_gc = (0x00<<2),
SPI_MODE_1_gc = (0x01<<2),
SPI_MODE_2_gc = (0x02<<2),
SPI_MODE_3_gc = (0x03<<2),
SPI_MODE_0_gc = (0x00<<2),
SPI_MODE_1_gc = (0x01<<2),
SPI_MODE_2_gc = (0x02<<2),
SPI_MODE_3_gc = (0x03<<2),
SPI_MODE_0_gc = (0x00<<2),
SPI_MODE_1_gc = (0x01<<2),
SPI_MODE_2_gc = (0x02<<2),
SPI_MODE_3_gc = (0x03<<2),
SPI_MODE_0_gc = (0x00<<2),
SPI_MODE_1_gc = (0x01<<2),
SPI_MODE_2_gc = (0x02<<2),
SPI_MODE_3_gc = (0x03<<2),
SPI_MODE_0_gc = (0x00<<2),
SPI_MODE_1_gc = (0x01<<2),
SPI_MODE_2_gc = (0x02<<2),
SPI_MODE_3_gc = (0x03<<2),
SPI_MODE_0_gc = (0x00<<2),
SPI_MODE_1_gc = (0x01<<2),
SPI_MODE_2_gc = (0x02<<2),
SPI_MODE_3_gc = (0x03<<2)
} |
|
enum | SPI_PRESCALER_enum {
SPI_PRESCALER_DIV4_gc = (0x00<<0),
SPI_PRESCALER_DIV16_gc = (0x01<<0),
SPI_PRESCALER_DIV64_gc = (0x02<<0),
SPI_PRESCALER_DIV128_gc = (0x03<<0),
SPI_PRESCALER_DIV4_gc = (0x00<<0),
SPI_PRESCALER_DIV16_gc = (0x01<<0),
SPI_PRESCALER_DIV64_gc = (0x02<<0),
SPI_PRESCALER_DIV128_gc = (0x03<<0),
SPI_PRESCALER_DIV4_gc = (0x00<<0),
SPI_PRESCALER_DIV16_gc = (0x01<<0),
SPI_PRESCALER_DIV64_gc = (0x02<<0),
SPI_PRESCALER_DIV128_gc = (0x03<<0),
SPI_PRESCALER_DIV4_gc = (0x00<<0),
SPI_PRESCALER_DIV16_gc = (0x01<<0),
SPI_PRESCALER_DIV64_gc = (0x02<<0),
SPI_PRESCALER_DIV128_gc = (0x03<<0),
SPI_PRESCALER_DIV4_gc = (0x00<<0),
SPI_PRESCALER_DIV16_gc = (0x01<<0),
SPI_PRESCALER_DIV64_gc = (0x02<<0),
SPI_PRESCALER_DIV128_gc = (0x03<<0),
SPI_PRESCALER_DIV4_gc = (0x00<<0),
SPI_PRESCALER_DIV16_gc = (0x01<<0),
SPI_PRESCALER_DIV64_gc = (0x02<<0),
SPI_PRESCALER_DIV128_gc = (0x03<<0),
SPI_PRESCALER_DIV4_gc = (0x00<<0),
SPI_PRESCALER_DIV16_gc = (0x01<<0),
SPI_PRESCALER_DIV64_gc = (0x02<<0),
SPI_PRESCALER_DIV128_gc = (0x03<<0),
SPI_PRESCALER_DIV4_gc = (0x00<<0),
SPI_PRESCALER_DIV16_gc = (0x01<<0),
SPI_PRESCALER_DIV64_gc = (0x02<<0),
SPI_PRESCALER_DIV128_gc = (0x03<<0),
SPI_PRESCALER_DIV4_gc = (0x00<<0),
SPI_PRESCALER_DIV16_gc = (0x01<<0),
SPI_PRESCALER_DIV64_gc = (0x02<<0),
SPI_PRESCALER_DIV128_gc = (0x03<<0),
SPI_PRESCALER_DIV4_gc = (0x00<<0),
SPI_PRESCALER_DIV16_gc = (0x01<<0),
SPI_PRESCALER_DIV64_gc = (0x02<<0),
SPI_PRESCALER_DIV128_gc = (0x03<<0),
SPI_PRESCALER_DIV4_gc = (0x00<<0),
SPI_PRESCALER_DIV16_gc = (0x01<<0),
SPI_PRESCALER_DIV64_gc = (0x02<<0),
SPI_PRESCALER_DIV128_gc = (0x03<<0),
SPI_PRESCALER_DIV4_gc = (0x00<<0),
SPI_PRESCALER_DIV16_gc = (0x01<<0),
SPI_PRESCALER_DIV64_gc = (0x02<<0),
SPI_PRESCALER_DIV128_gc = (0x03<<0),
SPI_PRESCALER_DIV4_gc = (0x00<<0),
SPI_PRESCALER_DIV16_gc = (0x01<<0),
SPI_PRESCALER_DIV64_gc = (0x02<<0),
SPI_PRESCALER_DIV128_gc = (0x03<<0),
SPI_PRESCALER_DIV4_gc = (0x00<<0),
SPI_PRESCALER_DIV16_gc = (0x01<<0),
SPI_PRESCALER_DIV64_gc = (0x02<<0),
SPI_PRESCALER_DIV128_gc = (0x03<<0),
SPI_PRESCALER_DIV4_gc = (0x00<<0),
SPI_PRESCALER_DIV16_gc = (0x01<<0),
SPI_PRESCALER_DIV64_gc = (0x02<<0),
SPI_PRESCALER_DIV128_gc = (0x03<<0)
} |
|
enum | SPI_INTLVL_enum {
SPI_INTLVL_OFF_gc = (0x00<<0),
SPI_INTLVL_LO_gc = (0x01<<0),
SPI_INTLVL_MED_gc = (0x02<<0),
SPI_INTLVL_HI_gc = (0x03<<0),
SPI_INTLVL_OFF_gc = (0x00<<0),
SPI_INTLVL_LO_gc = (0x01<<0),
SPI_INTLVL_MED_gc = (0x02<<0),
SPI_INTLVL_HI_gc = (0x03<<0),
SPI_INTLVL_OFF_gc = (0x00<<0),
SPI_INTLVL_LO_gc = (0x01<<0),
SPI_INTLVL_MED_gc = (0x02<<0),
SPI_INTLVL_HI_gc = (0x03<<0),
SPI_INTLVL_OFF_gc = (0x00<<0),
SPI_INTLVL_LO_gc = (0x01<<0),
SPI_INTLVL_MED_gc = (0x02<<0),
SPI_INTLVL_HI_gc = (0x03<<0),
SPI_INTLVL_OFF_gc = (0x00<<0),
SPI_INTLVL_LO_gc = (0x01<<0),
SPI_INTLVL_MED_gc = (0x02<<0),
SPI_INTLVL_HI_gc = (0x03<<0),
SPI_INTLVL_OFF_gc = (0x00<<0),
SPI_INTLVL_LO_gc = (0x01<<0),
SPI_INTLVL_MED_gc = (0x02<<0),
SPI_INTLVL_HI_gc = (0x03<<0),
SPI_INTLVL_OFF_gc = (0x00<<0),
SPI_INTLVL_LO_gc = (0x01<<0),
SPI_INTLVL_MED_gc = (0x02<<0),
SPI_INTLVL_HI_gc = (0x03<<0),
SPI_INTLVL_OFF_gc = (0x00<<0),
SPI_INTLVL_LO_gc = (0x01<<0),
SPI_INTLVL_MED_gc = (0x02<<0),
SPI_INTLVL_HI_gc = (0x03<<0),
SPI_INTLVL_OFF_gc = (0x00<<0),
SPI_INTLVL_LO_gc = (0x01<<0),
SPI_INTLVL_MED_gc = (0x02<<0),
SPI_INTLVL_HI_gc = (0x03<<0),
SPI_INTLVL_OFF_gc = (0x00<<0),
SPI_INTLVL_LO_gc = (0x01<<0),
SPI_INTLVL_MED_gc = (0x02<<0),
SPI_INTLVL_HI_gc = (0x03<<0),
SPI_INTLVL_OFF_gc = (0x00<<0),
SPI_INTLVL_LO_gc = (0x01<<0),
SPI_INTLVL_MED_gc = (0x02<<0),
SPI_INTLVL_HI_gc = (0x03<<0),
SPI_INTLVL_OFF_gc = (0x00<<0),
SPI_INTLVL_LO_gc = (0x01<<0),
SPI_INTLVL_MED_gc = (0x02<<0),
SPI_INTLVL_HI_gc = (0x03<<0),
SPI_INTLVL_OFF_gc = (0x00<<0),
SPI_INTLVL_LO_gc = (0x01<<0),
SPI_INTLVL_MED_gc = (0x02<<0),
SPI_INTLVL_HI_gc = (0x03<<0),
SPI_INTLVL_OFF_gc = (0x00<<0),
SPI_INTLVL_LO_gc = (0x01<<0),
SPI_INTLVL_MED_gc = (0x02<<0),
SPI_INTLVL_HI_gc = (0x03<<0),
SPI_INTLVL_OFF_gc = (0x00<<0),
SPI_INTLVL_LO_gc = (0x01<<0),
SPI_INTLVL_MED_gc = (0x02<<0),
SPI_INTLVL_HI_gc = (0x03<<0)
} |
|
enum | IRDA_EVSEL_enum {
IRDA_EVSEL_OFF_gc = (0x00<<0),
IRDA_EVSEL_0_gc = (0x08<<0),
IRDA_EVSEL_1_gc = (0x09<<0),
IRDA_EVSEL_2_gc = (0x0A<<0),
IRDA_EVSEL_3_gc = (0x0B<<0),
IRDA_EVSEL_4_gc = (0x0C<<0),
IRDA_EVSEL_5_gc = (0x0D<<0),
IRDA_EVSEL_6_gc = (0x0E<<0),
IRDA_EVSEL_7_gc = (0x0F<<0),
IRDA_EVSEL_OFF_gc = (0x00<<0),
IRDA_EVSEL_0_gc = (0x08<<0),
IRDA_EVSEL_1_gc = (0x09<<0),
IRDA_EVSEL_2_gc = (0x0A<<0),
IRDA_EVSEL_3_gc = (0x0B<<0),
IRDA_EVSEL_4_gc = (0x0C<<0),
IRDA_EVSEL_5_gc = (0x0D<<0),
IRDA_EVSEL_6_gc = (0x0E<<0),
IRDA_EVSEL_7_gc = (0x0F<<0),
IRDA_EVSEL_OFF_gc = (0x00<<0),
IRDA_EVSEL_0_gc = (0x08<<0),
IRDA_EVSEL_1_gc = (0x09<<0),
IRDA_EVSEL_2_gc = (0x0A<<0),
IRDA_EVSEL_3_gc = (0x0B<<0),
IRDA_EVSEL_4_gc = (0x0C<<0),
IRDA_EVSEL_5_gc = (0x0D<<0),
IRDA_EVSEL_6_gc = (0x0E<<0),
IRDA_EVSEL_7_gc = (0x0F<<0),
IRDA_EVSEL_OFF_gc = (0x00<<0),
IRDA_EVSEL_0_gc = (0x08<<0),
IRDA_EVSEL_1_gc = (0x09<<0),
IRDA_EVSEL_2_gc = (0x0A<<0),
IRDA_EVSEL_3_gc = (0x0B<<0),
IRDA_EVSEL_4_gc = (0x0C<<0),
IRDA_EVSEL_5_gc = (0x0D<<0),
IRDA_EVSEL_6_gc = (0x0E<<0),
IRDA_EVSEL_7_gc = (0x0F<<0),
IRDA_EVSEL_OFF_gc = (0x00<<0),
IRDA_EVSEL_0_gc = (0x08<<0),
IRDA_EVSEL_1_gc = (0x09<<0),
IRDA_EVSEL_2_gc = (0x0A<<0),
IRDA_EVSEL_3_gc = (0x0B<<0),
IRDA_EVSEL_4_gc = (0x0C<<0),
IRDA_EVSEL_5_gc = (0x0D<<0),
IRDA_EVSEL_6_gc = (0x0E<<0),
IRDA_EVSEL_7_gc = (0x0F<<0),
IRDA_EVSEL_OFF_gc = (0x00<<0),
IRDA_EVSEL_0_gc = (0x08<<0),
IRDA_EVSEL_1_gc = (0x09<<0),
IRDA_EVSEL_2_gc = (0x0A<<0),
IRDA_EVSEL_3_gc = (0x0B<<0),
IRDA_EVSEL_4_gc = (0x0C<<0),
IRDA_EVSEL_5_gc = (0x0D<<0),
IRDA_EVSEL_6_gc = (0x0E<<0),
IRDA_EVSEL_7_gc = (0x0F<<0),
IRDA_EVSEL_OFF_gc = (0x00<<0),
IRDA_EVSEL_0_gc = (0x08<<0),
IRDA_EVSEL_1_gc = (0x09<<0),
IRDA_EVSEL_2_gc = (0x0A<<0),
IRDA_EVSEL_3_gc = (0x0B<<0),
IRDA_EVSEL_4_gc = (0x0C<<0),
IRDA_EVSEL_5_gc = (0x0D<<0),
IRDA_EVSEL_6_gc = (0x0E<<0),
IRDA_EVSEL_7_gc = (0x0F<<0),
IRDA_EVSEL_OFF_gc = (0x00<<0),
IRDA_EVSEL_0_gc = (0x08<<0),
IRDA_EVSEL_1_gc = (0x09<<0),
IRDA_EVSEL_2_gc = (0x0A<<0),
IRDA_EVSEL_3_gc = (0x0B<<0),
IRDA_EVSEL_4_gc = (0x0C<<0),
IRDA_EVSEL_5_gc = (0x0D<<0),
IRDA_EVSEL_6_gc = (0x0E<<0),
IRDA_EVSEL_7_gc = (0x0F<<0),
IRDA_EVSEL_OFF_gc = (0x00<<0),
IRDA_EVSEL_0_gc = (0x08<<0),
IRDA_EVSEL_1_gc = (0x09<<0),
IRDA_EVSEL_2_gc = (0x0A<<0),
IRDA_EVSEL_3_gc = (0x0B<<0),
IRDA_EVSEL_4_gc = (0x0C<<0),
IRDA_EVSEL_5_gc = (0x0D<<0),
IRDA_EVSEL_6_gc = (0x0E<<0),
IRDA_EVSEL_7_gc = (0x0F<<0),
IRDA_EVSEL_OFF_gc = (0x00<<0),
IRDA_EVSEL_0_gc = (0x08<<0),
IRDA_EVSEL_1_gc = (0x09<<0),
IRDA_EVSEL_2_gc = (0x0A<<0),
IRDA_EVSEL_3_gc = (0x0B<<0),
IRDA_EVSEL_4_gc = (0x0C<<0),
IRDA_EVSEL_5_gc = (0x0D<<0),
IRDA_EVSEL_6_gc = (0x0E<<0),
IRDA_EVSEL_7_gc = (0x0F<<0),
IRDA_EVSEL_OFF_gc = (0x00<<0),
IRDA_EVSEL_0_gc = (0x08<<0),
IRDA_EVSEL_1_gc = (0x09<<0),
IRDA_EVSEL_2_gc = (0x0A<<0),
IRDA_EVSEL_3_gc = (0x0B<<0),
IRDA_EVSEL_4_gc = (0x0C<<0),
IRDA_EVSEL_5_gc = (0x0D<<0),
IRDA_EVSEL_6_gc = (0x0E<<0),
IRDA_EVSEL_7_gc = (0x0F<<0),
IRDA_EVSEL_OFF_gc = (0x00<<0),
IRDA_EVSEL_0_gc = (0x08<<0),
IRDA_EVSEL_1_gc = (0x09<<0),
IRDA_EVSEL_2_gc = (0x0A<<0),
IRDA_EVSEL_3_gc = (0x0B<<0),
IRDA_EVSEL_4_gc = (0x0C<<0),
IRDA_EVSEL_5_gc = (0x0D<<0),
IRDA_EVSEL_6_gc = (0x0E<<0),
IRDA_EVSEL_7_gc = (0x0F<<0),
IRDA_EVSEL_OFF_gc = (0x00<<0),
IRDA_EVSEL_0_gc = (0x08<<0),
IRDA_EVSEL_1_gc = (0x09<<0),
IRDA_EVSEL_2_gc = (0x0A<<0),
IRDA_EVSEL_3_gc = (0x0B<<0),
IRDA_EVSEL_4_gc = (0x0C<<0),
IRDA_EVSEL_5_gc = (0x0D<<0),
IRDA_EVSEL_6_gc = (0x0E<<0),
IRDA_EVSEL_7_gc = (0x0F<<0),
IRDA_EVSEL_OFF_gc = (0x00<<0),
IRDA_EVSEL_0_gc = (0x08<<0),
IRDA_EVSEL_1_gc = (0x09<<0),
IRDA_EVSEL_2_gc = (0x0A<<0),
IRDA_EVSEL_3_gc = (0x0B<<0),
IRDA_EVSEL_4_gc = (0x0C<<0),
IRDA_EVSEL_5_gc = (0x0D<<0),
IRDA_EVSEL_6_gc = (0x0E<<0),
IRDA_EVSEL_7_gc = (0x0F<<0),
IRDA_EVSEL_OFF_gc = (0x00<<0),
IRDA_EVSEL_0_gc = (0x08<<0),
IRDA_EVSEL_1_gc = (0x09<<0),
IRDA_EVSEL_2_gc = (0x0A<<0),
IRDA_EVSEL_3_gc = (0x0B<<0),
IRDA_EVSEL_4_gc = (0x0C<<0),
IRDA_EVSEL_5_gc = (0x0D<<0),
IRDA_EVSEL_6_gc = (0x0E<<0),
IRDA_EVSEL_7_gc = (0x0F<<0)
} |
|
enum | AES_INTLVL_enum {
AES_INTLVL_OFF_gc = (0x00<<0),
AES_INTLVL_LO_gc = (0x01<<0),
AES_INTLVL_MED_gc = (0x02<<0),
AES_INTLVL_HI_gc = (0x03<<0),
AES_INTLVL_OFF_gc = (0x00<<0),
AES_INTLVL_LO_gc = (0x01<<0),
AES_INTLVL_MED_gc = (0x02<<0),
AES_INTLVL_HI_gc = (0x03<<0),
AES_INTLVL_OFF_gc = (0x00<<0),
AES_INTLVL_LO_gc = (0x01<<0),
AES_INTLVL_MED_gc = (0x02<<0),
AES_INTLVL_HI_gc = (0x03<<0),
AES_INTLVL_OFF_gc = (0x00<<0),
AES_INTLVL_LO_gc = (0x01<<0),
AES_INTLVL_MED_gc = (0x02<<0),
AES_INTLVL_HI_gc = (0x03<<0),
AES_INTLVL_OFF_gc = (0x00<<0),
AES_INTLVL_LO_gc = (0x01<<0),
AES_INTLVL_MED_gc = (0x02<<0),
AES_INTLVL_HI_gc = (0x03<<0),
AES_INTLVL_OFF_gc = (0x00<<0),
AES_INTLVL_LO_gc = (0x01<<0),
AES_INTLVL_MED_gc = (0x02<<0),
AES_INTLVL_HI_gc = (0x03<<0),
AES_INTLVL_OFF_gc = (0x00<<0),
AES_INTLVL_LO_gc = (0x01<<0),
AES_INTLVL_MED_gc = (0x02<<0),
AES_INTLVL_HI_gc = (0x03<<0),
AES_INTLVL_OFF_gc = (0x00<<0),
AES_INTLVL_LO_gc = (0x01<<0),
AES_INTLVL_MED_gc = (0x02<<0),
AES_INTLVL_HI_gc = (0x03<<0),
AES_INTLVL_OFF_gc = (0x00<<0),
AES_INTLVL_LO_gc = (0x01<<0),
AES_INTLVL_MED_gc = (0x02<<0),
AES_INTLVL_HI_gc = (0x03<<0)
} |
|