RTEMS 4.9.6 On-Line Library

PowerPC Specific Information Processor Initialization

RTEMS CPU Architecture Supplement

7.6.2: Processor Initialization

If this PowerPC implementation supports on-chip caching and this is to be utilized, then it should be enabled during the reset application initialization code. On-chip caching has been observed to prevent some emulators from working properly, so it may be necessary to run with caching disabled to use these emulators.

In addition to the requirements described in the Board Support Packages chapter of the RTEMS C Applications User's Manual for the reset code which is executed before the call to rtems_initialize_executive, the PowrePC version has the following specific requirements:

Must leave the PR bit of the Machine State Register (MSR) set to 0 so the PowerPC remains in the supervisor state.
Must set stack pointer (sp or r1) such that a minimum stack size of MINIMUM_STACK_SIZE bytes is provided for the RTEMS initialization sequence.
Must disable all external interrupts (i.e. clear the EI (EE) bit of the machine state register).
Must enable traps so window overflow and underflow conditions can be properly handled.
Must initialize the PowerPC's initial Exception Table with default handlers.

RTEMS CPU Architecture Supplement