RTEMS 4.9.5 On-Line Library

ARM Specific Information Interrupt Processing

RTEMS CPU Architecture Supplement

2.4: Interrupt Processing

ARM Specific Information Vectoring of an Interrupt Handler

ARM Specific Information Interrupt Levels

ARM Specific Information Interrupt Stack

Although RTEMS hides many of the processor dependent details of interrupt processing, it is important to understand how the RTEMS interrupt manager is mapped onto the processor's unique architecture. Discussed in this chapter are the ARM's interrupt response and control mechanisms as they pertain to RTEMS.

The ARM has 7 exception types:

Reset
Undefined instruction
Software interrupt (SWI)
Prefetch Abort
Data Abort
Interrupt (IRQ)
Fast Interrupt (FIQ)

Of these types, only IRQ and FIQ are handled through RTEMS's interrupt vectoring.

RTEMS CPU Architecture Supplement