RTEMS 4.9.3 On-Line Library

M68xxx and Coldfire Specific Information Processor Initialization

RTEMS CPU Architecture Supplement

5.6.2: Processor Initialization

The address of the application's initialization code should be stored in the first vector of the EVT which will allow the immediate vectoring to the application code. If the application requires that the VBR be some value besides zero, then it should be set to the required value at this point. All tasks share the same MC68020's VBR value. Because interrupts are enabled automatically by RTEMS as part of the context switch to the first task, the VBR MUST be set by either RTEMS of the BSP before this occurs ensure correct interrupt vectoring. If processor caching is to be utilized, then it should be enabled during the reset application initialization code.

In addition to the requirements described in the Board Support Packages chapter of the Applications User's Manual for the reset code which is executed before the call to initialize executive, the MC68020 version has the following specific requirements:

Must leave the S bit of the status register set so that the MC68020 remains in the supervisor state.
Must set the M bit of the status register to remove the MC68020 from the interrupt state.
Must set the master stack pointer (MSP) such that a minimum stack size of MINIMUM_STACK_SIZE bytes is provided for the initialize executive directive.
Must initialize the MC68020's vector table.

RTEMS CPU Architecture Supplement