An RTEMS based application is initiated when the i386 processor is reset.
When the i386 is reset,
The EAX register is set to indicate the results of the processor's
power-up self test. If the self-test was not executed, the contents of
this register are undefined. Otherwise, a non-zero value indicates the
processor is faulty and a zero value indicates a successful self-test.
The DX register holds a component identifier and revision level. DH
contains 3 to indicate an i386 component and DL contains a unique revision
level indicator.
Control register zero (CR0) is set such that the processor is in real
mode with paging disabled. Other portions of CR0 are used to indicate the
presence of a numeric coprocessor.
All bits in the extended flags register (EFLAG) which are not
permanently set are cleared. This inhibits all maskable interrupts.
The Interrupt Descriptor Register (IDTR) is set to point at address
zero.
All segment registers are set to zero.
The instruction pointer is set to 0x0000FFF0. The first instruction
executed after a reset is actually at 0xFFFFFFF0 because the i386 asserts
the upper twelve address until the first intersegment (FAR) JMP or CALL
instruction. When a JMP or CALL is executed, the upper twelve address
lines are lowered and the processor begins executing in the first megabyte
of memory.
Typically, an intersegment JMP to the application's initialization code is
placed at address 0xFFFFFFF0.
RTEMS CPU Architecture Supplement