RTEMS 4.9.1 On-Line Library

SPARC Specific Information System Reset

RTEMS CPU Architecture Supplement

9.6.1: System Reset

An RTEMS based application is initiated or re-initiated when the SPARC processor is reset. When the SPARC is reset, the processor performs the following actions:

the enable trap (ET) of the psr is set to 0 to disable traps,
the supervisor bit (S) of the psr is set to 1 to enter supervisor mode, and
the PC is set 0 and the nPC is set to 4.

The processor then begins to execute the code at location 0. It is important to note that all fields in the psr are not explicitly set by the above steps and all other registers retain their value from the previous execution mode. This is true even of the Trap Base Register (TBR) whose contents reflect the last trap which occurred before the reset.

RTEMS CPU Architecture Supplement