RTEMS CPU Architecture Supplement
The PowerPC architecture defines thirty-two non-floating point registers directly visible to the programmer. In thirty-two bit implementations, each register is thirty-two bits wide. In sixty-four bit implementations, each register is sixty-four bits wide.
These registers are referred to as gpr0 to gpr31.
Some of the registers serve defined roles in the EABI programming model. The following table describes the role of each of these registers:
| Register Name | Alternate Name | Description |
| r1 | sp | stack pointer |
| r2 | na | global pointer to the Small Constant Area (SDA2) |
| r3 - r12 | NA | parameter and result passing |
| r13 | NA | global pointer to the Small Data Area (SDA) |
RTEMS CPU Architecture Supplement
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