RTEMS 4.9.0 On-Line Library

MIPS Specific Information Interrupt Processing

RTEMS CPU Architecture Supplement

6.4: Interrupt Processing

MIPS Specific Information Vectoring of an Interrupt Handler

MIPS Specific Information Interrupt Levels

Although RTEMS hides many of the processor dependent details of interrupt processing, it is important to understand how the RTEMS interrupt manager is mapped onto the processor's unique architecture. Discussed in this chapter are the MIPS's interrupt response and control mechanisms as they pertain to RTEMS.

RTEMS CPU Architecture Supplement