RTEMS 4.8.0 On-Line Library

SPARC Specific Information Vectoring of Interrupt Handler

RTEMS CPU Architecture Supplement

8.4.2: Vectoring of Interrupt Handler

Upon receipt of an interrupt the SPARC automatically performs the following actions:

disables traps (sets the ET bit of the psr to 0),
the S bit of the psr is copied into the Previous Supervisor Mode (PS) bit of the psr,
the cwp is decremented by one (modulo the number of register windows) to activate a trap window,
the PC and nPC are loaded into local register 1 and 2 (l0 and l1),
the trap type (tt) field of the Trap Base Register (TBR) is set to the appropriate value, and
if the trap is not a reset, then the PC is written with the contents of the TBR and the nPC is written with TBR + 4. If the trap is a reset, then the PC is set to zero and the nPC is set to 4.

Trap processing on the SPARC has two features which are noticeably different than interrupt processing on other architectures. First, the value of psr register in effect immediately before the trap occurred is not explicitly saved. Instead only reversible alterations are made to it. Second, the Processor Interrupt Level (pil) is not set to correspond to that of the interrupt being processed. When a trap occurs, ALL subsequent traps are disabled. In order to safely invoke a subroutine during trap handling, traps must be enabled to allow for the possibility of register window overflow and underflow traps.

If the interrupt handler was installed as an RTEMS interrupt handler, then upon receipt of the interrupt, the processor passes control to the RTEMS interrupt handler which performs the following actions:

saves the state of the interrupted task on it's stack,
insures that a register window is available for subsequent traps,
if this is the outermost (i.e. non-nested) interrupt, then the RTEMS interrupt handler switches from the current stack to the interrupt stack,
enables traps,
invokes the vectors to a user interrupt service routine (ISR).

Asynchronous interrupts are ignored while traps are disabled. Synchronous traps which occur while traps are disabled result in the CPU being forced into an error mode.

A nested interrupt is processed similarly with the exception that the current stack need not be switched to the interrupt stack.

RTEMS CPU Architecture Supplement