RTEMS 4.8.0 On-Line Library

SPARC Specific Information CPU Model Implementation Notes

RTEMS CPU Architecture Supplement

8.1.2: CPU Model Implementation Notes

The ERC32 is a custom SPARC V7 implementation based on the Cypress 601/602 chipset. This CPU has a number of on-board peripherals and was developed by the European Space Agency to target space applications. RTEMS currently provides support for the following peripherals:

UART Channels A and B
General Purpose Timer
Real Time Clock
Watchdog Timer (so it can be disabled)
Control Register (so powerdown mode can be enabled)
Memory Control Register
Interrupt Control

The General Purpose Timer and Real Time Clock Timer provided with the ERC32 share the Timer Control Register. Because the Timer Control Register is write only, we must mirror it in software and insure that writes to one timer do not alter the current settings and status of the other timer. Routines are provided in erc32.h which promote the view that the two timers are completely independent. By exclusively using these routines to access the Timer Control Register, the application can view the system as having a General Purpose Timer Control Register and a Real Time Clock Timer Control Register rather than the single shared value.

The RTEMS Idle thread take advantage of the low power mode provided by the ERC32. Low power mode is entered during idle loops and is enabled at initialization time.

RTEMS CPU Architecture Supplement