RTEMS 4.8.0 On-Line Library

ARM Specific Information Vectoring of an Interrupt Handler

RTEMS CPU Architecture Supplement

1.4.1: Vectoring of an Interrupt Handler

Unlike many other architectures, the ARM has seperate stacks for each interrupt. When the CPU receives an interrupt, it:

switches to the exception mode corresponding to the interrupt,
saves the Current Processor Status Register (CPSR) to the exception mode's Saved Processor Status Register (SPSR),
masks off the IRQ and if the interrupt source was FIQ, the FIQ is masked off as well,
saves the Program Counter (PC) to the exception mode's Link Register (LR - same as R14),
and sets the PC to the exception's vector address.

The vectors for both IRQ and FIQ point to the _ISR_Handler function. _ISR_Handler() calls the BSP specific handler, ExecuteITHandler(). Before calling ExecuteITHandler(), registers R0-R3, R12, and R14(LR) are saved so that it is safe to call C functions. Even ExecuteITHandler() can be written in C.

RTEMS CPU Architecture Supplement