The macro PPC_DEBUG_MODEL is set to indicate the debug support features
present in this CPU model. The following debug support feature sets
are currently supported:
PPC_DEBUG_MODEL_STANDARD
indicates that the single-step trace enable (SE) and branch trace
enable (BE) bits in the MSR are supported by this CPU model.
PPC_DEBUG_MODEL_SINGLE_STEP_ONLY
indicates that only the single-step trace enable (SE) bit in the MSR
is supported by this CPU model.
PPC_DEBUG_MODEL_IBM4xx
indicates that the debug exception enable (DE) bit in the MSR is supported
by this CPU model. At this time, this particular debug feature set
has only been seen in the IBM 4xx series.
RTEMS CPU Architecture Supplement