RTEMS 4.7.2 On-Line Library

SPARC Specific Information Processor Initialization

RTEMS CPU Architecture Supplement

7.6.2: Processor Initialization

It is the responsibility of the application's initialization code to initialize the TBR and install trap handlers for at least the register window overflow and register window underflow conditions. Traps should be enabled before invoking any subroutines to allow for register window management. However, interrupts should be disabled by setting the Processor Interrupt Level (pil) field of the psr to 15. RTEMS installs it's own Trap Table as part of initialization which is initialized with the contents of the Trap Table in place when the rtems_initialize_executive directive was invoked. Upon completion of executive initialization, interrupts are enabled.

If this SPARC implementation supports on-chip caching and this is to be utilized, then it should be enabled during the reset application initialization code.

In addition to the requirements described in the Board Support Packages chapter of the Applications User's Manual for the reset code which is executed before the call to rtems_initialize_executive, the SPARC version has the following specific requirements:

Must leave the S bit of the status register set so that the SPARC remains in the supervisor state.
Must set stack pointer (sp) such that a minimum stack size of MINIMUM_STACK_SIZE bytes is provided for the rtems_initialize_executive directive.
Must disable all external interrupts (i.e. set the pil to 15).
Must enable traps so window overflow and underflow conditions can be properly handled.
Must initialize the SPARC's initial trap table with at least trap handlers for register window overflow and register window underflow.

RTEMS CPU Architecture Supplement