RTEMS 4.7.2 On-Line Library

SPARC Specific Information Floating Point Registers

RTEMS CPU Architecture Supplement

7.2.1.2: Floating Point Registers

The SPARC V7 architecture includes thirty-two, thirty-two bit registers. These registers may be viewed as follows:

32 single precision floating point or integer registers (f0, f1, ... f31)
16 double precision floating point registers (f0, f2, f4, ... f30)
8 extended precision floating point registers (f0, f4, f8, ... f28)

The floating point status register (fpsr) specifies the behavior of the floating point unit for rounding, contains its condition codes, version specification, and trap information.

A queue of the floating point instructions which have started execution but not yet completed is maintained. This queue is needed to support the multiple cycle nature of floating point operations and to aid floating point exception trap handlers. Once a floating point exception has been encountered, the queue is frozen until it is emptied by the trap handler. The floating point queue is loaded by launching instructions. It is emptied normally when the floating point completes all outstanding instructions and by floating point exception handlers with the store double floating point queue (stdfq) instruction.

RTEMS CPU Architecture Supplement