PowerPC Specific Information Vectoring of Interrupt Handler
RTEMS CPU Architecture Supplement
5.4.2: Vectoring of Interrupt Handler
Upon determining that an exception can be taken the PowerPC automatically
performs the following actions:
an instruction address is loaded into SRR0
bits 33-36 and 42-47 of SRR1 are loaded with information
specific to the exception.
bits 0-32, 37-41, and 48-63 of SRR1 are loaded with corresponding
bits from the MSR.
the MSR is set based upon the exception type.
instruction fetch and execution resumes, using the new MSR value, at a location specific to the execption type.
If the interrupt handler was installed as an RTEMS
interrupt handler, then upon receipt of the interrupt, the
processor passes control to the RTEMS interrupt handler which
performs the following actions:
saves the state of the interrupted task on it's stack,
saves all registers which are not normally preserved
by the calling sequence so the user's interrupt service
routine can be written in a high-level language.
if this is the outermost (i.e. non-nested) interrupt,
then the RTEMS interrupt handler switches from the current stack
to the interrupt stack,
enables exceptions,
invokes the vectors to a user interrupt service routine (ISR).
Asynchronous interrupts are ignored while exceptions are
disabled. Synchronous interrupts which occur while are
disabled result in the CPU being forced into an error mode.
A nested interrupt is processed similarly with the
exception that the current stack need not be switched to the
interrupt stack.
RTEMS CPU Architecture Supplement