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Motorola M68xxx and Coldfire Specific Information Interrupt Processing

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3.4: Interrupt Processing

  • Motorola M68xxx and Coldfire Specific Information Vectoring of an Interrupt Handler
  • Motorola M68xxx and Coldfire Specific Information CPU Models Without VBR and RAM at 0
  • Motorola M68xxx and Coldfire Specific Information Interrupt Levels
  • Motorola M68xxx and Coldfire Specific Information Disabling of Interrupts by RTEMS
  • Motorola M68xxx and Coldfire Specific Information Interrupt Stack
  • Different types of processors respond to the occurrence of an interrupt in its own unique fashion. In addition, each processor type provides a control mechanism to allow for the proper handling of an interrupt. The processor dependent response to the interrupt modifies the current execution state and results in a change in the execution stream. Most processors require that an interrupt handler utilize some special control mechanisms to return to the normal processing stream. Although RTEMS hides many of the processor dependent details of interrupt processing, it is important to understand how the RTEMS interrupt manager is mapped onto the processor's unique architecture. Discussed in this chapter are the MC68xxx's interrupt response and control mechanisms as they pertain to RTEMS.


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