An RTEMS based application is initiated or
re-initiated when the XXX processor is reset. When the
XXX is reset, the processor performs the following actions:
The tracing bits of the status register are cleared to
disable tracing.
The supervisor interrupt state is entered by setting the
supervisor (S) bit and clearing the master/interrupt (M) bit of
the status register.
The interrupt mask of the status register is set to
level 7 to effectively disable all maskable interrupts.
The vector base register (VBR) is set to zero.
The cache control register (CACR) is set to zero to
disable and freeze the processor cache.
The interrupt stack pointer (ISP) is set to the value
stored at vector 0 (bytes 0-3) of the exception vector table
(EVT).
The program counter (PC) is set to the value stored at
vector 1 (bytes 4-7) of the EVT.
The processor begins execution at the address stored in
the PC.
RTEMS CPU Architecture Supplement