RTEMS 4.7.1 On-Line Library

ARM Specific Information Interrupt Levels

RTEMS CPU Architecture Supplement

1.4.2: Interrupt Levels

The ARM architecture supports two external interrupts - IRQ and FIQ. FIQ has a higher priority than IRQ, and has its own version of register R8 - R14, however RTEMS does not take advantage of them. Both interrupts are enabled through the CPSR.

The RTEMS interrupt level mapping scheme for the AEM is not a numeric level as on most RTEMS ports. It is a bit mapping that corresponds the enable bits's postions in the CPSR:

FIQ: Setting bit 6 (0 is least significant bit) disables the FIQ.
IRQ: Setting bit 7 (0 is least significant bit) disables the IRQ.

RTEMS CPU Architecture Supplement