RTEMS SPARC Applications Supplement
The maximum period with traps disabled or the processor interrupt level set to it's highest value inside RTEMS is less than TBD microseconds including the instructions which disable and re-enable interrupts. The time required for the ERC32 to vector an interrupt and for the RTEMS entry overhead before invoking the user's trap handler are a total of 8 microseconds. These combine to yield a worst case interrupt latency of less than TBD + 8 microseconds at 15.0 Mhz. [NOTE: The maximum period with interrupts disabled was last determined for Release 4.2.0-prerelease.]
The maximum period with interrupts disabled within RTEMS is hand-timed with some assistance from SIS. The maximum period with interrupts disabled with RTEMS occurs during a context switch when traps are disabled to flush all the register windows to memory. The length of time spent flushing the register windows varies based on the number of windows which must be flushed. Based on the information reported by SIS, it takes from 4.0 to 18.0 microseconds (37 to 122 instructions) to flush the register windows. It takes approximately 41 CPU cycles (2.73 microseconds) to flush each register window set to memory. The register window flush operation is heavily memory bound.
[NOTE: All traps are disabled during the register window flush thus disabling both software generate traps and external interrupts. During a normal RTEMS critical section, the processor interrupt level (pil) is raised to level 15 and traps are left enabled. The longest path for a normal critical section within RTEMS is less than 50 instructions.]
The interrupt vector and entry overhead time was generated on the SIS benchmark platform using the ERC32's ability to forcibly generate an arbitrary interrupt as the source of the "benchmark" interrupt.
RTEMS SPARC Applications Supplement
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