RTEMS Porting Guide
The _CPU_ISR_Disable routine disable all external interrupts. It returns the previous interrupt level in the single parameter _isr_cookie. This routine is used to disable interrupts during a critical section in the RTEMS executive. Great care is taken inside the executive to ensure that interrupts are disabled for a minimum length of time. It is important to note that the way the previous level is returned forces the implementation to be a macro that translates to either inline assembly language or a function call whose return value is placed into _isr_cookie.
It is important for the porter to realize that the value of _isr_cookie has no defined meaning except that it is the most convenient format for the _CPU_ISR_Disable, _CPU_ISR_Enable, and _CPU_ISR_Disable routines to manipulate. It is typically the contents of the processor status register. It is NOT the same format as manipulated by the _CPU_ISR_Get_level and _CPU_ISR_Set_level routines. The following is a dummy implementation that simply sets the previous level to 0.
#define _CPU_ISR_Disable( _isr_cookie ) \
{ \
(_isr_cookie) = 0; /* do something to prevent warnings */ \
}
The following is the implementation from the Motorola M68K port:
XXX insert m68k port here
RTEMS Porting Guide
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